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8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 1 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary g eneral d escription the ics8430bi-71 is a general purpose, dual out- put crystal/lvcmos-to-3.3v differential lvpecl high frequency synthesizer and a member of the hiperclocks? family of high performance clock solutions from ics. the ics8430bi-71 has a se- lectable crystal oscillator interface or lvcmos test_clk. the vco operates at a frequency range of 250mhz to 700mhz. with the output configured to divide the vco frequency by 2, output frequency steps as small as 2mhz can be achieved using a 16mhz crystal or test clock. output frequencies up to 700mhz can be programmed using the serial or parallel interfaces to the configuration logic. the low jitter and frequency range of the ics8430bi-71 make it an ideal clock generator for most clock tree applications. b lock d iagram p in a ssignment f eatures ? dual differential 3.3v lvpecl outputs ? selectable crystal oscillator interface or lvcmos test_clk ? output frequency up to 700mhz ? crystal input frequency range: 12mhz to 27mhz ? vco range: 250mhz to 700mhz ? parallel or serial interface for programming counter and output dividers ? rms period jitter: 9ps (maximum) ? cycle-to-cycle jitter: 25ps (maximum) ? 3.3v supply voltage ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs compliant packages 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 xtal_out test_clk xtal_sel v cca s_load s_data s_clock mr m5 m6 m7 m8 n0 n1 n2 v ee v ee nfout0 fout0 v cco nfout1 fout1 v cc test xtal_in np_load vco_sel m0 m1 m2 m3 m4 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view ics8430bi-71 hiperclocks? ic s osc vco_sel xtal_sel test_clk xtal_in xtal_out s_load s_data s_clock np_load m0:m8 n0:n2 vco pll fout0 nfout0 fout1 nfout1 test n configuration interface logic m 0 1 0 1 16 phase detector mr 2 the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice.
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 2 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary specific default state that will automatically occur during power-up. the test output is low when operating in the parallel input mode. the relationship between the vco fre- quency, the crystal frequency and the m divider is defined as follows: the m value and the required values of m0 through m8 are shown in table 3b, programmable vco frequency function table. valid m values for which the pll will achieve lock for a 16mhz reference are defined as 125 m 350. the frequency out is defined as follows: serial operation occurs when np_load is high and s_load is low. the shift register is loaded by sampling the s_data bits with the rising edge of s_clock. the contents of the shift register are loaded into the m divider and n output di- vider when s_load transitions from low-to-high. the m divide and n output divide values are latched on the high- to-low transition of s_load. if s_load is held high, data at the s_data input is passed directly to the m divider and n output divider on each rising edge of s_clock. the serial mode can be used to program the m and n bits and test bits t1 and t0. the internal registers t0 and t1 determine the state of the test output as follows: note: the functional description that follows describes op- eration using a 16mhz crystal. valid pll loop divider values for different crystal or input frequencies are defined in the in- put frequency characteristics, table 5, note 1. the ics8430bi-71 features a fully integrated pll and there- fore requires no external components for setting the loop band- width. a parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. the output of the oscillator is divided by 16 prior to the phase detector. with a 16mhz crys- tal, this provides a 1mhz reference frequency. the vco of the pll operates over a range of 250mhz to 700mhz. the output of the m divider is also applied to the phase detector. the phase detector and the m divider force the vco output frequency to be 2m times the reference frequency by adjust- ing the vco control voltage. note that for some values of m (either too high or too low), the pll will not achieve lock. the output of the vco is scaled by a divider prior to being sent to each of the lvpecl output buffers. the divider provides a 50% output duty cycle. the programmable features of the ics8430bi-71 support two input modes to program the m divider and n output divider. the two input operational modes are parallel and serial. fig- ure 1 shows the timing diagram for each mode. in parallel mode, the np_load input is initially low. the data on inputs m0 through m8 and n0 through n2 is passed directly to the m divider and n output divider. on the low-to-high transition of the np_load input, the data is latched and the m divider remains loaded until the next low transition on np_load or until a serial event occurs. as a result, the m and n bits can be hardwired to set the m divider and n output divider to a f unctional d escription n fout = fvco = 16 2m fxtal x n 16 fvco = fxtal x 2m t1 t0 test output 0 0 low 0 1 s_data clocked into register 1 0 output of m divider 1 1 cmos fout f igure 1. p arallel & s erial l oad o perations time s erial l oading p arallel l oading t s t h t s t h t s m, n t1 t0 n2 n1 n0 m8 m7 m6 m5 m4 m3 m2 m1 m0 s_clock s_data s_load np_load m0:m8, n0:n2 np_load s_load
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 3 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d , 3 , 2 , 1 0 3 , 9 2 , 8 2 2 3 , 1 3 , 7 m , 6 m , 5 m , 2 m , 1 m , 0 m 4 m , 3 m t u p n in w o d l l u p f o n o i t i s n a r t h g i h - o t - w o l n o d e h c t a l a t a d . s t u p n i r e d i v i d m . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i d a o l _ p n 48 mt u p n ip u l l u p 6 , 51 n , 0 nt u p n in w o d l l u p c 3 e l b a t n i d e n i f e d s a e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e l b a t n o i t c n u f 72 nt u p n ip u l l u p 6 1 , 8v e e r e w o p. s n i p y l p p u s e v i t a g e n 9t s e tt u p t u o . n o i t a r e p o f o e d o m l a i r e s e h t n i e v i t c a s i h c i h w t u p t u o t s e t . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e d o m l e l l a r a p n i w o l n e v i r d t u p t u o 0 1v c c r e w o p. n i p y l p p u s r e w o p e r o c 2 1 , 1 1 , 1 t u o f 1 t u o f n t u p t u o . s l e v e l e c a f r e t n i l c e p v l v 3 . 3 . r e z i s e h t n y s e h t r o f t u p t u o l a i t n e r e f f i d 3 1v o c c r e w o p. n i p y l p p u s t u p t u o 5 1 , 4 1 , 0 t u o f 0 t u o f n t u p t u o . s l e v e l e c a f r e t n i l c e p v l v 3 . 3 . r e z i s e h t n y s e h t r o f t u p t u o l a i t n e r e f f i d 7 1r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a d e t r e v n i e h t d n a w o l o g o t ) x t u o f ( s t u p t u o e u r t e h t g n i s u a c t e s e r s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t ) x t u o f n ( s t u p t u o d e d a o l t c e f f a t o n s e o d r m f o n o i t r e s s a . d e l b a n e e r a s t u p t u o e h t d n a . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s e u l a v t d n a , n , m 8 1k c o l c _ st u p n in w o d l l u p r e t s i g e r t f i h s e h t o t n i t u p n i a t a d _ s t a t n e s e r p a t a d l a i r e s n i s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s f o e g d e g n i s i r e h t n o 9 1a t a d _ st u p n in w o d l l u p f o e g d e g n i s i r e h t n o d e l p m a s a t a d . t u p n i l a i r e s r e t s i g e r t f i h s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s 0 2d a o l _ st u p n in w o d l l u p . s r e d i v i d e h t o t n i r e t s i g e r t f i h s m o r f a t a d f o n o i t i s n a r t s l o r t n o c . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 2v a c c r e w o p. n i p y l p p u s g o l a n a 2 2l e s _ l a t xt u p n ip u l l u p e h t s a k c o l c t s e t r o r o t a l l i c s o l a t s y r c e h t n e e w t e b s t c e l e s . h g i h n e h w s t u p n i l a t x s t c e l e s . e c r u o s e c n e r e f e r l l p . s l e v e l e c a f r e t n i l t t v l / s o m c v l . w o l n e h w k l c _ t s e t s t c e l e s 3 2k l c _ t s e tt u p n in w o d l l u p. s l e v e l e c a f r e t n i s o m c v l . t u p n i k c o l c t s e t , 4 2 5 2 , t u o _ l a t x n i _ l a t x t u p n i . t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x 6 2d a o l _ p nt u p n in w o d l l u p s i 0 m : 8 m t a t n e s e r p a t a d n e h w s e n i m r e t e d . t u p n i d a o l l e l l a r a p e h t s t e s 0 n : 2 n t a t n e s e r p a t a d n e h w d n a , r e d i v i d m e h t o t n i d e d a o l . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e u l a v r e d i v i d t u p t u o n 7 2l e s _ o c vt u p n ip u l l u p . e d o m s s a p y b r o l l p n i s i r e z i s e h t n y s r e h t e h w s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 4 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary t able 3b. p rogrammable vco f requency f unction t able (note 1) t able 3a. p arallel and s erial m ode f unction t able y c n e u q e r f o c v ) z h m ( e d i v i d m 6 5 28 2 14 62 36 18421 8 m7 m6 m5 m4 m3 m2 m1 m0 m 0 5 25 2 1 00 111110 1 2 5 26 2 1 00 1111110 4 5 27 2 1 00 1111111 6 5 28 2 1 0 10000000 ? ? ????????? ? ? ????????? 6 9 68 4 3 10 10 11100 8 9 69 4 3 101011101 0 0 70 5 3 10 10 11110 f o y c n e u q e r f t u p n i k l c _ t s e t r o l a t s y r c o t d n o p s e r r o c s e i c n e u q e r f g n i t l u s e r e h t d n a s e u l a v e d i v i d m e s e h t : 1 e t o n . z h m 6 1 t able 3c. p rogrammable o utput d ivider f unction t able s t u p n i e u l a v r e d i v i d n y c n e u q e r f t u p t u o 0 t u o f n , 0 t u o f ) z h m ( 2 n1 n0 nm u m i n i mm u m i x a m 000 2 5 2 10 5 3 00 1 4 5 . 2 65 7 1 010 8 5 2 . 1 35 . 7 8 011 6 15 2 6 . 5 15 7 . 3 4 10 0 1 0 5 20 0 7 10 1 2 5 2 10 5 3 110 4 5 . 2 65 7 1 111 8 5 2 . 1 35 . 7 8 s t u p n i s n o i t i d n o c r md a o l _ p nmnd a o l _ sk c o l c _ sa t a d _ s hx xxx x x . w o l s t u p t u o s e c r o f . t e s e r ll a t a da t a dx x x m e h t o t y l t c e r i d d e s s a p s t u p n i n d n a m n o a t a d . w o l d e c r o f t u p t u o t s e t . r e d i v i d t u p t u o n d n a r e d i v i d l a t a da t a dl x x d e d a o l s n i a m e r d n a s r e t s i g e r t u p n i o t n i d e h c t a l s i a t a d . s r u c c o t n e v e l a i r e s a l i t n u r o n o i t i s n a r t w o l t x e n l i t n u lh xxl a t a d n o a t a d h t i w d e d a o l s i r e t s i g e r t f i h s . e d o m t u p n i l a i r e s . k c o l c _ s f o e g d e g n i s i r h c a e n o a t a d _ s lh xx la t a d e h t o t d e s s a p e r a r e t s i g e r t f i h s e h t f o s t n e t n o c . r e d i v i d t u p t u o n d n a r e d i v i d m lh xx la t a d. d e h c t a l e r a s e u l a v r e d i v i d t u p t u o n d n a r e d i v i d m lh xxl x x . s r e t s i g e r t f i h s t c e f f a t o n o d t u p n i l a i r e s r o l e l l a r a p lh xxh a t a d. d e k c o l c s i t i s a r e d i v i d m o t y l t c e r i d d e s s a p a t a d _ s w o l = l : e t o n h g i h = h e r a c t ' n o d = x n o i t i s n a r t e g d e g n i s i r = n o i t i s n a r t e g d e g n i l l a f =
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 5 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary t able 4a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c t able 4b. lvcmos/lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i t u p n i e g a t l o v h g i h 1 e t o n ; k l c _ t s e t5 3 . 2v c c 3 . 0 +v , a t a d _ s , d a o l _ s , l e s _ o c v , r m , d a o l _ p n , k c o l c _ s l e s _ l a t x , 2 n : 0 n , 8 m : 0 m 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h , d a o l _ p n , r m , 1 n , 0 n , 7 m - 0 m d a o l _ s , a t a d _ s , k c o l c _ s v c c v = n i v 5 6 4 . 3 =0 5 1a l e s _ o c v , l e s _ l a t x , 2 n , 8 mv c c v = n i v 5 6 4 . 3 =5a k l c _ t s e tv c c v = n i v 5 6 4 . 3 =0 0 2a i l i t u p n i t n e r r u c w o l , d a o l _ p n , r m , 1 n , 0 n , 7 m - 0 m d a o l _ s , a t a d _ s , k c o l c _ s v c c , v 5 6 4 . 3 = v n i v 0 = 5 -a , 2 n , 8 m , k l c _ t s e t l e s _ o c v , l e s _ l a t x v c c , v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a v h o t u p t u o e g a t l o v h g i h 2 e t o n ; t s e t6 . 2v v l o t u p t u o e g a t l o v w o l 2 e t o n ; t s e t 5 . 0v . e t a r e g d e t u p n i s n 1 h t i w d e z i r e t c a r a h c : 1 e t o n 0 5 h t i w d e t a n i m r e t s t u p t u o : 2 e t o n v o t o c c . 2 / l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 0 4 1a m i a c c t n e r r u c y l p p u s g o l a n a 5 1a m note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c t able 4c. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c , n o i t c e s " n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p " e e s . v 2 - . e r u g i f " t i u c r i c t s e t d a o l t u p t u o v 3 . 3 "
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 6 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary t able 7. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c t able 5. i nput c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i y c n e u q e r f t u p n i 1 e t o n ; k l c _ t s e t2 17 2z h m ; t u o _ l a t x , n i _ l a t x 1 e t o n 2 17 2z h m k c o l c _ s 0 5z h m t t u p n i _ r e m i t e s i r t u p n ik l c _ t s e t 5s n e h t n i h t i w e t a r e p o o t o c v e h t r o f t e s e b t s u m e u l a v m e h t , e g n a r y c n e u q e r f e c n e r e f e r d n a l a t s y r c t u p n i e h t r o f : 1 e t o n 7 6 1 e r a m f o s e u l a v d i l a v , z h m 2 1 f o y c n e u q e r f t u p n i m u m i n i m e h t g n i s u . e g n a r z h m 0 0 7 o t z h m 0 5 2 m . 6 6 4 5 7 e r a m f o s e u l a v d i l a v , z h m 7 2 f o y c n e u q e r f m u m i x a m e h t g n i s u m . 7 0 2 t able 6. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 2 17 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 0 7z h m t ) c c ( t i j3 , 1 e t o n ; r e t t i j e l c y c - o t - e l c y c z h m 5 . 7 8 > t u o f5 2s p z h m 5 . 7 8 < t u o f0 4s p t ) r e p ( t i j1 e t o n ; s m r , r e t t i j d o i r e p 5 . 9s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 5 1s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 7s p t s e m i t p u t e s d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n t h e m i t d l o h d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n c d oe l c y c y t u d t u p t u o n 18 42 5% 1 = n5 45 5% t k c o l e m i t k c o l l l p 1s m . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . s t u p n i l a t x g n i s u e c n a m r o f r e p r e t t i j : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 7 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary p arameter m easurement i nformation p eriod j itter o utput s kew 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl ? ? ? ? c ycle - to -c ycle j itter t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 o utput r ise /f all t ime v oh v ref v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram o utput d uty c ycle /p ulse w idth /p eriod t sk(o) nfoutx foutx nfouty fouty nfoutx foutx clock outputs 20% 80% 80% 20% t r t f v sw i n g t pw t period t pw t period odc = x 100% foutx nfoutx 2v -1.3v 0.165v v cca = 2v v ee v cc , v cco
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 8 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics8430bi-71 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 2 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. p ower s upply f iltering t echniques f igure 2. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc a pplication i nformation figure 3. c rystal i npu t i nterface c rystal i nput i nterface a crystal can be characterized for either series or parallel mode operation. the ics8430bi-71 has a built-in crystal oscillator circuit. this interface can accept either a series or parallel crystal without additional components and generate frequencies with accuracy suitable for most applications. additional accuracy can be achieved by adding two small capacitors c1 and c2 as shown in figure 3 . c1 18p x1 18pf parallel crystal c2 22p xtal_out xtal_in
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 9 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, termi- nating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched impedance tech- f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination niques should be used to maximize operating frequency and minimize signal distortion. there are a few simple ter- mination schemes. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recom- mended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs i nputs : c rystal i nput : for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. test_clk i nput : for applications not requiring the use of the test clock, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the test_clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 10 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary f igure 5a. s chematic of r ecommended l ayout l ayout g uideline the schematic of the ics8430bi-71 layout example used in this layout guideline is shown in figure 5a. the ics8430bi-71 rec- ommended pcb board layout for this example is shown in fig- ure 5b . this layout example is used as a general guideline. the layout in the actual system will depend on the selected com- ponent types, the density of the components, the density of the traces, and the stack up of the p.c. board. s_load tl1 zo = 50 ohm r7 10 c14 0.1u c2 s_clock vcc vcc c16 10u x1 r1 125 fout ref_in tl2 zo = 50 ohm r4 84 c1 u1 ics8430bi-71 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 m5 m6 m7 m8 n0 n1 n2 vee test vcc fout1 nfout1 vcco fout0 nfout0 vee mr s_clock s_data s_load vcca xtal_sel test_clk x_o u t m4 m3 m2 m1 m0 vco_sel np_load x_in r3 125 r2 84 c11 0.01u in+ xtal_sel c15 0.1u in- + - foutn vcc vcca vcc s_data
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 11 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary the following component footprints are used in this layout example: all the resistors and capacitors are size 0603. p ower and g rounding place the decoupling capacitors c14 and c15 as close as pos- sible to the power pins. if space allows, placing the decoupling capacitor at the component side is preferred. this can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. maximize the pad size of the power (ground) at the decoupling capacitor. maximize the number of vias between power (ground) and the pads. this can reduce the inductance between the power (ground) plane and the component power (ground) pins. if v cca shares the same power supply with v cc , insert the rc filter r7, c11, and c16 in between. place this rc filter as close to the v cca as possible. c lock t races and t ermination the component placements, locations and orientations should be arranged to achieve the best clock signal quality. poor clock signal quality can degrade the system performance or cause system fail- ure. in the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. any ring- ing on the rising or falling edge or excessive ring back can cause system failure. the trace shape and the trace delay might be re- stricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. ? the traces with 50 transmission lines tl1 and tl2 at fout and nfout should have equal delay and run adjacent to each other. avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the transmission lines. ? keep the clock trace on the same layer. whenever pos- sible, avoid any vias on the clock traces. any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. ? to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. ? make sure no other signal trace is routed between the clock trace pair. the matching termination resistors r1, r2, r3 and r4 should be located as close to the receiver input pins as possible. other termination schemes can also be used but are not shown in this example. c rystal the crystal x1 should be located as close as possible to the pins 24 (xtal_out) and 25 (xtal_in). the trace length be- tween the x1 and u1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. other signal traces should not be routed near the crystal traces. f igure 5b. pcb b oard l ayout for ics8430bi-71 tl1n c14 r1 tl1, tl21n are 50 ohm traces and equal length tl1 c1 close to the input pins of the receiver gnd tl1n c2 vcc r7 pin 1 x1 r3 via vcca c11 c15 c16 r4 tl1 u1 r2
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 12 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics8430bi-71. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8430bi-71 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 140ma = 485mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 60mw total power _max (3.465v, with all outputs switching) = 485mw + 60mw = 545mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1c/w per table 8 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.545w * 42.1c/w = 108c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67. 8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47. 9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 8. t hermal r esistance ja for 32- pin lqfp, f orced c onvection
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 13 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 14 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary r eliability i nformation t ransistor c ount the transistor count for ics8430bi-71 is: 3948 t able 9. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67. 8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47. 9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 15 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary p ackage o utline - y s uffix for 32 l ead lqfp t able 10. p ackage d imensions n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a 0 6 . 1 1 a 5 0 . 05 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 00 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 7 c c c 0 1 . 0 reference document: jedec publication 95, ms-026
8430byi-71 www.icst.com/products/hiperclocks.html rev. a february 17, 2006 16 integrated circuit systems, inc. ics8430bi-71 700mh z , l ow j itter , c rystal i nterface / lvcmos- to -3.3v lvpecl f requency s ynthesizer preliminary t able 11. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications with out notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademark, hiperclocks is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 7 - i y b 0 3 4 8 s c i1 7 - i y b 0 3 4 8 s c ip f q l d a e l 2 3y a r tc 5 8 o t c 0 4 - t 1 7 - i y b 0 3 4 8 s c i1 7 - i y b 0 3 4 8 s c ip f q l d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l 1 7 - i y b 0 3 4 8 s c il 1 7 - i b 0 3 4 8 s c ip f q l " e e r f - d a e l " d a e l 2 3y a r tc 5 8 o t c 0 4 - t f l 1 7 - i y b 0 3 4 8 s c il 1 7 - i b 0 3 4 8 s c ip f q l " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n

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