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AMIS-53000 frequency agile transceiver data sheet AMIS-53000 frequency agile transceiver dat a sh eet 1 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table of contents 1.0 o v er v i e w of the a m is-53000 ................................................................................................. ............................................................. 5 1.1 applications fo r the amis - 53000 ............................................................................................ .......................................................... 5 1.2 key f eatur es ............................................................................................................... ..................................................................... 5 1.3 technica l feat ures ......................................................................................................... .................................................................. 5 1.4 circuit overvi ew ........................................................................................................... ..................................................................... 6 1.4.1. tra n smi t ter ............................................................................................................. ............................................................................................. 6 1.4.2. recei v e r ................................................................................................................ ............................................................................................... 6 2.0 operational specifications ................................................................................................. ............................................................... 8 2.1 absolute ma xim u m ratings ................................................................................................... ........................................................... 8 2.2 recommended oper ating cond itions ........................................................................................... .................................................... 8 2.2.1. parame tri c volta g e an d c u rrent le v e ls ................................................................................... ......................................................................... 8 2.3 operational specific ations ................................................................................................. ............................................................... 9 3.0 block diagra ms ............................................................................................................. ................................................................... 12 3.1 AMIS-53000 overal l block diagram ............................................................................................... ................................................ 12 3.2 pa ckage .................................................................................................................... ...................................................................... 12 3.2.1. pin d e fini tion .......................................................................................................... ........................................................................................... 12 3.2.2. blo ck dia g ram/pin defi nition ............................................................................................ ............................................................................... 13 3.2.3. ph y s ic al characteristics ................................................................................................ ................................................................................... 14 4.0 a c ron y ms ................................................................................................................... ....................................................................... 15 5.0 hard w a re descript ion ....................................................................................................... ............................................................... 16 5.1 freque ncy .................................................................................................................. ..................................................................... 16 5.2 rece iver ................................................................................................................... ....................................................................... 18 5.2.1. recei v e r lo w noise a m p lifier (l n a ) ...................................................................................... ......................................................................... 19 5.2.2. if filter ............................................................................................................... ................................................................................................ 20 5.2.3. data fil t er ............................................................................................................. .............................................................................................. 20 5.3 trans m i tter ................................................................................................................ ...................................................................... 20 5.4 single an tenna op tion ...................................................................................................... .............................................................. 21 5.5 p eak ....................................................................................................................... ......................................................................... 22 5.6 ad c ........................................................................................................................ ........................................................................ 23 5.7 control interf ace serial bus ............................................................................................... ............................................................. 23 5.8 tx/rx data inte rface seri al bus ............................................................................................ ........................................................ 24 5.9 system clock ............................................................................................................... ................................................................... 25 5.10 power and gr ounds ......................................................................................................... ............................................................. 25 5.11 design s uggesti ons ........................................................................................................ .............................................................. 26 6.0 user?s gui d e ............................................................................................................... ...................................................................... 28 6.1 control serial inte rface bus de scripti on ................................................................................... ...................................................... 28 6.1.1. co ntr o l in terface pr oto c ol .............................................................................................. .................................................................................. 28 2 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6.1.2. serial c o ntrol i n ter f ace: con f igur atio n ................................................................................. .......................................................................... 30 6.1.3. 3-wire i n terface mo de ................................................................................................... .................................................................................... 31 6.1.4. i 2 c i n ter f a c e .................................................................................................................... ................................................................................... 32 6.2 comm and regist er ........................................................................................................... .............................................................. 35 6.3 functional flow diagram s ................................................................................................... ........................................................... 36 6.4 freque ncy .................................................................................................................. ..................................................................... 40 6.4.1. fre que nc y c o n t rol ....................................................................................................... ..................................................................................... 40 6.4.2. 10khz os cillator ........................................................................................................ ........................................................................................ 44 6.4.3. s y ste m cl ock ............................................................................................................ ......................................................................................... 44 6.4.4. quick sta r t ............................................................................................................. ............................................................................................ 45 6.4.5. self c a lib ration ........................................................................................................ .......................................................................................... 45 6.5 rece iver ................................................................................................................... ....................................................................... 47 6.5.1. recei v e r circuit brief o v er v i e w ......................................................................................... ............................................................................. 48 6.6 transmi tter .................................................................................................................... ................................................................. 57 6.6.1. tx c o n f ig ............................................................................................................... ............................................................................................ 58 6.6.2. output p o w e r............................................................................................................ ......................................................................................... 59 6.6.3. pream ble leng th ......................................................................................................... ...................................................................................... 59 6.6.4. fm trans m it da ta sh api n g ................................................................................................ ............................................................................... 59 6.7 id le ....................................................................................................................... ........................................................................... 60 6.7.1. idle co nfi g ............................................................................................................. ............................................................................................. 60 6.7.2. sniff mo d e oper atio n .................................................................................................... .................................................................................... 61 6.7.3. burs t tra n smi t data ..................................................................................................... ..................................................................................... 65 6.7.4. ho useke e p ing ............................................................................................................ ........................................................................................ 67 6.8 idle ret u rn ................................................................................................................ ...................................................................... 68 6.9 ee ......................................................................................................................... .......................................................................... 69 6.9.1. write ee ................................................................................................................ ............................................................................................. 69 6.9.2. l o ad ee ................................................................................................................. ............................................................................................. 69 6.10 calib rate ................................................................................................................. ...................................................................... 69 6.10.1. in ternal trim .......................................................................................................... .......................................................................................... 70 6.10.2. cali brate quic k start os cillator ....................................................................................... .............................................................................. 71 6.10.3. cali brate 10khz osc illato r ............................................................................................. ................................................................................. 71 6.10.4. cali brate pll .......................................................................................................... ......................................................................................... 71 6.10.5. cali brate ln a .......................................................................................................... ........................................................................................ 71 6.11 rom 2 regs ................................................................................................................ ............................................................... 71 6.12 chip reset ................................................................................................................ .................................................................... 72 6.13 adc co nversion ............................................................................................................ ............................................................... 72 6.13.1. a d c co n v ersio n res u lts ................................................................................................. ............................................................................... 72 6.13.2. sin g le a dc co n v ersi on .................................................................................................. ................................................................................ 73 6.13.3. c onti n u ous a d c c o n v e r sion .............................................................................................. ........................................................................... 74 7.0 data interf ace ............................................................................................................. ....................................................................... 75 7.1.1. chi p a d dr ess msb1 ....................................................................................................... ................................................................................... 77 7.1.2. chi p a d dr ess lsb ........................................................................................................ ..................................................................................... 77 7.1.3. data rate/ forma t ........................................................................................................ ...................................................................................... 77 7.1.4. ge neral optio n s a....................................................................................................... ...................................................................................... 78 7.1.5. ge neral optio n s b ....................................................................................................... ...................................................................................... 79 7.1.6. start of fr ame .......................................................................................................... .......................................................................................... 80 7.1.7. data rate 1 ............................................................................................................. ............................................................................................ 80 7.1.8. data rate 0 ............................................................................................................. ............................................................................................ 80 7.1.9. crc pol y nomi a l .......................................................................................................... ...................................................................................... 80 7.1.10. de faul t l e ngth o f packe t ............................................................................................... ................................................................................. 81 7.1.11. bro a dca s t id 1 ......................................................................................................... ........................................................................................ 81 7.1.12. bro a dca s t id 0 ......................................................................................................... ........................................................................................ 81 7.2 tx/rx data in terface pr otocol .............................................................................................. .......................................................... 81 7.2.1. a m is-5 30 00 in mas t er mo de ............................................................................................... .............................................................................. 83 7.2.2. a m is-5 30 00 in sla v e m o d e ................................................................................................ ............................................................................... 84 3 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 7.2.3. manc hes t er opera t io n .................................................................................................... .................................................................................. 84 7.2.4. packe t fr amin g .......................................................................................................... ....................................................................................... 84 7.2.5. use i d .................................................................................................................. ............................................................................................... 85 7.2.6. le ngth o f packet ena b le ................................................................................................. ................................................................................. 85 7.2.7. crc enab le .............................................................................................................. .......................................................................................... 85 7.2.8. sof b y te ................................................................................................................ ............................................................................................ 86 7.2.9. ti min g di agrams for vari ous pack et fr a m ing mod e s ........................................................................ ........................................................... 86 8 . 0 ge ne ra l sy s t em func tio n s ................................................................................................... ........................................................... 90 8.1 pull up disable ............................................................................................................ .................................................................... 90 8.2 brown- out por .............................................................................................................. ................................................................ 90 8.3 temperat ure s ensor ......................................................................................................... .............................................................. 90 8.3.1. cr y s tal te mpera t ure c o m p ensa tio n ........................................................................................ ....................................................................... 91 8.4 softw are ................................................................................................................... ....................................................................... 91 8.4.1. a m is part re v i sio n c ode ................................................................................................. ................................................................................ 91 9 . 0 built-in te s t func tio n s .................................................................................................... ................................................................. 92 9.1 tm unlo ck regi st er ......................................................................................................... ............................................................... 92 9.2 test r egist er s ............................................................................................................. .................................................................... 92 9.2.1. if a m p m a nual trim a .................................................................................................... .................................................................................. 92 9.2.2. if a m p m a nual trim b .................................................................................................... .................................................................................. 92 9.2.3. pll man u a l trim ......................................................................................................... ...................................................................................... 92 9.2.4. pll tes t modes .......................................................................................................... ....................................................................................... 93 9.2.5. po w e r dow n rf sectio ns .................................................................................................. ............................................................................... 93 9.2.6. a n a l og te st mo de ........................................................................................................ ..................................................................................... 93 9.2.7. rf tes t m odes ........................................................................................................... ........................................................................................ 93 9.2.8. a n a l og te st mux ......................................................................................................... ...................................................................................... 93 9.2.9. rf tes t m u x ............................................................................................................. ......................................................................................... 94 9.2.10. di gital t est mux a ..................................................................................................... ..................................................................................... 94 9.2.11. di gital t est mux b ..................................................................................................... ..................................................................................... 94 9.2.12. di gital t est mux c ..................................................................................................... ..................................................................................... 95 9.2.13. di gital t est mo de a .................................................................................................... ..................................................................................... 95 9.2.14. di gital t est mo de b .................................................................................................... ..................................................................................... 95 9.2.15. di gital t est mo de c .................................................................................................... ..................................................................................... 95 9.2.16. di gital t est mo de d .................................................................................................... ..................................................................................... 95 9.2.17. me mor y test m ode a d dr ess ............................................................................................... ........................................................................... 95 9.2.18. me mor y test m ode data .................................................................................................. ............................................................................... 95 10.0 register definition....................................................................................................... ................................................................... 96 11.0 a ppli cati ons .............................................................................................................. ...................................................................... 98 12.0 ordering informa tion ...................................................................................................... ................................................................ 99 1 3 . 0 compa n y or produc t in quirie s .............................................................................................. ........................................................ 99 4 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 1.0 overview of the AMIS-53000 t he amis-530 00 is the l a test hig h l y fl e x ib le member of am i se mico nduct o r?s ast ric? famil y of si ngl e-chi p w i rel e ss transce ivers. i t is ide a ll y s u ite d for lo w to m o derate data r a te, lo w p o w e r, sub 1ghz, n a rro w ban d, f sk/gf sk/ook, multipl e ch ann el, w i r e les s app licati ons in the med i ca l, a u tomotive an d ind u strial m a rk ets. t he amis-530 00 c an ea sil y b e i n terfac ed to a b a se b and proc ess or via a seria l interfac e bus. 1.1 a p p licatio n s fo r th e a m is-5 300 0 ? medic a l impla n t able c o mmun i cation s y stems (mics) ? wireless medic a l t e lemetr y s y stems ? wireless sens ors ? rfid ? remote monitoring ? access contro l and secur i t y ? key l ess entr y ? mobile wireles s data t e rminals ? key l ess entr y ? t i re pressure monitors ? wireless t o y s 1.2 ke y f eatu r es ? medic a l imp l an t communicati o n protoco l sup port ? ver y l o w p o w e r singl e-chi p c m os transceiv er ? patented qu ic k start cry s tal oscill ator ? lo w p o w e r rec e ive sn iff mode? ? perio d ic trans mit using burst mode ? internal lo w pow er 10k hz osci llator ? internal se lf cal i brati on functi o n s ? spi/i 2 c interface bus ? 3- w i re/4- w i r e s e rial data int e rface ? t w o a n a l og to digit a l conv erte r chann els ? internal fractio nal n freq ue nc y s y nth e sizer ? on/off shift key/frequenc y sh ift ke y mo dul atio n/gaussia n f sk (bt = 1) ? internal temp er ature sens or ? minima l e x tern al comp one nts 1.3 t ech n i cal f eatu r es ? operatin g volta ge ran ge: 2.2 to 3.3v ? operatin g temperatur e ran g e : -40 to + 8 5 o c ? operatin g freq uenc y ra ng e: 300 to 9 28mhz ? data rate: o 1 to 19.2kb p s (ook) o 2 to 128k bps ( f sk/gf sk) ? t r ansmit output po w e r: o + 15dbm ma x ( h ig h po w e r) o +0dbm max (low po w e r) ? t r ansmit current: 50ma typic a l (15 d bm) 5 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet ? receiv er sens i t ivit y o ?11 5dbm (ook @ 1kbps) o ?10 5dbm (f sk @ 20kbps) ? receiv er curre nt: 12ma (continu ous) ? minimum r x e nerg y d e tect time: 130us (s niff) 1 . 4 c i r c uit ov er v i e w 1.4.1. t r ansmitter t he amis-530 00 us es a driv e r and class e p o w e r ampl ifier t o out put the on/off shift key ed or fr equ enc y s h ift ke ye d rf w a veforms . t h e class e po w e r amplifi e r has t w o outp u t po wer rang es al lo w i ng mo r e efficie n t output p o w e r for the one se tting up to 0 d b m output an d th e other settin g for output po w e r greater tha n 0 d bm. t he class e po w e r a m plifier c an ac hiev e outp u t po w e r of + 12d b m to + 15dbm for freque ncies i n the ran ge of 30 0mhz to 915m hz. t he outpu t po w e r is pro g r ammabl e in e a ch of the t w o output p o w e r b ands. t he transmit data can be n r z or manchest e r enc o ded. data can a l so be mod u late d as on/ off shift ke yed or freq u enc y s h ift ke ye d . data r a tes for t he ook mo dul ation can b e a s hig h as 1 9 .2k bps. d a ta r a te s for the f sk/gf sk modul ati on c an be as h i gh as 128k bps . t he carry fre q u enc y dev iati on for the f sk modul ation is prog rammabl e, t y p i call y o ne h a lf to one times th e data rate. t he transmit data outp u t can be w a v e sha p e d w i t h a gauss i an fo rmat. t h i s can reduc e the occu pi ed ba nd w i dth of the sign al. 1.4.2. receiv er t he amis-530 00 has a s i ng le rece iver c h a n nel an d a si ng l e transm i t cha nne l, w h ich ca n b e co nn ecte d to ind i vi dua l anten nas or c a n b e combi ned into a sin g le ante n na. t he receiv er uses f our d i ffer ent meth ods to receiv e a n d recover data t hat has be en o n /off shif t key e d or freq ue nc y s h ift ke ye d m o d u late d. t he f sk/gf sk data is r e cove r e d usin g e i ther a pll c i rcuit or a f f t circuit a l on g w i t h a c d r circuit. t he ook data is rec o vere d usi ng a n rssi circuit alo ng a n opti o nal c dr circ uit. it is suggested that the c d r circuit b e us ed w h e n receiv in g ook signals. 1.4.2.1. on/off shift key modulatio n t he AMIS-53000 uses a l oga rithmic receiv e d sign al streng th indi c a tor (r ssi) detector to recover the data from the on/off shift key e d modu lated w a v e form. data ra tes can be up t o 19.2k bps. t he amis -53 0 0 0 has e i ght d i s c rete data filter s for common bau d rates. th e receiv er can d e tect either nr z or manchest e r enco d e d dat a. 1.4.2.2. low data rate fr equency shift key modulatio n t he amis-530 00 uses a d i g i tal p ll detecto r to recov e r th e d a ta from th e freq uenc y sh ift ke yed data bel o w 20kb p s. t he recov e re d data w a veform is a ppl ie d to t he cl ock and d a ta rec o ver y c i rcuit to pr od uc e the di gital da ta an d a s y nch r oniz ed c l ock. t he rece i v e r can detect eith er nrz or manche ster encod ed d a ta. 1.4.2.3. high data rate fr equency shift key modulatio n t he amis-530 00 uses a fast fourier transfor m (f ft ) to recove r data from frequ enc y shif t ke yed mo dul ated w a v e form s w h en t he dat a rate is h i g her t han 20k bps. t he d a ta rate ca n be as h i g h as 128k bps. t h e demo dul ated data w a veform is ap pli ed to th e clock an d d a ta recover y circ uit to produce th e digita l data a n d a s y nchro n iz ed clo ck. t he receiv er can d e tect either nr z or manchest e r enco d e d dat a. 1. 4. 2. 4. clock and data r ecovery t he amis-530 00 uses a c l oc k an d d a ta r e c o ver y c i rcuit al ong w i th the frequ enc y s h ift k e yed or on/off shift ke ye d dat a d e tector ci r c u i ts to recover the data stream. t he cdr circuit s y nchr oniz e s a clock w i th t he data rate of the received data. t h is same circuit c an be used w i t h the on/off shift key e d w a veform. 6 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 1. 4. 2. 5. manchester data e n coding t he AMIS-53000 can e n co de the dat a as n r z or manche ster. 1.4.2.6. oscillators t he AMIS-53000 re quir e s a singl e e x ter n a l cr y s tal w o rki n g w i th th e inte rnal vco and pll to g e n e rat e frequ enci e s f r om 30 0mhz to 928m hz. t he amis-5300 0 has i n terna l ca pacitors th at el iminat e t he n e ed for e x ter nal loa d cap a citor s w h e n usi ng a t y p i ca l 24m hz ext e rna l cr ystal . t he vco re quir e s a n e x ter nal in ductor an d ca pacitor (in c ludi ng inter n a l cap a citanc e) t o pro duc e th e desir ed transm it or receiv e rf freque nc y . t he amis-530 00 gener ates the desire d rf transmit an d rec e ive freq ue nci e s from 300m hz to 928m hz b y selecti ng th e p r oper i n d u ctor and c a p a citor valu e al on g w i t h pr o g rammi ng the frequ enc y in the am is-5 300 0. a pate n t ed quick sta rt circuit is use d to force the cr ystal oscill ator o n to the desir e d freque nc y in microseco nds r a ther than i n m illis eco nds. a lo w po w e r internal 10khz oscillator pr ovid es the timing f o r sniff, burst and housek eepi ng. t he ami s -53000 self-c alibr a tion c irc u i t s can tune th is o scillator to w i t h i n t w o perce nt of 10khz. 1. 4. 2. 7. i n terface serial b u s t he AMIS-53000 h a s sep a rat e interfac es for data an d co ntrol. t he transfer of t x /rx d a t a bet w e en the amis-5300 0 a nd a n e x tern a l host/control l er is d one w i th a 3- w i r e s e ria l i n terface or a 4 - w i re spi c o m patib le s e ria l i n terface. co ntrol i n formati on is w r i tten to t he amis-5300 0 r egisters or r e a d from th e am is-5300 0 re gis t ers usi ng eith er a 3- w i r e s e r i al interfac e or a 2- w i r e i 2 c c o mpati b le seri a l interface. once the ami s -530 00 co nfig uratio n reg i ster s have data w r itten to them fo r various op era t iona l mod e s s u ch as, t x , rx, sniff or o th er , placi ng th e amis-5300 0 into o ne of these mo des is accom p l i she d throu gh a sing le w r ite t o the comman d register. tx/rx da ta in te rface t he transmit o r receive data interface of th e amis-5300 0 can be progr ammed to be either a pro p ri etar y 3- w i re se rial interfac e o r a 4- w i re s p i co mpatib le ser i al bus. t he dat a interfac e ca n be s e t up to do e i ther dat a transfers i n to a b u ffer in t he amis-53 0 0 0 or streamin g dat a (data is tra n s m itt ed as it is r e ceiv ed b y t h e amis-5300 0 or data is se nt to the h o st/controll er as it is recover ed i n th e amis-5300 0 re ceiver). w h en usi ng th e buffered data mo d e , the amis- 5 3 000 can b e th e master or sl av e, but it must b e the master to do streami ng d a ta. con t rol in terfa c e once the amis-530 00 is firs t po w e r e d on, an e x terna l h o s t/controlle r se ts the t y pe of i n terface to the amis-530 00 ( 3 - w ire or i 2 c) b y simpl y w r iti ng t o the amis-53 000 w i t h the d e sire pr otoco l . t he AMIS-53000 w i ll c ontin ue to use th at interface pr oto c ol unti l p ow e r i s remove d from the amis-530 0 0 . t he amis-5300 0 is al w a ys a slave dev ice for the control interface. 7 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 2.0 operational specifications 2.1 a b so lu te maxi mu m ratin g s table 1: absolut e maximum rati ngs sy mbo l parameter min. max. units notes vdd dc suppl y volta ge -0.3 3.6 v vin input pin voltage -0.3 vdd+0.3 v iin input pin cur r ent -10.0 10.0 ma 25c ts trg storage t e mper ature -55 150 c sso p tlead lead temp eratu r e 300 c 10 sec esd hbm human bod y mo del 2 kv esd cdm charged -device model 750 v esd mm machine model 200 v 2 . 2 re c o mme nded ope r a t ing condi tio n s table 2: operati ng conditions sy mbo l parameter min. max. units notes v d d d c suppl y 2.2 3 . 3 v idd d y namic cur r ent 70 ma (1) co ntinuous t x idds standb y cur r ent (off curre nt) 2 ua (2) vss grou nd 0.0 0.0 v t a a m b i e n t tempe r a t u r e - 4 0 8 5 c not e s: 1. dy namic cu rren t is w i th the tran smi t ter enabled a t max i mum outpu t pow er + 15dbm i n fsk m ode a t 92 8mhz. 2. s t andby curr ent is w i th all a nalog ce lls in pow er dow n. other logi c pow ered up w i th no clo c ks running. all outp u ts un load ed and inp u ts tied high or l o w . n o floa ting inpu t s . 2.2.1. para metric vo l t age an d curr e n t levels (t esting for the belo w c u rrents assumes a sta t ic test setup w i th measur eme n ts performed w h il e st atic dat a is app lie d to the dev ice.) 2. 2. 1. 1. i nputs table 3: pin inp u t paramete rs pin vil vih iil (1) iih (1) notes (2) min. (v) max. (v) min. (v) max. (v) min. ua max. ua min. ua max. ua a i 0 . 0 1 . 0 - 1 . 0 0 . 0 a n a l o g i n p u t disu 0.0 0.3 0.8 1.0 0.0 1.0 -30 -90 cmos w i th pull up schmitt d i s c 0 . 0 0 . 3 0 . 8 1 . 0 0 . 0 1 . 0 - 1 . 0 0 . 0 cmos s c h m i t t not e s: 1. iil an d iih are te sted at vdd = vddm ax v o lts. not te sted at le ss than room temperature . 2. pu = pull up , p d = pull dow n, sc = schmi t t, su = s c hmitt & pull up and sd = s c hmitt and p u ll dow n. 3. cmos v a lues ar e 'vin * vdd' and ttl v a lues are ab sol u te v o ltage s. 8 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 2. 2. 1. 2. outputs table 4: pin out put paramete rs pin vol (1) voh (2) iol (1,3) ioh (2,3) notes min. (v) max. (v) min. (v) max. (v) min. ma max. ma min. ma max. ma a o a n a l o g o u t p u t s do 0 0.4 vdd-.4 2 -2 cmos not e s: 1. vol , iol are te s t e d at vdd = vddmin v o lts u n less oth e r w ise stated . 2. voh , ioh are tested a t vd d = vddmin v o lts unle s s other w i se stated . 3. pola rity on curre nts indi ca te s dir e cti on o f curren t : (+) fo r si nkin g an d (- ) for sour cing . 2. 2. 1. 3. i / o p i ns table 5: i/ o pin parameters pin vil v min. vil v max. vih v min. vih v max. vol v (1) vol v max. (1) voh v min. (2) voh v (2) iol ma min. (1) ioh ma min. (2) iozl ua max. (3) iozh ua max. (3) notes a i o dio 0 0.3 0.8 1 0 0.4 vdd-.4 vdd 2 -2 1 -1 schmitt n o tes : 1. vol , iol are te ste d at vdd = 3.1 v o lts. 2. voh , ioh are tested a t vd d = 3.1 v o lts. 3. i o z i s te sted w i th vdd = 3 . 5 v o lts. *** lea kage on i/o pin s i s ty pically ch ecked for +/- 10 mi croam p s w i th the o u tpu t dev ice turn ed off and no pu or p d dev ice pre sen t. 2.3 op eratio n a l sp ecificatio n s table 6: operati onal specificatio ns parameter min. ty p . max. units com m en t recei v e r freque nc y ra ng e 3 0 0 9 2 8 m h z -107 -114 dbm @ 10khz data ra te (fsk/ gfsk m odulation) sensitiv ity -104 -111 dbm @ 10khz data ra te (ook mod u lation) noise f i g u r e 6 . 0 7 . 8 9 . 0 d b iip2 +60 dbm dual tone test us ing rssi iip3 +5 dbm dual tone test us ing rssi image rejection 30 40 50 db modulated desire d , single tone interfere r 1 5 - j 3 5 ? @ 900mhz serie s equivalent input impedance 7 2 - j 6 2 ? @ 433mhz serie s equivalent rssi g a in 14 16 18 mv/db i in 8 ma receiver current consumption at 900mhz f u ll shutdo w n 2 ua standb y current (no clocks enable d ) i sb cr y s tal mode 2 ma s y stem clock output enabled ( 6 m h z) t on 100 us standb y to recei v er on time t rx _t x / t tx _ r x 100 us transition time from rx to tx o r tx to rx la n input trim 1.2 4 pf internal capacitor range fo r the receiver input output trim 0.32 0.912 pf internal capacitor range fo r the out put of the lna in the receiver 9 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 6: operati onal specificatio ns (continued ) parameter min. ty p . max. units com m en t trans m itt e r freque nc y ra ng e 3 0 0 9 2 8 m h z t on 100 us standb y to trans mitter on time t tx _ r x 100 us transition time fr om tx to rx ook on/ o ff r a ti o 60 db fsk freq uenc y separation 0 200 khz allow able transm i t/receive peak deviation -20 15 dbm range of ou tput po w e r in the high po w e r mo de cw output p o wer -25 0 dbm range of ou tput po w e r in the lo w po w e r mo de p harmoni c s 35 dbc with complete matching net w o rk tx p a output cap. 2 7.5 pf internal capac itor range fo r the pa adjustable trim output s w itch r 5 18 ? on/ o f f r a t i o 6 0 d b output harmonic s -35 dbc with typical 50 ? matching circuits oper ating cur r e n t 50 68 ma 15dbm cw oper ating cur r e n t 12 24 ma 0dbm cw high power 1 4 1 6 . 5 1 7 d b m max power lo w power - 1 4 . 5 5 . 7 d b m matching net w o r k for 50 : 92 8mh z high high power 15.8 16.5 17 dbm max power lo w power 3 4 5 dbm matching net w o r k for 50 : 43 3mh z high cr y s tal oscilla tor center freq u e n c y 2 4 m h z t r i m m e d tolerance 20 ppm required cr y s tal tolerance startup time 50 100 us quick start enabl ed startup time 2 5 ms quick start disabled trim cap 0 45 pf internal trim cap a citor (self calibration sets) t r im resolution 145 160 175 ff i d d 8 0 0 u a normal ope ration idd 1.5 ma during quick start 10khz osci llat o r output freq uenc y 9.8 10 10.2 khz after trimming oper ating cur r e n t 300 375 450 na after trimming dut y c y c l e 5 0 % a dc r e s o l u t i o n 8 b i t s fsr vss vref v full scale input range c i 1 p f input c a p a c i t a n c e vref 2.0 v internal voltage r e ference r e f e r e n c e offset 1 % f s r fclk 0.01 2 mhz clock frequenc y conversion rate 200 ksps clock rate = 2mhz conversion time 10 tc l k 10 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 6: operati onal specificatio ns (continued ) parameter min. ty p . max. units com m en t data f ilter 3db do w n point 110 120 130 %f da ta am data filter ba nd w i dth (r elative to associated defined data rates) tem p erat ure se nsor output v o l t a g e 0 . 9 3 0 . 9 7 1 . 0 1 v at 27 o c voltage range 0.61 0.97 1.4 v output s l o p e - 5 . 2 4 mv/ o c d v / d t rssi buffer input range 0 vdd v oper ating cur r e n t 135 185 250 ua unit y gain-bw 615 1000 1700 khz 100k ? /100p f loa d pll 1 2 m h z transmit mode ( 24mhz exte rnal cr y s t a l ) reference in put freque nc y 16 mhz receive mode (2 4mhz exte rnal cr y s t a l) resolution 91.55 hz freque nc y step s i ze 9 . 6 2 1 2 1 4 . 4 m h z / v @ 4 0 0 m h z v c o gai n constant 2 5 . 6 3 2 3 8 . 4 m h z / v @ 9 0 0 m h z @ 900mhz, alth ough la y out p c b parasitics and co mponent placement w ill change this value settling time 100 us internal loop filter phase noise -90 -80 dbc/hz inte rnal loop filter @ 10khz offset phase noise -120 -110 dbc/hz internal loop filter @ 3mhz offset max spu r ious level -70 -50 dbc internal loop filter po r dela y time 28 43 60 ms b r ow n - ou t tr ip 1.2 1.6 1.8 v 11 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 3.0 block diagrams 3.1 a m is-5 30 00 ov e r all blo ck diag ram f i g u r e 1 : a m i s - 5 3000 b l ock diagra m 3 a c k ag 3 . p i n d n t 7 : p i n o n s . 2 p e . 2 . 1 e f i n i t i o a b l e d e f i n i t i pin# -001 -002 pin t y pe descrip tion 1 lnavdd lnavdd power a dc short (ind u c to r) is connected to vdd fr om this pin 2 rfin rfin a n a l o g i n p u t the r f i n p u t t o t he receiver circuits 3 r f v s s rf v s s g r o u n d g r ound fo r the rf cir c uits 4 rfout rfout analog output rf tra n smit output 5 r f p w r u t p u t po w e r the rf tr ansmitter (req u ires a dc short {inductor} rfp w r a n a l o g o v a r i a b l e d c v o l t a g e o u t p u t t o connection to rf out) 6 avdd avdd power vdd po w e r f o r th e a n a l o g c i r c u i t s 7 adc1 a d c 1 i n p u t a n a l o g input to t he a nalog to digital conversion circuit 8 adc2 adc2 a n a l o g i n p u t input to the a nalog to di gital conversion circuit 9 rssi rssi analog io analog voltage r e lated to the stre ngth of the received rf 10 peak peak analog analog voltage for ext e rnal auto - slice capacitor 11 avss avss g r ound g r ound fo r the analog cir c uits 12 xtal2 xtal2 analog connection to an exter nal cr y s tal 13 xtal1 xtal1 analog connection to an exter nal cr y s tal 14 int int digital output interrup t to e x ternal controller 15 dopt dopt digital input optional data pin for the 4 - w i re da ta interface mod e 16 dssn dssn d i g i t a l i o active low select line for the data i n terface 12 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 7 : p i n d t a b l e e f i nitions (continue d) pin# -001 -002 pin t y pe descrip tion 17 drxt x drxt x digital io serial data input (transmit) o r outp u t (received) 18 dclk dclk digital io recovered clock output (dat a inter f ace clock) 19 s y sclk s y sclk digital output s y stem clock output 20 dvss dvss grou nd grou nd for t he di gital circuit s 21 dvdd dvdd power vdd po w e r f o r th e digital circuit s 22 corere g ssn digital -001 (cont rol and status for the se rial data interface ) -002 (d ecoupling capacitor pin for the internal reg u lator) 23 sclk sclk digital bi-directional cl o ck for the 2- w i re serial interface 24 sdata sdata digital bi-directional data for the 2 - w i re s e rial interface 25 x b urs t x b urs t digital input active low input interr upt that w ill immediatel y cause a burst transmi ssion 26 loopout loopout analog output to the opti onal exte rnal loop filter 27 loopin loopin analog input from th e op tional external lo op filter 28 lo vss lo vss grou nd grou nd for t he lo cal oscillator circuits 29 lon lon analog negative side of the vco t ank 30 lop lop analog positive side of the vco t ank 31 lovdd lovdd power vdd for t he local oscillator circuits 32 rfvdd rfvdd power vdd po w e r f o r th e rf circuits 3.2.2. block di agra m / p in defi nitio n f i gure 2: b l ock diagram/p in definition * * no t ac t u al p a ck ag e m a rk i n gs . p l e a s e s e e m a rk i n g f o rm a t i n 3. 2 . 3. 3. 13 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 3.2.3. physical char acteristics 3. 2. 3. 1. p a ckage type 32 pi n lqf p 3. 2. 3. 2. p a ckage dimensions table 8: amis-5 3000 l q fp package dimensions sy mbo l min. nom. max. units t h i c k n e s s - - 1 . 6 0 m m d 9.00 bsc mm d 1 7 . 0 0 b s c m m e 9.00 bsc mm e 1 7 . 0 0 b s c m m e 0.80 bsc mm f i gure 3: p a ckag e 3. 2. 3. 3. p a ckage marking f o rmat (amis logo) bbb is the ami s device vers io n xxxxyzz is the date a nd trac tabilit y co de* ** * is the countr y of origin (fou n d on un ders i de of chip). t he year in w h i c h the mask w o rk w a s first fixed in a sem i co nductor ch ip pr oduct ma y als o appe ar. amis53000 a 1960 8-b bb xxxx yzz w here: a is the market appl icatio n 14 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 4.0 acronyms t he follo w i n g a c ron y ms are u s ed in this d o c u ment. am amplitu de mod u late d sig nal asic integrated circ uit desi g n ed fo r a singl e custo m er requ ireme n t ask amplitude shift key assp a custom integrated circuit, that may be used in gener al designs ast ric ami semicond uctor?s famil y o f w i re less pr od ucts cca clear c h a n n e l assessment cdr clock a nd dat a recov e r y , d a t a is recovere d from the recei v ed sig nal usin g a s y nchro n o u s clock crc c y c lic re du nd anc y ch eckin g ; data error che cking cw conti nuo us w a ve, a sing le frequ enc y or mo dul ated si gna l carrier dac digita l to anal o g conv ersio n db decib e ls; a lo g a rithmic me asu r e of signa l lev e l dbm log arithmic m easur e of sign al lev e l ab ove a milli- w a tt df ft digita l or discr ete f a st f ourie r t r ansform dpll digita l phas e l o cked l o o p cir c uit to create a precise freq ue nc y ee electrical er as abl e memor y f f t f a st f ourier t r ansform; transform bet w e en ti me and freq ue nc y f m f r eque nc y m o dul ated si gna l f sk f r eque nc y s h if t ke y gf sk gaussia n data w a veform modul ated si gna l if intermedi ate f r equ enc y kbps data rate in th ousa nd b i ts pe r second khz f r eque nc y in ki loh e rtz per sec ond lo loca l oscillato r frequenc y; us ed to conv er t signa ls bet w e en rf frequenc y and if freque n c y lop b y te i ndic a tin g the len g th of a packet mhz f r eque nc y in mega hertz mics medic a l impla n t able c o mmun i cation s y stem mv milli-v o lts ook on/off method of creating an amplit ude modulated signal ot a t r ansconducta nce ampl ifier pll phase l o cke d loo p circuit to create a prec is e freque nc y por po w e r- on-r e s e t is a threshol d circuit for limi t ing op erati on at lo w volta ges rf radi o f r equ en c y rssi receiv ed si gn al strength in di cati on; meas ur ement of rf signa l strength sof b y te i ndic a tin g start of packet in data prot ocol vco voltag e contro l l ed var i ab le fre que nc y oscil l at or 15 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 5.0 hardw a re description 5 . 1 fre que ncy t he amis-530 00 uses an int e rna l vco, pl l a nd trim c a p a citors w i t h an e x tern al oscil l a tor cr ystal to gen erate t he r f freque ncies for both t x and r x . t he extern al cr y s t a l is a para lle l reso na nt m ode cr ysta l w i t h req u ir ed loa d in g cap a cit o rs. t he amis-530 00 co n tains intern al l o a d capac itors, t y p i c a ll y suffici ent f o r use w i t h the sugg ested 24 mhz. it is suggested th at a 2 4 mhz w i th 20 p p m toler ance b e used w i t h the amis-5300 0. f i gure 4: external crystal circuit t he interna l v c o requ ires a n e x tern al par a llel lc t o set th e fr equ enc y f o r r x or t x . t here is an inter n al ca pacit ance that ne e ds to b e consi dere d w h en s e lecti ng t he v a lu es of t he i n d u ctor a n d ca pacitor. t he amis-530 00 is se nsitive to the pos itio nin g of th e l c compo nents in the la yout of the pc b. t he traces to the lc nee d to be a s s y mmetric a l as is possib l e. t he locatio n o f the lc ne eds to be as c l ose to the amis-530 0 0 pi ns as is pr actical. a sim p le l a yo ut cha n ge to thes e p a r a meters ca n m ean th at the a m is-5300 0 vc o freque nc y w i ll chan ge ca usi n g a n eed to c h ang e the va lu e s of the in duct o r, capac itor a nd/or the v a lu e s in the re giste r s control l i n g the rf frequenc y. t he value of the in ductor an d/or the capac i t or ma y ne ed to be adj usted t o allo w th e amis-5300 0 to cal i brate the pll for a giv en freq ue nc y of op eratio n. t he la y o ut of the pri n ted circuit bo ard fo r the in d u ctor and c apac itor shou ld ro ute traces co nnecti n g other comp on e n ts a w a y from the in ductor a n d capac itor pa ds. t he vco in the amis-530 00 is a differ entia l neg ative res i stance oscil l at or (dnro), com m onl y fo und in the liter ature. it uses an inter n a l voltag e var i ab l e ca pacitor (va r actor) in comb inati on w i th an ext e rna l l an d c to pr ovid e th e d e sire d freq u enc y. t he outp u t freq u enc y is found sim p l y b y : w here: ltot an d ctot are the total i n d u ctanc e a n d cap a cita nce r e spectiv e l y at the vco p i ns. t h is inc l u d e s the i n terna l capac ita nc e o f appr o x imate l y 2pf . 16 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 5: v c o external lc circuit t he AMIS-53000 has an i n ter nal l o o p filter to w o rk w i th th e pll i n creati ng the freq ue n c y of the d e vic e . t here is an option to use an ex t e rnal loop filter. table 9: inte rnal loop param e ter s filter com p o n en t value units com m en ts r 1 6 0 k ? c1 64 pf second ord e r c 2 3 p f r 110 k ? additional pole c 1 p f 17 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 18 f i gure 6: optional e x ternal loop f i lter circuit an i n tern al 10k hz osc ill ator provid es timi ng for functi ons; s n iff mod e , burs t transmit a n d hous eke epi ng, w h en t he amis-530 00 is in it s lo w e st po w e r mode ( i dl e/sta ndb y). t h is o scillator req u ir es no e x ter nal compo n e n ts. t he 10khz os cillator ? s i n tern al trim ca pac itor i s trimmed b y 8 b i ts of trim c ontr o l i n a se lf ca li bratio n. onc e the trim is set, the osc ill ator fr equ enc y w i l l b e acc u rate t o w i t h in t w o perc ent over spec ified voltag es an d temperatur es. 5 . 2 r e ce i v e r t he amis-530 00 h a s a sin g l e chan ne l rec e iv er. t he lna f o r the r e ceiv er inp u t req u ires a dc c o n necti on to grou nd o n the inp u t ( mus t not be a n rf groun d co nn ection). t he lna for the r e ceiv er in put requ ires a d c conn ectio n to rf vdd on th e outp u t. t hese conn ectio n s ar e supp lie d thro ugh i n d u ctors becom ing p a rt of the matchin g circuit for the receiver i nput. figure 7: receive r input matching circuit a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 5.2.1. receiv er low noise a m plifi e r (lna) t he receiver i n put of the ami s -530 00 is a s i ngl e e n d ed i n put an d sin g l e end ed o u t put devic e. t he input is match e d to 50 ? us ing an ext e rna l match i ng net w o rk, w h ich prov ides a dc p a th to g r oun d fo r bias i ng th e rec e iv er?s lna. t he o u tput of th e ln a is tu ned to th e desir ed o perati ng frequ enc y u s ing a n e x tern al in ductor a n d on-chi p ca p a c i tor. t he ind u ctor is also provi des the l n a w i th dc sup pl y voltag e. on-chip tuni ng ca pac itors are bi nar y w e ig hted a nd digit a ll y co ntrol l ed. t he internal i n put capac itanc e is 1.2pf to 4 p f . w i th this c apac itanc e set to the mid val u e (register set to 0 x 80), the i m ped an ce of the receiv er is sho w n in f i g u re 8. t he internal o u tput cap a citan c e is 0.32pf to 0.912pf . f i gure 8: rx i nput i m pedance 19 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet figure 9: receive r lna output inductor selection 5.2.2. if f ilter a passiv e p o l y -p has e filter and active fi lterin g are use d in t he amis -530 00 for fre que nc y se lect i v it y and rej e ction of the ima g e freque nc y . it is desig ne d to provid e an o p tim a l ima ge rej e cti on of 50 db at 500khz. 5.2.3. data f ilter t he ook lo w - pass data filter is used for ad di tio nal p o st-de t ection sig nal fi lterin g in accor danc e w i th the ook signal d a ta rate (1.2, 1.8, 2.4, 4.8, 7.2, 9.6, 14.4, 19.2k hz). t he rssi buffer is used to drive the r ssi signal off chip for e x ter n al mon i torin g , and ca n als o b e intern all y co nfi gure d for monit o rin g other sig nals su c h as th e ana lo g temp sense vo ltag e or ban dg ap vol t age. 5.3 t r an smitter t he AMIS-53000 transm i tter i s a t w o-stag e output ampl ifie r. w hen b o th stages ar e se l e cted, the hig h e st outp u t po w e r at frequ en cie s from 300m hz to 928m hz is + 15dbm. w h en o n l y one st age is us ed, the amis-53 0 0 0 can outp u t up to 0 d bm w i th better po w e r efficienc y tha n w h en o u tputti ng the sam e p o w e r l e vel w i t h both st ages. t he voltage ou tput level on th e rf pw r pin controls the rf output p o w e r l e vel of th e amis-530 00. a d c conn ectio n must be mad e bet w e en th e r f ou t pin and the rf pw r pi n. t he non-li n ear output of the a m is-5300 0 ma y req u ir e e x ter nal com pon ent s to match to a load a nd to re duce the s puri ous harm onics. t he output im ped anc e of th e amis-53 000 can be matc hed to the im ped anc e of an e x tern al loa d , usin g th e spr eads he et amis - 53rf m at ch.xls prov ide d b y amis. t h is spreads he et is e x plai ne d i n the app licati on not e, amis-52 x 0 0 ante nna imp eda nce m a tchi ng consi der atio ns . t he goa l of the transm i t o u tput match i ng w i th th is spr e adsh eet is to optimiz e the o u tput p o w e r w h ile re duci ng th e harmo nic po w e r. 20 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet figure 10: transmitter output matching circuit 5 . 4 single a n te nna optio n t he AMIS-53000 is designed such that w hen the transmitt er is off or the receiver is o ff, the pins are grounde d. t h is provides a kn ow n impe danc e for the off port (transmit or receiv e) in comb ini n g the receiver a nd the transmi t t er to a single anten na. f i gure 11: single a n tenna p o rt t/r matching circuit 21 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 5.5 peak t he AMIS-53000 has thre e modes for slic i ng the rece ive d sign al to rec o ver the dat a. one method i s to set a threshol d valu e th a t is fixe d a nd to w h ich th e receiv er compar es th e recover ed si gna l. t he other t w o m e tho d s have the am is-5300 0 aut o m aticall y s e ttin g a thresho l d l e ve l to w h ic h the r e ceiv er comp a r es the rec o ve red si gna l. bo th of these aut omatic thres h o l d meth ods re q u ire an e x te rna l capac itor on th e peak pin to oper ate. in the avera g i ng metho d , the amis-530 00 simpl y ad ds a lo w pass filt er w i th a cutoff frequ enc y set b e lo w th e data rate filter se tting. t h is second fil t er ex tracts a n avera ge rssi level as the d a ta s lice thr e s hol d. t he capacitor o n the p eak pin sets t he time co n stant (corner fre que nc y ) for t h is filt er. a t y p i cal c apac itor val ue w o ul d a llo w t h e aver age lev e l to settle to 95 perce nt of the rss i leve l in 2 bit interva l s (reme mber that man c hester enc od i ng ma y h a ve transiti ons t w ic e the data rat e ). t he avera ge thresh ol d method w i ll h a ve chatter befor e a sign al is rece ived a nd after the sig nal ends w h ich th e e x ter nal h o st/control l er must be ab l e to han dle. in the pe ak me thod the amis- 530 00 us es a peak detector t o find th e ma xi mum inp u t sig n a l lev e l and t h e n sets the thre shol d 6db l ow er than that lev e l. t he exter nal peak ca pac it or is used to b l e ed or d i schar g e the pe ak volt age i n the circ uit. t he volta ge s w i n g on the r ssi fo r a ty pica l 12 d b si gn al to no i s e ra tio a t 1 0 -3 be r is 240mv. t he c apac itor va lue shou ld not ch a nge the v o lta g e b y m o re th a n this 240mv dur ing a stri ng of zeros. t he value is d epe nd e n t on t he n u mb er of zeros that are all o w e d i n the chos en d a ta protoc o l, nr z or manch e ster enco d e d . f i gure 12: p e ak capacitance circu it 22 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 5 . 6 a dc t he adc is a s u ccessiv e ap pr oximati on a nal og to d i gita l co nverter, usi ng an int e rna l 8 b i t dac as the r e ferenc e. t he adc dat a for the selecte d in put chan nel(s) w i ll be stored in th e associ ated re gister, all o w i ng for exte rn al ac cess to the con v ersio n data th roug h the seri a l interface. co n v ersio n sp eed is reg i ster se le ctable up to 1 28ks/ s. c o mmands in the control r e g i ster all o w for sin g l e or c onti n uo u s oper ation of the adc. a voltage re gu l a tor gen erates the 2.0v refe re nce for the ad c and da c ba sed up on a n in ternal b a n dga p voltage so urce . t he adc ha s six i n p u ts, t w o of w h ich ar e av aila bl e to t he d e sig ner for use in their ap plic a t ion. 5.7 co n t ro l in terface se rial bu s t he AMIS-53000 uses a 3- w i re or 2- w i r e i 2 c interface to communic a te w i t h the amis-530 00 internal registers. t he AMIS-53000 w ill automatic all y d e termin e w h ic h interface to us e b y determ i ni ng the states o f the three li ne s; sdat a, sc lk an d ssn (the int e rface is se t w h e n the e x ter nal h o st/control l er w r ites th e first data to the amis-5300 0). once the amis-530 00 h a s d e termin ed the t y p e of int e r fa ce , it w i ll conti n u e w i t h that conf i g uratio n until po w e r is remov e d from the part or the part is reset. i 2 c: if ssn is hig h an d an i 2 c start bit is detected, i 2 c mode is en ab led. spi: if ssn is lo w , an d a ne g a tive ed ge o n sclk detect e d , spi mode is enab led. t he AMIS-53000 is des ig ned to conform to the phi lip s e mi cond uctor i 2 c standar d w i th th e amis-5300 0 as the slave de vice. f i gure 13: i 2 c serial b u s connectio ns 23 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 14: 3-w i re control b u s conn ections 5.8 t x /rx data interfa ce seri al bu s t he AMIS-53000 uses a 3- w i re or 4- w i re spi serial da ta interfac e to transfer data bet w e e n the ext e rna l host control l er a nd the amis-5300 0. t he interface is selected b y w r it ing to a re gi ster in the amis-530 00. t he dopt line is u ndefi n e d in the 3- w i re in t e rfac e. t he 4- w i re inte rface of th e a m is-5300 0 is desi gne d to b e comp atibl e w i t h the d e finiti on of a stan dard spi interface. t he amis- 530 00 can be a s l ave or master devi c e. t he stat us of the amis-5300 0, master o r slave, and th e interface mo de, read or w r ite, determi ne the defin ition of the drxt x a nd d o pt pin?s as o u tputs or inp u t s . f i gure 15: sp i co mpatible serial data i n terface 24 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 16: 3-w i re serial data i n terface 5 . 9 sy s t em c l oc k t he s y stem clo ck can pr ovi de a clock to the e x tern al host co ntro ll er. t he clock can be div i ded do w n from the 2 4 mhz cr ystal fre qu enc y of the AMIS-53000. w hen a desi gn des ires to use the s y st em clock as the clock to an e x tern al h o st/controll er, the s y s t em clock can b e output u nder th e follo w i n g : ? will be o u tput i n rx or t x , unless the out put is off in gen eral options b (bit 1:0). ? t he output w i ll start back up in idle mo de afte r a packet is re ceive d . ? t he output w i l l start back up in ho usek ee pi ng if w a k e u p ext e rn a l host/c ontrol l er is en abl ed i n ho use k eep ing c onfi g uratio n (bit 6). table 10: s y ste m clock control mode con t rol bits ou tpu t s com m en ts 0x0d ge neral options b 1:0 freque nc y : 12, 6 , 3mhz or off rx t x 2:1 por state: stan db y , idle, rx, tx standb y gene ral options a 0 output in standb y idle idle config 4:3 clock cy cles before stop 5 . 1 0 po w e r a n d gr oun ds t he amis-530 00 h a s fo ur diff erent po w e r i n puts a nd t w o d i fferent gr o unds . t h is allo w s the d e si gn of th e amis-53 000 in a n a p p l i cation to separate rf po w e r from th e ana lo g and d i gital po w e r. t he same a p p l i e s to the grou n d s, w h ere a se parate gr ou nd pla ne for the rf grou nds ca n re duce the amou nt of noise i ndu ced into th e se nsitive rf circ uits. 25 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 5 . 1 1 de s i gn sugge s t ions t he follo w i n g schematic a nd l a yout sug gests at least one w a y to cre a te a printe d circuit b oard for ap pl ications us in g the amis- 5300 0. f i gure 17: typica l design schematic f i gure 18: typica l design layout su ggestion 26 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 19: minimum design schematic f i gure 20: minimum design layout suggestio n 27 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 28 6.0 user?s gu ide t h is user?s gui de divi des the control regist e r descriptio n of the AMIS-53000 into functi o nal are a s; command re gister flo w dia g r ams , freque nc y ge n e ratio n , receiv er, transmitter, idle, d a ta /contr o l interfac es, burst transmit, and mics featur es. 6.1 co n t ro l serial in terface bu s desc rip t io n table 11: co ntr o l interface ph y s i c al configuration clock data interfa ce func tio n pin source ou tpu t inpu t select a m is -53000 i 2 c c o n t r o l s c l k m a s t e r s d a t a s d a t a n o n e s l a v e only 3-wire control sclk master sdata sdata ssn slave only t he AMIS-53000 emp l o y s t w o different con t rol interfaces. communic a tio n w i t h the amis-530 00 co ntrol regist ers is throu gh eith er a 3- w i re b u s or throu gh a 2- w i r e ( w it h third li n e for control/status) i 2 c compatibl e bus. t he state of t he control b u s is detected b y th e amis-5300 0 at the first communic a tion, i 2 c or 3- w i r e , and is set in that function (3- w ir e or i 2 c) as long as po w e r rema i n s app lie d to the part. 3- w i re co ntrol c o mmunic a tio n bus i 2 c control com m unic a tion b u s amis-5300 0 is al w a ys the sl a v e 6.1.1. contro l interface protocol t he AMIS-53000 contro l inter f ace all o w s an ext e rna l contro ller to w r ite ins t ructions to the regi sters of the amis-5300 0 and co n trol the functions of th e amis-53 0 0 0 . t he e x tern al control l er c an also rea d th e r egisters an d st atus of th e am is-5300 0. t h e contro l i n terface can be co nfig u r ed as a slav e devic e in eit her a 2- w i re i 2 c int e rface bus or a 3- w i re seri al i n terface. f i gure 21: contro l i 2 c p r otocol f o r m at a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 12: i 2 c ad dressing a d d r es s descrip tion 0 1 1 0 1 0 0 x a m i s - 5 3 0 0 0 i 2 c address 01101000 AMIS-53000 writ e command 01101001 AMIS-53000 r e a d command f i gure 22: 3-w i re control p r otocol f o rmat table 13: 3 - wire control (i n1 and in0) con t rol wor d bi ts in1 in0 descrip tion 0 0 single register read 0 1 single register write 1 0 sequential register read 1 1 sequential register write i 2 c device ad dr ess: o 0x68 he x for d e vice w r it e o 0x69 he x for d e vice re ad exter nal co ntro ller ca n w r ite re gisters 29 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet exter nal co ntro ller ca n read re gisters exter nal co ntro ller ca n issue a immediat e transmit via the xburst input exter nal co ntro ller ca n receiv e an in terru pt (xi n t ) from the amis-5300 0 setup reg i sters descripti ons: i 2 c/3- w i re select - f i rst w r ite to the interfac e sets the t y pe of interface unti l amis-5300 0 is po w e r c y cl ed. 6.1.2. serial c ontro l in terface: confi gurati on t he AMIS-53000 can autom aticall y det ect the t y p e of int e rface for the serial c ont rol bus. t he interface pins are then giv en th e defin itions as sho w n in t able 14. t he detec tion de pe nds o n the status of the amis-530 0 0 pins as sh o w n in f i gur e 23. table 14: co ntr o l port pin definitions pin name i 2 c mo de 3-wire mod e s c l k s c l s c l k sdata sda r/w controlled ssn internal pull up ssn f i gure 23: contro l i n terface selectio n s i m p l y ad dres t h e des ired p r o r f ace s e lecti on. after the first c o mmunic a tio n w i t h the part, the selecti on is loc the d e vice. t he interna l l o gic for determi nin g w h ich prot ocol to use on i n itia l po w e r u p is w s : i 2 c: if ssn is hig h an d an i 2 c start bit is detected, i 2 c mode is en ab led. 3- w i re: if ssn is lo w , a nd a n egativ e ed ge o n sclk det ected, 3- w i r e mod e is ena bl ed. t he internal p u ll ups o n sclk and sdat a can als o be d i sa ble d for i 2 c applicati ons us in g e x terna l pu ll ups. table 15: co ntr o l interface pull up cont rol sing t he part w i t h t o c o l p e rfor ms in iti a l i n t e k ed u n til po w e r is remov ed fro m a s f o l l o mode sclk, sd a t a p u ll ups ssn pin co nfi g uratio n i 2 c controlled b y bit 3 of the gene ral options a register not used (inter na l pull up) 3- w i re controlled b y bit 3 of the gene ral options a register ssn: normal mo de 30 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6.1.3. 3-w i re interfac e mode t he AMIS-53000 is al w a ys th e slave d e vice. f i gure 24: master/slave for b i - d irectional 3- w i re mode f i gure 2 4 ill ustrates the con n e ctions b e t w e e n the master spi port and the slave 3- w i r e p o rt in the amis-530 00. f i gure 25: single control r e gister r e ad/w r ite using th e 3-w i re i n terface 31 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 2 5 sho w s a si ngl e rea d or sing le w r it e control d a ta trans fer. t he operati on starts w i t h ssn trans itioni ng l o w to i ndic a te a start of transfer. t he first t w o bits transferre d are the instructio n fo r the slave interface of th e amis-5300 0 , in1 and in0. f o llo w i n g the instructio n are the si x a ddr ess bits to sp ecif y w h ich ad dress to read or w r ite from. if the in struction is to w r it e a r egister , the data to be w r itte n to ad dr ess locati on a < 5:0> is specifi ed w i th th e ne xt 8 bits, d< 7:0> . if the operat i on is a r ead, t he slav e out put buf fer is en abl ed at the end of th e addr ess bits, and the data bi ts d< 7:0> are buffered o u t of the part msb first. f o r singl e read / w rite, the ssn line ca n remai n active bet w e en success ive read a nd w r ite oper ations. f i gure 26: sequential control r e gis t er r e ad/w r ite using the 3- w i re i n terface f i gure 2 6 is a diagr am for sequ enti a l rea d s or sequ enti a l w r it es for 3- w i re contro l dat a transfer. t h e format of the instructi on and addr ess is id en tical to that for a sing le re ad/ w r ite oper atio n, w i t h the a ddr e ss correspo n d i ng to the first register l o cati on t o read or w r ite. t he first 8 bits of data transferred corr espo nd to the ad dr ess se lecte d . t he address i s interna l l y inc r emente d after each dat a by t e transferred. t h is task is m o st useful for writing to or re a d in g from vari abl es sp ann in g over m u lti p le addr ess l o cati ons suc h a s t h e fractiona l pll w o rd (re gisters 03-05). t he ssn line must be de-as serted at the comp l e tion of a sequ enti a l rea d / w r i te in or der for the slave spi controller to correctl y i n t e r p r e t the ne xt 8 bits as a comman d and not d a ta. 6.1.4. i 2 c interface t he i 2 c interface for the amis-530 00 is co mpat ib le w i th t he phi lip sem i cond uctor i 2 c standar d, w i t h the amis -530 0 0 as the slav e devic e. 32 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6. 1. 4. 1. i 2 c device a ddressing a contro l b y t e i s the first b y t e receiv ed fo ll o w ing the st art co nditi on from th e master dev ic e. t he contro l b y t e co nsists o f a 7-bits for the devic e a ddress , and 1-b i t for a read or w r ite c o mman d . f o r the am is-5 300 0, the devic e a ddress is ? 0 1 1 0 100 ? b i nar y. t he l a st b i t of t h e control b y te d e f ines the op era t ion to be perf o rmed. w hen set to ?1 ?, a read op eratio n is selected. w h e n set to ?0?, a w r it e op e ration is selecte d . f o ll o w in g th e start cond itio n, the amis-5300 0 m onitors t he s d a bus c hecki n g the dev ice t y pe i d e n tifier be ing tra n smi tted. upo n rece ivin g its devic e ad dr ess, the am is-530 00 outputs an ack n o w l e dg e sig nal on th e sda lin e. de p end ing on th e state of the r/ w bit, the amis-5300 0 w i l l select a read or w r ite operati on. 6. 1. 4. 2. single r e gister w r ite f i gure 27: single control data r e ad /w rite with the i 2 c interface t he master de vice iss ues the start con d itio n, then issu es th e d e vice a ddre ss, and the n is sues th e si ng le r/w bit, a lo gi c lo w s tate. t h is indic a tes to the address ed sl a v e receiv er tha t a b y te w i t h a r egister a ddr es s w i ll fol l o w after the slav e ha s gener ated an ackn o w l e dge bit duri ng the ni nth clock c y c l e. t her efore, the ne xt b y t e trans mitted b y the master is the register a ddres s to be w r itten w i th d a t a. after receivi n g an ot her ackno w l e d ge s i gn al from the amis-5 30 00, the mast er dev ice w i l l tr ansmit th e d a t a w o r d to b e w r itte n, a nd t h e amis-5300 0 w i ll ackn o w l edg e agai n. t he w r ite c y cl e en ds w i t h the master gener atin g a stop cond itio n. a similar ap pro a ch is use d to read a re gister value. t he mast er devic e is sues the start cond it ion, the n issues the dev ice ad dr e ss, an d then iss ues t h e sin g l e r/w b i t, a lo gic l o w s t ate. t h is indic a tes to the ad d r essed s l av e r e ceiv er that a b y t e w i th a r e g i ster a ddress w i ll follo w after th e slave has ge n e rated an ackn o w le dg e b i t dur ing th e ninth cl ock c y cle. t her efore, the ne xt b y t e transmitte d b y t he master is the register addr ess to be read. after recei v ing a noth e r a ckn o w l e d ge si gna l from the amis-5300 0, the master devic e w i ll imm e di ate l y follo w w i th an o t her start seq u ence, h o w e ver , the r/w bit is no w s e t hi gh t e lli ng th e sl ave devic e that th e master w a nt s the co n tents of the re gister ( a ddress ed w i th the w r ite com m and) to b e p l aced on the s d a bus li ne. afte r 8 bits of data are r ead b y the m a ster, the master does n o t ackno w l e dg e but sen d s the stop seq uenc e. 33 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6. 1. 4. 3. sequential r e gister w r ite f i gure 28: sequential control data r e ad/w r ite with the i 2 c interface w hen s e tting the amis-5 30 0 0 u p for a n ap plicati o n it s o m e times is n i ce to w r ite d a ta t o a n u mb er of re gisters on e aft e r the oth er. t h e w r it e co ntrol b y te, register ad d r ess a nd first d a ta b y te are tra n smitted to the amis-530 00 i n the same w a y as i n a b y te w r it e. ho w e ver, instea d of g e n e ratin g a sto p cond ition, th e master can c o ntinu e to w r it e register lo cati o n s. upo n rec e ipt of eac h w o r d , the a d dress is intern all y incr e m ented b y ? 1 ?. i f the master sh oul d transmit mo re w o rds th an the amis-5 300 0 h a s a ddr ess loc a tio n s, the a ddr ess w i ll roll over. it is a similar appro a ch to rea d a register val ue. t he w r ite control b y te a n d register ad dr e ss are transm i tted to the amis-530 00 i n the same w a y as i n a b y t e w r it e. after rece ivi ng a noth e r ack n o w l e d ge s i gn al from th e am is-5300 0, the master dev ice w i ll imme diate ly follo w w i th an o t her start seq u ence, h o w e ver , the r/w bit is no w s e t hi gh t e lli ng th e sl ave devic e that th e master w a nt s the co n tents of the register (a d d resse d w i th th e w r ite comma nd) to be pl ace d on t he sda bus li ne. after the 8 bits are r ead b y the ma ster, the master ackno w l e dg es the rec eptio n. t he amis-530 00 w i ll i n creme n t the r egist er addr ess a n d c ontin ue t o o u tp ut reg i ster va lu es. after the last register va lue i s receive d b y t he master, the master does n o t respon d w i th an ackno w l e d ge but se nds the stop se que nce. 6. 1. 4. 4. current a ddress r e ad t he interna l a d d ress co unter mainta ins th e l a st ad dress ad dresse d, incr e m ented b y ?1?. if the last instr u ction rece ived w a s to acc e ss register n, the current ad dres s read op erati on w i l l rea d the c ontents fro m register n+ 1 . t he timing for the current addr ess re ad i s to send a start bi t follo w ed b y t he 7-bit dev ice address, w i th the r/ w bit se t to one. t he slave w i ll ackn o w le dg e, after w h ich th e 8- bit register co nten ts w i l l be trans mitted. t he master does n o t ackno w l e dg e the tr ansmiss io n, but does g e nerate a sto p b i t. 34 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6. 1. 4. 5. i n terface options table 16: i 2 c ad dress auto incre m ent regist er num b er (hex ) name bits func tio n 0x0c gene ral options a 3 disable the inter nal pull up resist ors on sdata a nd ssn lines 5,4 select a clock rat e for the inte rface when the amis -53000 is master 0x0d gene ral options b 3 disable auto increment for i 2 c co ntrol interface re gister addressing additi ona l i n ter f ace opti ons g i ve the amis- 530 00 th e fle x ibil it y to t a il or the interfac e to spec ific req u ireme n ts. t h ese o p tio ns ar e avail a b l e in th e interface opti o ns regist er, an d can be stor e d into ee at bo ard assem b l y to best suit the app licati on. 6. 1. 4. 6. p u ll up disable t he AMIS-53000 inc l ud es bu i l t in pul l up resi stors for use w i th the i 2 c operation to red u ce the overal l s y s t em compon en t count. t he pull ups are as serted at por until mo de sel e ct ion occurs. if mode is deter mine d to be 3- w i re, the pu ll u p s are remov e d. if mo de is determi ned to be i 2 c, this option bit det ermin e s w h eth e r the pull u p s are to be remove d. 6.2 co mman d re g i ster t he amis-530 00 c ontai ns a singl e 8-bit r e g i ster that all o w s sin g le w r ites to the r egi st er to pl ace t he a m is-5300 0 i n t o a des ire d mo de. it is ver y im por tant to rem e mb er that all reg i s t ers associ ated w i th th at mo d e must b e prep rogramme d for the si ng le w r it e to th i s regist er to operate c o rrectl y . t he command register al lo w s the user ap p lic atio n to issu e a sing le re gi ster w r ite to th e amis-5300 0 to initiate the function l i sted in t able 17. w hen th e functi on is st arted, the amis-530 00 us es the r egister va lu es associat ed w i th the functio n selecte d as the param eters of the functio n . t hes e register values w i ll b e the def au lt values or th e val ues the us er app licati on h a s w r itte n to the registers b e for e the functio n i s calle d out in t he comma nd r egister. table 17: com m and - 0x00 [ 0 ] bit com m an d com m en t [ 7 : 4 ] [ 3 : 0 ] 0000 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1111 standb y receive transmit idle idle return write ee read ee cal i b rate qs os c calibrate rc calibr a te pll calibr a te lna rom2r egs global reset put the part into standb y put the part into r e ceive mode put the part into t r ansmit mode put the part into i d le mode use to retu rn to i d le after interrupt for hk or receive during sniff write the content of the w o rking re gisters into ee read the conten t s of the ee calibr a tes the quick star t osci llat o r calibr a tes the 10khz rc oscillator calibrates the pl l calibrates the l n a matching write the content of the r o m into the shado w r egisters resets the part c o mpletel y [ 7 : 6 ] [ 5 : 0 ] 01 xxxxxx 100000 single adc conversion do an adc one t i me on the chann el selected loop filter output 11 xxxxxx 100000 continuous adc conversions do an adc on th e channel selected continuousl y loop filter output standb y is b o t h a state for the transceiv er, and a comm an d give n to the transceiv er. t he actua l op er ation of stan db y mod e can be either a lo w - po w e r mod e w h e r e all inter nal c i rcuitr y of the am is-5300 0 e x ce pt for the i n terface w i ll b e disa ble d , or a clock-o n ly mode w h er e the cr ys tal osci ll ator w i ll b e ena bl ed t o co ntinu e pro v idin g a s y ste m clock for a n ext e rna l micr o p rocess or. a bit av ail a bl e i n the gen eral o p tio n s a register all o w s sel e ction of po w e r- do w n or clock-on l y o perati on in sta ndb y mo de. 35 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet man y of th e i n structions for t he p a rt are fini te in durati on and th e e nd p o int of th e task is contro ll ed b y th e amis-53 000, suc h as the calibr a tio n instr u ctions. f o r these instructi o n s , the amis- 53000 w i ll r e turn to its standb y mode at the c o mpleti on of the task . t he user ma y pol l the status/f lag 1 re g i ster bus y b i t to determin e the compl e tion of the cal i brat i on i n struction. oth er instructions suc h as rec e iv e or transmit are ind e finite in l e n g th an d user c ontrol l ed. t o return to the sta ndb y state, th e amis-5300 0 w a its for the st and b y instruction to end rece ive or transmit, at w h ich poi nt the tr ansceiver w i l l return to its stand b y stat e. note that there are t w o lo w - po w e r mod e s for the amis-530 0 0 ; standb y a n d idle. sta ndby allo w s the sysclk output idle is the ver y lo w po w e r state w i t h out sysclk output 6 . 3 func tio n a l f l o w dia g ra ms f i gure 29: r e ceiver f l ow diagram 36 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 30: transmit f l ow diagram 37 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet figure 31: multi-channel tx/rx 38 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 32: i d le state f l ow diagram 39 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 33: ee f l o w diagram e p r ogramme d to gener ate the t x freque nc y and to ge ner ate the lo freque nc y t o pr o duce th e mi xi ng frequ enc y f o r converti ng the receive d sig n a l to the l o w if (about 50 0k hz). t he amis-5300 0 can do a se lf-cali b ration, w h ich w i ll trim i n tern a l capac itanc e to tune the t x and r x frequ en cies . t he amis-530 00 ne ed s to run the self-c alibr a tio n (must be started b y the e x ter n al host/controller) at least once bet w een startup and ent ering a command suc h as t x , rx , sniff, etc. 6.4.1. f r eque ncy co ntrol amis has dev elo ped a n e x e c utabl e pr ogr a m (a mis-53c alc.e x e, avai l abl e from ami s , w h ic h g ene rates the reg i s t er valu es for t he freque nc y divi d e r and fractio n a l w o rd to pro duce a g i ven fr equ enc y. f i rst, the AMIS-53000 must hav e the correct lc for the des ire d freque nc y c o n nected to the vco pins. t h ere is inter n a l capac it anc e that is part of the capac it anc e for determin i n g the valu e o f the ind u ctor. t he follo w i n g eq uati on can b e use d to determin e the appr o x imat e valu e of the lc comp one nt s. remember that the vco i s sensitiv e to the pl aceme n t of t he lc c o mp on ents - th e y s h o u ld be p l ace d as cl ose t o the amis-530 00 a s practic a l ( e v en s hort tra ce s add si gnific ant paras itics) and the traces to t he compo n e n ts shou ld b e mad e s y mmetric al. 6 . 4 fre que ncy t he amis-530 00 uses an int e rna l pl l/vco to g ener ate th e rf fre que nci e s for both tra n smit a nd r e ce ive. on l y o ne set of re gister s nee d s t o b w here: ltot and ctot are the total ind u ctanc e and c apac ita n ce resp ective l y at the vc o p i ns. t h is includ es the inter nal capac i tanc e of appr o x imate l y 2pf . t he rf pll is a 24-b i t sigma delta b a se d fractiona l n s y nth e size r us ed to provi de the lo signa l for recei v e, and a d i rec t rf ou tput for transmit. 40 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet setup reg i sters descripti ons: rf di v i der - t he rf frequenc y of the rece ive r must be configure d . t h is is don e in t w o st e p s, one is setti ng the rf divi d e r and the other is set t ing the fractio nal n w o rd. rf fre que nc y - program the 3 register fracti ona l n w o rd. peak d e v i atio n - w hen the data modu latio n is to be f sk, the 2 reg i ster p eak dev iatio n must also be s e t. t he deviati on sho u l d be set to a valu e bet w e en ? a nd 1 times the data rate. pll - configur e the param ete r s for the pll. loo p f ilte r - config ure the p a r ameters for the loop filter. 6. 4. 1. 1. r f divider setting the rf chan nel fre que nc y is don e throug h the rf di vider re gister, alo ng w i th th e rf frequenc y 2, 1 and 0 re gi sters. t he rf divid e r reg i ster is used to spe c if y the i n teg e r portio n of the d i vide v a lu e, an d the rf frequ enc y 2, 1 an d 0 registers ar e used to specif y the fraction. t he val ues ar e calcul ated as fol l o w s: w here f c hann el is the desire d r f center freque nc y . t he va lue for the rf divider reg i ster is foun d b y , w here inte ger i s the value use d for rf divide r. t he last st e p is to calcul ate the fraction al value. t h is is don e as, r action is the value to b e u s ed in the rf freque nc y 2, 1 and 0 re gister s. as an exa m ple, if the de sired rf frequ enc y cha n n e l is 903.5m hz, f f o r this exam ple, the rf di freque nc y 0 to 0x54.t h i s v a l u vider re gister i s w r itten to 0 x 26, rf freque nc y 2 is w r itten to 0xf e , rf frequenc y 1 t o 0x95, an d r f e + y to the pl l as n0 an d n 1 . (i.e. if 63, send 64 a nd 6 5 to the pll) table 18: r f di vider - 0x05 [5] / - 1 is fed directl bit name com m en t 7:0 rf_divide [7:0] e d 4bh: divide b y 75 4ch thro ugh f f h : not allow e d 0 0 h t h r o u gh 0bh: not allow 1ah: divide b y 26 1bh: divide b y 27 --- --- -- --- 4ah: divide b y 74 41 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6. 4. 1. 2. r f f r equency 2 table 19: r f f r equenc y 2 = 0x0 6 [6] bit name com m en t 7:0 rf_f req [2 3:1 6 ] upper 8 bits of the rf fr action 6. 4. 1. 3. r f f r equency 1 table 20: r f f r equenc y 1 - 0x0 7 [7] bit name com m en t 7:0 rf_f req [1 5:8] center 8 bits of the rf f r action 6. 4. 1. 4. r f f r equency 0 table 21: r f f r equenc y 0 - 0x0 8 [8] bit name com m en t 7:0 rf_f req [7 :0] lo w e r 8 bits of the rf fr action 6. 4. 1. 5. p e ak deviation 1 t he peak devi a tion for f sk transmissi ons i s determin ed b y the pe ak dev iatio n 1 registe r and the pe ak deviati on 0 re gister. t h i s value is also us ed in side the df t fsk detector. calcul atio n of the valu e for the peak d e vi ation is straightfor w a r d: t he result of th is equ atio n, c onverted to he x, is entered i n to the peak d e via t ion reg i sters. t 2 2 : p v i a t i o n 1 - 0 x 0 a b l e e a k d e 9 [9] bit name com m en t 7:0 peak_dev [15:8] upper 8 bits of the peak deviation t 2 3 : p v i a t i o n 0 - 0 x 0 6. 4. 1. 6. p e ak deviation 0 a b l e e a k d e a [10] bit name com m en t 7:0 peak_dev [7:0] lo w e r 8 bits of the peak deviation 42 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6. 4. 1. 7. r f p ll options conta i ns g ener al opti ons for the setup of the rf pll. table 24: r f pl l options - 0x2 8 [40] bit name state com m en t 1 the kicker has been calibrated 7 kicker calibration status 0 the kicker has not been calibrate d 1 use the t y pe 1 c o mpensation for exter nal cr y s tal w i th curves similar to t y pe 1 (se e figure 32 ) 6 temper ature compensation c u rve 0 use the t y pe 2 c o mpensation for exter nal cr y s tal w i th curves similar to t y pe 2 (se e figure 33 ) 5 4 1 3 i n t e r n a l loop f i l t e r 0 enable using the internal loop filter for the p ll (us ed for calibration ) 1 50ua 2 charge pum p c u rrent 0 25ua 1 i v c o [ 1 : 0 ] 11 01 10 00 ivco= 1.2ma ivco= 800ua ivco= 600ua ivco= auto level control f i gure 34: typica l crystal temperature curve for crystal with type 1 characteristics 43 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 35: typica l crystal temperature curve for crystal with type 2 characteristics 6.4.1.8. loop filter table 25: loo p filter - 0x39 [5 7] bit name com m en t 7:0 loop_fil ter [ 7 :0] internal loop filter 6.4.2. 10kh z osc ill at or t he amis-530 00 h a s a n i n te rnal 10khz os cillator. t h is o scillator is ru n n in g w h en ever the amis-53 0 00 is in sta n d b y or id le m ode s. t h is ver y l o w po w e r osci llat o r provi des th e clock for tim i ng fu nc tions s u ch as sniff r e ceiv e, burst transmit or ho u s ekee pin g . th e oscill ator is trimmed in the c a libr a tio n instru ctions. setup reg i sters descripti ons: 10k oscillator trim - t he value of the cal i br ation for the 1 0 k hz oscill ator. (see sectio n 6 . 10.1.4)** 6.4.3. system cl ock t he AMIS-53000 pr ovid es a divid ed v e rsi on of the e x terna l refere nc e oscil l ator (t ypical l y 2 4 mhz ) as an o u tpu t to an e x tern a l host/control l er or other circu i ts need in g a clo ck. 44 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 26: s y ste m clock control regist er num b er (hex ) name bits func tio n 11 por sta r ts in tx 10 por sta r ts in rx 01 por sta r ts in idle 2,1 0x0c gene ral options a 00 por sta r ts in standb y 0 standb y mo de w i th s y stem clock o u tput 11 exte rnal xt al refere nce divided b y 2 (12m hz) 10 exte rnal xt al refere nce divided b y 4 (6mhz ) 01 exte rnal xt al refere nce divided b y 8 (3mhz ) 0x0d gene ral options b 1,0 00 s y stem clock off 11 s y stem clock continues for 1024 clock cy cles 10 s y stem clock continues for 512 clock cy cles 01 s y stem clock continues for 256 clock cy cles 0 x 1 0 i d l e c o n f i g 4 , 3 00 s y stem clock shuts dow n aft e r idle command asap setup reg i sters descripti ons: crystal oscillator trim - t he value of the ca librati on for the 10k hz osci llat o r. (see section 6.10. 1.1)** 6.4.4. quick start t he AMIS-53000 incl ud es the ast ric famil y p a t ente d quick start oscilla tor. t h is circui t uses a ?kicker? to force the cr y s tal o sc ill ator close to the fin a l des ired freq uenc y. t h is reduces the time r equ ired for the cr y s tal osci ll ator to settle to the rf freque n c y . table 27: kicker calibration regist er num b er (hex ) name bits func tio n 0x28 rf pll options 7 kicker calibration status setup reg i sters descripti ons: qu ick start t r im - t he value of the calibr a tio n for the kicker . (see section 6.10.1.3)** 6.4.5. self cal i brati o n t he AMIS-53000 h a s inter n a l trim functions fo r the pll, t x pl l, r x pl l, 10khz oscil l a tor, and k i cke r (quick start). a self cal i b rat i on is started b y writing an instru ction to the co mmand reg i ste r . t h is self ca l i brati on ne eds to be do ne at l east o n ce after the a mis-53 00 0 has b e e n p o w e red o n a nd bef ore the amis-5 300 0 is plac ed into a n y mo de such as tra n sm it or rece ive. t he a p p licati on shou ld mo ni tor the status regis t ers and trim va lu e registers t o determi ne th at the calibr a tio n w a s successf ul. table 28: self c a libration comm and regist er num b er (hex ) name code func tio n 0x07 calibrate the quick start (kicker) 0x08 calibrate the 10k hz oscillator 0x09 calibrate the pl l 0 x 0 0 c o m m a n d 0x0a calibrate the ln a bit 2 calibrate pll du ring hk bit 1 calibrate 10khz oscillator during hk 0x1b housekeeping config bit 0 calibrate kicker during hk 45 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet setup reg i sters descripti ons: status - conta i ns the results o f calibrati ons, i n stru ctions a n d activit y in th e amis-5300 0. soft w a re stat e - sho w s the c u rrent mod e of the amis-530 0 0 . 6. 4. 5. 1. status/f lag1 t he purpos e of the status1 re gister is to pro v ide informati o n back to the h o st on th e stat us of the part. t h is register s hou ld be quer i ed at the completi on of cali brati o n sequ enc es to ensure pr op er oper ation. t he flags w i l l be re set w h en th e register is re ad. checks um ind i cates w heth e r an attempt to read or w r ite the ee has fail ed due to an i n co rrect checksu m . instruction en a b le in dic a tes that the amis- 530 00 is rea d y to receive an instructio n. t h is can be use d to insure that the amis- 5300 0 does n o t miss a comman d in struction du e to the amis-53 000 n o t be ing read y. alo ng w i t h the b u s y fl ag, these statu s flags can p o lice the flo w of com m ands to the a m is-5300 0. table 29: status /flag1 - 0x01 [1] bit name state com m en t 1 pll out of lock on startup (rx, t x , sniff, burst) 7 p l l x l o c k 0 1 pll calibration for transmit failed 6 tx pll cal 0 1 pll calibration for receive failed 5 rx pll cal 0 1 10khz rc oscilla tor calibr a tion failed 4 rc cal 0 1 quick start calibration failed 3 quick start cal 0 1 ee checksum failed 2 checksum 0 1 the amis-53 000 is in a state of operation that can accept instructio ns 1 i n s t r u c t i o n e n a b l e 0 1 adc conversion complete 0 adc done 0 6. 4. 5. 2. status/f lag2 t he status2 register prov ides informati on on the oper atin g status of t he par t. t he bus y bit is asserted for an y of the follo w i ng r easo n s: calibration: t he b u s y bit w i ll remain hig h fo r the durati on of a ca li brati o n sequ ence. status2 ca n be r epe ated l y po lle d duri n g a cali bratio n se que nce to dete rmine w h en it?s complete. read /w rite ee: w h ile the amis-5300 0 is read ing from or w r it ing to the e e , the bus y bit w i ll rem a in s e t. buffered rx: w hen in rec e ive mod e , and a valid ch ip i d is found, th e amis-5300 0 w i ll b egi n pro c essin g of this packet. durin g the time the packet is b e in g process e d , the bus y b i t w ill be s e t hig h . buffe re d tx: after the com m and is g i ve n for transmit w i t h the buffere d packet optio n ena ble d , the b u s y bit w i l l rem a in hi gh until the p a rt h a s compl e ted the actua l trans mission of the packet. ho u seke ep in g : busy is ass e rted dur in g a hous eke epi ng c y cl e. burst tx: busy is assert ed d u rin g a burst transmissi on. 46 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet status2 a l so c ontai ns i n form ation on the re ason an int e rrupt w a s iss u e d to th e e x ter n al h o st. t he cca ch an nel status bits pro v ide informati on ba ck to the host on w h ich ch ann el w i th in the mics ban d is bein g us ed for commu nicati on. after a cca enab le d transmissio n , these bits w i ll b e set to in dicat e w h ic h ch ann el w a s use d . f o r mics ena ble d rece ivers performi ng mu l t i-chan nel s niff, these bits are used to in dic a te the cha nne l upo n w h ic h eit her en erg y or a n entire p a cket w a s fo und. if cca is en ab l ed for o per atio n other t han mi cs, bit 0 (c ca faile d) is us ed to ind i cate w h e t her or n o t the chan nel is cl ea r. t h e flags w i ll be reset w h en the register is r ead. table 30: status /flag2 - 0x02 [2] bit name state com m en t 7:4 cca chann el [3:0] indicates channel selected during cca 3:1 interrup t t y pe 111 110 101 100 011 010 001 000 rx crc failed receive energ y dwell timer timed out cca failed transmit complete buffer data fo r t x data has been re ceived housekeeping lo w batte r y 1 AMIS-53000 is b u sy 0 b u s y 0 6. 4. 5. 3. software state displ a y s the cu rrent mode of the amis-530 0 0 . t h is status register ca n be used to monit o r the activit y o f the AMIS-53000. table 31: soft ware state - 0x3c [60] bit name state com m en t 7:0 software stat e 1111 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 undetermined startup cop y ing rom d a t a to registers calibrating lna calibrating pll calibrating 10kh z oscillator calibr a ting q u ick star t ( k icker ) oscillator reading ee data writing ee data idle transmitting receiving standb y 6 . 5 r e ce i v e r t he AMIS-53000 rece iver is desi gne d for ei ther on/off shift ke y (am) mod u late d sign als or freque nc y s h ift ke y (f m) modu late d si gn al s. t he receiver i n clud es al l the c i rcuitr y to rec o ver data from eit her th e ook or the f sk m odu late d sig nal carrier. t he receiv er op erat es on fi xe d frequ e n cies i n the op eratin g frequ en c y ra ng e of 30 0 to 92 8mhz u s ing an i n tern a l fraction al n p ll to set the fr equ enc y. t h e receiv er can re duce po w e r co nsumpti on us in g the sniff mod e to ac qu ire th e incom i n g sig nal. t he recei v er can set a u s er defin ed fixed thresho l d for d a ta detecti on o r it can form a thresho l d from t he incom i n g si gna l for deter minin g the pr e s ence of si gn al and the state of the recover ed w a veform. t h e receiver ca n use a s y nchr o nous d a ta dete c tor to extract the data cl ock and the d a ta from the incom in g sign al (f sk modu latio n al w a ys us es this method of d a ta d e tection). ook modulati on (am) o manch e ster en codi ng o p tion o cdr dat a dete c tion opti on (re commen ded th at this be use d ) o common data rates from 1.2kbps to 19.2k bp s or user defin ed f sk/gf sk modul ation (f m) 47 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet o manch e ster en codi ng o f f t or pll demodu latio n (de pen ds on d a ta rate) o common data rates from 1.2kbps to 12 8kbps or user defin e d t he AMIS-53000 rece iver is a lo w if frequenc y s i n g le d o w n c onv ersi o n , sub-sampl i n g , image rej e ctio n architectur e w i t h a commo n am/fm if chain. t h ree dem odu lators ar e used for s i g nal detectio n w i t h add ition a l pos t-detection an d filterin g cap a b ilities f o r data recover y . a co mp lex fft d e m o d u l a t o r is u s e d fo r fsk sig n a ls w i th da ta ra te s > 2 0 k b p s . a digita l pll d e mod u lator is used for f sk sign als w i th data rates less than 20kbps. a logar ithmic ( r ssi) detector is used for ook/ask signals. 6.5.1. receiv er circ u i t brief overview clo ck an d d a t a r eco v e r y : t he amis-530 00 c an e x tract a s y nc hron ous clock sig nal from the rece ive d d a ta. in th is mode, th e data i n the rec e ive d si gna l is detecte d, filtere d a nd t hen f ed into th e clock an d d a t a recov e r y b l oc k w her e a d d i tio nal di gital filteri n g is perform e d . t he w a v e form is samp led usi ng a d a ta cl oc k in th e amis- 530 00 to s y nc hron ousl y reco ver the data. sign al s ensitiv i t y is improv ed and the recover ed data jitter is re duce d b y t h is method. lo fre que nc y : a s ub-sam p lin g lo freq u enc y architect u re is imp l em ented that do w n co nverts t he incom i ng rf sign al to t he if freque nc y of a bout 500k hz. t he lo freque nc y is pro duce d from th e i n te rnal v c o fre q u enc y. t he fre que nc y d e si gn of the lo si gn a l reduc es the po w e r cons umpti on of the amis-530 00 a nd si mplifies th e rec e iver, ach i evi n g reli abl e, qua drature lo sig nal g e n e ratio n. if top olo g y : t he receiver i m pleme n ts a q uadr ature do wn-conv ersio n a r chit ecture imp r ovin g im age r e jecti on an d cr eatin g th e si gn als re q u ire d fo r the co mp lex fft fsk sign al dete c tio n . t h e rece ive r u s e s th is q u a d r a t u r e do w n -co n v e r sion an d a co mbin a t ion o f pa ss ive and activ e po l y -phas e filterin g to provide im a ge sup p ressi on . sniff signa l a c quis i tion: as w i th e a rli e r ast ric de vices, the am is-5300 0 c a n red u ce the r e ceiv er p o w e r req u irem ents b y implem enti ng t he s n iff mod e for rf si gn al detecti on. s n iff mod e is a metho d us in g the qu ick sta r t oscill ator to quickl y w a ke t he receiv er, chec k for signal en erg y an d retur n to sleep or start t he receive function. t he quick sta r t can start the receiver cr ystal oscill ator in as little as 1 0 mic r o-seco nds. using th is fast start time, the sniff mode ca n turn on the r e ceiver, check f o r s ign a l e ner g y and retur n to sl eep i n as little as 130 micr o-s e con d s. more informati on ab out this sniff mode is i n sectio n 6.7.2. table 32: recei v e command regist er num b er (hex ) name code func tio n 0 x 0 0 c o m m a n d 0 x 0 1 instruction to place the amis-530 00 into receive (rememb er that a ll parameters for receive must be set before issuing this command) setup reg i sters descripti ons: rx config - options for the receiver must be set. rf fre que nc y - t he rf frequenc y of the rec e iver must be c onfig ured. (se e section 6. 4.1 . 1) 48 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6. 5. 1. 1. r x configuration f i gure 36: r e ceiver timing chart table 33: recei v er timing timi ng sy mbo l min. ty p . max. units com m en ts t pr e m o d 1 m o d 1 d b i t s the tx p r eambl e should be mad e long enough to allow the receiver to acquire the signal t e 0 255 d bits the ene rg y d w ell timer should be set long enough t o allow the receiver to detect the ener g y 2 t id 0 2 5 5 d b i t s the id d w ell timer should be set long enough t o allow the receiver t o detect the chip id or glo bal id 2 t lo p 1 default 255 d bits the length of p a cket w ill turn the receiver off after the number of da ta bits is received not e s: 1. the need for a p r eamble and the ty pe o f pr eamble i s d e termined by the d a ta mod u lati on sele cted . 2. the dw ell timer s need to be long e nough to allow the receiv er to stay acti v e from the time i t turns on due to ene rgy and th e time th at the de sir ed ev ent o c curs. how e v e r, making thi s number the max i mum may in th e ca se o f fal s e energy detection or sig nal corr uptio n m a y w a ste sy stem p o w e r unnece ssa r ily. 49 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet t he rx confi g register is use d to se t options for receive mo de op erati on. w ake o n en erg y : w hen ena ble d , the cdr circuit is he ld i n reset unti l the ener g y thres hol d is met. this opti on ca n be use d to make the normal receiver f unction to perform simila r to sniff. t he energy d w ell time r is used t o dete rmine how long the receiv er w i ll st a y on c heck i ng for ener g y (w i t h f f in the e n e rg y d w e l l time register, the re ceiver w i ll sta y on u n til th e thr e s ho ld is met). ga te on ene r gy : t h is o p tio n can b e us ed in f m rec e ive mode on l y , an d w i ll gate th e data i n terface w h il e th e e nerg y on rssi is bel o w the e n e rg y t h resh old. am _ f m _ r x : sets the mode of operati on for receive. forc e mics cha nne l: w hen this bit is s e t, the b i ts in statu s 2 use d to sh o w w h ic h ch an n e l the r adi o is on ca n b e over w r itte n to force a parti cular ch ann el. table 34: rx co nfig - 0x0e [14] bit name state com m en t 1 rssi output du ring rx 7 r s s i a c t i v e 0 1 sniff cy cle perf o r m ed at multiple pre-defined cha n n e ls 6 multi channel 0 5 4 lna mode[1:0] 11 10 01 00 no opera t ion defined linear mode high gain mode normal gain mod e 3 forc e mics channel 1 0 force receive m ode on a specif ic mics channel (s tatus2) 1 am receive mode 2 a m _ f m _ r x 0 fm receive mod e 1 clock and data o u tputs gated fo r rssi AMIS-53000 frequency agile transceiver data sheet 51 6.5.1.3. receiver paramete rs figure 37: rec e iv er sensitivity vs. d a ta rate : r f i g u r e 3 8 ssi c u rve a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6 . 5. 1. 4. data r ecovery table 36: recei v er configuration rx con f ig urati o n regi sters 0 x 0 e r x c o nfi g 0x1f cd r op tion s a 0 x 0 b d a t a rat e forma t 0x1e filter slice bit 2 mod bit 0 demo d bit 3 code bit 1:0 data ra ge preamble cdr so f 0 nrz slice 1 2 >20k ? 128k 10pattern y e s 3 no 0 fft 1 man slice 2 > 2 0 k ? 1 2 8 k 10pattern y e s 3 no 4 0 nrz slice 1 2 < 2 0 k 10pattern y e s 3 no 0 fm 1 pll 0x55 1 man slice 2 <20k all 1 or 0?s y e s 3 0xaa 0 nrz slice 2 1k ? 19.2k cw opt 7 0x55 0 na 6 1 man slice 2 1k ? 19.2k cw opt 7 0x0a 0 nrz slice 2 1k ? 19.2k cw opt 7 0x55 1 am 1 na 6 1 man slice 2 1k ? 19.2k cw opt 7 0x0a not e s: 1. long s t ri ngs o f 1?s or 0 ? s w ill degra de the pe rf orma nc e o f t h e c d r c i r c uits. sl ice can u s e the parame t er s i n t able 38 . s ed t o de t e ct t h e d a t a . (se e table 4 1 and table 42 f o r c dr paramet er s ) a sof. a unique s o f (sugge sted 0x 66) i s u s ed to bi t-alig n th e man c he ste r d e coder to the r e c overed da ta . 0 x 55 or 0 x 0a s o f hav e the foll ow i ng requi rements: i t i s s ugge s t ed t h a t cdr w i t h ac t i v i t y check be enab led w i t h 8 or 16 bit t i mes (10 or 20 bit times) i t i s s ugge s t ed t h a t cdr w i t h ac t i v i t y check be enab led w i t h 4 bi t t i me s it i s sugge sted tha t the preamble be lo ng enoug h to trigg e r a c tiv i ty check t the parame t er is n o t av ailable for the am/ook modula t e d si gnal s. m data reco ver y w i th rssi t he logarithmi c am detector, used w i th ook /ask modula t ed sign als, pr oduc es an rs si out put sign al w i th a ppro x i m atel y 18mv/d b output l e vel. a lo w p a ss filt er provi des ad ditio nal fi lterin g matche d to the am sign al data rate (1. 2 , 1.8, 2.4, 4.8, 7.2, 9.6 , 14.4, 19.2kb p s). t h is filtered sig nal is sampl ed an d compar ed to the slice thres hol d to recover the digita l dat a. t he slice thresho ld can b e set to a fixed v a lu e or it can u s e a sign al trac king circ uit to set a peak or av erag e thresh ol d. t he rssi outp u t sig nal ca n al so b e app lie d t o a clock a n d data r e cov e r y circuit, w h ich s y nc hro n izes a n amis-530 00 i n terna l cl oc k with the incom i ng d a ta rate (see c dr operati on). setup reg i sters descripti ons: slic e thre s hold - t he slice o perati on ne eds to be sel e cted , fixe d or aut o m atic. t he val ue for th e fi xe d thresh old ne e d s to b e set. filter/slice - f ilter settings an d slice mo de n eed to b e selec t ed. slice threshold 2 . 3. y e s indi c a t e s t h at cdr i s alw a y s u 4. man c he ster en coded da ta require s 5 . 0x 55 the fo llow i ng is sugge ste d : i t i s s ugge s t ed t h a t cdr w i t h f a st pha se alignmen t be e n a b led it i s sugge sted tha t the preamble be lo ng enoug h to trigg e r a c tiv i ty check 0x 0a the follow i ng is sugge ste d : i t i s s ugge s t ed t h a t cdr w i t h f a st pha se alignmen t be e n a b led 6. na i ndicate s t h a 7. opt indi c a tes that cdr i s an opt io n t o de t e c t t h e da t a how e v er, it i s rec o mmended that cdr be u s ed . (see table 41 andtable 42 f o r cdr paramet ers ) a sets the data s lice lev e l for a m receptio n. t h is thresh old is used w h en the slice metho d sets in the am data filter and sl i c e optio ns is set to dac. 52 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 37: slice threshold - 0x1 d [29] bit name com m en t 7:0 sl_thresh [ 7 : 0 ] am slice threshold in dac mode = sl_thresh*7 . 8125mv am data filter a nd slice options t h is register contai ns setting s for determini ng the meth od of slicin g for am receive mo d e . a m _ f ilter: sets the post- detectio n filter ban d w i d th for rssi duri ng a m receive. t hese filter b a n d w i d ths ar e set for the corresp ond in g data rates. t h ese filter settin g s can als o be used w i t h custom data rates. a m _hyst: sets the amou nt of h y steres is i n the am slice compar ator. am _ s l i c e : used to se lect the method fo r provid ing a r e ferenc e to th e am slice co mparator. da c mode: t h is is a fixed thresho l d lev e l progr ammed i n to the slice thre shol d register. av e r ag e mo d e : t h is is an automatic t h re shol d lev e l w h ere the amis -530 00 s e ts the thresho l d leve l to the aver ag e lev e l of the rssi sign a l . an ex ter n a l capac itor is re quir ed o n the peak pin to s e t a ban d w i d th for the lo w p a ss filter respo n se of the avera g in g circu i t. due to the potenti a l fo r lo ng strings of 1? s or 0?s in nrz data this threshol d method is not recommen ded f o r use w i th n r z data. peak mo d e : t h is is similar to the aver ag e mode, b u t on l y the hi ghest l e vel is determ i ned from th e i n comi ng si gn al and th e amis-5300 0 s e ts the thres h o l d to a lev e l 6d b lo w e r tha n th e pe ak va lue. an e x tern al c a pacitor on th e peak pin dete rmines a ble ed off (disch arge) rate for the pe ak detect o r circuit. table 38: am d a ta filter and slice options - 0x1 e [30] bit name state com m en t [7:5] am_filter[ 2:0] 000 001 010 011 100 101 110 111 rssi filter band w i dth =30 0 hz rssi filter band w i dth = 60 0hz rssi filter band w i dth = 1. 2khz rssi filter band w i dth = 2. 4khz rssi filter band w i dth = 4. 8khz rssi filter band w i dth = 9. 6khz rssi filter band w i dth = 19 .2khz rssi filter band w i dth = 38 .4khz 4 nu [ 3 : 2 ] a m _ s l i c e [ 1 : 0 ] 00 01 10 11 dac mode: slice threshold set in r egister 1bh average mode: am threshold set using averaging filter peak detect mod e : am thre shold set using peak detector dac mode: slice threshold set in register 1bh [1:0] am_h y s t[1:0] 00 01 10 11 0mv slice hy ster esis 25mv slice hy ste r esis 50mv slice hy ste r esis 100mv slice hy st eresis fm ff t t he AMIS-53000 rece iver us es a f f t function to recov e r data from a f m /f sk modula t ed sign al w h e n the data rat e is hig her tha n 20kb p s. t he f f t detector us es a t w o- bit d f ft to demod ulate th e i n co ming if sig n a l . t h is circuit al so uses the s a me clock r e co ve r y block (cd r ) as the am detector (see sectio n 6.1.4) to dete c t the data. a pattern of 1?s and 0?s is re q u ire d as a pr ea mble. a sof i s not re quir ed unl ess manc he ster enco d e d d a ta is used, r e quiri ng a un iq ue pream ble to bit - alig n the man c hester dec od er to the recov e red d a ta. setup reg i sters descripti ons: data rate - c a n be s pecifi ed i n the d i screte data rate r e g i ster, or spec ified as a 1 6 -bit w o rd for a us er d e fine d d a ta rat e . (see section 7.1. 3) peak d e v i atio n - t he peak de viatio n regist er stores the val u e to be use d fo r both transmit and rec e iv e. in the f f t f m receiv e mode, this value is used to set - up the fft bins. (see sections 6. 4.1.5 and 6.4.1.6) 53 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet fm pll de te c t or loo p fi lte r - f o r the discr ete data r a tes, the val ues for t he l oop fi lter c oefficie n ts are pre-pr ogramm ed. f o r user defi n e d d a ta rates, this valu e ne eds to be calc ulat ed. pll detector l o op filter setting a program (am i s-53cal c.e x e avai lab l e fro m amis) has been cre a ted to aid i n the des ig n of loop filt er settings. table 39: pll d e tector loop filter setting - 0x2b [43] bit name com m en t 7:0 pll_co [ 7 :0] pll loop filter setting fm pll (l o w data ra te fsk ) t he AMIS-53000 uses a pl l function to rec o ver the data fr om a f m /f sk modu lated si gn al w i th dat a rates 20kb p s or lo w e r. t h is ci rcuit uses an a d p l l for demo dul a t ion, the out put of w h ich is fe d to the am cd r circuit to rec o ver the cl ock, and a d d i tion al l y filter the outp u t data. t he preamble sent by t he am is-53000 w hen confi gured as nrz fm is a r epeat ing sequence of 1?s and 0?s. t h is giv e s the cdr cir c u it and pl l dem odu lator suffici ent edg es to acqu ire lock. hence, for the nrz case it is unnec essa r y to incl ud e a sof by t e . i n manch e ster m ode, the pre a m b le is spec ifie d as al l 1?s ( o r 0 ? s). t h is gives t he cl ock recov e r y c i rcuit th e most edg es for lock ac quis i tio n . ho w e v e r, due t o the ambi gu ity of the pre a m b le, a sof b y t e is necess a r y for t he manch e s ter decod in g block. t he suggeste d sof fo r this is eith er # 55h or #aah. t he length of preamb l e nec essar y for this mode is de pe nda nt up on th e loo p b and w i dth for the cl o c k recover y pll. setup reg i sters descripti ons: data rate - c a n be s pecifi ed i n the d i screte data rate r e g i ster, or spec ified as a 1 6 -bit w o rd for a us er d e fine d d a ta rat e . (see section 7.1. 3) peak d e v i atio n - t he peak de viatio n regist er stores the val u e to be use d fo r both transmit and rec e iv e. in the f f t f m receiv e mode, this value is used to set - up the fft bi ns. (see sections 6.4.1.5 and 6.4.1.6) m pll de te c t or loop fil t e r - f o r the discr ete data rates, the val ues for the lo op filt er coefficie n ts are prepr ogramm ed. f o r user defi n e d d a ta rates, this valu e ne eds to be calc ulat ed. (see pll d e te ctor loop f ilter setting) 6. 5. 1. 5. clock and data r ecovery t he AMIS-53000 dev ice performs clock and dat a rec o ver y for both am /ook/ask an d fm/fsk si gnals. an inter nal clock in th e amis-5300 0 is progr ammed to be near l y the sam e rate as the e x p e c t ed dat a rate in the inc o min g sig nal. t h i s clock is th e n s y nc hro n ize d t o the i n comi ng data rate b y e x tractin g a c l oc k fr om the dat a . t h is loo p rec o ver y meth od r e covers data w i t h o u t mu ch of the jitter and n o ise ass o ciate d w i t h w i r e less communic a tio n links. before l a u n chi ng h e a d lo ng in to the o per atio n of the detect o rs, and ho w t o set them up, it is i n structive to revi e w th e follo w i n g r e late d registers, setu p optio ns an d their functi ons. setup reg i sters descripti ons: f ast ph as e a l ig n m en t: in both the am an d pll b a sed f m modes (lo w er dat a rate), t he amis-5 300 0 can be co nfi gure d to quickl y acq u ire phas e l o ck o n inc o min g d a t a. t he patter n nec essar y f o r the fast p h a se a lig nme n t is simpl y ?1 01 0?. t h is function c an b e en abl ed i n th e cdr o p tio n s a register. w i th this functio n ena ble d , the cdr circu i t w i l l operat e w i th minimum po w e r consum ption u n til the ? 101 0? seq u e n c e is receive d . a 32-bit correl a tion is use d to not onl y reco gniz e the 101 0 pattern, but a l so to ins t antane ous l y p r ovid e a p has e corr ection to the c l oc k rec o ver y c i rcuit allo w i ng ver y f a st (less than 4 bit) lock times locki ng the inc o min g da ta. a c ti v i t y ch ec k: t h is functi o n ca n b e use d in c onj uncti on w i t h th e fast p hase al ig nmen t to reset th e c l ock a nd data r e cover y b l o ck b a ck in to i t s mi n i mal p o w e r co n s u m p t io n mod e w hen n o tra n s i t i o n s a r e de te cte d on th e da ta l i n e fo r a sp e c i f ie d p e r io d . t he check can be confi gur ed for 4, 8 or 16 bit times. 54 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet o v e r -sa m p ling clo ck (t s cl o ck): al l thre e detectors use the t s clock as the s a mpl i ng c l ock for th e tra n sitio n from an alo g to digit a l. t h is cl ock sho u l d b e set to the hig hest rate possi ble, b u t not gr eater th an 400 x th e d a ta rate , to ensur e a d equ ate phas e informat i on. f o r the di screte data rat e s, th is value i s pre-pro g ram m ed for those r a tes. data rate cla m p: t he data rate c l amp restricts the cl o ck recover y c i r c uit from w a n deri ng w h e n a n actu al si gn al is n o t prese n t, and th e ph ase error s i gn als bei ng ge nerate d com e onl y from no is e. smal l fracti ona l va lues for the cl amp c a n lea d to lon ger lock tim e s since the cl ock recover y p ll ma y not b e abl e to make a s large of a cor r ection as is n e c essar y al l at once. cha nne l cla m p: t h is clampi ng circ uit is us ed to h o l d the l o w d a ta rate f sk pll d e tect or w i thi n the s p ecifie d lim its to preve n t the pll from w and erin g in the absenc e of sig nal. cdr opera t io n t h is circuit utilizes an all d i git a l pll (adpl l ) to recover the cl ock from the ra w sl ice d d a ta. t he slicer output is integ r ate d over a bi t time to provid e a phase error, and the si gn of the integrati o n is used to dete rmine the d a ta s y mb ol. w hen usi ng th e amis-530 00 in am mod e w i t h an y of the packet fram in g opti ons e nab led, it is n e ces s ar y to have t he sof b y te f o r prop er start-up of the am cd r circuit. it is recommend ed t hat the cdr is set up w i t h the acti vit y c h e ck, and fast phase ali g n m ent features e n a b l ed for th e p a c k et framing m o des. t he prea mble th at the amis-5300 0 w ill tra n smit in a m mode is cw , hence the s o f b y t e is used b y the fast phase alig nment f eat ure in the c d r to acquire l o ck . t he s uggested sof for am nrz format is #55 h. t h i s w i ll provi de the m o st transitions f o r the cl ock re cover y circu i t to acq u ire lock prior to th e inc o min g pack e t. f o r manch e ster op era tion, the sugg ested so f is #0a. t h is w i ll pr ovid e ear l y trans itio ns for phase l o ck, and 4 bits to al ig n the manch e s t er decod e. becaus e there are no transiti ons duri ng t he pream ble i n am mode, the cdr reli es on th e fast phase al ignm ent for acquiri ng l o ck. a s this is the case , the le ngth of the pre a mbl e c an b e q u ite s h ort as lo ng as the activ i t y c h e ck is en abl ed. t he preamb l e shou ld be l o n g eno ug h to trip the activit y d e tection circ uit r y suc h that the fa st phase a lignm ent circu i t is rese t at the beg in nin g of the sof . t h is guar ante e s tha t the fast p has e a lig nment w i l l kick in dur ing the sof . t he sugg ested le n g th for th e pre a mbl e is 4 bt ?s for ma nc hest e r w i t h activit y ch eck set to 4 b t ?s, and 10 or 20 for nrz , w i t h acti v i t y chec k set to 8 or 1 6 res pective l y . note in the n r z case , ena bl in g activit y c heck w i ll r equ ire th e data b e forma tted to guar ant ee at l east on e transitio n in th e dat a duri ng t he l ength of ac tivit y check (i.e. ever y 8 or 16 b t ?s). setup reg i sters descripti ons: id d w el l - set a time that the cdr circu i t w i ll continu e to se arch for the chi p id. cdr config - set the param eters for the clock and d a ta r e cover y circ uit s . data rate - ca n be s pecifi ed i n the d i screte data rate r e g i ster, or spec ified as a 1 6 -bit w o rd for a us er d e fine d d a ta rat e . (see section 7.1. 3) sta r t of fra m e - by te used to tell the AMIS-53000 receiver that data w i ll start. (see section 7.1.6) cloc k re c o v e ry loop filte r - f o r the discrete data rates, the valu es for the lo o p filter c oefficie n ts are pre-pr ogramm ed. f o r user defi n e d d a ta rates, this valu e ne eds to be calc ulat ed. chip id dw ell t i mer used to s pecif y h o w l o n g the clock a nd d a ta recover y circ ui t w i ll sta y activ e after en erg y has b e e n dete c ted, look in g fo r a val id c h i p id . t he part w i l l lo ok for either th e chip id or the glob al id. table 40: chip i d d w ell timer - 0x14 [20] bit name com m en t 7:0 c_dwell [7:0] 00h: code d w ell timer disabled (f or standard receive w a ke on cod e ) 01h ? f f h: cod e d w ell time = c_dwell*bit time * 8 55 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet cdr options a t h is register contai ns setting s for determini ng the clock an d data recov e r y p a rameters. dr_c l amp: li mits the cdr frequ enc y drift bet w e en d a ta packets. cha nne l_c l am p: restricts the ban d w i d th to the chan ne l ba nd w i dth. activit y ch eck: sets a numbe r of bit times that the cdr circ uit w i ll sh ut do w n if there is n o data pres ent. fast phase ali gnme n t: forces the cdr circ uit to quickl y s y nchro n ize to th e incom i ng d a t a . f m mode: t he f m detector used in the rec e i v er dep en ds o n the data rate of the incomi ng signa l. table 41: c dr optionsa - 0x1 f [31] bit name state com m en t 1/64 1/32 1/16 7,6 dr clamp<1> 11 10 01 00 1/8 the clamp restricts the clock reco ver y pll to + - th e fraction selected of the freq uenc y selected by the b audclk w h ich pr events clock w a ndering b e t w e en data packets 11 +-150 10 +-100 01 +-50 5,4 channel clamp 00 +-16 the clamp restricts the pll detect o r to onl y lock on signals that are w i thin the specified w i ndo w , cent ered +-50 0khz of the if fr equenc y 3,2 activity check <1> 11 10 01 00 reset after 16 bit times of no activity reset after 8 bit times of no activit y reset after 4 bit times of no activit y activity check dis abled, clock r e co very w ill alw a y s run 1 the cd r circuit w ill perform fast phase alignment 1 fpa enable 0 cdr al w a y s run n ing 1 p l l 0 f m m o d e 0 f f t cdr options b t he sample cl ock valu es are w r itten from r o m w i th the d i screte dat a rat e selecte d . t he samp le rate shoul d be as fast as possib le w i t h o u t exc e e d i ng 4 00 sam p le s per bit time. table 42: c dr optionsb - 0x20 [32] bit name state com m en t 1 cdr is held rese t 7 cdr reset 0 6 nu 5 n u 4 nu 3:0 sample clock 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 45khz 90khz 187.5khz 375khz 750khz 1.5m 3m 6m 8m 12m 16m 24m 56 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet clock recover y loop filter settin g a program (am i s-53cal c.e x e avai lab l e fro m amis) has been cre a ted to aid i n the des ig n of the cdr l oop filter settin g s. table 43: clock recover y lo op f ilter setting - 0x2 c [44] bit name com m en t 7:0 cdr_c o [7:0] clock r e covery filter setting 6.6 t r an smitter f i gure 39: typica l output p o wer vs. p o wer r e g i s t e r s e t t i n g * * n ? . t a o t e : curv e is fo r outpu t ma tched to 50 b l e 4 4 : t r ans m i t c o m m a n d regist er num b er (hex ) name code func tio n 0 x 0 0 c o m m a n d 0x02 instruction to place the amis-530 00 into transmit (rememb er that a ll parameters for transmit must be set before issuing this command) h e a m i p o w e r pa can be b y p a ssed t o l l o w a h /ook/ask d a ta modulati on . a r e c t m o on . t he pll lo o p runs at h a lf o f the desir ed tr ansmit fr eq uen c y p r o v i d n i n the pll. ? o ? f ? b ? f ? h setup reg i sters descripti ons: t s - 5 3 0 0 0 u s e s a s w it chin g class e po w e r amplifi e r as the high p o w e r out put dri v er. t h e h i g h i g h e f f i c i e n c y at a low e r output pow er. t he output drivers are t u rned on a nd off directly in a m a d i d u l a ti on pl l is us ed to form the f m /f sk signal f o r trans missi e e x ce llent o n /off ratio for am, and to lo w e r current consumpti o t o o k m o d u l a t i on (am) sk modulati o n (f m) u r s t m o d e t r a n smit m w a ve sh ap i ng i g h po w e r an d lo w p o w e r ra nge 57 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet data rate - ca n be s pecifi ed i n the d i screte data rate r e g i ster, or spec ified as a 1 6 -bit w o rd for a us er d e fine d d a ta rat e . (see t e r m u s t be confi gur ed. (see section 6 . 4.1) m deviation must be s e t for f m operat ion. (see se ction 6. 4.1.5 a nd 6.4.1.6) preamble - set a reason ab le l ength of pr eam ble to ins u re th at the receiver can detect the sign al. 6.6.1. t x e n e r a l opti o n s for transmit. sha p ing: w hen en abl ed, th e f sk transitio ns are di gital l y shape d in the fractional n p ll w i th a pr e-p r ogramme d se que nce. ng is gaussia n w i th a bt = 1 . t h is reduces th e high fre q u enc y co ntent of the d a ta w a v e form that lates the c a h i s o n s p bit in ge nera l optio ns a is en abl ed . d t o n s m i t t x : w n t h i s o t i on is en abl ed i n conj unctio n w i t h use id an d lop enab le, the packet for transmission i s load e d r n a l r a m r i o r t o the rf being e n a b le d. h a l: w i t i s s e t to 1, bits[7:4] of status 2 can be w r itten to f o rce the trans mitter to opera t e on a s p e c i f i c m i c s c h nel. an n e l a se ssm en t: w hen one of the cca mo des of operatio n ar e ena ble d , the amis- 5300 0 w i ll en abl e its receive r e c k f o r p r e s e n t e 4 5 i g - 0 x 0 f ] section 7.1. 3) rf fre que nc y - t he rf frequenc y o f t h e t r a n s m i t outp ut po w e r - sets the rf output leve l for the amis-530 0 0 . peak d e v i atio n - t h e f tx confi g - options for the transmitter must be set. config g am _ f m _ t x : used to set the mode for trans mit. t he filter for the sh api modu r r i e r . id for tx: t e o p t i e c i f i e s w h ic h id the amis-5300 0 w i ll transm i t w h e n t h e use id o a l l d e v i c es, chip id w i ll transmit the transmitters chip id. globa l i s u s t r a b u f f e r e d t i n t o i n t e h e p p forc e m i c s c nne h e n t h i s b a n clear ch s t o f i r s t c h t h e c e of energ y o n th e specifi ed ch a nne l befor e transmitting. a b l : t x co n f [ 1 5 bit name state com m en t 7,6 clear chan nel assessment 01 00 a s s e s s m e n t ( p r e - d e f i n e d chan nels) single clear channel assessment prior to tr ansmit ( a n y fr equenc y) no clear channel assessment performed, no rmal o peration 1 1 1 0 not allowed m i c s m u l t i - c h a n n e l 1 5 forc e mics channel 0 1 enable smooth p o wer up of pa (r educes t he spurious response of t he tx on po w e r up ) 4 smooth tu rn on 0 3 nu 1 use the defined chip id from the chip id register 2 id for tx 0 use the defined global id from th e chip id register 1 gaussian fm dat a shaping enable d 1 shaping 0 fm data shaping disabled 1 am transmit mod e 0 am_fm_tx 0 fm transmit mod e 58 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6.6.2. output pow e r c_power: coarse o u tput p o w e r co ntrol fo r the po w e r am plifier. w hen s e t high, the ma x o u t is 15dbm - w h e n set lo w , the max output is 0dbm. f_ power: f i ne out put p o w e r co ntrol f o r the pa. t hese 7 bits c ontrol th e volt age on the r f pw r pin via an inter nal dac.f_power is sent to the dac as t he up per 6 bits. lo w e r 2 bits are 0. table 46: outpu t power - 0x18 [ 24] bit name com m en t 7 c_power coarse outpu t po w e r selection sent to pa 6:0 f _ p o we r [6 : 0 ] fine output po we r control (up per 7 bits of the dac, lsb of dac=0) 6.6.3. prea mb le le ng th t h is by t e is us ed to defi ne th e len g th of pre a mbl e to send prior to data i n both transmit a nd burst mode transmit. table 47: pre a m b le length - 0x1 a [26] bit name com m en t 7 preamblelen [7: 0 ] length, in bit times, of cw (am), or ? 10 (fm ) sent prior to p r eamble in burst table 48: sugg e s ted preambles modul atio n preamble com m en t am nrz w i th cd r cw sof required a n d suggested as 0 x 55 1 am manchester w i th c dr cw sof required a n d suggested as 0 x 0a 2 fm ff t 1/0 pattern no sof is requir ed fm pll (nrz ) 1/0 pattern no sof is requir ed fm pll (ma n chester) all 1s or 0s sof is require d and suggested to be 55(h e x) or a a (hex) 3 not e s: 1. w hen using so f w i th nrz data , i t is sugge sted tha t fa st pha se alignmen t is e nabled , a c tiv i ty che c k i s se t to 8 or 16 and pr eamble le ngth is 10 or 20 b i t times. 2. w hen u s ing so f w i th manchester coded da ta, i t is su ggested tha t fa st p hase alignmen t is enabled, a c tiv i ty check i s se t to 4 bit times and preamble length is se t long enough to tri gger th e activ i ty check. 3. the length o f thi s p r eamble is depe ndent on th e loop b andw idth of the r e cov e r y clock pl l. 6.6.4. f m t r ansmit d a ta shap in g t he amis-530 00 a llo w s the user to ena bl e data s h a p in g of the d a ta w a veform to impr ove th e rf sp ectral effici enc y. w h e n e n a b l ed , the cl ock rec o v e r y nco is us ed to pr ovid e an intern al clo ck at 1 6 tim e s the selected data rate. t h is clock is used to cy cle th ro ug h a pre-d e fine d pat tern w h e nev er a transitio n is d e tected o n the t x input. t he shap ing p a tter n is gaussia n w i t h a bt = 1 . t he inter me d i ate valu es for the shap ing ar e det ermine d from the pe ak dev iati on re g i ster w h en an e x ter n a l host/control l er w r it es the ?ro m 2 regs? to t h e amis-5300 0 comman d regist er. 59 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6.7 idle table 49: idle c o mmand regist er num b er (hex ) name code func tio n 0x03 enable the idle state 0 x 0 0 c o m m a n d 0x04 return to idle sta t e table 50: idle c onfiguration regist er num b er (hex ) name bits func tio n 0x02 status/flag2 0 AMIS-53000 is b u sy 2:1 select state that AMIS-53000 en t e rs on por 0x0c gene ral options a 0 output s y ste m clock in standby m ode 0x0d gene ral options b 1, 0 select the sy ste m clock frequency note that there are t w o l o w - p o w e r mod e s fo r AMIS-53000 ? standb y a nd idle. stand b y allo w s th e sys clk outp u t. id le is the ver y lo w po w e r state w i t hout syscl k output. table 51: idle m odes idle tas ks descrip tion sniff receiver periodic w a ke up a nd r f energ y de tection check burst transmit periodic w a ke an d transmit function housekeeping used to perfo rm periodic te mpera t ure corr ection, calibration or to wake exter nal host/controller standb y lo w - po wer mo de w i th no activity ma y be p r og ram m ed to continue t o output s y stem clock t he amis-530 00 all o w s for a lo w - p o w e r mo d e . po w e r req u i r ements are re duce d w h e n th e ver y lo w p o w e r 1 0 khz osci ll ator is the clo ck for the device. t h is oscillat o r runs the timer s for either the sniff w a k e up time r, the burst transmit timer or the hous ekee pi n g w a k e up timer. ho w e v e r, even w h en the l o w p o w e r 10khz osci llat o r is ru nn ing, t he amis-53 0 0 0 can still prov ide a cl ock sig nal outp u t to an ext e rna l host/control l er dev ic e such as a microproc esso r after re ceptio n of a valid d a ta packet or a hous eke epi n g c y cl e w h ere t he amis-5300 0 h a s bee n pro g ra mmed to issue a w a ke u p to the e x terna l host / controll er. t he AMIS-53000 w i ll r e turn t o this l o w p o w e r idl e state after acti viti es su ch as transm i t, receiv e or the vario u s timers are d o ne an d th e ext e rna l host/control l er w r ites the ?retur n to idle ? i n structio n to the AMIS-53000 comm and register. setup reg i sters descripti ons: idle conf ig - t he opti ons for i d le mo de must be set. 6.7.1. idle co nfig t he idle confi g uratio n register is used to spe c if y w h ich p e ri odic tasks are performe d onc e the idl e com m and is g i ven i n registe r 0. any combination of sniff, burst and hous ekeeping c an be enabled. int to dssn t i ming: t h is is the time bet w e en the amis-5 300 0 issui ng a n inte rru pt to in dicate that d a ta is read y a nd the time that data transf e r starts w i th th e assertio n of the dssn si gn al. idle to sy stem clock stop: once the amis-530 00 h a s co mplete d a task and is iss u e d the id le comma nd, the s y stem clock can produc e additiona l clock c y cles to allo w the ex ternal host/controller to finish its tasks. 60 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 52: idle c onfig - 0x10 [16] bit name state com m en t dssn going active is delay ed 8 b i t times from int 7:5 wait timing between int and dssn f o r sniff receive 111 ? 000 dssn is immediatel y active after int 11 s y stem clock outputs 1024 clock cy cles befor e shutdo w n afte r idle command 10 s y stem clock outputs 512 clock cycles before shutdown after idle co mmand 01 s y stem clock outputs 256 clock cycles before shutdown after idle co mmand 4,3 wait timing between idle instr u ction a nd sy stem clock shutoff time 00 s y stem clock im mediatel y shuts do w n afte r idle command 1 periodic housekeeping enabled ( h k settings must be set) 2 housekeeping enable 0 1 periodic burst mode enabled (b u r st settings must be set) 1 burst enable 0 1 periodic sniff mode enabled (sniff settings must be set) 0 s n i f f e n a b l e 0 6.7.2. sniff mode op eratio n table 53: sniff mode configu r ation regist er num b er (hex ) name bits func tio n 1 force the receiver to not o u tput clk&data < ener g y level 0 x 0 e r x c o n f i g 0 set the receiver t o wake w hen at energ y level thre shold 0x10 idle config 2 enable periodic sniff mode t he quick star t techno log y e nab les th e am is-5300 0 to o perate its re c e iver i n a mod e cal l e d sn iff mode. as impl emente d i n th e amis-5300 0, this sniff mode can w a k e the receiv er and ac quir e the trans mitted messag e in as little as 130 micr oseco nds. figure 40: sniff w a veform 61 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet t he sniff mode of operati on puts t he amis-530 00 rece iver into a c y cl ic mode of sle epi n g and p e rio d ic all y w a k i n g to check for re ceived sign al en erg y . w hen e nerg y is d e tected the rece iver is pla c ed in rece ive mode a nd th e amis-5300 0 attempts to r e co ver d a ta. t h e receiv er in snif f mode can be configur ed to check for a val i d id . t he failure to receiv e a valid id w i ll cause the rec e i v er to go back to slee p. t he AMIS-53000 rece iver av erag e sup p l y c u rrent can b e e s timated as: w here, is recei v er current con s umptio n in co ntinu ous rec e iv e mode, eq u a l to or less than 12ma; is receiv er current consum ptio n in sle ep mo d e , equa l to or l e ss than 2 u a; is progr ammab l e rece iver en e r g y sca n imp u l s e on time (snif f time), appro x i m atel y eq ual to 130 s minimum; is progr ammab l e r e c e iver off time peri od le ng th bet w e e n rec e iver e nerg y sc an imp u lses (s niff mode inter v al). s e t u p r e code d w e l l ti me - once rf ener g y has b e en det ected th e receiv er can determi ne if th e messag e ha s the uni qu e id for that thre s hold - t h e num ber of ti mes a w a ke u p is r e ceiv ed can b e mo nito red for fa lse w a ke ups an d the e ner g y th resho l d adj usted to acc ount for the no i s e leve l. he sniff config register is us ed to set add iti ona l opti ons fo r the operati on of the part duri ng a sniff c y c l e , be yond th ose se t in the rx config re sniff_ fil t e r : setting for t he e nerg y dete c tion filter. t h is allo w s for diff erent settin g s of the am data filter bet w e en sniff and a u to-thre s hold count va lu e : num ber of sniff c y c l es us ed to determi n e w h ether to r a ise or l o w e r t he e ner g y thre shol d for mu l t i ch an n e l: t h is bit is u s ed in mics mode of op era t ion to ena ble the amis-5300 0 to scan t he nin e pre-d e fin e d mics sniff interv al resolution: determines the clock for t he sniff interval timer. g i sters descripti ons: sniff config -this sets the opt ions i n the snif f mode. sniff interv al - set the time interval b e t w ee n receiv er w a ke u p s in the sniff mode. ene r g y thre s hold - t he threshol d for detec ting the inc o mi ng rf ener g y must be set (see sectio n 6.5. 1.2). energ y d w e ll time - set the time interv al tha t the receiver w ill rema in activ e look ing for r f energ y det ec tion. receiv er. t he time interv al for looki ng for th is id must be set. (see chip id dw ell t i mer) 6.7.2.1. sniff config t gister. receiv e. t he energ y d w e l l timer nee ds to be ext end ed l ong eno ug h to allo w for this filter t o settle duri ng the sniff c y cl e. sniff. any value other than 0x00 in this regi st er w i ll enable t he aut o-threshold function. chan nels progr ammed i n to the amis-5300 0. 62 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 54: sniff config - 0x11 [ 1 7] bit name state com m en t 7:5 sniff_ filte r 000 001 010 011 100 101 110 111 rssi filter band w i dth =30 0 hz rssi filter band w i dth = 60 0hz rssi filter band w i dth = 1. 2khz rssi filter band w i dth = 2. 4khz rssi filter band w i dth = 4. 8khz rssi filter band w i dth = 9. 6khz rssi filter band w i dth = 19 .2khz rssi filter band w i dth = 38 .4khz 11 100 10 500 01 100 4,3 auto-th r eshold count value 00 disable this is the number of sniff c y cles to count false wa ke ups due to the noise level, so th at the threshold l e vel can be adjusted. it is adjusted higher w h en the nu mbe r of false w a ke u p s exceeds the w a ke u p targ et n u mber. it is adju s ted do w n w h e n there ar e fe w e r false w a ke ups t han the tar get nu mber. ente ring a number oth e r than 00 in this re gister w ill enable the auto-th reshol d. 2 n u 1 nu 1 sniff interval timer resolution is 100m s (interval bet w e en sniff signal detection events is (sniff in terval) times (sniff resolution) 0 sniff interval resolution 0 sniff interval timer resolution is 500us 100ms (inter val betw e e n sniff signal detection events is (sniff interv al) times (sniff resolution) 6.7.2.2. sniff interval time r used to spec ify the p e rio d (time bet w e en s n i ff events) of the sniff op erati on. t he sn iff interval is this value times the snif f interval resol u tion va lu e (set in the sn iff config regist er). table 55: sniff i n terval timer - 0 x 12 [18] bit name com m en t 7:0 sniff_i n t [7:0 ] sniff interval timer =sniff _int* s n iff interval timer resolution 6. 7. 2. 3. e n ergy dwell timer len gth of time receiv er w i ll sta y o n in a snif f cy c l e check i n g for the prese n ce of a signa l . also used for a receive co mmand w h en the w a ke on en erg y bit is asserte d in r x co nfig. w hen used for a mi cs mark e t device, th is m a y ne ed to be set to 10 m ill i-s e con d s f or c c a to be compati b l e w i t h the mic s standard. table 56: ene r g y d w ell timer - 0 x 13 [19] bit name com m en t 7:0 e_dwell[7:0] 00h: energ y d w ell timer not used, energ y dete r mined b y an impulse sample 01h ? feh: en er g y d w ell time = e_dwell * 100us ffh: r e ceiver re mains on until energ y t h reshold is met 6. 7. 2. 4. e n ergy threshold sets the thresh old for eith er w a ke on e ner g y or sniff mode sign al acq u isiti on. if the auto m atic nois e flo o r detectio n is ena bl e d in sn iff, the amis-530 0 0 w i ll ov er w r it e the contents o f this r egister e a ch time a ne w threshol d is ca lculat ed. 63 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet a u t o ma tic t h re shol d o p ti miz a t i on in s n if f mo d e an optio n ava i l abl e in the s n i ff mode config register w i ll e nab le the ami s -530 00 to a u tomatica ll y ad ju st the energ y t h resh old o f the amis-5300 0 to optimiz e the s ensitivit y of the sniff mod e . t he targ et n u m ber of w a ke up s (register 0 x 2 f ) allo w s the u s er to sp e cif y a valu e for the number of false w a ke u p s the amis-5300 0 is allo w e d w i t h the sel e cted co nf igur ation of the sniff mode (b y b i ts [4: 3 ] i n the snif f _ conf ig register) nu mber of sniff cycl es. as a n ex a m pl e: if the number o f sniff cy cl es is set to 500 (sni ff config [bit 4:3]), if the target number of false w a ke ups is set to 50 (target n u m ber w a k e ups ), t hen over the course of the n e xt 5 00 sniff cy cl es the rad i o is trigger ed fals el y b y en erg y : more than 5 0 ti mes, the threshol d w i l l be inc r ease d to redu ce the sensitiv i t y , less than 50 ti mes, the threshol d w i l l be d e c rease d to incr ease the s ensit ivit y . using this opti on to s e t the t h resh old for e nerg y detecti o n can h a ve a dramatic impa ct on the life o f batter y p o w e r ed d e vic e s, a s the amis-5300 0 w ill a d just to c h ang ing lev e ls of backgr oun d nois e w h ile sti l l mainta in ing maximum se ns itivit y , a nd not w a stin g po w e r by contin ual l y w a k i ng a nd pr oces sing b a ckgro un d nois e . additi ona ll y, th e e nerg y thres hol d setti ng c a n b e m onitor e d b y a n e x t e rn al host/contro ll er. t he am ou nt the thresh ol d w i ll incr eas e or decre ase is b a s ed on t able 5 7 , w i t h the ord e r of the ro w s i n the same or d e r as the amis-530 00 w i ll ev a l uate the c ond itions. table 57: auto t h reshold adjust con d iti on ad j u s t m e n t select the numb e r of sniff c y cles as the test period enter the desired number of f a lse w a ke u p s per period note: a false w a k e up is w h e n the receiver det ects energ y but fails to detect the id in the packet then if w a ke ups /period > targ et threshold is increased then if w a ke ups /period < targ et threshold is decr eased t he threshol d of the amis-53 000 c an v a r y o v er a w i d e ra n ge from one de vice to th e n e x t, due to des ig n , manufactur i n g toler anc es , and envir onme n t chan ges; temp erature a nd v o ltag e. t h is automatic thre shol d optimiz a t ion can b e u s ed to adj ust the thresho l d b y monitori ng th e level of false wake u p s du e to backgr oun d n o ise. t he adj u s tment in this f a shi on ca n re d u ce the effects of desi g n a nd manufactur i ng on the thres hol d setting of the AMIS-53000. setup reg i sters descripti ons: ta rge t - set a valu e for the all o w e d numb e r of false w a ke u p s desir ed. target thr e shold t he number o f false w a ke u p s occurri ng d u rin g a per iod of time is used to autom ati c all y a d just th e ener g y thres hol d in the s n if f oper ation. t h is al lo w s the amis-5300 0 t o aut omatica l l y adj ust its i n put lev e l t o c o mpe n sate for , manufactur i n g , comp one nts, envir onme n t, temper ature, an d/or voltag e. table 58: t a rget wake ups - 0x2 f [47] bit name com m en t 7:0 target [ 7 :0] t he number of wake- ups that the sniff cir c ui t w ill tr y to adjust the threshold to not hav e more false w a ke ups or less missed signal detec tions. this register allow s the num ber to be 0 to 255, b u t t h is number should alw a ys be less than the numb e r of sniff count (sn i ff config bit 4:3). 64 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6.7.3. burst t r ansmit data table 59: burst transmission configuration regist er num b er (hex ) name bits func tio n 0x10 idle config 1 enable burst tra n smissions burst mode of transmissio n is a functio n t hat can ca use th e amis-5300 0 to transmit a m e ssag e at a pr ogramm ed tim e interv al or b y assertin g the xburst pin to active (the am is-530 00 must be in the xbu r st mode), ca us in g the amis-530 00 to im medi atel y trans mi t a messa ge. t he burst mod e can als o b e started b y en a b lin g th e bu rst mode in th e i d le r egist er an d then w r iti ng to the comm a n d register to set t he amis-53 0 0 0 into i d l e mod e . t he xb urs t modes sets a timed a u tom a tic transmissi on of reg i ster v a lu es (a mess a ge) or adc conv er sion va lues. setup reg i sters descripti ons: burst config - set the burst tr ansmission parameters. burst inter v al - set the time interval bet w e e n burst transmissions. use r data a - message for timer initiat ed transmissions. use r data b - message for xburst initiated transmissions. figure 41: data packet format show ing order for burst tx content 65 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet used to set the options for the burst mode of oper ation: r_bu rst: t hese b i ts set th e numb e r of tim e s the pack e t i s to be re p eate d eac h b u rst in terval. t h is ca n be us ed to in creas e the prob ab ilit y that all p a ckets w i ll g e t throug h w h en sev e ral burst transmitters are loc a ted in the same ar ea. se nd chi p id : t h is option is inclu d e d to allo w for the o perati ng case of havin g multi p le transmitter s sendi ng to a singl e receiv er. t he multipl e tra n s m itters w i l l nee d to be co nfigu r ed to se nd t h e g l ob al chi p i d i n the t x co nfig opti ons s o that th e receiv er w i ll w a ke on e a ch transmitters pac ket. sending t he chi p id as part of the pa yl oad a llo w s th e receiv er to differenti a t e the packets. send internal a dc data: w hen en ab led, t he amis-5 300 0 w i ll perform conv ers i ons on the batter y vo l t age, a nd t e mp eratu r e sensor a nd i n cl ude thes e conv ersio n s as part of the packet pa yl oad. send external a d c data: w hen e nab le d , the amis-53 000 w i ll perfor m c onversi ons on the t w o e x ternal ad c in p u ts and inclu de th ese c onvers i ons as part of the pac ket pa ylo ad. burst inter v al resolution: used to defi ne the clock freq ue nc y for the bur s t interval timer . table 60: burst config - 0x16 [ 2 2] bit name state com m en t 1 7 0 1 6 0 5 : 4 r _ b u r s t [ 1 : 0 ] 00 01 10 11 packet is sent on e time packet is repeated once packet is repeated t w o times packet is repeated three times repeat interval* 1 chip id is includ ed as part of th e packet 3 send chip id 0 1 data for t e mpera t ure and b a tter y i s sent 2 send intern al adc data 0 1 data for ex t1, e x t2 is sent 1 send exte rnal adc data 0 1 burst interval timer resolution is 15s 0 burst interval resolution 0 burst interval timer resolution is 50ms note: w hen the burst tran smission is repea ted the in te rv al bet w een transmissio n s i s a random time period produced in a random number generator w i th the ch ip id v a lue used to seed the ra ndom number gene rator . 6. 7. 3. 1. b u rst i n terval defin e s the per iod f o r the nor mal burst tra n s m ission to occ u r. t h is is a c yclic mo de an d t he amis-5 300 0 w i ll tra n smit t he c ont ents of a register at the end of eac h i n terval. t h is int e rval is fi xed b y th e reg i ster v a lu e un lik e the rand om time i n terval w h e n t he tr ansm i ssion is repe ated. table 61: burst i n terval - 0x17 [2 3] bit name com m en t 7:0 burst_in t [7:0 ] burs t i n terv al = (burst_in t+1) * b urst interval resolution 66 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6. 7. 3. 2. user defined data a table 62: user defined data a - 0x2d [45] bit name com m en t 7:0 use_dataa [7: 0 ] optional data to be sent in normal burst mode if no n-zero 6. 7. 3. 3. user defined data b table 63: user defined data b = 0x2e [46] bit name com m en t 7:0 use_datab [7: 0 ] optional data to be sent in interru pt triggered burst if non-zero 6.7.4. hous ekee pi ng table 64: ho usekeeping enable regist er num b er (hex ) name bits func tio n 0 x 1 0 i d l e c o n f i g 0 enable housekeeping timed functions hous ekee pi ng is anoth e r per i odic o per ation m ode, w h ich c an be use d to peri odic a ll y per fo rm operati o n s such as osci ll ator cali br ati o n s , pll cal i br ation , ee refresh, or temperatur e compe n satio n . it can also b e u s ed to per io dic a ll y w a ke an ex ternal host/controller to allo w it to perform w h atever tasks it ma y n e e d to. t he housekee pin g config ur at ion reg i ster co ntains the o p ti ons to specif y w h at is to o ccur duri ng a h ouse k eep ing c y cl e, and the hous e k eep ing i n terva l time r is used t o control h o w frequ entl y the w a ke up occ u rs. setup reg i sters descripti ons: ho u seke ep in g co n f ig - set the burst trans mission param eters. ho u seke ep in g in ter v al - set the time interv al bet w e e n bur s t transmission s. 6.7.4.1. hous ekeeping config t he houseke e p in g confi gurati on reg i ster is u s ed to specif y w h ich tasks th e amis-5300 0 shou ld p e rform durin g a ho us ekee pin g c y cl e. hk in ter v al r eso lu tio n : used to specif y th e clock frequ en c y for the ho us ekee pin g interv al timer. w ake: w hen ena ble d , the amis-5300 0 w i l l enab le the s y s t em clock outp u t, and issu e a n interru pt to an e x terna l cont roller. write ee: t h i s option is use d to store the valu es of an y calibr a tio n s that ma y h a ve b een p e rforme d durin g ho usek eep ing . t he entire w o r k ing re gister b ank w i l l be w r itten to ee. read int a d c channels: t he AMIS-53000 w i l l do co nv ersio n s on the batter y v o ltag e and temper atu r e sensor. t h is can be used as a met hod to p e rio d ic all y u pdat e the temperatur e co mpens ation l o o p . read ext a d c channels: w hen en ab led, the t w o e x ter n al adc i nputs w i ll b e conv erted dur ing a ho useke epi ng c ycle. cal pll, rc, kicke r: allo w s perio dic cal i b r ation of the os cillators of the amis-5300 0. 67 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 65: ho usekeeping config - 0x1b [27] bit name state com m en t 1 five minute resolution setting 7 hk interval resolution 0 one second r e solution setting 1 issue interrupt a nd enable clock to exte rnal host/controller 6 wake 0 1 curre nt register data w r itten to ee (perfo rmed aft e r all cal?s complete)* 5 w r i t e e e 0 1 temp sensor an d batter y inputs converted 4 read in t adc chann els 0 1 ext1 and ext2 adc inputs converted 3 read ext adc chann els 0 1 pll calibration performe d during housekeeping 2 cal pll 0 1 rc oscillator cali bration perf o rme d during houseke eping 1 c a l r c 0 1 kicker calibration perform ed durin g housekeeping 0 cal kicker 0 note: * bit 5 is set high to a llow the e e to be au tom a ti cal l y w r itten a f ter a cal i bration i s com p le te . 6.7.4.2. housekeeping interval sets the interv al (time that the amis-5300 0 is in sle ep mod e ) for the hous ekee pin g routi ne. table 66: ho usekeeping interval - 0x1c [28] bit name com m en t 7:0 hk_int [7: 0 ] housekeeping interval = (hk_in t + 1)* (hk interval resolution) 6.8 idle return table 67: idle r e turn regist er num b er (hex ) name code func tio n 0 x 0 0 c o m m a n d 0 x 0 4 in most conditions, the amis-530 00 must be retu r ned to idle mode at the end of a t a sk b y this command t h is command is used to put the p a rt b a ck i n to i d le mo de. it shou ld be u s ed b y th e h o s t to pl ace the a m is-5300 0 bac k into id le mod e after the AMIS-53000 has inte rrupted the hos t for reception of a packet in sniff, or to end a hous ekeeping c y cle. 68 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6.9 ee t he AMIS-53000 uses i n tern al ee memor y to store registe r settings (eith e r defau lt factor y settin g s or u s er defin ed set t ings). table 68: calibr a tion results regist er num b er (hex ) name bits func tio n 0x05 write the register contents to ee 0 x 0 0 c o m m a n d 0x06 read the conten t s of the ee 0x01 status/flag1 2 ee checksum st atus 0x1b housekeeping config 5 write register dat a to ee (auto af t e r calibration complete) 6.9.1. w r ite ee t he serial inter f ace pr ovid es a me ans to re ad and w r it e t he w o rki ng r e g i sters of th e a m is-5300 0. t o reta in th e inf o rmatio n h e l d b y these re gisters , on-bo ard e e is prov ide d to store al l of th e register c onte n t s nee ded for oper ation. t h e w r ite e e co mmand c opi es the current c onte n ts of th e w o rki n g re gisters into ee, a l on g w i th a ch ecksum. t he ch ecksu m is use d to ve rif y t hat th e c o ntent of t he ee is valid w h e n the ee is dumpe d back into th e registers. 6.9.2. loa d ee t he load ee c o mman d w i ll r e fresh th e co ntents of the w o r k ing r egist ers w i t h the val ues stored in ee, i f the ee c hec ksum is v a li d. if the ee checks um fails an err o r bit w i ll be se t in the status2 register. 6.10 calib rate table 69: calibr a tion results regist er num b er (hex ) name bits func tio n 0x07 per f or m a q u ick star t oscillator calibr a tion 0x08 per f or m a 10khz rc oscillator cal i br ation 0x09 perform a pl l calibration 0 x 0 0 c o m m a n d 0x0a per f or m a q u ick star t oscillator calibr a tion 6 tx pll calibration status 5 rx pll calibration status 4 10khz rc oscilla tor calibr a tion status 0x01 status/flag1 3 quick start oscillator calibration status 2 perform th e pll calibration 1 per f or m the 10k hz rc oscillator calibr a tion 0x1b housekeeping config 0 perform th e kicker calibration 0x33 kicker slope options 4 kicker calibr a tion status setup reg i sters descripti ons: trim - sho w s the trim valu e for the circuit. pll trim ta rge t - set a value that the pll tri m tr ies to achie v e in cal i brati o n. 69 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6.10.1. internal t r i m 6. 10. 1. 1. crystal trim table 70: c r y s ta l trim - 0x21 [33] bit name com m en t 7:0 xtal_trim [7:0 ] 24mhz internal tr im caps; ff is max capacitance, 00 is min 6. 10. 1. 2. lna trim table 71: lna t r im - 0x22 [34] bit name com m en t 7:4 lna_out[3:0 } lna output tank cap trim f is max cap 3:0 lna_in [3:0] lna input shunt capacitor tr im, f is max, 0 is min 6. 10. 1. 3. quick start oscillator trim t h is register contai ns the val ue of the trim from the self cali bratio n. t able 72: q u ick star t o scillator tr im - 0x23 [35] bit name com m en t 7:0 qs_t rim [7:0] trim for th e quic k start (kicker), this regist er is w r i tten to b y the calibration circuit 6.10.1.4. 10k oscillator trim t h is register contai ns the val ue of the trim from the self cali bratio n. t able 73: 10khz o scillator t r im - 0x24 [36] bit name com m en t 7:0 rc_tri m [7:0] trim for th e 10k hz oscillator, this regist er is writte n b y the calibrati on circuit 6. 10. 1. 5. a nalog trim1 t h is is an i n ter nal use r egist e r w i t h n o us er defin ed m ean i ng. t h is regist er is set at the factor y an d ch ang ing the v a l ue w i ll c aus e t he amis-5300 0 to not operat e. 6. 10. 1. 6. a nalog trim2 t h is is an i n ter nal use r egist e r w i t h n o us er defin ed m ean i ng. t h is regist er val ue is set at the factor y a nd ch an gin g th e val u e w i l l ca use the amis-530 0 0 to not oper ate. 6. 10. 1. 7. r f p ll trim t h is register c ontai ns the v a l ue of th e trim f r om the s e lf c a libr a tio n . t h is regi ste r i s val u ab l e to mo ni to r to de te rmi ne i f t he p ll tri m calibr a tio n p a s s ed, b u t w i th t he h i g hest trim valu e or lo w e s t tr im value w h i c h in dicat e s th at the trim is n earl y all the w a y to t he edg e o f the cali bratio n. 70 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 74: r f pl l trim - 0x2 7 [3 9] bit name state com m en t 7 6:4 tx mode pll t r im value 111 -- 000 max vc o trim va lue from the self calibration min vco trim value from the self c a libration 3 2:0 rx mode pll t r im value 111 -- 000 max vc o trim va lue from the self calibration min vco trim value from the self c a libration 6. 10. 1. 8. p ll target v a lue t h is register is used b y th e amis-5300 0 dur ing se lf calibr a tion. t h is is an intern al use re gister w i th n o u s er defin ed me ani ng . 6.10.2. cali brate quic k start oscillator t he quick star t oscill ator m u s t be c a li brate d prior t o o per ati ons s u ch as s n iff or b u rst tra n smit. t h is co mmand w i ll per form a n i n te rn al calibr a tio n of t he osc ill ator, w r it e the resu lt to the qu ick st art trim regis t er, issue a ca l i brati on c o mpl e te fla g , as w e ll as a ca libr a ti on goo d/ba d ind i c a tor. t h is command ca n be is sued from an y valid state th at accepts cha n g e s in the instru ctions. 6.10.3. cali brate 1 0 kh z osc ill ator in an y of the i d le mo des of oper ation, a n i n terna l 10k hz oscill ator is us ed as the ti me keep ing r e fere nce for the int e rval timer s. t h e calibr a te 10kh z oscil l ator c o mmand w i l l e n abl e the cr ysta l osci lla tor t o c r eate a n acc u r a te time base to use for t he calibr a tio n of t h is oscill ator, and then perform t he cali brati on and store the result. a cal don e and stat us flag w i l l be issued u pon compl e tion o f the calibr a tio n . t h is command ca n be issu ed fro m an y v a li d state that accepts chan ges i n the instructio ns. 6.10.4. cali brate pl l cali brate t he p ll p e rforms a calibr a tio n for t he pl l i n b o th tr ansmit a nd r e ceiv e mo de. t he pll status register r e p o rts the ca libr a tio n valu e for both modes, as w e ll as the status for the cali brati on. t h is command ca n be i ssued from an y val i d state th at accepts changes in the instructi o ns. 6.10.5. cali brate l n a t h is command turns o n th e r f receiver ch ai n a nd optimiz e s both the lna outp u t tuni ng structure a nd t he lna inp u t matchin g trim fo r maximum sig n a l lev e l on rs si. t h is is a calibr a tio n t y p i c a ll y p e rformed at board ass e mbl y in t he pr e s ence of a kn o w n rf sign al . t h e amis-5300 0 w ill a u to-tun e bo th the in put an d outp u t intern al vari ab le ca p a citanc es of th e lna to o p tim i ze ga in, com p ensati ng fo r the tolera nce of e x ternal com pon ents for the match. 6.11 rom 2 regs t h is command starts internal amis-5300 0 pr ocesses suc h as: multi-chan nel: calc ulat es t he fre q u enc y i n formatio n to form ni ne ch an nels of 300k hz ba nd w i dth. f our of thes e c han nels are at hig her frequ enci e s than the programm ed rf fr eque n c y a nd four ch ann els are at lo w e r freq ue nci e s. wav e sha p ing: calculates t he volta ge step s to form the gaussi an w a v e shap ing of the data for the dat a rate selecte d . 71 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet defined data rate s: calcu l ates all the par ameters for the selected d a ta rate (selecte d from the defin e d data rates). rf fre que nc y : calcul ates the param eters n eed ed to set the t x /rx frequ enc y a m filters: c a lcul ates p a ra meters for the filter defi ned b y the data rate s e lecti on (defi n e d data rates). 6.12 ch ip reset resets the e n ti re chip, simil a r to a por. t h i s operati on w i ll reset the unl o ck test mux register. 6.13 a d c co n v er si o n table 75: adc configuration regist er num b er (hex ) name bits func tio n 010xxxxx perform a single a dc conversion (see table 84 ) 0 x 0 0 c o m m a n d 110xxxxx perform continuo us a dc conversions (see table 8 5 ) 0x01 status/flag1 0 the adc conve r sion has complet ed 4 do an adc conv ersion for the int e rnal measurem ents 0x1b housekeeping config 3 do an adc conv ersion for the e x t e rnal measurem ents t he amis-530 00 co ntai ns a n 8 b i t an alo g t o di gita l co nve r ter. t h is adc can meas ur e the v o lta ge o n a numb e r of intern al fu nctio ns, batter y volta g e , temperature, receiv ed si gna l strength i ndic a tion v o ltag e, and loo p filter voltag e. t he results of thes e conve rsi ons a r e avail a b l e thro u gh rea d in g the registers w h er e that data i s stored or b y using the fea t ure of the burst transmissio n to send tha t informati on to anoth e r no de. t he AMIS-53000 a l so conta i ns t w o a dc chan nels av ail a ble o n the devi c e pins. t he adc can conv er t sign als at a co nversi on rate u p to 128k sam p les/sec o n d . setup reg i sters descripti ons: te mp - contai n s the value fro m the last ad c of the interna l temperatur e se nsor. battery - co nta i ns the val ue from the last ad c of t he intern al batter y volta ge (div ide d b y 2). rssi - contai n s the value fro m the last adc of the signa l le vel samp le in t he rece iver. a dc1 - c onta i n s the value fro m the last adc of the exter nal anal og i nput. a dc2 - c onta i n s the value fro m the last adc of the exter nal anal og i nput. loo p f ilte r - contai ns the val ue from the las t adc of the loop filter volta g e . 6.13.1. adc co nversi on res u lts 6. 13. 1. 1. temp a d c table 76: t e mp adc - 0x34 [ 52] bit name com m en t 7:0 temp_adc [7:0] temper ature sen s or adc rea d ing 72 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6. 13. 1. 2. b a ttery adc table 77: batte r y adc - 0x35 [5 3] bit name com m en t 7:0 b a t t _ a d c [7 : 0 ] batter y voltage a dc reading (v ba tt /2 ) 6. 13. 1. 3. r ssi table 78: rssi - 0x36 [54] bit name com m en t 7:0 rssi_adc [7:0] rssi voltage adc reading 6. 13. 1. 4. e x ternal i nput 1 adc table 79: e x tern al input1 adc - 0 x 37 [55] bit name com m en t 7:0 e x t 1 _ a d c [ 7 :0 ] external input 1 adc reading 6. 13. 1. 5. e x ternal i nput 2 adc table 80: e x tern al input2 adc - 0 x 38 [56] bit name com m en t 7:0 e x t 2 _ a d c [ 7 :0 ] external input 2 adc reading 6.13.1.6. loop filter table 81: loo p filter - 0x39 [5 7] bit name com m en t 7:0 loop_fil t [7:0] internal loop filter 6.13.2. sing le adc c o nversi on t he singl e co n v ersio n comm a nd performs an adc c onvers i on on th e ch an nel s pec ified a s part of th e co mmand. onc e compl e te, a fl a g is set, and the 8 bit data for th e convers i on is avail abl e in its associate d reg i ster. table 82: single adc conversio n s regist er num b er (hex) name bits (7:6) bits (5:0) func tio n 01 000001 perform an adc on the e x ternal in put 1 01 000010 perform an adc on the e x ternal in put 2 01 000100 perform an adc on the internal te mperatu r e sensor 01 001000 perform an adc on the inte rnal b a tter y voltage 01 010000 perform an adc on the receiver r ssi 0 x 0 0 c o m m a n d 01 100000 perform an adc on the loop filter 73 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 6.13.3. conti nuo us ad c conv ersio n t h is command can be give n to the rad i o a n d oper ate i n p a rall el w i t h tra n smit or receiv e. t h is mode can als o be en tered int o fr om an idle state. in this mode the sp ecifie d a dc ch ann el is co ntin uous l y c onv erted, and its ass o ciate d regist e r is continu ousl y ov er w r itten. table 83: single adc conversio n s regist er num b er (hex) name bits (7:6) bits (5:0) func tio n 11 000001 perform continuo us adc on the e x tern al input 1 11 000010 perform continuo us adc on the e x tern al input 2 11 000100 perform continuo us adc on the in ternal tempe r atur e sensor 11 001000 perform continuo us adc on the in ternal batter y volt age 11 010000 perform continuo us adc on the re ceiver rssi 0 x 0 0 c o m m a n d 11 100000 perform continuo us adc on the lo op filter 74 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 7.0 data interface table 84: co ntr o l/data interface ph y s ical configuration clock data interfa ce func tio n pin source ou tpu t inpu t select a m is -53000 data b u fferin g i 2 c c o n t r o l s c l k m a s t e r s d a t a s d a t a n o n e s l a v e only n / a c o n t r o l s c l k m a s t e r sdat a s d a t a s s n slave only n / a d c l k m a s t e r d r x t x d r x t x d s s n m a s t e r o p t i o n a l 3 -wire data d c l k m a s t e r d r x t x d r x t x d s s n s l a v e buffered onl y d c l k m a s t e r d r x t x d o p t d s s n m a s t e r o p t i o n a l 4 - w i r e d a t a d c l k m a s t e r d r x t x d o p t d s s n s l a v e buffered onl y f i gure 42: 4-w i re sp i compatible data i n terface 75 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 43: 3-w i re serial data i n terface w i r e or a 4- w i re spi like i n terfac e. selecti ng the i n terface, 3- w i r e or 4- w i re is d one b y w r iti ng t o bit 7 of the g ener al o p tio n s b g i s t . t he AMIS-53000 em plo y s t w o differe nt dat a interfac es. t r ansmit and r e ceiv e dat a is exc h a n g ed w i t h an e x tern al control l er thro u gh i t h e r a 3 - e r e e r spi serial data interface 3- w i re ser i al da ta interface amis-5300 0 c a n b e t h e slave or master s e t u p r e the data pack e t to identif y a uni que ra di o. a l f i xe d data rates. t a r a t e s t h at are not on e of the fixe d dat a rates. broa d ca s t id - a genera l chi p id allo w i n g for transmissi on s to be receive d b y all ra dios. g i sters descripti ons: chip a ddres s - allo w s a u n iq ue val ue to be transmitted an d receiv ed w i th fixed data ra tes - sel e ct the optio ns for one o f s e v e r general optio n s a - co nfig ur e the interfac e optio ns. general optio n s b - config ur e the interfac e optio ns. sta r t of fra m e - set a code va lue that in dic a tes the start of a data p a cket. pre a mble le ngth - select a typ e of pream bl e and set the l ength i n bits. (see sectio n 6. 6.3) custom data rate s - confi g u r e param e t e r s f o r d a crc poly nom ial - value of th e crc p o l y n o m ial. defau l t l e n g t h o f packet- set a default length for packets. 76 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 7.1.1. chip a ddress msb1 t he 16 bit id that can be us ed for severa l purp o ses in th e amis -5300 0 is stored in the chip a ddress msb, and chi p addr ess ls b registers. table 85: chip address1 - 0x03 [3] bit name com m en t 7:0 chip_add [15:8] upper b y te of chi p address 7.1.2. chip a ddress lsb table 86: chip address0 - 0x04 [4] bit name com m en t 7:0 chip_add [7:0] lo w e r b y te of chi p address 7.1.3. data rate/form a t t he data rate/format register is used to sel e ct the data rate and format for both rece ive and transmit. t he ddrat e [2:0} optio n bit s allo w s e l e ction of one of ei ght pre-pr ogramm ed data rat e s. w hen on e of the discrete d a ta rates is select ed, the rom2 regs comma nd is used to lo ad clock an d data recover y settin g s for t he desir ed data rat e int o their assoc i at ed reg i sters. t he manchester optio n bit config ures the am is-5300 0 to transmit and receive in th e manchester e n cod ed format , w h i l e the d a ta interface rem a i n s nrz. if a d a ta rat e o t her tha n on e of the ava ila bl e d i screte rate s is desir ed, th e us er s hou ld set the use cu stom bit, a n d then pr og ram t h e custom d a ta ra te reg i ster for t he desir ed dat a rate. w h en the us e custo m data r a te op tion is e nab le d , it is u p to t h e user to set the correct sampl e clock freque n c y in the c dr optio ns b regis t er, se t clock recover y l oop fi lter settings, a nd if usin g the pll bas ed f sk detector, set the pll det ector loo p filter. note: f o r dat a rates that are ne ar o ne of the pre- defi n e d data r a tes, a discr ete dat a rate co ul d first be chos en, the rom2re gs command giv e n to load all of the settings fo r the various blocks for that dat a rate, and then the c u stom data rate option enabl e d a nd th e ne w data rate informa tio n ent ered. for e x amp l e, if the desir ed da ta rate is 1 00k bps, set ddra t e to 110 for 9 6 kbps op erati o n. ne xt, iss u e the rom2r e gs comman d in the comma nd register. a ll of the pr oper se ttings for the c l ock a nd data recover y c i rcui t for a 96k dat a rate w i ll be l oad ed in to the w o rkin g re giste r s from rom (sampl e clock frequ enc y, cl oc k recover y lo o p filter s e ttings ). f i nall y , en a b le th e us e c u stom optio n, a n d progr am data r a te 1, and 0 w i t h the valu e for a 100k d a ta rat e . custom freq ue nc y is set i n d a ta rate 1 an d data rate 0. if cu stom is 0, rom contents for sele cte d di screte data r a te are loa d e d i n to data rate 1 a n d data rate 0. 77 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 87: dat a rate/fo r mat - 0x0b [11] bit name state com m en t 7 n u 6 nu 5 n u 1 enables user pro g rammable data rate 4 use custom 0 1 manchester enco d ing selected 3 m a n c h e s t e r 0 nrz encoding s e lected 2:0 ddrate [2: 0 ] 000 001 010 011 100 101 110 111 1.2kbps 2.4kbps 4.8kbps 9.6kbps 19.2kbps 57.6kbps 96kbps 128kbps 7.1.4. genera l option s a t he genera l op tions a register contains a nu mber of optio n s that specif y t he op erat i on of the part in its vario u s modes. sta ndby mode : determi nes w h ether th e cr y s tal oscill at or is ena bl ed durin g stand b y . f o r ap pli c ations re l y in g on the amis-5300 0 to provid e an d e x tern al h o st/controll er w i t h a s y stem clock, th is bit shou ld b e enab le d, and i s the def au lt state. por state: specifi e s the po w e r on state of the device. once th is has b een store d i n to ee, the d e vic e w i ll p o w e r u p i n th e chose n state after the ee has bee n sha d o w e d into the w o rk i ng reg i sters. pull up disabl e : f o r ap pl ica t ions not usin g an o pen dr ain t y pe driver to drive the r e g i ster i n terface pi n s (sdat a , sclk a n d ssn) the pul l u p s on thes e pin s can be dis a b l ed via this o p ti on bit to save p o w e r. t e mp eratu r e co mp en satio n : w hen ena ble d , the adc output for the temperature s ensor is use d to compens ate the rf center freq uen c y for cr ystal freque nc y erro r. a ne w c o r r ec tion factor i s calcul ated e a ch time the adc performs a n e w convers i on o n the temper ature sensor. crc enable: enab les int e rn al crc ch ecki ng in r x , an d app en ds a cr c in t x . l e n g t h o f packet en ab le: allo w s b u ffering of packets, als o all o w s cr c w h e n en abl ed. use id in rx and tx: w hen ena ble d , in r e c e ive m ode the part w i ll n o t out put dat a u n til a vali d id is fo u nd, an d i n t x , the p a rt w i ll a u tomatic a l l y se nd pr eam ble a nd ch ip id before en ab lin g the data i n ter f ace. 78 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 88: gene r a l optionsa - 0x 0c [12] bit name state com m en t 1 wake on id in r x , send id in tx 7 use id in rx an d tx 0 1 enables the part to frame packets 6 length of packet enable 0 1 enables crc (p acket length must be enabled) 5 c r c e n a b l e 0 1 rf center f r eque ncy temper ature compensation enabled 4 temper ature compensation 0 temper ature co mpensation is disabled 1 pull ups on iic clock and data and ssn pins disabled 3 pull up disable 0 [2:1] po r state 00 01 10 11 standb y idle rx tx 1 cr y s tal onl y mod e , s y stem clock o u tput active 0 s t a n d b y mo d e 0 lo w - po wer stand b y mode 7.1.5. genera l option s b genera l opti o n s b contains m o re opti on b i ts for t he gen eral setup an d op er at ion of the am is-5300 0. sy s t em cloc k outp ut fre q u e ncy : sets the freque nc y of the outp u t cl oc k on the syscl k pin w h en e n a b le d. rxtx sa mpling ed ge : specifies w h ic h ed ge of dclk sh oul d be us ed to sampl e the r x t x pi n. a u to in creme n t disab le: when e n a b le d, a multipl e addr e ss read or w r it e co mman d on the register int e rface w i ll rea d / w r i te onl y the a ddr e ss given i n the comman d multi p le times. da ta inte rfa c e cloc k fre quenc y : sets the clock freq ue nc y for th e d a ta i n terfac e w h e n the amis-53 0 0 0 is co nfig ured to b e the master of the d a ta i n terfa c e. f o r mod e s in w h ich th e amis-5300 0 does not b u ffe r the p a cket, the i n terface s p eed w i l l al w a ys be the data rate, reg a r dless of this s e tting. d a ta inte r f ac e slav e / ma s t er : specifies w h e t her the amis-530 00 is the m a ster or slave f o r the data i n te rface. 4-w i re data in terfa ce: ena b l e s the 4- w i r e spi data interfac e. w hen lo w , rxt x is bi- d ir e c tiona l. table 89: gene r a l optionsb - 0x 0d [13] bit name state com m en t 1 e n a b l e d 7 4-wire data in terface 0 1 AMIS-53000 is slave 6 data inter f ace slave/master 0 AMIS-53000 is m a ster, clock spee d determined b y bits 5, 4 5,4 data inter f ace clock frequenc y 11 10 01 00 1mhz 500khz 100khz baud clock 3 nu 1 data bits are sa mpled on the rising edge of dclk on the interface 2 r x t x sampling e d g e 0 data bits are sa mpled on the falling edge of dclk on the interface 11 12mhz (24mhz exter nal cr y s tal) 10 6mhz (24mhz e x tern al cr y s tal) 01 3mhz (24mhz e x tern al cr y s tal) 1,0 s y stem clock output freque nc y 00 off 79 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 7.1.6. start of f r ame t he start of frame b y te is tran smitted w h e n this register is n on-zer o . it?s used as an ai d for the receiver clock an d data rec over y circu i t in mod e s w her e the fast phas e al i gnme n t feature is en ab le d. table 90: sta r t o f frame - 0x19 [ 25] bit name com m en t 7:0 sof [7: 0 ] 8-bit code sent p r ior to chip id in tx and burst 7.1.7. data rate 1 t he data rate 1 an d d a ta rat e 0 r egisters a r e use d to s e t user defin ed data rat e s. t hese r e g i ster s are l o a d e d from rom w h e n a discrete d a ta rate is selecte d . t he follo w i n g equati on is us ed to calcu l ate the valu e for cust _ dr: w h er e datar a t e is the des ire d data rate, a n d f sample_clock is the frequ enc y selecte d for the sampl e cl ock . t h is register is loa d e d w i th th e discrete rate if selected. table 91: dat a rate1 - 0x2 9 [41 ] bit name com m en t 7:0 cust_d r [15:8] upper b y te of user defined dat a r a te/discrete data rate 7.1.8. data rate 0 table 92: dat a rate0 - 0x2a [42 ] bit name com m en t 7:0 cust_d r [7:0] lo w e r b y te of user defined dat a r a te/discrete data rate 7.1.9. crc poly no mi al t h is register allo w s a des ig ne r to change th e crc pol y n o m ial use d in th e amis-5300 0. t he register repres ents the prese n ce of t he po w e rs in the crc eq uati on. for examp l e: t he pol y n o mia l x8+ x 5+ x2+ x + 1 is enco d e d b y ass u min g the pol yn omia l w i l l al w a ys h a ve a high or der b i t. so the bin a r y repres entati on i s : 1 0010 01 1 1 t h is is set as the val ue 0 x 27 (hex) i n the re gister (see ?ko opma n , p. & chakra vart y , t . , ? cc y l ic red u n danc y code ( crc) p o l y n o mia l sel e ction for emb edd ed n e t w ork s ? dsn04, ju n e 2004.? for more information.) table 93: c rc poly - 0x30 [4 8] bit name com m en t 7:0 crc_p o l y [7:0] crc pol ynomial value 80 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 7.1.10. defau l t len gth of packet t h is register al lo w s a defa u lt valu e for t he l o p (5 b y tes) s u ch th at the a m is-5300 0 do es n o t h a ve to sen d th e lop w i th a buffer ed packet. table 94: def ault lop - 0x31 [49 ] bit name com m en t 7:0 default _lop [ 7 :0] default value for the length of pac ket to be used in buffered tx/rx 7.1.11. broadc ast id 1 man y ap plic ati ons in the w i r e less market make use of a broadc ast function w h ere th e ma ster note in a s y stem c an transmit to all w i rel e ss no des in the net w o rk w i t h o u t addr es sing e a ch n ode indivi du all y , b u t still not broa dcastin g to nod es in an other n e t w o r k . table 95: bro a d c ast id1 - 0x3a [ 58] bit name com m en t 7:0 global_id1 [7:0 ] lo w e r b y te of the global address 7.1.12. broadc ast id 0 table 96: bro a d c ast id0 - 0x3b [ 59] bit name com m en t 7:0 global_id0 [7:0 ] upper b y te of the global address 7 . 2 tx/rx da ta in te rfac e protocol t he AMIS-53000 t x /rx data format can be streamin g data w h ere th e tran smitter transmi ts each bit of d a ta as it is rec e ived or it can b e packetiz ed. p a cketize d data can b e i n pac kets up to 25 6 b y tes. pack e t ized data ca n ad d a pream b l e, start of fra m e, id entific a tion code, le ngth of packet, and c rc error ch ec ksum. f i gure 44: data protocol f o rmat streamin g or p a cketize d data b y te max i mum b u f f e r s i z e i s 2 5 6 packet overh e ad 81 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 82 f i gure 45: 3-w i re data transfer p r otocol f i gure 46: 4-w i re data transfer p r otocol a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 97: tx/ r x data protocols modul atio n detec t or cdr preamble so f id/l op/crc slice a m r s s i o p t 1 c w yes 2 see table 98 fixed/auto fm (<20kbps) pll ye s 1 0 pattern --- --- - see table 98 --- --- -- --- -- fm (>20k bps ) fft yes 3 4 see tabl e 98 --- --- -- --- -- not e s: 1. the us e o f t h e cdr f unct i on to re cov e r t he da t a is re commended f o r am/ook modu lat i o n . 2. the sof for am modula t ion is sugg este d to be 5 5 (he x ) for nrz an d 0a (hex ) for ma nche ster enco ded data . 3. the preamble f o r fm (fft) w i t h nr z dat a i s a 1 0 r epe at ing patt e rn . the preamble f o r fm (f ft) w i t h manc he ster en c oded da t a i s all 1 s o r all 0 s . 4. a sof is only re quired f o r fm (fft) w hen t h e da t a i s manc he s t er en c o d e d . the s ugge st ed s o f is a patt e rn o f 5 5 (he x ) or aa (he x ) . table 98: inte rfa c e data protocol s tx/rx da ta prot ocol interfa ce da ta protoc ol com m en ts lop crc interfa ce data n n a c t i v e stream 1 data is streamed out the interface as it is received n n active* stream * data is streame d out the interf ace starting w i th th e wakeup on id y n interrup t buffered an interrupt is issued w hen d a ta r e ception is comp lete y y interrup t buffered an interrupt is issued w hen d a ta r e ception is comp lete not e s: 1. w hen th e in ter f a c e u s e s streaming data , the amis- 530 00 must be the ma ste r . t he serial d a ta interface for th e amis-530 00 can b e co nfigu r ed to b e a 3- w i re int e rface or a 4- w i r e spi in terface. t he amis-53 00 0 ca n be confi gur ed to act as a mas t er or a slave f o r both rec e ive and tr ansmit o perati on. bit 2 in t he ge ner al options b re gi ster a llo w s th e user to sel e ct w h eth e r dat a w i ll b e samp le d on the r i sin g , or falli ng e dge of dclk. t he setting for the sampli ng pol ari t y ap pl ie s to a l l modes. table 99: serial data inter f ace c onfiguration genera l o p ti on s b data por t co nfi gurati on pin fu ncti on de finiti on bit 7 bit 6 bit 2 # port pins a m is -53000 edge sample dclk dssn drxtx dopt 0 0 x 3 m a s t e r x o u t p u t o u t p u t i / o x 0 1 x 3 slave x input input i/o x 1 0 x 4 m a s t e r x o u t p u t o u t p u t o u t p u t i n p u t 1 1 x 4 slave x input input output input x x 0 x x f a l l i n g x x 1 x x rising 7.2.1. amis-5300 0 in master mode in re cei v e mo de , th e d ssn pi n w i l l tra n s i t i o n lo w w hen the amis -53 0 0 0 has rec e ive d data. imm edi atel y fo llo w i n g the trans itio n of dssn, the amis-530 00 w i ll pr ovid e a s y nchr oniz ed bit cl o ck on dclk, an d the receiv ed data w i ll ap pe a r on dr xt x. in transmit mo de, the trans iti on of dss n is used to s i gn al an e x ter nal ho st/controlle r th at the amis-53 000 is rea d y fo r transmi t data an d is rea d y to r e ceive th at d a ta on the dr xt x pin. imm edi atel y fo llo w i ng th e trans iti on of dssn, the amis-53 0 00 w i ll prov ide a s y nc hro nous cl ock on dc lk for the host/con troller to use fo r load ing tra n smit data into th e amis-5300 0. 83 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 7.2.2. amis-5300 0 in slave mod e t he amis-530 00 ca nn ot be the sl ave for str eamin g data. t he requir e m ents of a d d i ng hea der inform ation s u ch as pream ble or s o f requ ires th at the amis-5 300 0 b e i n co ntrol of the data in terface transfe r. t he receiv e r has s i mil a r r equ ireme n ts w i th remov i n g the hea der inf o rma tion. as the slave for the data interfac e, the amis-530 00 w i ll sim p l y issue a n int e rrupt to the external h o st indi cating d a ta is avai la bl e a fte r a data pack e t ha s been rec e iv e d . f o r buffered tr ansmit op erati on, the amis-530 00 w i ll iss u e an i n terr upt i ndic a ting it is read y to l o a d the pack e t. after the p ack e t is receiv ed b y the AMIS-53000, the transmitter i s enab le d, an y packet formatti ng is do ne a n d the packet is sent. 7.2.3. manch e st er operati on f i gure 47: manchester coded data if the manche ster optio n is selecte d in th e data rate and format registe r , the AMIS-53000 w i ll inter n all y e n co de a n d dec ode bot h transmit and re ceive d a ta resp ectivel y . t he format for the signa l interfac e remai n s nrz in this mode. table 100: r egister configuratio n bits 7.2.4. packet f r ami n g t h ree options bits locate d in the ge nera l opt ions a re gister determin e the method w i t h w h ich th e tran sceiver w i ll pr o c ess packe ts: use id, len g th of p a cket (lop) e nab le an d c y cl i c red und anc y check ( crc) e nab le. an a d d itio nal bit in the t x c onfi g r egister en ab l es th e buffered t x mode of o perati o n. genera l o p ti on s a tx co nfig so f bit 7 bit 6 bit 5 bit 3 bit 2 al l use com m en ts 0 x x x x x n o i d 1 x x x x x id x x 0 x x x no lo p 1 1 x x x x lop/id the id must be e nabled w i th lop for data alignme n t x no crc x 0 x x x 1 1 1 x x x crc/id/l op x 1 x 1 x x buffer/l o p tx must have l o p enabled whe n using data buff e ring x x x 0 x x no buffer x x x x 0 x c h i p i d x x x x 1 x global id x x x x x 0x 0 0 no s o f ? x x x x all other so f certain configura t ions requi re sof to detect id b y t e 84 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 7.2.5. use id table 101: id regist er num b er (hex ) name bits func tio n 0x0c gene ral options a 7 wake on id in r x /send id w i th t x 0x0f tx config 2 select either the chip id or gl obal id to be used in t r ansmissions 0x16 burst config 3 send id w i th bur s t packet t he chip id is a 16 bit w o rd w h ich can be p r ogramme d i n registers 3 a n d 4. in rece ive mode, w h e n th e use id bit i n gen eral opt io ns a is set, the amis-530 00 w i ll n o t beg in e x port i ng or bufferi ng data u n til a v a lid id match i ng the valu e stor ed in th e ch ip addr es s registers is receiv ed. t he id is use d i n more a d vanc ed mod e s of o perat i on for b y t e ali gnm ent. in add itio n to w a kin g on its o w n uni qu e i d, the amis-5300 0 w ill a l so w a ke o n a pre- defi ned glob al ch ip id. t he def au lt valu e for the gl o bal id is i n the register tab l e. t h is value can be over w r itten, but is not stored in ee so car e must be take n w h e n over w r i t ing the val ue. w i th the use i d bit en abl ed in transmit mo de, the amis-530 00 w i ll tr a n smit the chi p id prior to e nab lin g the d a t a interface. a n add ition a l o p tio n bit in the t x config re gister allo w s s e l e ctio n of either the chip id or gl ob al id valu e for transmit. in eith er tra n s m it or r e ceiv e, w h e n th e us e i d bit is en abl e d w i t hout lop ena ble d , the a m is-5300 0 w i ll not buffer dat a. h enc e wh e n ena ble d stand alo ne, the data interface must be c onfig ure d w i t h the amis-530 00 as the master. 7.2.6. len gth of pack et enabl e t he length of p a cket ena bl e (lop) bit locate d in ge nera l op tions a, enab le s the AMIS-53000 to buffer p a ckets. t he use id bit m ust b e used i n con j un ction w i th lop to allo w th e rec e iver to b y te al i gn on i n comi ng data. in receiv e mo d e w i th t he lop ena bl ed, the a m is-5300 0 w i ll interpr e t the fir s t b y te f o ll o w i n g eith er a v a l i d chip id, or g l o bal id t o be the len g th of the in comin g packet. t h is b y te sp e c ifies the n u mber of b y t e s fol l o w i ng the lop to be receiv ed (no n -inc lus i ve of the crc if ena ble d ). w h e n e n a b le d, the amis-5300 0 w i ll buffer th e i n c o min g p a cket i n to i n tern al ra m. f o ll o w i n g r e cepti o n of th e last b y t e of th e packet, an inte rrupt is issued on the interr upt pin, and de pe ndi ng on the c onfig uratio n of the data interfa c e, the packet w i ll e i ther be s ent out of the data interface b y th e amis-5300 0 as master, or w a it for the e x terna l host/cont roller to stream the packet out as the master. havin g the lop ena ble d in tr ansmit mod e a llo w s for th e u s e of the b u ffered t x packet optio n in tra n s m it, or the amis-530 00 ca n s t ill act as master and pr ocess th e packet on th e fl y . w i th lop enab l ed, a n d buffered t x disabl ed, t he amis-5300 0 must be the master for the d a ta interfa c e. in t h is m o de, the pr eam ble an d c h ip i d (o r gl oba l id ) w i l l be s ent b e fore th e data interface is acti vated. o n c e t h e dssn is pul le d lo w b y th e a m is-5300 0, th e first b y t e rec e ive d into the part is e x pecte d to be the lop b y t e . t r ansmission c onti n ues until the amis- 530 00 h a s det ermine d that al l b y t e s hav e b een rec e iv e d , at w h ich p o i n t the data i n terface is dis abl ed , and the a mis- 530 00 w i ll r e tu rn to stand b y . w hen b u ffered t x is enab le d, after the trans mit instruction i s given to th e amis-5300 0, a n inter rupt from the amis-53 0 0 0 w i l l b e iss u e d in dicati ng th e part is re ad y t o lo ad in th e d a ta pack e t. t h e actua l l oad in g of the data p a cket d ep en d s on the data i n terfa c e setup as to w h eth e r the a m is-5300 0 is master or slav e. t he fi rst b y te is aga in e x p e cted to b e the lop b y te. after the com p lete p a cket is loa d e d int o the rad i o, the rf w i l l be ena bl ed, th e pre a mb le an d chi p id tra n s m itted, foll o w e d b y th e pac ket. after completio n of the transmission, the ami s -530 00 w i ll re turn to standb y. 7.2.7. crc en abl e t he crc e nab le l o cate d in ge nera l o p tions a is the fi nal tier of inte lli genc e for the amis-5 300 0 p a cket h and lin g ca pa bil i t y . i n order fo r the amis-53 0 0 0 to do crc c hecki ng, this o p tion must b e used in con j u n c tion w i t h both use id a nd l o p ena ble. operati on of the interface f o r b o t h receiv e a nd transmit w i th t he c rc ena bl ed is no differe nt from that e x plai ne d u n d e r the lop en abl e d sectio n. w i t h the cr c ena b l ed, th e amis- 530 00 w i l l a p p end the c a lc ul ated crc in transmit as the last b y te. in r e ceiv e mo de, i n terrupts to th e ext e rna l contro ller w i ll on l y be issue d for pack e ts passin g the crc. 85 a m i se m i co nd uc t o r ? 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AMIS-53000 frequency agile transceiver data sheet 7.2.8. sof byte table 102: sug g e sted sof modul atio n detec t or codi ng preamble so f n r z c w 5 5 ( h e x ) am rssi m a n c h e s t e r c w 0a ( h e x ) fm (<20kbps) pll 1 0 pattern 1 0 pattern not requir ed nrz repeating 1/0 not requir ed fm (>20k bps ) fft manchester all 1?s or 0?s 55 (hex) o r aa ( h ex) dep end in g on w h eth e r the mode of o perati on is am or f m , nrz or manchester, it ma y b e necess a r y for a sof b y te to preced e the chip id. t h is b y t e is user pr ogramm abl e, a nd is us ed to e n su re pr op er c dr op erati on and b i t al i gnm ent prior to rec eptio n of th e c h i p id. w hen the contents of the sof b y te reg i ster are lo ad ed to an y no n-zer o valu e, this b y te w i ll be trans mitted prior to t he c hi p id. f o r modes not re q u irin g the sof b y t e , setting th i s register to 00 h w i l l pr ohi bit transmissi on of this b y te. mor e informati on o n w h e n the sof b y t e is requ ire d is in the cloc k and dat a rec o ver y s e ctio n. 7.2.9. t i mi ng di agr a m s for vario u s packet f r ami n g modes 7. 2. 9. 1. use i d e nabled, n o cr c, no p a cket length table 103: r e ceive parameter ac t i o n id data interface im mediatel y rea d y after id d e tected no lop radio sta y s in r x until instructed to change data is shifted out data por t as re ceived no crc error checking is not perfo rmed a nd crc is not att a ched to packet table 104: tran smit parameter ac t i o n transmit transmit comma nd immediat el y p o wers the t r ansm i tter on transmits pream ble id transmits the id starts data interf ace and uses a synchrono us cl ock to clock in the tx data (m aster onl y ) transmits each b i t as received transmitter retur n s to standb y aft e r transmission complete 86 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 48: data interface p r otocol ( i d only) 7. 2. 9. 2. use i d e nabled, n o cr c, lop e nabled table 105: r e ceive parameter ac t i o n id data interface im mediatel y rea d y after id d e tected lop receiver loads rest of packet into buffer memo r y after last data b y te is received, radio returns to th e previous state an interrupt is issued to the e x te rn al controller/microprocessor data is transferr e d out the po rt w i t h the amis-530 0 0 as master or th e exte rnal control l er as master no crc error checking is not perfo rmed a nd crc is not att a ched to packet table 106: tran smit parameter ac t i o n buffered transmit if buffered t r ans mit is sele cted, the AMIS-53000 w ill open the d a t a interface and t r ansfer all tx dat a into memor y w i th AMIS-53000 as master or e x te rn al controller as master transmit transmit comma nd (or e nd of tx data transfe r) im mediatel y po w e r s the transmitter on transmits pream ble (length of pr e a mble as specified) id transmits the s o f an d the id starts data interf ace and uses a synchrono us cl ock to clock in the tx data (m aster onl y ) or clocks data out of memory ( b uffer ed t x ) after the packet is transmitted, the transmitter ret u r n s to standb y sta t e 87 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 49: data interface p r otocol ( i d and lop) 7. 2. 9. 3. use i d e nabled, c r c e nabled, lop e nabled table 107: r e ceive parameter ac t i o n id data interface im mediatel y rea d y after id d e tected crc as soon as the id is validated, the crc starts p r o c essing the data lop the l o p is received the rest of t he re ceived data packet is buffered into memor y crc invalid the last b y te is t he crc a nd if invalid, the receive r w a its for a com m and from th e e x tern al host/contr o ller, or if the rec e iver came fr om idle it w ill r e tur n to r e ceive crc valid receiver returns to previous state and an inte r r upt i s issued to the extern al controller the data inte rfac e is started and t he data is sent to the controller, e xcept for the c r c table 108: tran smit parameter ac t i o n buffered transmi t if buffered t r ans mit is sele cted, the AMIS-53000 w ill open the d a t a interface and t r ansfer all tx dat a into memory w i th AMIS-53000 as master or e x te rn al controller as master transmit transmit comma nd (or e nd of tx data transfe r) im mediatel y po w e r s the transmitter on transmits pream ble (length of pr e a mble as specified) id transmits the s o f an d the id crc the cr c begins processing the data w i th the id starts data interf ace and uses a synchrono us cl ock to clock in the tx data (m aster onl y ) or clocks data out of memory ( b uffer ed t x ) lop the first b y t e is defined to be the lop of the packet crc b y te at the end of the packet, the data stops and the c rc value is sent after the packet is transmitted, the transmitter w a its for a command f r om the e x ter nal host/controller 88 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet f i gure 50: data interface p r otocol ( i d , lop and cr c) 89 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 8.0 general system functions 8.1 pu ll u p disab le t he AMIS-53000 inc l ud es bu i l t in pul l-up res i stors for use w i t h the i 2 c op eratio n to redu ce the over a ll s y stem com p o nent cou n t. t h e pull ups are as serted at por until m ode s e l e ct ion occurs. if mode is d e termine d to b e 3- w i re, th e pu ll ups ar e remo ved. if mo de i s determi ned to be i 2 c, this option bit det ermin e s w h eth e r the pull u p s are to be remove d. table 109: i 2 c p u ll up control regist er num b er (hex ) name bits func tio n 0x0c gene ral options a 3 disable internal pull up resistors on i 2 c bus 8.2 bro w n-out por t he bro w n- out por serves t w o purp o ses. t he first is to provid e a por signa l to reset the digit a l w h e n po w e r is i n itia ll y ap pli ed to th e part. t he second is to prov i de a por sho u ld the vo ltag e on the sup p l y drift belo w n o rmal op eratin g range to prev ent a bro w n - o u t cond ition. table 110: po w e r-on - reset sta r t up state regist er num b er (hex ) name bits func tio n 00 standb y 01 idle 10 rx 0 x 0 c g e n e ral options a 2 , 1 11 tx 8.3 t e mp eratu r e sen s o r t he temperatu r e sens or is cr eated b y us in g a dar lin gton p a ir of pnp tra n s isto rs. t he tw o trans istors create a 5mv/ o c slo pe th at can be sens ed w i t h an an alo g to digital co nvert e r. w i thout a m plificati on, an 8 bit adc w i t h a 2v referen c e voltag e w i ll have a res ol u t ion better than t w o degre e s. t he temperature sensor ca n be trimmed to an accur a c y of 3c. as the trim is incr eas ed, the output volt age a l so i n crea ses. t he temperature voltag e relat i ons hip is g i ve n b y : w here v is the output volta g e and t is the te mperatur e in c e lsius. setup reg i sters descripti ons: a dc te mpe r ature - regist er sho w s the va lu e of the temper at ure sens or adc. (see section 6.1 3 .1.1) 90 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 8.3.1. crystal t e mpe r ature co mpen sation an on-c h ip t e mperatur e sen s or combi n e d w i t h a n on-c h i p a/d an d a lo ok-up ta ble en abl e the part to mai n tain rf freque nc y acc u ra c y wi t h i n 2.5p p m over all op e r ating v o lta ges and temp erat ures (-4 5c to 85c). t h is f unctio n ca n b e ena bl ed v i a c onfig uratio n b i t 4 locate d in g e n e ral o p tio n s a. w hen this functio n is en a b le d, a ne w c a lcul atio n for the cent er freq uenc y w o rd w i ll be p e rforme d w h e never th e temper ature se nsor storag e r egi ster is u p d a t ed w i th a n e w value. t heref ore it is poss i b l e to up date th e compe n sat ion valu e eith er in hous eke epi ng, as part of a b u rst transmit cycl e, or as co n t rolle d e x tern all y b y issui ng th e instructi on to perf orm an a d c measur ement of the temp sensor. table 111: r f f r equenc y tempe r ature compens ation regist er num b er (hex ) name bits func tio n 0x0c gene ral options a 4 enable rf fr equ enc y tempe r atur e compensation 8.4 so ft w a re t he version of the amis-530 00 is w r itten to a register at the e nd of t he manufactur i ng process. t h is code ca n h e l p amis w i r e l e ss prod uct supp or t w h en there is an issu e w i th the amis-530 0 0 . setup reg i sters descripti ons: a m is id - reg i ster contains a code sh o w i ng t he versi on of the amis-530 0 0 . 8.4.1. amis part revision c o d e table 112: ami s part revision code - 0x4 1 [65] bit name com m en t 7:0 amis_id [7:0] revision status o f the amis-5300 0 91 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 9.0 built-in test functions t he AMIS-53000 has a n u mb er of test registers. t hese registers are n o t avail a b l e to t he gen eral us er of the amis-5 300 0. ho w e v er, man y of these registers co ntrol test f eatures that are useful in the dev elo p m ent of appl ica t i ons usi ng the amis-5300 0. setup reg i sters descripti ons: t est un lo ck - a specia l cod e is requ ired to u n lock the fu ncti ons of the test registers. table 113: test unlock code - 0 x 40 [64] t est - reg i ster s that route sig nals to pi ns for moni tori ng or t u rn inter nal circuits off for test . 9.1 t m un lo ck re g i ster t he devel op er desi gni ng t he amis-5300 0 m a y d e sire t o us e some of th e t e st mod e s to monitor t he op eratio n of th e amis-5300 0 or t o determi ne the activit y of some param eter. t hese register s are locke d from use b y a c ode w o rd. t o unl ock the test registers co nt act amis w i r e l e ss prod uct sup por t to obtai n the code. e n ter th is cod e i n the unl ock reg i ster to access th e test registers. t h is r egister w i ll be reset w i th a reset of the par t and thus w i l l l o ck the user o u t of the test registers. setup reg i sters descripti ons: t est un lo ck - regist er contai ns a code abo ut t he state the AMIS-53000 i s operati ng i n . ** reg i sters w i th the ** mark can be tri mme d if the test registers are un loc k ed. bit name com m en t 7:0 unlock [7:0] code to unlock o peration of the te st registers (cont act amis for the code to unlock the test register functions) 9.2 t est reg i ster s t he follo w i ng r egisters all o w f o r sig nals to b e route d to pin s fo r monitor i n g . t h e y a l so t u rn functi ons i n the amis-5 3 000 on a nd off for measuri ng the oper ation a l p a r a meters of the amis-5300 0. 9.2.1. if amp manu al t r im a t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 9.2.2. if amp manu al t r im b t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 9.2.3. pll man u a l t r im t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 92 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 9.2.4. pll t e st mode s t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 9.2.5. pow e r dow n rf sections t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 9.2.6. anal og t e st mode digita l pa d te s t: all digital pads ex c ept s ystem clo ck out, and x i nterrupt are 1ma i/o w i t h pull ups and schmitt triggers. t he sysclock and x i nterr upt pads are 2ma outputs. a u to increment disable: t h is d i sab l es th e autom at ic i n c r ementi ng of the i 2 c register a ddress e s. it can a llo w re pe a t ed w r ite s to the same re gister, useful fo r adjus ti ng a p a rameter to opt imize its val ue. table 114: anal og test mode - 0 x 47 [71] bit name state com m en t 1 enable the test mode for de termi nation of capacitance trim value 7 c a p _ t r i m 0 1 enable the adc 1 input channel a s a direct input to the data filter 6 pipe adc1 to da ta f ilter 0 normal ope ration 1 override th e bro w n - out p o r to allow test at a n y v o ltage 5 bro w n-o u t po we r do w n 0 1 address increment disabled (iic onl y ) 4 auto increment disable 0 1 3 0 1 ignore cr y s tal control (digital clock gating) 2 ignore xta l co ntrol 0 enabled: input enabled: correspo nding o u tput 1 sssn dclock dssn xb urs t doptional rxtx xint sy sclk 1 dig pad test a 0 d i s a b l e d enabled: input enabled: correspo nding o u tput 1 doptional xb urs t rxtx sssn xint dssn 0 dig pad test b 0 disabled 9.2.7. rf t e st modes t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 9.2.8. anal og t e st mux t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 93 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 9.2.9. rf t e st mux t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 9.2.10. digita l t e st mux a table 115: digit a l test mux a - 0x4b [75] bit test pi n com m en t 1111 space q channel clk 0111 energ y d w ell ena ble 1110 mark q channel clk pll increment 0110 1 1 0 1 n c 0 1 0 1 t x e n a b l e 1100 data q cha nnel 0 1 0 0 1 0 k h z c l o c k 1011 pn code from ? 0011 software state [3 ] 7:4 mux to sclk 1111 - 00 00 1 0 1 0 s t a r t 0 0 1 0 b a n d g a p re ad y 1001 analog data out 0001 adc clk 1 0 0 0 p l l detect/data o u t 0 0 0 0 n o r m a l / s y s tem c l o c k 1111 space i channel clk 0111 code d w ell enabl e 1110 mark i channel c l k 0110 pll decrement 1101 pll detect/nc o out 0101 kicker 1100 energ y detected 0100 pll z 1011 data i channel 0011 software state [2 ] 1010 rf pll clk f e e dback 0010 pll xreset 1001 is locked (encoder) 0001 adc po w e r do wn 3:0 mux to dopt 1111 - 00 00 1000 tx data 0000 d optional 9.2.11. digita l t e st mux b table 116: digit a l test mux b - 0x4c [76] bit test pi n com m en t 1 1 1 1 e n c o d e r i n 0111 cal done kicker 1110 decoder in 0110 pll in range 1 1 0 1 s n i f f 0 1 0 1 i n t 0 1100 ? output 0 1 0 0 t r a n s m i t d o n e 1011 rf pll ( r efe r enc e clk) 0011 software state [1 ] 7:4 mux to xi nt 1111 - 00 00 1 0 1 0 b r o w n-o u t output 0 0 1 0 x t a l on 1 0 0 1 r e c e i v e d o n e 0 0 0 1 a d c d o n e 1 0 0 0 t s c l k 0 0 0 0 x i n t e r r u p t 1111 recover ed clock 0111 pa enable 1110 decoder out 0110 pll cal timer overflow 1101 encoder out 0101 pll cal enable 1100 cdr ena ble 0100 xtal p d 1011 baud clock (cdr out) 0011 software state [0 ] 1010 crc failed 0010 isstopmode 1001 rx enable 0001 watch dog reset 3:0 mux to xbu r st 1111- 000 0 1000 nc 0000 ssn normal mod e 94 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 9.2.12. digita l t e st mux c table 117: digit a l test mux c - 0x4d [77] bit test pi n com m en t 1111 encoder i n 0 1 1 1 r a m b i s t b a d 1110 decoder in 0110 ee bist done 1101 ee bist good 0101 ee bist bad 1100 ee low voltage detect 0 1 0 0 b u s y 1011 mux to cpena 0011 instruction enable 7:4 1111 - 00 00 data ssn 1 0 1 0 r o m bist done 0010 bandgap po wer do w n 1 0 0 1 r o m bist b a d 0 0 0 1 x t a l 1000 ram bist done 0000 data ssn no rma l mode 3:0 1111- 000 0 9.2.13. digita l t e st mode a t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 9.2.14. digita l t e st mode b t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 9.2.15. digita l t e st mode c t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 9.2.16. digita l t e st mode d t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 9.2.17. memory t e st mode ad dress t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 9.2.18. memory t e st mode d a ta t h is register is used for factor y testin g of the amis-5300 0 a nd has n o user functions. 95 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 10.0 register definition t able 118 bel o w c ontai ns the address for all of the intern al regist ers. once the ee has bee n w r i tten, the por st ates for the r egiste r s becom e the d a ta l a st w r itten . sho u ld the checks um fai l , all r egist ers w i ll return to t he por st ate sho w n, an d an error fl ag w i ll b e w r itte n to a status register. table 118: r egister list a d d r es s r/w hex dec regist er na me descrip tion po r sta t e ee sectio n r / w 0 x 0 0 0 command instruction r e g i s t e r 0 0 0 0 _ 0 0 0 0 6 . 2 r/w 0x01 1 status1 part status, flags 0000_0000 6.4.5.1 r/w 0x02 2 status2 part status, flags 0000_0000 6.4.5.2 r/w 0x03 3 chip address 1 upper 8 bits of chip address 0000_0000 x 7.1.1 r/w chip address 0 0x04 4 lo w e r 8 bits of chip address 0000_0000 x 7.1.2 r/w 0x05 5 rf divider integer po rtion of rf fre quenc y 0000_0000 x 6.4.1.1 r/w 0x06 6 upper 8 bits of rf fraction rf f r equenc y 2 0000_0000 x 6.4.1.2 r/w 0x07 7 rf f r equenc y 1 center 8 bits of rf fraction 0000_0000 x 6.4.1.3 r/w 0x08 8 rf f r equenc y 0 lo w e r 8 bits of rf fraction 0000_0000 x 6.4.1.4 r/w 0x09 9 peak deviation 1 upper 8 bits of f m deviation 0000_0000 x 6.4.1.5 r/w 0x0a x 10 peak deviation 0 lo w e r 8 bits of f m deviation 0000_0000 6.4.1.6 r/w 0x0b 11 data rate / form at set discrete data rate and e n coding option 0000_0000 x 7.1.3 r / w gene ral options a gene ral options for interface, p o r state, etc. x 0 x 0 c 1 2 0 0 0 0 _ 0 0 0 0 7 . 1 . 4 r/w 0x0d 13 gene ral options b gene ral options for interface, p o r state, etc. 0000_0000 x 7.1.5 r/w 0x0e 14 rx config receiver options 0000_0000 x 6.5.1.1 r/w 0x0f 15 tx config transmit options 0000_0000 x 6.6.1 r/w 0x10 idle mode option s 16 idle config x 6.7.1 r/w 0x11 17 sniff config sniff mode optio ns 1011_0100 x 6.7.2.1 r / w 0 x 1 2 1 8 sniff i n t e r v a l interval bet w een sniff cy cles 0000_1010 x 6.7.2.2 r/w 0x13 19 energ y d w ell ti me length of time to dwell in sniff mode 0000_0000 x 6.7.2.3 r/w 20 after ene rg y 6.5.1.5 number of bit times to wait for cod e 0x14 code d w ell timer 0 0 0 0 _ 0 0 0 0 x r/w 0x15 21 energ y thr e shold threshold fo r w a ke on rssi, sniff and cca 0000_0000 x 6.5.1.2 r/w 0x16 22 burst config burst transmit op tions 0000_0000 x 6.7.3 r/w 0x17 23 burst interval interval timer for burst transmit 0001_1000 x 6.7.3.1 r/w 0x18 24 output po wer output p o w er 0001_0000 x 6.6.2 r/w 0x19 25 start of f r ame b y te used fo r bur st transmit/cdr w a ke u p 0001_0000 x 7.1.6 r / w 0 x 1 a 2 6 preamble length length of cw, o r ?10? repeated in bu rst/tx (bt?s) 0 0 0 1 _ 0 0 0 0 x 6 . 6 . 3 r/w 0x1b 27 hk config housekeeping o p tions register x 6.7.4.1 r / w 0 x 1 c 2 8 hk i n t e r v a l interval timer for housekeeping x 6.7.4.2 r/w 0x1d 29 slice threshold energ y threshold for am dac mo de data slice x 6.5.1.4 r / w 0 x 1 e 3 0 filter/slice am/rssi filter setting and am slice mode x 6.5.1.4 r/w 0x1f 31 cdr options a clock and data r e cover y options a x 6.5.1.5 r/w 0x20 clock and data r e cover y options b 32 cdr options b 1000_0000 x 6.5.1.5 r/w 0x21 33 cry s tal tr im cry s tal trim 0000_0000 x 6.10.1.1 r/w 0x22 34 lna trim lna input and o u tput matching tri m 0000_0000 x 6.10.1.2 r/w 0x23 35 q u ick star t t r im quick start oscillator trim 0000_0000 x 6.10.1.3 96 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet table 118: r egister list (continu ed) a d d r es s r/w hex dec regist er na me descrip tion po r sta t e ee sectio n r/w 0x24 36 10k osc trim 10khz oscillator trim 0000_0000 x 6.10.1.4 0x25 37 analog trim bandgap and t e mp sensor trim 0000_0000 x 6.10.1.5 0x26 38 analog trim 2 capacitance trim 0010_0100 x 6.10.1.6 0x27 39 rf pll t r im pll calibration storage r egister 0100_0100 x 6.10.1.7 0x28 40 rf pll options rf pll options r egister 0000_0000 x 6.4.1.7 0x29 41 data rate 1 user defined dat a rate upp er bits 0000_0000 x 7.1.7 0x2a 42 data rate 0 user defined dat a rate lo w e r bits 0000_0000 x 7.1.8 0x2b 43 pll loop co user defined pl l detector ban d w idth 0000_0000 x 6.5.1.4 0x2c 44 cdr loo p co user defined clock recover y loop 0 0 0 0 _ 0 0 0 0 x 6 . 5 . 1 . 5 0x2d 45 user data transmitted on n o rmal interval bu rst 0000_0000 x 6.7.3.2 0x2e 46 6.7.3.3 user data transmitted on i n terrupt trigger ed burst x 0x2f 47 targn u mwakeu ps target number of w a ke u p s for x 6.7.2.4 0x30 48 crcpol y crc pol ynomial register x 7.1.9 0x31 49 defaultlop default lop regi ster x 7.1.10 0 x 3 2 5 0 c h e c k s u m eepro m c h e c k s u m x 6 . 9 . 1 0x33 51 0x34 storage r egister f o r the temp sens or reading 0000_0000 5 2 t e m p a d c 6 . 1 3 . 1 . 1 0x35 53 battery a dc storage r egister f o r the batt e r y rea d ing 0000_0000 6.13.1.2 0x36 54 rssi adc storage r egister f o r the rssi readi ng 0000_0000 6.13.1.3 0x37 55 ext1 adc storage r egister f o r the ext1 inp u t 0000_0000 6.13.1.4 0 x 3 8 5 6 e x t 2 a d c storage r egister f o r the ext2 inp u t 0 0 0 0 _ 0 0 0 0 6 . 1 3 . 1 . 5 0x39 5 7 l o o p f i l t e r 6 . 4 . 1 . 8 0x3a 58 global chip id1 7.1.11 0x3b 59 global chip id0 7.1.12 0x3c 60 software stat e 6.4.5.3 0 x 3 d 6 1 0x3e 62 0x3f 6 3 0x40 64 unlock reg 1010_0101 9.1 0x41 8.4.1 65 amis id code 0011_0001 0x42 66 if amp t r im a 9.2.1 0x43 67 if amp t r im b 9.2.2 0x44 68 manual pll trim 9.2.3 0x45 69 9.2.4 pll test mode 0x46 70 pdtestrf 9.2.5 0x47 71 analog test mod e 9.2.6 0x48 72 rftm 9.2.7 0x49 73 analog test mux 9.2.8 0x4a 74 rf test mu x 9.2.9 0x4b 75 digital test mux a 0000_0000 9.2.10 0x4c 76 digital test mux b 0000_0000 9.2.11 digital test mux c 0x4d 77 0000_0000 9.2.12 0x4e 78 dtm a 0000_0000 9.2.13 0 x 4 f 7 9 d t m b 0 0 0 0 _ 0 0 0 0 9 . 2 . 1 4 0x50 80 dtm c 0000_0000 9.2.15 0 x 5 1 8 1 d t m d 9 . 2 . 1 6 0x52 82 mtm address 9.2.17 0 x 5 3 8 3 m t m d a t a 9 . 2 . 1 8 0x54 84 pllcaltarg et pll calibration target value 0000_0000 6.10.1.8 97 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 11.0 applicati o ns t h is section intentio nal l y left b l ank. 98 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com
AMIS-53000 frequency agile transceiver data sheet 12.0 ordering information table 119: ord e r ing information orderi ng c ode produc t na me package ty p e oper a t in g tem p erat u re range indu str y a p p lic atio n differe ntia tin g feat ure shippi ng con f igur atio n 19608-00 1-xtp ( o r ?xtd ) AMIS-53000 -i/a 32 lqfp -40c to 8 5 c industrial, automotive, other ex tra l o w po w e r tape & reel (-x tp); tubes (-x td) 19608-00 2-xtp ( o r ?xtd ) AMIS-53000 -i/a 32 lqfp -40c to 8 5 c industrial, automotive, other spi interface; ganged t r ansceiver s tape & reel (-x tp); tubes (-x td) 19637-00 1-xtp ( o r ?xtd ) AMIS-53000 -m 32 lqfp -40c to 8 5 c medical ex tra l o w po w e r tape & reel (-x tp); tubes (-x td) 19637-00 2-xtp ( o r ?xtd ) AMIS-53000 -m 32 lqfp -40c to 8 5 c medical spi interface; ganged t r ansceiver s tape & reel (-x tp); tubes (-x td) 13.0 company or product inquiries for more infor m ation about ami semicond u c tor, our techn o lo g y an d our prod ucts, visit our w eb site at : http:// w w w . a m is.com . north americ a t e l: + 1 .208.23 3.469 0 f a x: + 1 .208.2 3 4 .679 5 europe t e l: + 32 (0) 55.33.22.1 1 f a x: + 32 (0) 55 .31.81.1 2 dev i ces sold by amis are cov e red by the w a rranty and p a ten t indem nifi ca tio n prov isions appea ring in its terms o f sale only . am is make s no w a rranty , ex press, sta t u t ory , implied or by descri p tion , regardin g the in formation se t forth herein or regardi n g t he fre edom of th e described dev ice s from pa ten t infr in gem ent. am is m a kes n o w a rranty o f merchan tabili ty or fitne ss for a n y purpose s . amis r e se rves the righ t to di scontinue p r odu ctio n and chan ge specifi c ati ons and pr i c e s at any time and w i thout no ti ce. ami semicondu ctor's p r oducts a r e intende d for u s e in comme rcial ap plicatio ns. applica t ion s re quiri ng ex tended tempe r ature r ange , u nu su al env ironmental re quirements, or high reliabili ty applicati o ns, su ch a s mili tary , medical li fe-suppo rt or li fe- s u s tai n i ng equipment, are spe c ifi c ally not re com m ended w i thout ad ditional pro c essing by amis for su ch applica t ion s . copyright ?2005 ami se micondu ctor, inc. 99 a m i se m i co nd uc t o r ? aug. 05, rev. 1.0 www.amis.com

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