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freescale semiconductor document number: MMA8653FC data sheet: product preview rev. 0, 08/2012 ? 201 2 freescale semiconductor, inc. all righ ts reserved. this document contains information on a new product. specifications and information herein are subject to c hange without notice. xtrinsic MMA8653FC 3-axis, 10-bit digital accelerometer the MMA8653FC is an intelligent, low-power, three-axis, capacitive micromachined accelerometer with 10 bits of resolution. this accelerometer is packed with embedded functions with flexible user programmable options, configurable to two interrupt pins. embedded interrupt functions enable overall power savings, by relieving the host processor from continuously polling data. there is access to either low-pass or hi gh-pass filtered data, which minimizes the data analysis required for jolt detection and faster transitions. the device can be configured to generate inertial wake-up interrupt signals from any combination of the configurable embedded functions, enabling the MMA8653FC to monitor inertial events and to remain in a low-power mode during periods of inactivity. the MMA8653FC is available in a small 10 -pin dfn package (2 mm x 2 mm x 1 mm). features ? 1.95v to 3.6v supply voltage ? 1.62v to 3.6v digital interface voltage ? 2g, 4g, and 8g dynamically selectable full-scale ranges ? output data rates (odr) from 1.56 hz to 800 hz ? 10-bit digital output ?i 2 c digital output interface with programmable interrupts ? one embedded channel of configurable motion detection (freefall) ? orientation (portrait/landscape) detection with default hysteresis ? automatic odr change triggered by the auto-wake / sleep state change ?self-test typical applications ? ecompass applications tilt compensation ? static orientation detection (portrait/landscape, up/down, left/right, back/ f ront position identification) ? notebook, ereader, and laptop tumble and freefall detection ? real-time orientation detection (virtual reality and gaming 3d user position feedback) ? real-time activity analysis (pedometer step counting, freefall drop detection for hdd, dead-reckoning gps backup) ? motion detection for portab le product power saving (auto-sleep and au to-wake for cell phone, pda, gps, gaming) ? shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging) ? user interface (menu scrolling by orientation change) ordering information part number temperature range package description shipping MMA8653FCr1 -40c to +85c dfn-10 tape and reel MMA8653FC top view pin connections vdd scl int1 byp int2 sda gnd gnd vddio gnd 1 2 3 4 5 10 9 8 7 6 10-pin dfn 2 mm x 2 mm x 1 mm case 2162 top and bottom view MMA8653FC MMA8653FC
MMA8653FC sensors 2 freescale semiconductor, inc. feature comparison of the MMA8653FC devices feature list mma8652fc MMA8653FC digital resolution (bits) 12 10 digital sensitivity in 2g mode (counts/g) 1024 256 low-power mode yes yes auto-wake yes yes auto-sleep yes yes 32-level fifo yes no low-pass filter yes yes high-pass filter yes no transient detection with high-pass filter yes no orientation detection portrait to landscape = 30, landsc ape to portrait = 60, and fixed 45 threshold yes yes programmable orientation detection yes no data-ready interrupt yes yes single-tap interrupt yes no double-tap interrupt yes no directional tap interrupt yes no freefall/motion interrupt yes yes transient interrupt with direction yes no
MMA8653FC sensors freescale semiconductor, inc. 3 contents 1 block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 orientation definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 recommended application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 mechanical and electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 i2c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 zero-g offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 device calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 8-bit or 10-bit data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 low power modes vs. high resolution modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 auto-wake/sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5 freefall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.6 orientation detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.7 interrupt register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.8 serial i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 register bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.5 portrait/landscape embedded function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6 motion and freefall embedded function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.7 auto-wake/sleep detectio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.8 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.9 data calibration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7 mounting guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1 overview of soldering considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.2 halogen content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.3 pcb mounting/soldering recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8 tape and reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.1 tape dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.2 device orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
MMA8653FC sensors 4 freescale semiconductor, inc. 1 block diagram and pin descriptions 1.1 block diagram figure 1. mma8653 block diagram c-to-v converter sda scl i 2 c embedded functions c-to-v internal osc clock gen adc converter vddio gnd x-axis transducer y-axis transducer z-axis transducer freefall/motion detection orientation with hysteresis and z-lockout auto-wake/auto-sleep configurable with debounce counter and multiple motion interrupts for control auto-wake/sleep active mode sleep vdd int1 int2 mode options low power low noise + power high resolution normal mode options low power low noise + power high resolution normal active mode wake byp interface mux voltage regulator gain aaf anti-aliasing filter
MMA8653FC sensors freescale semiconductor, inc. 5 1.2 pin descriptions figure 2. direction of the detectable accelerations 1.3 orientation definitions figure 3 shows the device configuration in the 6 different orientation modes. there are several registers to configure the orientation detection and are described in detail in the register setting section. figure 3. landscape/portrait orientation direction of the detectable accelerations (bottom view) x y z 1 (top view) 1 5 6 10 vdd scl int1 byp int2 sda gnd vddio gnd gnd top view pu earth gravity pin 1 x @ 0g y @ -1g z @ 0g xout @ 1g yout @ 0g zout @ 0g xout @ 0g yout @ 1g zout @ 0g xout @ -1g yout @ 0g zout @ 0g ll pd lr side view front xout @ 0g yout @ 0g zout @ 1g back xout @ 0g yout @ 0g zout @ -1g pu = portrait up lr = landscape right pd = portrait down ll = landscape left
MMA8653FC sensors 6 freescale semiconductor, inc. 1.4 recommended application diagram figure 4. application diagram table 1. pin descriptions pin # pin name description notes 1 vdd power supply device power is supplied through th e vdd line. power supply decoupling capacitors should be placed as near as possible to the pins 1 and 8 of the device. 2scli 2 c serial clock 7-bit i 2 c device address is 0x1d. the control signals scl and sda are not tolerant of voltages more than vddio + 0.3v. if vddio is removed, then the control signals scl and sda will clamp any logic signals with their internal esd protection diodes. the sda and scl i 2 c connections are open drain, and therefore usually require a pullup resistor. 3 int1 interrupt 1 the interrupt source and pin settings are user-programmable through the i 2 c interface. 4 byp internal regulator output capacitor connection 5 int2 interrupt 2 see int1. 6 gnd ground 7 gnd ground 8 vddio digital interface power supply 9 gnd ground 10 sda i 2 c serial data see scl. vdd scl int1 byp int2 sda vddio 1 2 10 9 8 7 6 0.1 f 1 f 0.1 f 3 4 5 top view vddio vddio 1 k 1 k note: 1 k pullup resistors on int1/int2 are only needed for open-drain. .1 f MMA8653FC
MMA8653FC sensors freescale semiconductor, inc. 7 2 mechanical and electr ical specifications 2.1 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. exposure to maximum rating conditions for extended periods may affect device reliability. table 2. maximum ratings rating symbol value unit maximum acceleration (all axes, 100 s) g max 10,000 g supply voltage vdd -0.3 to + 3.6 v input voltage on any control pin (scl, sda) vin -0.3 to vddio + 0.3 v drop test d drop 1.8 m operating temperature range t op -40 to +85 c storage temperature range t stg -40 to +125 c table 3. esd and latch-up pr otection characteristics rating symbol value unit human body model hbm 2000 v machine model mm 200 v charge device model cdm 500 v latch-up current at t = 85c ? 100 ma cause the part to otherwise fail. this device is sensitive to mechani cal shock. improper handling can cause permanent damage of the part or this part is esd-sensitive. improper handl ing can cause perman ent damage to the part.
MMA8653FC sensors 8 freescale semiconductor, inc. 2.2 mechanical characteristics table 4. mechanical characteristi cs at vdd = 2.5v, vddio = 1.8v, t = 25c unless otherwise noted parameter test conditions symbol min typ max unit measurement range fs[1:0] set to 00 2g mode fs 2 g fs[1:0] set to 01 4g mode 4 fs[1:0] set to 10 8g mode 8 sensitivity fs[1:0] set to 00 2g mode so 256 counts/g fs[1:0] set to 01 4g mode 128 fs[1:0] set to 10 8g mode 64 sensitivity accuracy soa 2.64 % sensitivity change vs. temperature fs[1:0] set to 00 2g mode tcso 0.04 %/c fs[1:0] set to 01 4g mode fs[1:0] set to 10 8g mode zero-g level offset accuracy (1) 1. before board mount. fs[1:0] 2g, 4g, 8g tyoff 40 mg zero-g level offset accuracy post-board mount (2) 2. post-board mount offset specifications are based on an 8-layer pcb, relative to 25c. fs[1:0] 2g, 4g, 8g tyoffpbm 60 mg zero-g level change vs. temperature -40c to 85c tcoff 0.3 mg/c self-test output change (3) x y z 3. self-test is one direction only. fs[1:0] set to 0 4g mode vst 50 50 50 lsb odr accuracy 2 mhz clock -20 +20 % output data bandwidth bw odr/3 odr/2 hz output noise normal mode odr = 400 hz noise 216 g/ hz operating temperature range top -40 +85 c package weight tbd g
MMA8653FC sensors freescale semiconductor, inc. 9 2.3 electrical characteristics table 5. electrical characteristi cs at vdd = 2.5v, vddio = 1.8v, t = 25c unless otherwise noted parameter test conditions symbol min typ max unit supply voltage vdd (1) 1. there is no requirement for power supply sequencing. the vddio input voltage can be higher than the vdd input voltage. 1.95 2.5 3.6 v interface supply voltage vddio (1) 1.62 1.8 3.6 v low power mode odr = 1.56 hz i dd lp 6 a odr = 12.5 hz 6 odr = 50 hz 14 odr = 100 hz 24 odr = 200 hz 44 odr = 400 hz 85 odr = 800 hz 165 normal mode odr = 1.56 hz i dd 24 a odr = 12.5 hz 24 odr = 50 hz 24 odr = 100 hz 44 odr = 200 hz 85 odr = 400 hz 165 odr = 800 hz 165 current during boot sequence, 0.5 msec max duration using recommended bypass cap vdd = 2.5v idd boot 1 ma value of capacitor on byp pin -40c to 85c cap 75 100 470 nf standby mode current at 25c vdd = 2.5v, vddio = 1.8v standby mode i dd stby 1.8 5 a standby mode current over temperature range vdd = 2.5v, vddio = 1.8v standby mode i dd stby tbd tbd a digital high level input voltage scl, sda vih 0.75*vddio v digital low level input voltage scl, sda vil 0.3*vddio v high level output voltage int1, int2 i o = 500 a voh 0.9*vddio v low level output voltage int1, int2 i o = 500 a vol 0.1*vddio v low level output voltage sda i o = 500 a vols 0.1*vddio v output source current voltage high level vout = 0.75 x vdd, vdd = 2.5v i source 3m a output sink current voltage high level vout = 0.25 x vdd, vdd = 2.5v i sink 3m a power-on ramp time tpu 0.001 1000 ms time from vddio on and vdd > vmin until i 2 c is ready for operation cbyp = 100 nf bt 350 500 s turn-on time (standby to first sample available) ton 2/odr + 1 (2) ms turn-on time (power down to first sample available) to n 2/odr + 2 (2) ms
MMA8653FC sensors 10 freescale semiconductor, inc. 2.4 i 2 c interface characteristics figure 5. i 2 c slave timing 2. note that the first sample is typicall y not very precise; only the second or thir d or fourth sample (depending on odr/mods se ttings) has full precision. table 6. i 2 c slave timing values (1) 1. all values referred to vih (min) and vil (max) levels. parameter symbol i 2 c fast mode unit min max scl clock frequency f scl 0 400 khz bus free time between stop and start condition t buf 1.3 s (repeated) start hold time t hd;sta 0.6 s (repeated) start setup time t su;sta 0.6 s stop condition setup time t su;sto 0.6 s sda data hold time t hd;dat 0.05 0.9 (2) 2. this device does not stretch the low period (t low ) of the scl signal. s sda valid time (3) 3. t vd;dat = time for data signal from scl low to sda output. t vd;dat 0.9 (2) s sda valid acknowledge time (4) 4. t vd;ack = time for acknowledgement signal from scl low to sd a output (high or low, depending on which one is worse). t vd;ack 0.9 (2) s sda setup time t su;dat 100 ns scl clock low time t low 1.3 s scl clock high time t high 0.6 s sda and scl rise time t r 20 + 0.1 c b (5) 5. c b = total capacitance of one bus line in pf. 300 ns sda and scl fall time t f 20 + 0.1 c b (5) 300 ns pulse width of spikes on sda and scl that must be suppressed by internal input filter t sp 05 0n s handbook, full pagewidth msc610 s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta
MMA8653FC sensors freescale semiconductor, inc. 11 3 terminology 3.1 sensitivity the sensitivity is repr esented in counts/g. ? in 2g mode, sensitivity = 256 counts/g. ? in 4g mode, sensitivity = 128 counts/g. ? in 8g mode, sensit ivity = 64 counts/g. 3.2 zero-g offset zero-g offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if the sensor is stationa ry. a sensor stationary on a horizontal surface will measure 0g in x- axis and 0g in y-axis, whereas the z-axis will measure 1g. the output is ideally in the middle of the dynamic range of the s ensor (content of out registers 0x00, data expressed as a 2's complement number). a deviation from ideal va lue in this case is called zero-g offset. offset is to some extent a result of st ress on the mems sensor, and therefore the of fset can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. 3.3 self-test self-test can be used to verify the transducer and signal c hain functionality without the need to apply external mechanical stimulus. when self-test is activated: ? an electrostatic actuation force is applied to the sensor, simulating a small acceleration. in this case, the sensor outputs w ill exhibit a change in their dc levels which, are related to the selected full scale through the device sensitivity. ? the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force.
MMA8653FC sensors 12 freescale semiconductor, inc. 4 modes of operation figure 6. operating modes for MMA8653FC some registers are reset when transitioning from standby to active. these registers are all noted in the device memory map register table. the sleep and wake modes are active mode s. for more information about how to use the sleep and wake modes and how to transition between these modes, see section 5, ?functionality? . table 7. operating modes mode i 2 c bus state vdd vddio description off powered down <1.8v vddio can be > vdd ? the device is powered off. ? all analog and digital blocks are shutdown. ?i 2 c bus inhibited. standby i 2 c communication with MMA8653FC is possible on vddio = high vdd = high active bit is cleared ? only digital bl ocks are enabled. ? analog subsystem is disabled. ? internal clocks disabled. active (wake/sleep) i 2 c communication with MMA8653FC is possible on vddio = high vdd = high active bit is set all blocks are enabled (digital, analog). sleep wake standby off active
MMA8653FC sensors freescale semiconductor, inc. 13 5 functionality the MMA8653FC is a low-power, digital output 3-axis linear accelerometer with a i 2 c interface, and has embedded logic that is used to detect events and notify an exter nal microprocessor over interrupt lines. ? 8-bit or 10-bit data ? four different oversampling options that allow for the optimum resolution vs. current consumption trade-off to be made for a given application ? low power and au to-wake/sleep modes for reduci ng current consumption ? freefall/motion detection (1 channel) ? single default angle for portrait landscape detecti on algorithm, for addressing screen orientation ? two independent interrupt out put pins that are programmable among 4 interrupt sources (data ready, freefall/motion, orientation, auto-wake) all functionality is available in 2g, 4g or 8g dynamic measurement ranges. there are many configuration settings for enabling a ll of the different functions. separate application notes are availabl e to help configure the device for each embedded functionality. 5.1 device calibration the device is factory calibrated for sensitivity and zero-g offset for each axis. the trim values are stored in non-volatile me mory (nvm). on power-up, the trim parameters are read from nvm and a pplied to the circuitry. in norma l use, further calibration in t he end application is not necessary. however, the MMA8653FC allows you to adjust the offset for each axis after power-up, by changing the default offset values. the user offset adjustments are stored in 3 volatile 8-bit registers (off_x, off_y, off_z). 5.2 8-bit or 10-bit data the measured acceleration data is stored in the following registers as 2?s complement 10-bit numbers: ? out_x_msb, out_x_lsb ? out_y_msb, out_y_lsb ? out_z_msb, out_z_lsb the most significant 8-bits of each axis are stored in out_x (y , z)_msb, so applications needing only 8-bit results can use these 3 registers (and ignore the out_x/y/z_lsb registers). to do th is (use only 8-bit results), the f_read bit in ctrl_reg1 must be set. when the f_read bit is cleared, the fast read mode is disabled. ? when the full-scale is set to 2g , the measurement range is -2g to +1.996g, and each count corresponds to (1/256)g (3.8mg) at 10-bit resolution. ? when the full-scale is set to 4g , the measurement range is -4g to +3.99 2g, and each count corresponds to (1/128)g ? (7.8mg) at 10-bit resolution. ? when the full-scale is set to 8g , the measurement range is -8g to +7.984g, and each count corresponds to (1/64)g (15.6 mg) at 10-bit resolution. ? if only the 8-bit results are used , then the resolution is reduced by a factor of 16. for more information about the data manipulation between data formats and modes, see application note an4083, data manipulation and basic settings for xtrinsic mma865xfc accelerometers . there is a device driver available that can be used with the sensor toolbox demo board (lfstbeb865xfc) with this application note. table 8. accelerometer 10-bit output data 10-bit data range 2g (3.9 mg) range 4g (7.8 mg) range 8g (15.6 mg) 01 1111 1111 1.996g +3.992g +7.984g 01 1111 1110 1.992g +3.984g +7.968g ?? ? ? 00 0000 0001 0.003g +0.007g +0.015g 00 0000 0000 0.000g 0.000g 0.000g 11 1111 1111 -0.003g -0.007g -0.015g ?? ? ? 10 0000 0001 -1.961g -3.992g -7.984g 10 0000 0000 -2.000g -4.000g -8.000g
MMA8653FC sensors 14 freescale semiconductor, inc. 5.3 low power modes vs. high resolution modes the MMA8653FC can be optimized for lower power modes or for hig her resolution of the output data. one of the oversampling schemes of the data can activated when mods = 10 in register 0x2b, which will improve the resolu tion of the output data only. the highest resolution is achieved at 1.56 hz. there is a trade-off between low power and high resolution. low power can be achieved when the oversampling rate is reduced. when mods = 11, the lowest power is achieved. the lowest power is achieved when the sample rate is set to 1.56 hz. 5.4 auto-wake/sleep mode the MMA8653FC can be configured to transition between sample rates (with their respective current consumption) based on four of the interrupt functions of the device. the advantage of using the auto-wake/sl eep is that the syste m can automatically transition to a higher sample rate (higher current consumption) when needed, but spends the majority of the time in the sleep mode (lower current) when the device does not require higher sampling rates. ? auto-wake refers to the device being triggered by one of the inte rrupt functions to transition to a higher sample rate. this may also interrupt the processor to transiti on from a sleep mode to a higher po wer mode. ? sleep mode occurs after the accelerometer has not detected an interrupt for longer than the user-definable timeout period. the device will transition to the specified lower sample rate. it ma y also alert the processor to go into a lower power mode, t o save on current during this period of inactivity. the interrupts that can wake the device from sleep are the following: orientation detection, and fr eefall/motion detection. the interrupts that can keep the device from falling asleep are the same interrupts that can wake the device. 5.5 freefall detection MMA8653FC has a flexible interrupt architecture for detecting either a freefall or a motion. ? freefall can be enabled where the set threshold must be less than the configured threshold. ? motion can be enabled where the set threshold must be greater than the configured threshold. 8-bit data range 2g (15.6 mg) range 4g (31.25 mg) range 8g (62.5 mg) 0111 1111 1.984g +3.968g +7.937g 0111 1110 1.968g +3.937g +7.875g ?? ? ? 0000 0001 +0.015g +0.031g +0.062g 0000 0000 0.000g 0.000g 0.000g 1111 1111 -0. 015g -0.031g -0.062g ?? ? ? 1000 0001 -1.984g -3.968g -7.937g 1000 0000 -2.000g -4.000g -8.000g table 9. accelerometer 8-bit output data 8-bit data range 2g (15.6 mg) range 4g (31.25 mg) range 8g (62.5 mg) 0111 1111 1.9844g +3.9688g +7.9375g 0111 1110 1.9688g +3.9375g +7.8750g ?? ? ? 0000 0001 +0.0156g +0.0313g +0.0625g 0000 0000 0.000g 0.0000g 0.0000g 1111 1111 -0. 0156g -0.0313g -0.0625g ?? ? ? 1000 0001 -1.9844g -3.9688g -7.9375g 1000 0000 -2.0000g -4.0000g -8.0000g table 8. accelerometer 10-bit output data (continued)
MMA8653FC sensors freescale semiconductor, inc. 15 the motion configuration has the option of enabling or disabling a high-pass filter to eliminate tilt data (static offset); the freefall configuration does not use the high-pass filter. MMA8653FC has an interrupt architecture for detecting a freefall. ? freefall can be enabled where the set threshold must be less than the configured threshold. the freefall configuration does not use a high-pass filter. 5.5.1 freefall detection the detection of ?freefall? invo lves the monitoring of the x, y , and z axes for the condition where the acceleration magnitude is below a user-specified threshold for a user-definable amount of time . the usable threshold ranges are normally between 100 mg and 500 mg. 5.6 orientation detection the MMA8653FC incorporates an advanced algorithm for orientati on detection (ability to detect all 6 orientations), with one default trip point setting. the transition from portrait to land scape is at a fixed 45 threshold angle and at a fixed 15 hys teresis angle. this allows for smooth transition from portrait to landscape at approximately 30, and then from landscape to portrait a t approximately 60. the MMA8653FC orientation detection algorithm confirms the reli ability of the function with a configurable z-lockout angle. based on the known functionality of linear accelerometers, it is not possible to rotate the device about the z-axis, to detect change in acceleration at slow angular speeds. the angle at which the device no longer detects the orientation change is referred to a s the ?z-lockout angle?. the device operates at a fixed 29 angle from the flat position, with an accuracy of 2. ? figure 7 shows the definition of the orientat ions (pu, pd, ll, lr, back, front). ? figure 8 shows the definitions of the trip an gles, going from landscape to portrait and then from portrait to landscape. figure 7. landscape/portrait orientation top view pu earth gravity pin 1 x @ 0g y @ -1g z @ 0g xout @ 1g yout @ 0g zout @ 0g xout @ 0g yout @ 1g zout @ 0g xout @ -1g yout @ 0g zout @ 0g ll pd lr side view front xout @ 0g yout @ 0g zout @ 1g back xout @ 0g yout @ 0g zout @ -1g
MMA8653FC sensors 16 freescale semiconductor, inc. figure 8. landscape to portrait transition figure 9 shows the z-angle lockout region. . figure 9. z-tilt angle lockout transition 5.7 interrupt register configurations there are 4 configurable interrupts in the MMA8653FC: data ready, motion/freefall, orientation, and auto-sleep events. figure 10. system interrupt generation portrait landscape to portrait 90 trip angle = 60 0 landscape portrait portrait to landscape 90 trip angle = 30 0 landscape upright normal 90 z-lock = 29 0 flat detection region lockout region when lifting the device upright from the flat position, the device will be active for orientation detection as low as 29 from 0 flat. this is the only setting available. interrupt controller data ready motion/freefall orientation auto-sleep int enable int cfg int1 int2 77 4 configurable interrupts these 4 interrupt sources can be routed to one of two interrupt pins. the interrupt source must be enabled and configured. if the event flag is asserted because the event condition is detected, then the corresponding interrupt pin (int1 or int2) will assert.
MMA8653FC sensors freescale semiconductor, inc. 17 ? the MMA8653FC features an interrupt signal that indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device. ? the MMA8653FC may also be configured to generate other interrupt signals accordingly, to the programmable embedded functions of the device for motion, freefall, and orientation. 5.8 serial i 2 c interface acceleration data may be accessed through an i 2 c interface, thus making the device particul arly suitable for direct interfacing to a microcontroller. the acceleration data and configuration re gisters embedded inside the MMA8653FC are accessed through the i 2 c serial interface ( table 10, ?serial interface pins "). ? to enable the i 2 c interface, vddio line must be tied high (i.e., to the interface supply voltage). if vdd is not present and vddio is present, then the MMA8653FC is in off mode?and communications on the i 2 c interface are ignored. ?the i 2 c interface may be used for co mmunications between other i 2 c devices; the MMA8653FC does not affect the i 2 c bus. the i 2 c interface is compliant with fast mode (400 khz), and normal mode (100 khz) i 2 c standards ( table 6, ?i2c slave timing values "). i 2 c operation: 1. the transaction on the bus is started through a start condition (start) signal. a start condition is defined as a high-to- low transition on the data line while the scl line is held high. after start has been transmitted by the master, the bus is considered busy. 2. the next byte of data transmitted after start contains the slave address in the first 7 bits, and the 8th bit tells whether the master is receiving data from the slave or is transmitting data to the slave . 3. after a start condition and when an address is sent, each device in the system compares the first 7 bits with its address. if the device?s address matches the sent address, then the device considers itself addressed by the master. 4. the 9th clock pulse following the slave address byte (and each subsequent byte) is the acknowledge (ack). the transmitter must release the sda line during the ack period. the receiver must then pull the data line low, so that it remains stable low during the high period of the acknowledge clock period. 5. a master may also issue a repeated start during a data transfer. the MMA8653FC expects repeated starts to be used to randomly read from specific registers. 6. a low-to-high transition on the sda line while the scl line is high is defined as a stop condition (stop). a data transfer is always terminated by a stop . the MMA8653FC's standard slave address is 0011101 or 0x01d. the slave addresses are factory programmed; alternate addresses are available upon request. 5.8.1 single byte read 1. the transmission of an 8-bit command begins on the falling edge of scl. after the 8 clock cycles are used to send the command, note that the data returned is sent with the msb first after the data is received. figure 11 "single byte read timing (i 2 c)" shows the timing diagram fo r the accelero meter 8-bit i 2 c read operation. 2. the master (or mcu) transmits a start condition (st) to t he MMA8653FC [slave address (0x1d), with the r/w bit set to ?0? for a write], and the MMA8653FC sends an acknowledgement. table 10. serial interface pins pin name pin description notes scl i 2 c serial clock there are two signals associated with the i 2 c bus; the serial clock line (scl) and the serial data line (sda). ? sda is a bidirectional line used for sending and receiving the data to/from the interface. ? external pullup resistors connected to vddio are expected for sda and scl. when the bus is free, both scl and sda lines are high. sda i 2 c serial data table 11. i 2 c device address sequence command [6:0] device address [6:0] device address r/w 8-bit final value read 0011101 0x1d 1 0x3b write 0011101 0x1d 0 0x3a
MMA8653FC sensors 18 freescale semiconductor, inc. 3. next the master (or mcu) transmits the address of the register to read, and the MMA8653FC sends an acknowledgement. 4. the master (or mcu) transmits a repeated start conditio n (sr) and then addresses the MMA8653FC (0x1d), with the r/ w bit set to ?1? for a read from the previously selected register. 5. the slave then acknowledges and transmits the data from the requested register. the master does not acknowledge (nak) the transmitted data, but transmits a stop condition to end the data transfer. figure 11. single byte read timing (i 2 c) for the following subsections, use the following legend. 5.8.2 multiple byte read (see table 11, ?i 2 c device address sequence " for next auto-increment address.) 1. when performing a multi-byte read or ?burst read?, t he MMA8653FC automatically increments the received register address commands after a read command is received. 2. after following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each MMA8653FC acknowledgment (ak) is received, 3. until a no acknowledge (nak) occurs from the master, 4. followed by a stop condition (sp), which signals the end of transmission. figure 12. multiple byte read timing (i 2 c) 5.8.3 single byte write 1. to start a write command, the master transmits a start condition (st) to the MMA8653FC, slave address ($1d) with the r/w bit set to ?0? for a write, 2. the MMA8653FC sends an acknowledgement. 3. next the master (mcu) transmits the address of the register to wr ite to, and the MMA8653FC sends an acknowledgement. 4. then the master (or mcu) transmits the 8-bit data to wr ite to the designated register, and the MMA8653FC sends an acknowledgement that it has received the data. because th is transmission is complete, the master transmits a stop condition (sp) to the data transfer. the data sent to the MMA8653FC is now stored in the appropriate register. master st device address[7:1] w register address[7:0] sr device address[7:1] r nak sp slave ak ak ak data[7:0] legend st: start condition sp: stop condition nak: no acknowledge w: write = 0 sr: repeated start condition ak: acknowledge r: read = 1 master st device address[7:1] w register address[7:0] sr device address[7:1] r ak slave ak ak ak data[7:0] master ak ak nak sp slave data[7:0] data[7:0] data[7:0] master st device address[7:1] w register address[7:0] data[7:0] sp slave ak ak ak
MMA8653FC sensors freescale semiconductor, inc. 19 figure 13. single byte write timing (i 2 c) 5.8.4 multiple byte write (see table 11, ?i 2 c device address sequence " for next auto-increment address.) 1. after a write command is received, the MMA8653FC automatically increments the received register address commands. 2. therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers after each MMA8653FC acknowledgment (ack) is received. figure 14. multiple by te write timing (i 2 c) master st device address[7:1] w register address[7:0] data[7:0] data[7:0] sp slave ak ak ak ak
MMA8653FC sensors 20 freescale semiconductor, inc. 6 register descriptions 6.1 register address map note: auto-increment addresses that are not a simple increment are highlighted in bold . the auto-increment addressing is only enabl ed when device registers are read using i 2 c burst read mode . the internally stored auto-increment address is cleared whenever an i 2 c stop condition is detected. table 12. MMA8653FC register address map field type register address auto-increment address default hex value comment f_read = 0 f_read = 1 status (1)(2) 1. the register data is only valid in active mode. 2. register contents are reset when transition from standby to active mode occurs. r 0x00 0x01 00000000 0x00 real time status out_x_msb (1) r 0x01 0x02 0x03 output ? [7:0] are 8 msbs of 10-bit sample. out_x_lsb (1) r 0x02 0x03 0x00 output ? [7:6] are 2 lsbs of 10-bit real-time sample out_y_msb (1) r 0x03 0x04 0x05 output ? [7:0] are 8 msbs of 10-bit real-time sample out_y_lsb (1) r 0x04 0x05 0x00 output ? [7:6] are 2 lsbs of 10-bit real-time sample out_z_msb (1) r 0x05 0x06 0x00 output ? [7:0] are 8 msbs of 10-bit real-time sample out_z_lsb (1) r 0x06 0x00 output ? [7:6] are 2 lsbs of 10-bit real-time sample reserved r 0x07?0x0a ? 00000000 0x00 reserved. read return 0x00. sysmod r 0x0b 0x0c 00000000 0x00 current system mode int_source (1)(2) r 0x0c 0x0d 00000000 0x00 interrupt status who_am_i (3) 3. register contents are preserved when transit ion from active to standby mode occurs. r 0x0d 0x0e 01001010 0x5a device id (0x5a) xyz_data_cfg (3)(4) 4. modification of this register?s content can only occur when device is in standby mode, except ctrl_reg1 active bit and ctrl_r eg2 rst bit. r/w 0x0e 0x0f 00000000 0x00 dynamic range settings reserved r 0x0f ? 00000000 0x00 reserved. read return 0x00. pl_status (1)(2) r 0x10 0x11 00000000 0x00 landscape/portrait orientation status pl_cfg (3)(4) r/w 0x11 0x12 10000000 0x80 landscape/portrait configuration. pl_count (3)(4) r/w 0x12 0x13 00000000 0x00 landscape/portrait debounce counter pl_bf_zcomp (3) r 0x13 0x14 01000100 0x44 back/front, z-lock trip threshold pl_ths_reg (3) r 0x14 0x15 10000100 0x84 portrait to landscape trip angle ff_mt_cfg (3)(4) r/w 0x15 0x16 00000000 0x00 freefall/motion functional block configuration ff_mt_src (1)(2) r 0x16 0x17 00000000 0x00 freefall/motion event source register ff_mt_ths (3)(4) r/w 0x17 0x18 00000000 0x00 freefall/motion threshold register ff_mt_count (3)(4) r/w 0x18 0x19 00000000 0x00 freefall/motion debounce counter reserved r 0x19?0x28 ? 00000000 0x00 reserved. read return 0x00. aslp_count (3)(4) r/w 0x29 0x2a 00000000 0x00 counter setting for auto-sleep/wake ctrl_reg1 (3)(4) r/w 0x2a 0x2b 00000000 0x00 data rates, active mode. ctrl_reg2 (3)(4) r/w 0x2b 0x2c 00000000 0x00 sleep enable, os modes, rst, st ctrl_reg3 (3)(4) r/w 0x2c 0x2d 00000000 0x00 wake from sleep, ipol, pp_od ctrl_reg4 (3)(4) r/w 0x2d 0x2e 00000000 0x00 interrupt enable register ctrl_reg5 (3)(4) r/w 0x2e 0x2f 00000000 0x00 interrupt pin (int1/int2) map off_x (3)(4) r/w 0x2f 0x30 00000000 0x00 x-axis offset adjust off_y (3)(4) r/w 0x30 0x31 00000000 0x00 y-axis offset adjust off_z (3)(4) r/w 0x31 0x0d 00000000 0x00 z-axis offset adjust
MMA8653FC sensors freescale semiconductor, inc. 21 6.2 register bit map note: bits showing ??? can read as either 0 or 1, and these bits have no definition. reg field definition typ e bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 status data status r zyxow zow yow xow zyxdr zdr ydr xdr 01 out_x_msb 10-bit x data r xd9 xd8 xd7 xd6 xd5 xd4 xd3 xd2 02 out_x_lsb 10-bit x data r xd1 xd0 0 0 0 0 0 0 03 out_y_msb 10-bit y data r yd9 yd8 yd7 yd6 yd5 yd4 yd3 yd2 04 out_y_lsb 10-bit y data r yd1 yd0 0 0 0 0 0 0 05 out_z_msb 10-bit z data r zd9 zd8 zd7 zd6 zd5 zd4 zd3 zd2 06 out_z_lsb 10-bit z data r zd1 zd0 0 0 0 0 0 0 07? 0a reserved ? r 0 0 0 0 0 0 0 0 0b sysmod system mode r 0 0 0 0 0 0 sysmod1 sysmod0 0c int_source interrupt status r src_aslp 0 0 src_lndprt 0 src_ff_mt 0 src_drdy 0d who_am_i id register r 0 1 0 1 1 0 1 0 0e xyz_data_cfg data config r/ w 00 0 0 0 0 f s 1f s 0 0f reserved ? r ? ? ? ? ? ? ? ? 10 pl_status portrait landscape status r newlp lo 0 0 0 lapo[1] lapo[0] bafro 11 pl_cfg portrait landscape configuration r/ w dbcntm pl_en 0 0 0 0 0 0 12 pl_count portrait landscape debounce r/ w dbnce[7] dbnce[6] dbnce[5] dbnce[4] d bnce[3] dbnce[2] dbnce[1] dbnce[0] 13 pl_bf_zcomp portrait landscape back/front z comp r0 1 0 0 0 1 0 0 14 pl_ths_reg portrait landscape threshold r1 0 0 0 0 1 0 0 15 ff_mt_cfg freefall/motion config r/ w ele oae zefe yefe xefe 0 0 0 16 ff_mt_src freefall/motion status r ea 0 zhe zhp yhe yhp xhe xhp 17 ff_mt_ths freefall/motion threshold r/ w dbcntm ths6 ths5 ths4 ths3 ths2 ths1 ths0 18 ff_mt_count freefall/motion debounce r/ w d7 d6 d5 d4 d3 d2 d1 d0 19? 28 reserved ? r ? ? ? ? ? ? ? ? 29 aslp_count counter setting for auto-sleep/wake r/ w d7 d6 d5 d4 d3 d2 d1 d0 2a ctrl_reg1 control reg1 r/ w aslp_rate1 aslp_rate0 dr2 dr1 dr0 0 f_read active 2b ctrl_reg2 control reg2 r/ w st rst ? smods1 smods0 slpe mods1 mods0 2c ctrl_reg3 control reg3 r/ w ? ? wake_lndprt ? wake_ff_mt 0 ipol pp_od 2d ctrl_reg4 control reg4 r/ w int_en_aslp ? ? int_en_lndprt ? int_en_ff_mt 0 int_en_drdy 2e ctrl_reg5 control reg5 r/ w int_cfg_aslp ? ? int_cfg _lndprt ? int_cfg_ff_mt 0 int_cfg_drd y 2f off_x x 8-bit offset r/ w d7 d6 d5 d4 d3 d2 d1 d0 30 off_y y 8-bit offset r/ w d7 d6 d5 d4 d3 d2 d1 d0 31 off_z z 8-bit offset r/ w d7 d6 d5 d4 d3 d2 d1 d0
MMA8653FC sensors 22 freescale semiconductor, inc. 6.3 data registers the following are the data registers for the MMA8653FC. for more information about data manipulation of the MMA8653FC, see application note, an4083 . 6.3.1 0x00: status, data status register this register contains the x, y, z data overwrite and data ready flags. figure 15. 0x00: status, data status register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 zyxow zow yow xow zyxdr zdr ydr xdr table 13. status register bits field description zyxow x, y, z-axis data overwrite . default value: 0 zyxow is set whenever a new acceleration data is produced befo re completing the retrieval of the previous set. this event occurs when the content of at least one acceleration data register (i.e., out_x, out_y , out_z) has been overwritten. zyxow is cleared when the high-bytes of the acceleration data (out_x_msb, out_y_msb, out_z_msb) of all the channels are read. 0: no data overwrite has occurred 1: previous x, y, or z data was overwritten by new x, y, or z data before it was read zow z-axis data overwrite . default value: 0 zow is set whenever a new acceleration sample related to the z-axis is generated before the retrieval of the previous sample. when this occurs the previous sample is overwritten. zow is cleared anytime out_z_msb register is read. 0: no data overwrite has occurred 1: previous z-axis data was overwritte n by new z-axis data before it was read yow y-axis data overwrite . default value: 0 yow is set whenever a new acceleration sample related to the y-axis is generated before the retrieval of the previous sample. when this occurs the previous sample is overwri tten. yow is cleared anytime out_y_msb register is read. 0: no data overwrite has occurred 1: previous y-axis data was overwritte n by new y-axis data before it was read xow x-axis data overwrite . default value: 0 xow is set whenever a new acceleration sample related to the x-axis is generated before the retrieval of the previous sample. when this occurs the previous sample is overwritten. xow is cleared any time out_x_msb register is read. 0: no data overwrite has occurred 1: previous x-axis data was overwritten by new x-axis data before it was read zyxdr x, y, z-axis new data ready . default value: 0 zyxdr signals that a new sample for any of the enabled cha nnels is available. zyxdr is cleared when the high-bytes of the acceleration data (out_x_msb, out_y_msb, out_z_msb) of all the channels are read. 0: no new set of data ready 1: a new set of data is ready zdr z-axis new data available . default value: 0 zdr is set whenever a new acceleration sample related to the z-axis is generated. zdr is cleared any time out_z_msb register is read. 0: no new z-axis data is ready 1: a new z-axis data is ready ydr y-axis new data available . default value: 0 ydr is set whenever a new acceleration sample related to the y-axis is generated. ydr is cleared any time out_y_msb register is read. 0: no new y-axis data ready 1: a new y-axis data is ready xdr x-axis new data available . default value: 0 xdr is set whenever a new acceleration sample related to th e x-axis is generated. xdr is cleared any time out_x_msb register is read. 0: no new x-axis data ready 1: a new x-axis data is ready
MMA8653FC sensors freescale semiconductor, inc. 23 6.3.2 0x01: out_x_msb, accelerometer x-axis data register 6.3.3 0x02: out_x_lsb, accelerometer x-axis data register 6.3.4 0x03: out_y_msb, accelerometer y-axis data register 6.3.5 0x04: out_y_lsb, accelerometer y-axis data register 6.3.6 0x05: out_z_msb, accelerometer z-axis data register 6.3.7 0x06: out_z_lsb, accelerometer z-axis data register these registers contain the x-axis, y-axis, and z-axis10-bit output sample data expressed as 2's complement numbers. figure 16. 0x01: out_x_msb, x_msb register (read only) figure 17. 0x02: out_x_lsb, x_lsb register (read only) figure 18. 0x03: out_y_msb, y_msb register (read only) figure 19. 0x04: out_y_lsb, y_lsb register (read only) figure 20. 0x05: out_z_msb, z_msb register (read only) figure 21. 0x06: out_z_lsb, z_lsb register (read only) out_x_msb, out_x_lsb, out_y_msb, out_y_lsb, out_z_ msb, and out_z_lsb are stored in the auto-incrementing address range of 0x01 to 0x06 to reduce reading the status followed by 10-bit axis data to 7 bytes. if the f_read bit is set ( 0x2a bit 1), auto increment will skip over lsb registers. this will sh orten the data acquisition from 7 bytes to 4 bytes. the lsb re gisters can only be read immediately following the read access of the corresponding msb register. a random read access to the lsb registers is not possible. reading the msb register and then the lsb register in sequence ensures that both bytes (lsb and msb) belong to the same data sample, even if a new data sample arrives between reading the msb and the lsb byte. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xd9 xd8 xd7 xd6 xd5 xd4 xd3 xd2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x d 1x d 0000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 yd9 yd8 yd7 yd6 yd5 yd4 yd3 yd2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y d 1y d 0000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z d 9z d 8z d 7z d 6z d 5z d 4z d 3z d 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z d 1z d 0000000
MMA8653FC sensors 24 freescale semiconductor, inc. 6.4 system registers 6.4.1 0x0b: sysmod, system mode register the system mode register indicates the current devi ce operating mode. applications using the auto-sleep/w ake mechanism should use this register to syn chronize the application with the device operating mode transitions. figure 22. 0x0b: sysmod, system mode register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 0 sysmod1 sysmod0 table 14. sysmod register field description sysmod[1:0] system mode . default value: 00. 00: standby mode 01: wake mode 10: sleep mode
MMA8653FC sensors freescale semiconductor, inc. 25 6.4.2 0x0c: int_source, system interrupt status register in the interrupt source register the status of the various embedd ed features can be determined. the bits that are set (logic ?1 ?) indicate which function has asserted an interrupt and conversely the bits that are cleared (logic ?0?) indicate which function has not asserted or has de-asserted an interrupt. the bits are set by a low to high transition and are cleared by reading the appropriate interrupt source register. figure 23. 0x0c: int_source, system inte rrupt status register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 src_aslp 0 0 src_lndprt 0 src_ff_mt 0 src_drdy table 15. int_source register field description src_aslp auto-sleep/wake interrupt status bit . default value: 0. ? logic ?1? indicates that an interrupt event that can cause a wake to sleep or sleep to wake system mode transition has occurred. ? logic ?0? indicates that no wake to sleep or sleep to wake system mode transition interrupt event has occurred. wake to sleep transition occurs when no interrupt occurs for a ti me period that exceeds the user specified limit (aslp_count). this causes the system to tr ansition to a user specified low odr setting. sleep to wake transition occurs when the user specified interr upt event has woken the system; thus causing the system to transition to a user specified high odr setting. ? reading the sysmod register clears the src_aslp bit. src_lndprt portrait/landscape orientation interrupt status bit . default value: 0. logic ?1? indicates that an interrupt was generated due to a change in the device orientation status. logic ?0? indicates that no change in orientation status was detected. ? this bit is asserted whenever ? newlp ? bit in the pl_status is asserted and the interrupt has been enabled. ? this bit is cleared by readi ng the pl_status register. src_ff_mt freefall/motion interrupt status bit . default value: 0. logic ?1? indicates that the freefall/motion function interrupt is active. logic ?0? indicates th at no freefall or motion event was detected. ? this bit is asserted whenever ?ea? bit in the ff_mt_src register is asserted and the ff_mt interrupt has been enabled. ? this bit is cleared by readi ng the ff_mt_src register. src_drdy data ready interrupt bit status . default value: 0. logic ?1? indicates that the x, y, z data ready interrupt is active indicating the presence of new data and/or data overrun. otherwise if it is a logic ?0? the x, y, z interrupt is not active. ? this bit is asserted when the zyxow and/or zyxdr is set and the interrupt has been enabled. ? this bit is cleared by reading the x, y, and z data. it is not cleared by simply reading the status register (0x00).
MMA8653FC sensors 26 freescale semiconductor, inc. 6.4.3 0x0d: who_am_i, device id register the device identification register identifies the part. the default value is 0x5a . this value is factory programmed. consult th e factory for custom alternate values. figure 24. 0x0d: who_am_i, device id register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01011 0 1 0
MMA8653FC sensors freescale semiconductor, inc. 27 6.4.4 0x0e: xyz_data_cfg register the xyz_data_cfg register sets the dynamic range. figure 25. 0x0e: xyz_data_cfg register (read/write) the default full scale value range is 2g. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00000 0 f s 1 f s 0 table 16. xyz_data_cfg register field description fs[1:0] output buffer data format full scale . default value: 00 (2g). table 17. full scale range fs1 fs0 full scale range 00 2g 01 4g 10 8g 1 1 reserved
MMA8653FC sensors 28 freescale semiconductor, inc. 6.5 portrait/landscape embedded function registers for more details on the meaning of the different user configurable settings and for example code refer to freescale application note an4078. 6.5.1 0x10: pl_status, portrait/landscape status register this status register can be read to get updated information on any change in orientation by reading bit 7, or on the specifics of the orientation by reading the other bits. for further understanding of portrait up, portrait down, landscape left, landscape right, back and front orientations please refer to figure 3 "landscape/portrait orientation" . the interrupt is cleared when reading the pl_status register. figure 26. 0x10: pl_status, portrait/landscape status register (read only) ? newlp is set to 1 after the first orientation detection afte r a standby to active transition, and whenever a change in lo, bafro, or lapo occurs. ? newlp bit is cleared anytime pl_status register is read. ? the orientation mechanism state change is limited to a maximum 1.25g. ? lapo bafro and lo continue to change when newlp is set. ? the current position is locked if the absolute value of the acce leration experienced on any of the three axes is greater than 1.25g. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 newlp lo 0 0 0 lapo[1] lapo[0] bafro table 18. pl_status register field description newlp portrait/landscape status change flag . default value: 0. 0: no change 1: bafro and/or lapo and/or z-tilt lockout value has changed lo z-tilt angle lockout . default value: 0. 0: lockout condition has not been detected 1: z-tilt lockout trip angle has been exceeded. lockout has been detected. lapo[1:0] (1) 1. the default power up state is bafro = 0, lapo = 0, and lo = 0 . landscape/portrait orientation . default value: 00 00: portrait up: equipment standing ver tically in the normal orientation 01: portrait down: equipment standing ve rtically in the inverted orientation 10: landscape right: equipment is in landscape mode to the right 11: landscape left: equipment is in landscape mode to the left bafro back or front orientation . default value: 0 0: front: equipment is in th e front facing orientation 1: back: equipment is in the back facing orientation
MMA8653FC sensors freescale semiconductor, inc. 29 6.5.2 0x11: pl_cfg, portrait/landscape configuration register this register enables the portrait/landscape function and sets the behavior of the debounce counter. figure 27. 0x11: pl_cfg, portrait/landscape configuration register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbcntm pl_en 0 0 0 0 0 0 table 19. pl_cfg register field description dbcntm debounce counter mode selection . default value: 1 0: decrements debounce whenever cond ition of interest is no longer valid 1: clears counter whenever condition of interest is no longer valid. pl_en portrait/landscape detection enable . default value: 0 0: portrait/landscape detection is disabled 1: portrait/landscape detection is enabled
MMA8653FC sensors 30 freescale semiconductor, inc. 6.5.3 0x12: pl_count, portrait/landscape debounce counter register this register sets the debounce count for the orientation stat e transition. the minimum debounce latency is determined by the data rate set by the product of the selected system odr and pl_c ount registers. any transition from wake to sleep or vice versa resets the internal landscape/portrait debounce counter. note the debounce counter weighting (time st ep) changes based on the odr and the oversampling mode. table 21, ?pl_count relationship with the odr " explains the time step value for all sample rates and all oversampling modes. figure 28. 0x12: pl_count, portrait/landscape debounce counter register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbnce[7] dbnce[6] dbnce[5] dbnce[4] dbnce[3] dbnce[2] dbnce[1] dbnce[0] table 20. pl_count register field description dbcne[7:0] debounce count value . default value: 0000_0000. table 21. pl_count relationship with the odr odr (hz) max time range (s) time step (ms) normal lpln highres lp normal lpln highres lp 800 0.319 0.319 0.319 0.319 1.25 1.25 1.25 1.25 400 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 200 1.28 1.28 0.638 1.28 5 5 2.5 5 100 2.55 2.55 0.638 2.55 10 10 2.5 10 50 5.1 5.1 0.638 5.1 20 20 2.5 20 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 20.4 0.638 40.8 20 80 2.5 160 1.56 5.1 20.4 0.638 40.8 20 80 2.5 160
MMA8653FC sensors freescale semiconductor, inc. 31 6.5.4 0x13: pl_bf_zcomp, back/front and z compensation register the z-lock angle compensation bits allow the user to operate t he device at the default, the z-lockout angle is fixed to 30 up on power up. the back to front tr ip angle is fixed to 75. figure 29. 0x13: pl_bf_zcomp, back/front and z compensation register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01000100 table 22. pl_bf_zcomp register field description 0100 0100
MMA8653FC sensors 32 freescale semiconductor, inc. 6.5.5 0x14: pl_ths_reg, portrait/landscape threshold and hysteresis register this register represents the portrait to landscape trip thres hold register used to set the trip angle for transitioning from po rtrait to landscape and landscape to portrait. this register includes a value for the hysteresis. figure 30. 0x14: pl_ths_reg, portrait/landscape threshold and hysteresis register (read only) : bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10000100 table 23. pl_ths_reg register field description 1000 0100
MMA8653FC sensors freescale semiconductor, inc. 33 6.6 motion and freefall embe dded function registers the freefall/motion function can be configured in either freefall or motion detection mode via the oae configuration bit (0x15: ff_mtg_cfg, bit 6). the freefall/motion detection block can be dis abled by setting all three bits zefe, yefe, and xefe to zero. depending on the register bits ele (0x15: ff_mtg_cfg, bit 7) and oae (0x15: ff_mtg_cfg, bit 6), each of the freefall and motion detection block can operate in four different modes: 6.6.1 motion and freefall mode 6.6.1.1 mode 1: freefall detection with ele = 0, oae = 0 in this mode, the ea bit (0x16: ff_mtg_src, bit 7) indicates a freefall event after the debounce counter is complete . the zefe, yefe, and xefe control bits determine which ax es are considered for the fr eefall detection. once the ea bit is set, and dbcntm = 0, the ea bit can get cleared only after the delay specified by ff_mt_count. this is because the counter is in decrement mode. if dbcntm = 1, the ea bit is cleared as soon as the freefall condition disappears, and will not be set again before the delay specified by ff_mt_count has passed. reading the ff_mt_src register does not clear the ea bit. the event flags (0x16) zhe, zhp, yhe, yhp, xhe, and xhp reflect the motion detection status (i.e. high g event) without any debouncing, provided that the corresponding bits zefe, yefe, and/or xefe are set. 6.6.1.2 mode 2: freefall detection with ele = 1, oae = 0 in this mode, the ea event bit indicates a freefall event after the debounce counter . once the debounce counter reaches the time value for the set threshold, the ea bit is set, and remains set until the ff_mt_src register is read. when the ff_mt_src register is read, the ea bit and the debounce counter are cleared and a new event can only be generated after the delay specified by ff_mt_cnt. the zefe, yefe, and xefe control bits determine which axes are considered for the freefall detection. while ea = 0, the ev ent flags zhe, zhp, yhe, yh p, xhe, and xhp reflect the motion detection status (i.e., high g event) without any de bouncing, provided that the corresponding bits zefe, yefe, and/or xefe are set. the event flags zhe, zhp, yhe, yhp, xhe, and xhp are latched when the ea event bit is set. the event flags zhe, zhp, yhe, yhp, xhe, and xhp will start changing only after the ff_mt_src register has been read. 6.6.1.3 mode 3: motion detection with ele = 0, oae = 1 in this mode, the ea bit indicates a motion event after the debounce counter time is reached . the zefe, yefe, and xefe control bits determine which axes are taken into consideration for motion detection. once the ea bit is set, and dbcntm = 0, the ea bit can get cleared only after the delay specified by ff_mt_ count. if dbcntm = 1, the ea bit is cleared as soon as the motion high g condition disappears. the event flags zhe, zhp, yhe, yhp, xhe, and xhp reflec t the motion detection status (i.e., high g event) without any debouncing, provided that the corresponding bits zefe, yefe, and/or xefe are se t. reading the ff_mt_src does not clear any flags, nor is the debounce counter reset. 6.6.1.4 mode 4: motion detection with ele = 1, oae = 1 in this mode, the ea bit indicates a motion event after debouncing . the zefe, yefe, and xefe control bits determine which axes are taken into consideration for motion detection. once the debounce counter reaches the threshold, the ea bit is set, and remains set until the ff_mt_src regist er is read. when the ff_mt_ src register is read, all register bits are cleared and the debounce counter are cleared and a new event can only be generated after the delay specified by ff_mt_cnt. while the bit ea is zero, the event flags zhe, zhp, yhe, yh p, xhe, and xhp reflect the motion detection status (i.e., high g event) without any debouncing, prov ided that the corresponding bits zefe, yefe, and/or xefe are set. when the ea bit is set, these bits keep their current value until the ff_mt_src register is read.
MMA8653FC sensors 34 freescale semiconductor, inc. 6.6.2 0x15: ff_mt_cfg, freefall/motion configuration register this is the freefall/motion configurat ion register for setting up the conditio ns of the freefall or motion function. figure 31. 0x15: ff_mt_cfg, freefall/moti on configuration register (read/write) figure 32. ff_mt_cfg high and low g level bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ele oae zefe yefe xefe 0 0 0 table 24. ff_mt_cfg register field description ele event latch enable : event flags are latched into ff_mt_src register. reading of the ff_mt_src register clears the event flag ea and all ff_mt_src bits. default value: 0. ele denotes whether the enabled event flag wi ll to be latched in the ff_mt_src register or the event flag status in the ff_mt_src will indicate the real-time status of the event. if el e bit is set to a logic ?1?, then the event flags are frozen wh en the ea bit gets set, and are cleared by reading the ff_mt_src source register. 0: event flag latch disabled 1: event flag latch enabled oae motion detect / freefall detect flag selection . default value: 0. (freefall flag) oae bit allows the selection between motion (logical or comb ination) and freefall (logical and combination) detection. 0: freefall flag (logical and combination) 1: motion flag (logic al or combination) zefe event flag enable on z . default value: 0. zefe enables the detection of a motion or freefall event when the m easured acceleration data on x, y, z channel is beyond the threshold set in ff_mt_ths register. if the ele bit is set to l ogic ?1? in the ff_mt_cfg regist er new event flags are blocked from updating the ff_mt_src register. 0: event detection disabled 1: raise event flag on measured accel eration value beyond preset threshold yefe event flag enable on y event . default value: 0. yefe enables the detection of a motion or freef all event when the measured accelerati on data on x, y, z channel is beyond the threshold set in ff_mt_ths register. if the ele bit is set to l ogic ?1? in the ff_mt_cfg regist er new event flags are blocked from updating the ff_mt_src register. 0: event detection disabled 1: raise event flag on measured accel eration value beyond preset threshold xefe event flag enable on x event . default value: 0. xefe enables the detection of a motion or freef all event when the measured accelerati on data on x, y, z channel is beyond the threshold set in ff_mt_ths register. if the ele bit is set to l ogic ?1? in the ff_mt_cfg regist er new event flags are blocked from updating the ff_mt_src register. 0: event detection disabled 1: raise event flag on measured accel eration value beyond preset threshold +8g high-g + threshold (motion) low-g threshold (freefall) high-g - threshold (motion) -8g x, y, z high-g region x, y, z high-g region x, y, z low-g region negative positive acceleration acceleration
MMA8653FC sensors freescale semiconductor, inc. 35 6.6.3 0x16: ff_mt_src, freefall/motion source status register this register keeps track of the acceleration event which is trig gering (or has triggered, in case of ele bit in ff_mt_cfg regi ster being set to 1) the event flag. in particular ea is set to a logic ?1? when the logical combination of acceleration events flag s specified in ff_mt_cfg register is tr ue. this bit is used in combination with the values in int_en_ff_mt and int_cfg_ff_mt register bits to gene rate the freefall/motion interrupts. an x,y, or z motion is true when the acceleration value of the x or y or z channel is higher than the preset threshold value de fined in the ff_mt_ths register. conversely an x, y, and z low event is true when the acceleration value of the x and y and z channel is lower than the preset threshold value defined in the ff_mt_ths register. figure 33. 0x16: ff_mt_src, freefall and motion source status register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ea 0 zhe zhp yhe yhp xhe xhp table 25. ff_mt_src register field description ea event active flag . default value: 0. 0: no event flag has been asserted 1: one or more event flag has been asserted. see the description of the oae bit to determine th e effect of the 3-axis event flags on the ea bit. zhe z motion flag . default value: 0. 0: no z motion event detected 1: z motion has been detected this bit reads always zero if the zefe control bit is set to zero zhp z motion polarity flag . default value: 0. 0: z event was positive g, 1: z event was negative g this bit read always zero if the zefe control bit is set to zero yhe y motion flag . default value: 0. 0: no y motion event detected 1: y motion has been detected this bit read always zero if the yefe control bit is set to zero yhp y motion polarity flag . default value: 0 0: y event detected was positive g 1: y event was negative g this bit reads always zero if the yefe control bit is set to zero xhe x motion flag . default value: 0 0: no x motion event detected 1: x motion has been detected this bit reads always zero if the xefe control bit is set to zero xhp x motion polarity flag . default value: 0 0: x event was positive g 1: x event was negative g this bit reads always zero if the xefe control bit is set to zero
MMA8653FC sensors 36 freescale semiconductor, inc. 6.6.4 0x17: ff_mt_ths, freefall and motion threshold register ff_mt_ths is the threshold register used to detect freefall motion events. ? the unsigned 7-bit ff_mt_ths threshold register holds the threshold for the freefall detection where the magnitude of the x and y and z acceleration values is lower than the threshold value . ? conversely, the ff_mt_ths also holds the threshold for the motion detection where the magnitude of the x or y or z acceleration value is higher than the threshold value . figure 34. 0x17: ff_mt_ths, freefall and motion threshold re gister (read/write) the threshold resolution is 0.063g/lsb and the threshold register has a range of 0 to 127 counts. the maximum range is to 8g. note that even when the full scale value is set to 2g or 4g the motion detects up to 8g. dbcntm bit configures the way in which the debounce counter is re set when the inertial event of interest is momentarily not tru e. ? when dbcntm bit is ?1? , the debounce counter is cleared to 0 whenever the i nertial event of interest is no longer true as shown in figure 36 "dbcntm bit function" , (b). ? while the dbcntm bit is set to logic ?0? , the debounce counter is decremented by 1 whenever the inertial event of interest is no longer true ( figure 36 "dbcntm bit function" , (c)) until the debounce count er reaches 0 or the inertial event of interest becomes active. decrementing the debounce counter acts as a median enabling the system to filter out irregular spurious events which might impede the detection of inertial events. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbcntm ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 26. ff_mt_ths bit description s field description dbcntm debounce counter mode selection . default value: 0. 0: increments or decrements debounce, 1: increments or clears counter. ths[7:1] freefall /motion threshold : default value: 000_0000.
MMA8653FC sensors freescale semiconductor, inc. 37 6.6.5 0x18: ff_mt_count, debounce register this register sets the number of deboun ce sample counts for the event trigger. figure 35. 0x18 ff_mt_count, de bounce register (read/write) this register sets the minimum number of debounce sample c ounts of continuously matching the detection condition user selected for the freefall, motion event. when the internal debounce counter reaches the ff_mt_count value a freefall/motion event flag is set. the debounce counter will never increase beyond the ff_mt_count value. time step used for the debounce sample count depends on the odr chosen and the oversampling mode as shown in table 28, ?ff_mt_count relationship with the odr ". bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 table 27. ff_mt_count register field description d[7:0] count value . default value: 0000_0000 table 28. ff_mt_count relationship with the odr odr (hz) max time range (s) time step (ms) normal lpln highres lp normal lpln highres lp 800 0.319 0.319 0.319 0.319 1.25 1.25 1.25 1.25 400 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 200 1.28 1.28 0.638 1.28 5 5 2.5 5 100 2.55 2.55 0.638 2.55 10 10 2.5 10 50 5.1 5.1 0.638 5.1 20 20 2.5 20 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 20.4 0.638 40.8 20 80 2.5 160 1.56 5.1 20.4 0.638 40.8 20 80 2.5 160
MMA8653FC sensors 38 freescale semiconductor, inc. figure 36. dbcntm bit function high g event on count threshold ff ffea all 3-axis (motion detect) counter value high g event on count threshold debounce (a) all 3-axis (motion detect) counter value high g event on count threshold debounce ea all 3-axis (motion detect) counter value dbcntm = 1 (b) ea dbcntm = 0 (c)
MMA8653FC sensors freescale semiconductor, inc. 39 6.7 auto-wake/sleep detection 6.7.1 0x29: aslp_count, auto-wake/sleep detection register (read/write) the aslp_count register sets the minimum time period of inactivi ty required to change the curre nt odr value, from the value specified in the dr[2:0] register to aslp_rate register value, provided that the slpe bit is set to a logic ?1? in the ctrl_reg2 register. see table 30, ?aslp_count relationship with odr " for functional blocks that may be monitored for inactivity in order to trigger the ?retu rn to sleep? event. figure 37. 0x29: aslp_count auto-wake/sleep detection register (read/write) d7-d0 defines the minimum duration time to change current odr value from dr to aslp_rate . time step and maximum value depend on the odr chosen as shown in table 30, ?aslp_count relationship with odr ". in order to wake the device, the desired functions must be enabled in ctrl_reg4 and set to wake from sl eep in ctrl_reg3. all enabl ed functions will still function in sleep mode at th e sleep odr. only the fu nctions that have been selected for wake from sleep will wake the device. MMA8653FC has 2 functions that can be used to keep the sensor fr om falling asleep namely, orientation, and motion/freefall. one or more of these functions can be enabled. to wake the device, 2 functions are provided : orientation, and the motion/ freefall. the auto-wake/sleep interrupt does not affe ct the wake/sleep, nor does the data ready interrupt. if the auto-sleep bit is disabled, then th e device can only toggle between standby and wake mode . if auto-sleep interrupt is enabled, transitioning from ac tive mode to auto-sleep mode and vice versa generat es an interrupt. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 table 29. aslp_count register field description d[7:0] duration value . default value: 0000_0000. table 30. aslp_count relationship with odr output data rate (odr) duration odr time step aslp_count step 800 hz 0 to 81s 1.25 ms 320 ms 400 hz 0 to 81s 2.5 ms 320 ms 200 hz 0 to 81s 5 ms 320 ms 100 hz 0 to 81s 10 ms 320 ms 50 hz 0 to 81s 20 ms 320 ms 12.5 hz 0 to 81s 80 ms 320 ms 6.25 hz 0 to 81s 160 ms 320 ms 1.56 hz 0 to 162s 640 ms 640 ms table 31. sleep/wake mode gates and triggers interrupt source event restarts timer and delays return to sleep event will wake from sleep src_lndprt yes yes src_ff_mt yes yes src_aslp no no src_drdy no no
MMA8653FC sensors 40 freescale semiconductor, inc. 6.8 control registers note except for standby mode selection, the device must be in standby mode to change any of the fields within ctrl_reg1 (0x2a). 6.8.1 0x2a: ctrl_reg1, system control 1 register this register configures the auto-wake sample frequency, data rate selection, and enables the fast read mode and standby/ active selection. figure 38. 0x2a: ctrl_reg1, system control 1 register (read/write) dr[2:0] bits select the output data ra te (odr) for accelerati on samples in wake mode. the default value is 000 for a data rate of 800 hz. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 aslp_rate1 aslp_rate0 dr2 dr1 dr0 0 f_read active table 32. ctrl_reg1 register field description aslp_rate[1:0] configures the auto-wake sample frequency when the device is in sleep mode . default value: 00. see table 33, ?sleep mode rates ". dr[2:0] data rate selection . default value: 000. see table 34, ?system output data rate selection ". f_read fast read mode : data format limited to single byte default value: 0. 0: normal mode 1: fast read mode active standby/active selection . default value: 00. 0: standby mode 1: active mode table 33. sleep mode rates aslp_rate1 aslp_rate0 frequency (hz) notes 005 0 when the device is in auto-sleep mode, the system odr and the data rate for all the system functional blocks are overridden by the data rate set by the aslp_rate field. 0 1 12.5 1 0 6.25 1 1 1.56 table 34. system output data rate selection dr2 dr1 dr0 odr period notes 0 0 0 800 hz 1.25 ms default (standby mode) 0 0 1 400 hz 2.5 ms 010200 hz5 ms 0 1 1 100 hz 10 ms 1 0 0 50 hz 20 ms 1 0 1 12.5 hz 80 ms 1 1 0 6.25 hz 160 ms 1 1 1 1.56 hz 640 ms
MMA8653FC sensors freescale semiconductor, inc. 41 active bit selects between standby mode and active mode. f_read bit selects between normal and fast read mode. when se lected, the address auto-incr ement will skip over the lsb data bytes. table 35. full scale selection active mode 0 standby (default) 1active
MMA8653FC sensors 42 freescale semiconductor, inc. 6.8.2 0x2b: ctrl_reg2, system control 2 register this register is used enable self-test, software reset, and au to-sleep. in addition, it enables you to configure the sleep and wake mode power scheme selection. figure 39. 0x2b: ctrl_reg2, system control 2 register (read/write) when the reset bit is enabled, all registers are rest and are loaded with default values. writin g ?1? to the rst bit immediatel y resets the device, no matter whether it is in active/wake, active/sleep, or standby mode. the i 2 c communication system is reset to avoid accidental corrupted data access. at the end of the boot process the rs t bit is de-asserted to 0. reading this bit will return a value of zero. the (s)mods[1:0] bits select which oversampling mode is to be used shown in table 37, ?mods oversampling modes ". the oversampling modes are available in both wake mode mod[1:0] and also in the sleep mode smod[1:0]. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 st rst ? smods1 smods0 slpe mods1 mods0 table 36. ctrl_reg2 register field description st self-test enable . default value: 0. st bit activates the self-test function. when st is set, x, y, and z outputs will shift. rst bit is used to activate the softwa re reset. the reset mechanism can be enabled in standby and active mode. 0: self-test disabled 1: self-test enabled rst software reset. default value: 0. 0: device reset disabled 1: device reset enabled. smods[1:0] sleep mode power scheme selection . default value: 00. see table 37, ?mods oversampling modes " and table 38, ?mods oversampling modes current consumption and averaging values at each odr " slpe auto-sleep enable . default value: 0. 0: auto-sleep is not enabled; 1: auto-sleep is enabled. mods[1:0] wake mode power scheme selection. default value: 00. see table 37, ?mods oversampling modes " and table 38, ?mods oversampling modes current consumption and averaging values at each odr " table 37. mods oversampling modes (s)mods1 (s)mods0 power mode 00normal 0 1 low noise low power 1 0 high resolution 1 1 low power table 38. mods oversampling modes current consumption and averaging values at each odr odr mode normal (00) low noise low power (01) high resolution (10) low power (11) current a os ratio current a os ratio current a os ratio current a os ratio 1.56 hz tbd 128 tbd 32 tbd 1024 tbd 16 6.25 hz tbd 32 tbd 8 tbd 256 tbd 4 12.5 hz tbd 16 tbd 4 tbd 128 tbd 2 50 hz tbd 4 tbd 4 tbd 32 tbd 2
MMA8653FC sensors freescale semiconductor, inc. 43 note: tbd current values will be added later. 100 hz tbd 4 tbd 4 tbd 16 tbd 2 200 hz tbd 4 tbd 4 tbd 8 tbd 2 400 hz tbd 4 tbd 4 tbd 4 tbd 2 800 hz tbd 2 tbd 2 tbd 2 tbd 2 table 38. mods oversampling modes current consumption and averaging values at each odr (continued) odr mode normal (00) low noise low power (01) high resolution (10) low power (11) current a os ratio current a os ratio current a os ratio current a os ratio
MMA8653FC sensors 44 freescale semiconductor, inc. 6.8.3 0x2c: ctrl_reg3, system control 3 register this register is used to control the au to-wake/sleep function by setti ng the orientation or freefall/motion as an interrupt to wake up. this register also configur es the interrupt pins int1 and int2. figure 40. 0x2c ctrl_reg3, system control 3 register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? wake_lndprt ? wake_ff_mt 0 ipol pp_od table 39. ctrl_reg3 register field description wake_lndprt 0: orientation function is bypassed in sleep mode. default value: 0. 1: orientation function interrupt can wake up system wake_ff_mt 0: freefall/motion function is bypassed in sleep mode. default value: 0. 1: freefall/motion function interrupt can wake up ipol interrupt polarity active high, or active low . default value: 0. ipol bit selects the polarity of the interrupt signal. when ipol is ?0? (default value) any inte rrupt event will signaled with a logical 0. 0: active low 1: active high pp_od push-pull/open drain selection on interrupt pad . default value: 0. pp_od bit configures the interrupt pin to push-pull or in open drain mode. the default value is 0 which corresponds to push-pull mode. the open drain configurat ion can be used for connecting multiple interrupt signals on the same interrupt line. 0: push-pull 1: open drain
MMA8653FC sensors freescale semiconductor, inc. 45 6.8.4 0x2d: ctrl_reg4, interrupt enable register (read/write) this register enab les the following interrupts: auto -wake/sleep, orientation detection, freefall/moti on, and data ready. figure 41. 0x2d: ctrl_reg4, interrupt enable register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 int_en_aslp ? ? int_en_lndp ? int_en_ff_mt 0 int_en_drdy table 40. ctrl_reg4 register field description int_en_aslp auto-sleep/wake interrupt enable 0 interrupt is disabled (default) 1 interrupt is enabled note: the corresponding functional block interrupt enable bit enables the functional block to route its event detection flags to the syste m?s interrupt controller. the interrupt controller routes the enabled functional block interrupt to the int1 or int2 pin. int_en_lndprt orientation (landscape/portrait) interrupt enable int_en_ff_mt freefall/motion interrupt enable int_en_drdy data ready interrupt enable
MMA8653FC sensors 46 freescale semiconductor, inc. 6.8.5 0x2e: ctrl_reg5, interrupt configuration register (read/write) this register maps the desired interrupts to int2 or int1. figure 42. 0x2e: ctrl_reg5, interrupt configuration register the system?s interrupt controller shown in figure 10 "system interrupt generation" uses the corresponding bit field in the ctrl_reg5 register to determine the routing table for the int1 and int2 interrupt pins. if the bit value is logic ?0? the funct ional block?s interrupt is routed to int2, and if the bit value is logic ?1? then the interrupt is routed to int1. one or more functi ons can assert an interrupt pin; therefore a host application responding to an interrupt should read the int_source (0x0c) register to determine the appropriate sources of the interrupt. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 int_cfg_asl ? ? int_cfg_lndp ? int_cfg_ff_m 0 int_cfg_drd table 41. ctrl_reg5 register field description int_cfg_aslp auto-sleep/wake int1/int2 configuration 0 interrupt is routed to int2 pin (default) 1 interrupt is routed to int1 pin int_cfg_lndprt orientation int1/int2 configuration int_cfg_ff_mt freefall/motion int1/int2 configuration int_cfg_drdy data ready int1/int2 configuration
MMA8653FC sensors freescale semiconductor, inc. 47 6.9 data calibration registers the 2?s complement offset correction regist ers values are used to realign the zero-g position of the x, y, and z-axis after the device is mounted on a board. the resolution of the offset registers is 1.96 mg/lsb. th e 2?s complement 8-bit value would resul t in an offset compensation range 250 mg for each ax is. 0x2f: off_x, offset correction x register. figure 43. 0x2f: off_x, correction x register (read/write) 6.9.1 0x30: off_y, offset correction y register figure 44. 0x30: off_y, offset correction y register (read/write) 6.9.2 0x31: off_z, offset correction z register figure 45. 0x31: off_z, offset correction z register (read/write) bit 7 bit 6s bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 table 42. off_x register field description d[7:0] x-axis offset value . default value: 0000_0000. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 table 43. off_y register field description d[7:0] y-axis offset value . default value: 0000_0000. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 table 44. off_z register field description d[7:0] z-axis offset value . default value: 0000_0000.
MMA8653FC sensors 48 freescale semiconductor, inc. 7 mounting guidelines surface mount printed circuit board (pcb) la yout is a critical portion of the total design. the footprint for the surface mount packages must be the correct size to ensure proper solder co nnection interface between the pcb and the package. with the correct footprint, the packages will self-align when subjected to a solder reflow proce ss. these guidelines are for soldering a nd mounting the dual flat no-lead (dfn) package inertial sensors to pcbs. the purpose is to minimize the stress on the package after board mounting. the mma865xfc digi tal output accelerometers use the dfn package platform. this section describes suggested methods of soldering these devic es to the pcb for consumer applications. 7.1 overview of sold ering considerations information provided here is based on experiments executed on df n devices. they do not represent exact conditions present at a customer site. therefore, this information should be used as guidance only and proces s and design optimizations are recommended to develop an application specific solution. it shoul d be noted that with the proper pcb footprint and solder stenc il designs, the package will self-align during the solder reflow process. 7.2 halogen content this package is designed to be halogen free, exceeding most industry and customer standar ds. halogen free means that no homogeneous material within the assembly package shall contain ch lorine (cl) in excess of 700 ppm or 0.07% weight/weight or bromine (br) in excess of 900 ppm or 0.09% weight/weight. 7.3 pcb mounting/sold ering recommendations 1. the pcb land should be designed as non solder mask defined (nsmd) as shown in figure 46 "package mounting measurements" . 2. no additional via pattern underneath package. 3. pcb land pad is 0.6 mm x 0.225 mm as shown in figure 46 "package mounting measurements" . 4. solder mask opening = pcb land pad edge + 0.125 mm larger all around = 0.725 mm x 1.950 mm 5. stencil opening = pcb land pad -0.05 mm smaller all around = 0.55 mm x 0.175 mm. 6. stencil thickness is 100 or 125 um. 7. do not place any components or vias at a distance le ss than 2 mm from the package land area. this may cause additional package stress if it is too close to the package land area. 8. signal traces connected to pads are as symmetric as possi ble. put dummy traces on nc pads, to have same length of exposed trace for all pads. 9. use a standard pick and place process and equipment. do not use a hand soldering process. 10. use caution when putting an assembled pcb into an en closure, noting where the screw-down holes are and if any press-fitting is involved. it is important that the assembled pcb remain flat after assembly, to ensure optimal electronic operation of the device. 11. the pcb should be rated for the multiple lead- free reflow condition with max 260c temperature. 12. no copper traces on top layer of pcb under the package. this will cause planarity issues with board mount. freescale dfn sensors are compliant with restrictions on hazardous substances (rohs), having halide free molding compound (green) and lead-free terminations. these terminations are compatible with tin-lead (sn-pb) as well as tin-silver-copper (sn-ag-cu) solder paste soldering processes. reflow prof iles applicable to those processes can be used successfully for soldering the devices.
MMA8653FC sensors freescale semiconductor, inc. 49 figure 46. package mounting measurements table 45. board mounting guidelines description value (mm) landing pad width 0.225 landing pad length 0.600 solder mask pattern width 0.725 solder mask pattern length 1.950 landing pad extended length 0.200 i/o pads extended length 2.525 0.225 0.200 0.600 1.950 0.725 solder mask opening pcb landing pad 2x2 dfn package all measurements are in mm. package outline 2.525
MMA8653FC sensors 50 freescale semiconductor, inc. 8 tape and reel 8.1 tape dimensions figure 47. carrier tape 8.2 device orientation figure 48. device orientation on carrier tape reel carrier tape pin one orientation sprocket holes cover tape user direction of feed
MMA8653FC sensors freescale semiconductor, inc. 51 9 package dimensions figure 49. case 2162-02, issu e o, 10-lead dfn?page 1
MMA8653FC sensors 52 freescale semiconductor, inc. figure 50. case 2162-02, issu e o, 10-lead dfn?page 2
MMA8653FC sensors freescale semiconductor, inc. 53 figure 51. case 2162-02, issu e o, 10-lead dfn?page 3
MMA8653FC sensors 54 freescale semiconductor, inc. figure 52. case 2162-02, issu e o, 10-lead dfn?page 4
MMA8653FC sensors freescale semiconductor, inc. 55 10 revision history table 46. revision history MMA8653FC revision number revision date description of changes 0 08/2012 ? initial release
information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or im plied copyright licenses granted hereunder to design or fabricate any integr ated circuits based on the information in this document. freescale reserves th e right to make changes without fu rther notice to a ny products herein. freescale makes no warranty, repr esentation, or guarantee regarding the suitability of its products for any particular purpo se, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically di sclaims any and all liability, including without limitation consequential or in cidental damages. ?typical? parameters that may be provided in freescale da ta sheets and/or specifications can and do vary in different applications, and actual performa nce may vary over time. all ope rating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its pate nt rights nor the rights of others. freescale sells products pursuant to sta ndard terms and conditions of sa le, which can be found at the following address: freescale.com/salestermsandconditions. how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo, altivec, c-5, code test, codewarrior, coldfire, c-ware, energy efficient solutions logo, kinetis, mobilegt, powerquicc, processor expert, qoriq, qorivva, starcore, symphony, and vortiqa are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, corenet, flexis, magniv, mxc, platform in a package, qoriq qonverge, quicc engine, ready play, safeassure, smartmos, turbolink, vybrid, and xtrinsic ar e trademarks of freescale semiconductor, inc. all other product or service names ar e the property of their respective owners. ? 2012 freescale semiconductor, inc. document number: MMA8653FC rev. 0 08/2012

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