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05991 10/04/2011 rev: b EN6347QI 4a voltage mode synchronous buck pwm dc-dc converter with integrated inductor www.enpirion.com description the EN6347QI is a power system on a chip (powersoc) dc-dc converter. it integrates mosfet switches, small-signal circuits, compensation, and the inductor in an advanced 4mm x 7mm qfn package. the EN6347QI is specifically designed to meet the precise voltage and fast transient requirements of present and future high- performance, low-power processor, dsp, fpga, memory boards and system level applications in distributed power architecture. the devices advanced circuit techniques, ultra high switching frequency, and proprietary integrated inductor technology deliver high-quality, ultra compact, non-isolated dc-dc conversion. the enpirion solution significantly helps in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. in addition, a reduction in the number of vendors required for the complete power solution helps to enable an overall system cost savings. all enpirion products are rohs compliant and lead-free manufacturing environment compatible. figure 1: total solution footprint pwm mode (not to scale) total area 75 mm 2 features ! integrated inductor, mosfets, controller ! minimal external components. ! up to 4a continuous output current capability. ! 3 mhz operating frequency. switching frequency can be phase locked to an external clock. ! high efficiency, up to 95%. ! wide input voltage range of 2.5v to 6.6v. ! light load mode with programmable set point. ! output enable pin and power ok signal. ! programmable soft-start time. ! under voltage lockout, over current, short circuit and thermal protection. ! rohs compliant, msl level 3, 260c reflow. applications ! point of load regulation for processors, dsps, fpgas, and asics ! noise sensitive applications such as a/v, rf and gbit i/o ! low voltage, distributed power architectures such as 0.8v, 1.0v, 1.2, 2.5v, 3.3v, 5v rails ! blade servers, raid storage systems, lan/san adapter cards, wireless base stations, industrial automation, test and measurement, embedded computing, communications, and multi-function printers. ! ripple sensitive applications ! beat frequency sensitive applications en6347 qi output cap 47uf/ 1206 css 0402 input cap 22uf/ 1206 ra 0402 ca 0402 rb 0402
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 2 www.enpirion.com EN6347QI figure 2: typical application schematic (pwm mode) ordering information part number temp rating (c) package EN6347QI -40 to +85 38-pin qfn t&r EN6347QI3 -40 to +85 38-pin qfn t&r EN6347QI-e qfn evaluation board pin assignments (top view) figure 3: pinout diagram (top view) note: all pins must be soldered to pcb. pin description pin name function 1-2, 12, 34-38 nc(sw) no connect C these pins are internally connected to the common switching node of the internal mosfets. they are not to be electrically c onnected to any external signal, ground, or voltage. failure to follow this guideline may re sult in damage to the device. 3-4, 22-25 nc no connect C these pins may be internally connected . do not connect to each other or to any other electrical signal. failure to follow t his guideline may result in device damage. 5-11 vout regulated converter output. connect these pins to the load and place output capacitor between these pins and pgnd pins 13-15. 13-18 pgnd input/output power ground. connect these pins to t he ground electrode of the input and output filter capacitors. see vout and pvin pin des criptions for more details. 19-21 pvin input power supply. connect to input power supply. decouple with input capacitor to pgnd pins 16-18. 26 llm/sync dual function pin providing llm enable and external clock synchronization (see application section). at static logic high, device will allow automatic engagement of light load mode. at static logic low, the device is forc ed into pwm only. a clocked input to this pin will synchronize the internal switching frequen cy to the external signal. if this pin is left floating, it will pull to a static logic high, enab ling llm. 27 enable input enable. applying logic high enables the outp ut and initiates a soft-start. applying logic low disables the output. 28 pok power ok is an open drain transistor used for power system state indication. pok is logic high when vout is within -10% of vout nominal. 29 rllm programmable llm engage resistor to agnd allows for adjustment of load current at which light-load mode engages. can be left open for pwm only operation. 30 ss soft-start node. the soft-start capacitor is connec ted between this pin and agnd. the value of this capacitor determines the startup time . 31 vfb external feedback input. the feedback loop is close d through this pin. a voltage divider at vout is used to set the output voltage. the midpoin t of the divider is connected to vfb. a phase lead capacitor from this pin to vout is also required to stabilize the loop. 32 agnd analog ground. this is the controller ground return . connect to a quiet ground. 33 avin input power supply for the controller. connect to i nput voltage at a quiet point. 39 pgnd device thermal pad to be connected to the system gn d plane. see layout recommendations section.
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 3 www.enpirion.com absolute maximum ratings caution: absolute maximum ratings are stress rating s only. functional operation beyond the recommended operating conditions is not implied. s tress beyond the absolute maximum ratings may impair device life. exposure to absolute maximum r ated conditions for extended periods may affect device reliability. parameter symbol min max units supply voltage C pvin, avin, vout v in -0.5 7.0 v pin voltages C enable, pok, llm/sync -0.5 v in +0.3 v pin voltages C vfb, ss, rllm -0.5 2.75 v storage temperature range t stg -65 150 c maximum operating junction temperature t j-abs max 150 c reflow temp, 10 sec, msl3 jedec j-std-020a 260 c esd rating - all pins (based on hbm) 2000 v recommended operating conditions parameter symbol min max units input supply voltage v in 2.5 6.6 v operating junction temperature t j-op - 40 125 c operating ambient temperature t amb - 40 85 c reflow temp, 10 sec, msl3 jedec j-std-020a 260 c thermal characteristics parameter symbol min typ max units thermal shutdown t sd 160 c thermal shutdown hysteresis t sdh 35 c thermal resistance: junction to ambient ( note 1 ) # ja 30 c/w thermal resistance: junction to case # jc 3 c/w note 1 : based on 2oz. external copper layers and proper t hermal design in line with eia/jedec jesd51-7 standard for high thermal conductivity boards.
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 4 www.enpirion.com electrical characteristics note: v in =6.6v over operating temperature range unless other wise noted. typical values are at ta = 25c. parameter symbol test conditions min typ max units operating input voltage v in 2.5 6.6 v under voltage lock-out C v in rising v uvlor voltage above which uvlo is not asserted 2.3 v under voltage lock-out C v in falling v uvlof voltage below which uvlo is asserted 2.075 v shut-down supply current i s enable=0v 100 $ a operating quiescent current i q llm/sync = high 650 $ a feedback pin voltage EN6347QI EN6347QI3 v fb feedback node voltage at: v in = 5v, iload = 0, t a = 25c 0.7425 0.735 0.75 0.75 0.7575 0.765 v feedback pin voltage EN6347QI EN6347QI3 v fb feedback node voltage at: 2.5v v in 6.6v 0a iload 4a, t a = -40 to 85c 0.735 0.7275 0.75 0.75 0.765 0.7725 v feedback pin input leakage current (note 1) i fb vfb pin input leakage current -5 5 na v out rise time (note 1) t rise measured from when v in > v uvlor & enable pin voltage crosses its logic high threshold to when v out reaches its final value. c ss = 15 nf 0.9 1.2 1.5 ms soft start capacitor range c ss_range 10 68 nf output drop out voltage resistance (note 1) v do r do v inmin - v out at full load input to output resistance 240 60 360 90 mv m % continuous output current i out pwm mode llm mode (note 2) 0 0.002 4 4 a over current trip level i ocp v in = 5v, v out = 1.2v 6.5 a disable threshold v disable enable pin logic low. 0.0 0.6 v enable threshold v enable enable pin logic high 2.5v v in 6.6v 1.8 v in v enable lockout time t enlockout 3.2 ms enable pin input current (note 1) i enable enable pin has ~180k % pull down 40 $ a switching frequency (free running) f sw free running frequency of oscillator 3 mhz external sync clock frequency lock range f pll_lock range of sync clock frequency 2.7 3.3 mhz sync input threshold C low (llm/sync pin) v sync_lo sync clock logic level 0.8 v sync input threshold C high (llm/sync pin) v sync_hi sync clock logic level - (note 3) 1.8 2.5 v pok threshold pok threshold voltage as a fraction of expected output voltage 90 %
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 5 www.enpirion.com parameter symbol test conditions min typ max units pok output low voltage v pokl with 4ma current sink into pok 0.4 v pok output hi voltage v pokh 2.5v v in 6.6v v in v pok pin v oh leakage current (note 1) i pokl pok high 1 a llm engage headroom minimum v in -v out to ensure proper llm operation 800 mv llm logic low (llm/sync pin) v llm_lo llm static logic level 0.3 v llm logic high (llm/sync pin) v llm_hi llm static logic level 1.5 v llm/sync pin current llm/sync pin is <2.5v <100 na note 1 : parameter guaranteed by design. note 2 : llm operation is normally only guaranteed above t he minimum specified output current. contact enpiri on applications support for designs that need to opera te at a lower i out . note 3 : for proper operation of the synchronization circu it, the high-level amplitude of the sync signal should not be above 2.5v. typical performance characteristics efficiency v in = 3.3v, v out (from top to bottom) = 2.5, 1.8, 1.2, 1.0v efficiency v in = 5.0v, v out (from top to bottom) = 3.3, 2.5, 1.8, 1.2, 1.0v pwm output ripple: v in = 3.3v, v out = 1.0v, i out = 4a c in = 22 $ f, c out = 47 $ f/1206 + 10uf/0805 pwm output ripple: v in = 3.3v, v out = 1.0v, i out = 4a c in = 22 $ f, c out = 47 $ f/1206 + 10uf/0805 pwm/llm efficiency vs. load performance at vin=3.3v 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.01 0.1 1 10 load (a) efficiency ( %) vout=2.5 vout=1.8 vout=1.2 vout=1 vout=1 vout=1.2 vout=1.8 vout=2.5 #ref! pwm/llm efficiency vs. load performance at vin=5v 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.01 0.1 1 10 load (a) efficiency (% ) vout=3.3 vout=2.5 vout=1.8 vout=1.2 vout=1 vout=1 vout=1.2 vout=1.8 vout=2.5 vout=3.3 20 mhz bw limit 500 mhz bw
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 6 www.enpirion.com pwm output ripple: v in = 5.0v, v out = 1.0v, i out = 4a c in = 22 $ f, c out = 47 $ f/1206 + 10uf/0805 pwm output ripple: v in = 5.0v, v out = 1.0v, i out = 4a c in = 22 $ f, c out = 47 $ f/1206 + 10uf/0805 llm output ripple: v in = 5.0v, v out = 1.0v, i out = 0.1a, c in = 22 $ f, c out = 2x47 $ f/1206 llm output ripple: v in = 5.0v, v out = 3.0v, i out = 0.1a, c in = 22 $ f, c out = 2x47 $ f/1206 load transient: v in = 5.0v, v out = 1.0v, llm enabled ch.1: v out , ch.2: i out = 0.01 & 4a c in = 22 $ f, c out = 2x47 $ f/1206 load transient: v in = 5.0v, v out = 3.0v, llm enabled ch.1: v out , ch.2: i out = 0.01 & 4a c in = 22 $ f, c out = 2x47 $ f/1206 20 mhz bw limit 500 mhz bw
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 7 www.enpirion.com pwm load transient: v in = 5.0v, v out = 1.0v ch.1: v out , ch.2: i out = 0 & 4a c in = 22 $ f, c out = 47 $ f/1206 + 10f/0805 pwm load transient: v in = 5.0v, v out = 3.0v ch.1: v out , ch.2: i out = 0 & 4a c in = 22 $ f, c out = 47 $ f/1206 + 10f/0805 power up/down at no load: v in /v out = 5v/3.3v, 47nf soft-start capacitor, c out 50f ch.1: enable, ch. 2: v out , ch. 3: pok, ch.4: i out power up/down into 0.825 % load: v in /v out = 5v/3.3v, 47nf soft-start capacitor, c out 50f ch.1: enable, ch. 2: v out , ch. 3: pok, ch.4: i out
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 8 www.enpirion.com functional block diagram figure 4: functional block diagram functional description synchronous buck converter the EN6347QI is a synchronous, programmable power supply with integrated power mosfet switches and integrated inductor. the nominal input voltage range is 2.5v to 6.6v. the output voltage is programmed using an external resistor divider network. the control loop is voltage-mode with a type iii compensation network. much of the compensation circuitry is internal to the device. however, a phase lead capacitor is required along with the output voltage feedback resistor divider to complete the type iii compensation network. the device uses a low-noise pwm topology and also integrates a unique light-load mode (llm) to improve efficiency at light output load currents. llm can be disabled with a logic pin. up to 4a of continuous output current can be drawn from this converter. the 3 mhz switching frequency allows the use of small size input / output capacitors, and enables wide loop bandwidth within a small foot print. protection features: the power supply has the following protection features: ! over-current protection (to protect the ic from excessive load current) ! thermal shutdown with hysteresis. ! under-voltage lockout circuit to keep the converter output off while the input voltage is less than 2.3v.
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 9 www.enpirion.com additional features: ! the switching frequency can be phase- locked to an external clock to eliminate or move beat frequency tones out of band. ! soft-start circuit, allowing controlled startup when the converter is initially powered up. the soft start time is programmable with an appropriate choice of soft start capacitor. ! power good circuit indicating v out is greater than 90% of programmed value as long as the feedback loop is closed. ! to maintain high efficiency at low output current, the device incorporates automatic light load mode operation. enable operation the enable pin provides a means to enable normal operation or to shut down the device. when the enable pin is asserted (high) the device will undergo a normal soft start. a logic low on this pin will power the device down in a controlled manner. from the moment enable goes low, there is a fixed lock out time before the output will respond to the enable pin re- asserted (high) . this lock out is activated for even very short logic low pulses on the enable pin. see the electrical characteristics table for technical specifications for this pin. llm/sync pin this is a dual function pin providing llm enable and external clock synchronization. at static logic high, device will allow automatic engagement of light load mode. at static logic low, the device is forced into pwm only. a clocked input to this pin will synchronize the internal switching frequency C llm mode is not available if this input is clocked.. if this pin i s left floating, it will pull to a static logic high, enabling llm. frequency synchronization the switching frequency of the dc/dc converter can be phase-locked to an external clock source to move unwanted beat frequencies out of band. to avail this feature, the clock source should be connected to the llm/sync pin. an activity detector recognizes the presence of an external clock signal and automatically phase-locks the internal oscillator to this external clock. phase-lock will occur as long as the clock frequency is in the range specified in the electrical characteristics table. for proper operation of the synchronization circuit, the high-level amplitude of the sync signal should not be above 2.5v. please note llm is not available when synchronizing to an external frequency. spread spectrum mode the external clock frequency may be swept between the limits specified in the electrical characteristics table at repetition rates of up to 10 khz in order to reduce emi frequency components. soft-start operation during soft-start, the output voltage is ramped up gradually upon start-up. the output rise time is controlled by the choice of soft-start capacitor, which is placed between the ss pin (30) and the agnd pin (32). rise time: t r (c ss * 80k % ) 25% during start-up of the converter, the reference voltage to the error amplifier is linearly increased to its final level by an internal current source of approximately 10ua. typical soft- start rise time is ~3.8ms with ss capacitor value of 47nf. the rise time is measured from when v in > v uvlor and enable pin voltage crosses its logic high threshold to when v out reaches its programmed value. please note llm function is disabled during the soft-start ramp-up time. pok operation the pok signal is an open drain signal (requires a pull up resistor to v in or similar voltage) from the converter indicating the output voltage is within the specified range. the pok signal will be logic high (v in ) when the output voltage is above 90% of programmed v out . if the output voltage goes below this threshold, the pok signal will be logic low.
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 10 www.enpirion.com light load mode (llm) operation the EN6347QI uses a proprietary light load mode to provide high efficiency at low output currents. when the llm/sync pin is high, the device is in automatic llm detection mode. when the llm/sync pin is low, the device is forced into pwm mode. in automatic llm detection mode, when a light load condition is detected, the device will: (1) step v out up by approximately 1.0% above the nominal operating output voltage setting, v nom and as low as -0.5% below v nom , and then (2) shut down unnecessary circuitry, and then (3) monitor v out . when v out falls below v nom , the device will repeat (1), (2), and (3). the voltage step up, or pre-positioning, improves transient droop when a load transient causes a transition from llm mode to pwm mode. if a load transient occurs, causing v out to fall below the threshold v min , the device will exit llm operation and begin normal pwm operation. figure 5 demonstrates v out behavior during transition into and out of llm operation. v out i out llm ripple pwm ripple v max v nom v min load step figure 5 . v out behavior in llm operation. many multi-mode dcdc converters suffer from a condition that occurs when the load current increases only slowly so that there is no load transient driving v out below the v min threshold. in this condition, the device would never exit llm operation. this could adversely affect efficiency and cause unwanted ripple. to prevent this from occurring, the EN6347QI periodically exits llm mode into pwm mode and measures the load current. if the load current is above the llm threshold current, the device will remain in pwm mode. if the load current is below the llm threshold, the device will re-enter llm operation. there may be a small overshoot or undershoot in v out when the device exits and re-enters llm. the load current at which the device will enter llm mode is a function of input and output voltage, and the rllm pin resistor. contact enpirion applications support for details regarding the optimization of this resistor for specific operating conditions. for pwm only operation, the rllm pin can be left open. to ensure normal llm operation, llm mode should be enabled and disabled with specific sequencing. for applications with explicit llm pin control, enable llm after v in ramp up is complete. for applications with only enable control, tie llm to enable; and enable the device after v in ramp up is complete. for designs with enable and llm tied to v in , make sure the device soft-start time is longer than the v in ramp-up time. llm will start operating after the soft-start time is completed. note: for proper llm operation the EN6347QI requires a minimum difference between v in and v out , and a minimum llm load requirement as specified in the electrical characteristics table. for llm designs requiring lower voltage headroom or a lower minimum load, contact enpirion applications support. over-current protection the current limit function is achieved by sensing the current flowing through the power pfet. when the sensed current exceeds the over current trip point, both power fets are turned off for the remainder of the switching cycle. if the over-current condition is removed, the over-current protection circuit will enable normal pwm operation. if the over-current condition persists, the soft start capacitor will gradually discharge causing the output voltage to fall. when the ocp fault is removed, the output voltage will ramp back up to the desired voltage. this circuit is designed to provide high noise immunity.
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 11 www.enpirion.com thermal overload protection thermal shutdown circuit will disable device operation when the junction temperature exceeds approximately 150oc. after a thermal shutdown event, when the junction temperature drops by approx 20oc, the converter will re-start with a normal soft-start. input under-voltage lock-out internal circuits ensure that the converter will not start switching until the input voltage is above the specified minimum voltage. hysteresis and input de-glitch circuits ensure high noise immunity and prevent false uvlo triggers. compensation the EN6347QI uses a type 3 compensation network. as noted earlier, a piece of the compensation network is the phase lead capacitor ca in figure 6. this network is optimized for use with about 50-100 ! f of output capacitance and will provide wide loop bandwidth and excellent transient performance for most applications. voltage mode operation provides high noise immunity at light load. in some applications modifications to the compensation may be required. for more information, contact enpirion applications engineering support. application information the EN6347QI output voltage is programmed using a simple resistor divider network. figure 6 shows the resistor divider configuration. ) 75.0 ( * 75.0 200 v vout ra rb k ra ' ( % ( figure 6: v out resistor divider & compensation capacitor an additional compensation capacitor c a is also required in parallel with the upper resistor. input capacitor selection the EN6347QI requires about 20uf of input capacitance. low-cost, low-esr ceramic capacitors should be used as input capacitors for this converter. the dielectric must be x5r or x7r rated. y5v or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. in some applications, lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency decoupling. recommended input capacitors description mfg p/n 10f, 10v, 10% x7r, 1206 (2 capacitors needed) murata grm31cr71a106ka01l taiyo yuden lmk316b7106kl-t 22f, 10v, 20% x5r, 1206 (1 capacitor needed) murata grm31cr61a226me19l taiyo yuden lmk316bj226ml-t output capacitor selection the EN6347QI has been nominally optimized for use with approximately 50-100 ! f of output capacitance. low esr ceramic capacitors are required with x5r or x7r rated dielectric formulation. y5v or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. output ripple voltage is determined by the aggregate output capacitor impedance. output impedance, denoted as z, is comprised of effective series resistance, esr, and effective series inductance, esl: z = esr + esl placing output capacitors in parallel reduces the impedance and will hence result in lower pwm ripple voltage. in addition, higher output capacitance will improve overall regulation and ripple in light-load mode. n total z z z z 1 ... 1 1 1 2 1 ) ) ) (
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 12 www.enpirion.com typical pwm ripple voltages output capacitor configuration typical output ripple (mvp-p) (as measured on EN6347QI evaluation board)* 1 x 47 f 25 47 f + 10 f 15 * note: 20 mhz bw limit recommended output capacitors description mfg p/n 47f, 6.3v, 20% x5r, 1206 (1 or 2 capacitors needed) murata grm31cr60j476me19l taiyo yuden jmk316bj476ml-t 10f, 10v, 10% x5r, 1206 (optional 1 capacitor in parallel with 47f above) murata grm31cr71a106ka01l taiyo yuden lmk316bj226ml-t for best llm performance, we recommend using just 2x47uf capacitors mentioned in the above table, and no 10uf capacitor. the v out sense point should be just after the last output filter capacitor right next to the device. additional bulk output capacitance beyond the above recommendations can be used on the output node of the EN6347QI as long as the bulk capacitors are far enough from the v out sense point such that they dont interfere with the control loop operation. in some cases modifications to the compensation or output filter capacitance may be required to optimize device performance such as transient response, ripple, or hold-up time. the EN6347QI provides the capability to modify the control loop response to allow for customization for such applications. for more information, contact enpirion applications engineering support. power-up sequencing during power-up, enable should not be asserted before pvin, and pvin should not be asserted before avin. tying all three pins together meets these requirements. thermal considerations the enpirion EN6347QI dc-dc converter is packaged in a 7x4x1.85mm 38-pin qfn package. the qfn package is constructed with copper lead frames that have exposed thermal pads. the recommended maximum junction temperature for continuous operation is 125c. continuous operation above 125c will reduce long-term reliability. the device has a thermal overload protection circuit designed to shut it off at a junction temperature specified in the electrical characteristics table. the silicon is mounted on a copper thermal pad that is exposed at the bottom of the package. the thermal resistance from the silicon to the exposed thermal pad is very low. in order to take advantage of this low resistance, the exposed thermal pad on the package should be soldered directly on to a copper ground pad on the printed circuit board (pcb). the pcb then acts as a heat sink. in order for the pcb to be an effective heat sink, the device thermal pad should be coupled to copper ground planes or special heat sink structures designed into the pcb (refer to the layout recommendations section). the junction temperature, t j , is calculated from the ambient temperature, t a , the device power dissipation, pd, and the device junction-to- ambient thermal resistance, " ja in c/w, as follows: t j = t a + (p d ) ( " ja ) the junction temperature, t j , can also be expressed in terms of the device case temperature, t c , and the device junction-to- case thermal resistance, " jc in c/w, as follows: t j = t c + (p d ) ( " jc ) the device case temperature, t c , is the temperature at the center of the exposed thermal pad at the bottom of the package. the device junction-to-ambient and junction-to- case thermal resistances, " ja and " jc , are shown in the thermal characteristics table. the " jc is a function of the device and the qfn package design. the " ja is a function of " jc and the users system design parameters that include the thermal effectiveness of the customer pcb and airflow.
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 13 www.enpirion.com the " ja value shown in the thermal characteristics table on page 3 is for free convection with the device heat sunk (through the thermal pad) to a copper plated four-layer pc board with a full ground and a full power plane following eia/jedec jesd51-7 standard. the " ja can be reduced with the use of forced air convection. because of the strong dependence on the thermal effectiveness of the pcb and the system design, the actual " ja value will be a function of the specific application. layout recommendations figure 7 shows critical components and layer 1 traces of a recommended minimum footprint EN6347QI layout with enable tied to v in in pwm mode. alternate enable configurations, and other small signal pins need to be connected and routed according to specific customer application. please see the gerber files on the enpirion website www.enpirion.com for exact dimensions and other layers. please refer to this figure while reading the layout recommendations in this section. recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the EN6347QI package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the capacitors and the EN6347QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 2: three pgnd pins are dedicated to the input circuit, and three to the output circuit. the slit in figure 7 separating the input and output gnd circuits helps minimize noise coupling between the converter input and output switching loops. recommendation 3: the system ground plane should be the first layer immediately below the surface layer. this ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. please see the gerber files on the enpirion website www.enpirion.com . recommendation 4 : the large thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. figure 7: top pcb layer critical components and copper for minimum footprint the drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. do not use thermal reliefs or spokes to connect the vias to the ground plane. this connection provides the path for heat dissipation from the converter. please see figures: 7, 8, and 9. recommendation 5 : multiple small vias (the same size as the thermal vias discussed in recommendation 4 should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. it is preferred to put these vias under the capacitors along the edge of the gnd copper closest to the +v copper. please see figure 7. these vias connect the input/output filter capacitors to the gnd plane, and help reduce parasitic inductances in the input and output current loops. if the vias cannot be placed under c in and c out , then put them just outside the capacitors along the gnd slit separating the two components. do not use thermal reliefs or spokes to connect these vias to the ground plane.
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 14 www.enpirion.com recommendation 6 : avin is the power supply for the internal small-signal control circuits. it should be connected to the input voltage at a quiet point. in figure 7 this connection is made at the input capacitor close to the v in connection. recommendation 7 : the layer 1 metal under the device must not be more than shown in figure 7. see the section regarding exposed metal on bottom of package. as with any switch-mode dc/dc converter, try not to run sensitive signal or control lines underneath the converter package on other layers. recommendation 8: the v out sense point should be just after the last output filter capacitor. keep the sense trace as short as possible in order to avoid noise coupling into the control loop. recommendation 9 : keep r a , c a , and r b close to the vfb pin (see figures 6 and 7). the vfb pin is a high-impedance, sensitive node. keep the trace to this pin as short as possible. whenever possible, connect r b directly to the agnd pin instead of going through the gnd plane. design considerations for lead-frame based modules exposed metal on bottom of package lead frames offers many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. however, they do require some special considerations. in the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. this results in several small pads being exposed on the bottom of the package. only the large thermal pad and the perimeter pads are to be soldered to the pc board. the pcb top layer under the EN6347QI should be clear of any metal except for the large thermal pad. the grayed-out region in figure 8 represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the pcb. figure 8: lead-frame exposed metal. grey area highl ights exposed metal below which there should not be any metal (traces, vias, or pla nes) on the top layer of pcb. v in copper covered by soldermask acceptable near or under this exposed pad.
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 15 www.enpirion.com recommended pcb footprint figure 9: EN6347QI package pcb footprint dimensions in mm
05991 10/04/2011 rev: b EN6347QI " enpirion 2011 all rights reserved, e&oe 16 www.enpirion.com package and mechanical figure 10: EN6347QI package dimensions contact information enpirion, inc. perryville iii corporate park 53 frontage road - suite 210 hampton, nj 08827 usa phone: +1.908.894.6000 fax: +1.908.894.6090 enpirion reserves the right to make changes in circ uit design and/or specifications at any time withou t notice. information furnished by enpirion is believed to be accurate and reliable. enpirion assu mes no responsibility for its use or for infringeme nt of patents or other third party rights, which ma y result from its use. enpirion products are not auth orized for use in nuclear control systems, as criti cal components in life support systems or equipment used in hazardous environment without the express w ritten authority from enpirion.

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