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  1 ? HA-5033 250mhz video buffer the HA-5033 is a unity gain monolithic ic designed for any application requiring a fast, wideband buffer. featuring a bandwidth of 250mhz and outst anding differential phase/ gain characteristics, this high performance voltage follower is an excellent choice for video circuit design. other features, which include a minimum slew rate of 1000v/ s and high output drive capability, make the HA-5033 applicable for line driver and high speed data conversion circuits. the high performance of this pr oduct is a result of the intersil dielectric isolation process. a major feature of this process is that it produces both pnp and npn high frequency transistors which makes wide bandwidth designs, such as the HA-5033, practical. alternative process methods typically produce a lower ac performance. ordering information pinouts HA-5033 top view HA-5033 (metal can) top view features ? differential phase error . . . . . . . . . . . . . . . . 0.02 degrees ? differential gain error . . . . . . . . . . . . . . . . . . . . . . 0.03% ? high slew rate . . . . . . . . . . . . . . . . . . . . . . . . . 1100v/ s ? wide bandwidth (small signal) . . . . . . . . . . . . . . 250mhz ? wide power bandwidth . . . . . . . . . . . . . . dc to 17.5mhz ? fast rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ns ? high output drive. . . . . . . . . . . . . . 10v with 100 ? load ? wide power supply range . . . . . . . . . . . . . 5v to 16v ? replace costly hybrids applications ?video buffer ? high frequency buffer ? isolation buffer ? high speed line driver ? impedance matching ? current boosters ? high speed a/d input buffers ? related literature - an548, designer?s guide for HA-5033 part number (brand) temp. range ( o c) package pkg. dwg. # ha2-5033-2 -55 to 125 12 pin metal can t12.c ha3-5033-5 0 to 75 8 ld pdip e8.3 1 2 3 4 8 7 6 5 out nc sub- v- v+ nc nc in strate case nc 12 1 2 3 4 11 10 9 8 7 6 5 v+ out v- nc nc nc +in nc nc nc data sheet june 2003 fn2924.5 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 absolute m aximum ratings thermal information voltage between v+ and v- pins. . . . . . . . . . . . . . . . . . . . . . . . 40v dc input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v+ to v- output current (peak) (50ms on/1 second off) . . . . . . . . . 200ma esd rating human body model (per mil-std-883 method 3015.7) . . . . 2000v operating conditions temperature ranges HA-5033-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c HA-5033-5 (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c thermal resistance (typical, note 2) ja ( o c/w) jc ( o c/w) metal can package . . . . . . . . . . . . . . . 65 34 pdip package . . . . . . . . . . . . . . . . . . . 120 n/a maximum junction temperature (note 1) . . . . . . . . . . . . . . . . .175 o c maximum junction temperature (plastic packages) . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 175 o c for the metal can package, and below 150 o c for the plastic packages (see figure 5.). 2. ja is measured with the component mount ed on an evaluation pc board in free air. 3. the maximum operating temperature may have to be derated depending on the output load condition. see figure 5 for more informat ion. electrical specifications v supply = 12v, r s = 50 ? , r l = 100 ? , c l = 10pf, unless otherwise specified parameter test conditions temp. ( o c) HA-5033-2 HA-5033-5 units min typ max min typ max input characteristics offset voltage 25 - 5 15 - 5 15 mv full - 6 25 - 6 25 mv average offset voltage drift full - 33 - - 33 - v/ o c bias current 25 - 20 35 - 20 35 a full - 30 50 - 30 50 a input resistance 25 - 3 - - 3 - m ? input capacitance 25 - 1.6 - - 1.6 - pf input noise voltage 10hz to 100mhz 25 - 20 - - 20 - v p-p transfer characteristics voltage gain r l = 100 ? 25 0.93 - - 0.93 - - v/v r l = 1k ? 25 0.93 0.99 - 0.93 0.99 - v/v r l = 100 ? full 0.92 - - 0.92 - - v/v -3db bandwidth 25 - 250 - - 250 - mhz output characteristics output voltage swing r l = 100 ? full 8 10 - 8 10 - v r l = 1k ? , v s = 15v full 11 12 - 11 12 - v output current 25 80 100 - 80 100 - ma output resistance 25 - 8 - - 8 - ? full power bandwidth v out = 1v rms , r l = 1k ? 25 - 146 - - 146 - mhz full power bandwidth (note 4) 25 15.9 17.5 - 15.9 17.5 - mhz transient response rise time v out = 500mv 25 - 4.6 - - 4.6 - ns propagation delay 25 - 1 - - 1 - ns HA-5033
3 overshoot 25 - 3 - - 3 - % slew rate (note 4) 25 1 1.1 - 1 1.1 - v/ns settling time to 0.1% 25 - 50 - - 50 - ns differential phase error (note 5) 25 - 0.02 - - 0.02 - degree differential gain error (note 5) 25 - 0.03 - - 0.03 - % power supply characteristics supply current 25 - 21 25 - 21 25 ma full - 21 30 - 21 30 ma power supply rejection ratio full 54 - - 54 - - db harmonic distortion v in = 1v rms at 100khz 25 - <0.1 - - <0.1 - % notes: 4. v supply = 15v, v out = 10v, r l = 1k ? . 5. differential gain and phase error are nonlinear signal distor tions found in video system s and are defined as follows: differential gain error is defined as the change in amplitude at the color subcarrier frequenc y as the picture signal is varied from blanking to white lev el. differential phase error is defined as the change in the phase of the color subcarri er as the picture signal is va ried from blanking to white leve l. r l = 300 ? . electrical specifications v supply = 12v, r s = 50 ? , r l = 100 ? , c l = 10pf, unless otherwise specified (continued) parameter test conditions temp. ( o c) HA-5033-2 HA-5033-5 units min typ max min typ max test circuits and waveforms figure 1. slew rate and settling time figure 2. transient response figure 3. settling time and slew rate figure 4. rise time and overshoot +15v r l out in 0.1 f 0.1 f -15v +12v 100 ? out in 0.1 f 0.1 f -12v 10v input 90% output 10% error band 10mv from final value slew ? v/ ? t 0v ? v rate = ? t settling time input 90% output 10% 0v 500mv overshoot note: measured on both positive and negative transitions. HA-5033
4 schematic diagram +10v response +10v response t a = 25 o c, r s = 50w, r l = 100w pulse response test circuits and waveforms (continued) v out v in 0v 0v t a = 25 o c, r s = 50 ?, r l = 100 ? v out v in 0v 0v t a = 25 o c, r s = 50 ?, r l = 1k ? v out v in 0v 0v 500mv 500mv r 4 q 15 q 16 q 19 r 6 q 17 v+ q 18 r 3 q 13 q 14 q 12 q 11 q 3 q 5 v in r 5 v- r 8 q 4 r 9 q 6 r 2 q 10 q 7 q 8 r 1 r 13 q 9 q 2 r 10 r 11 q 1 r 12 v out HA-5033
5 application information layout considerations the wide bandwidth of the HA-5033 necessitates that high frequency circuit layout procedures be followed. failure to follow these guidelines can result in marginal performance. probably the most crucial of the rf/video layout rules is the use of a ground plane. a ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance. this ground plane shielding can also incorporate the metal case of the HA-5033 since pin #2 is internally tied to the package. this feature allows the user to make metal to metal contact between the ground plane and the package, which extends shielding, provides additional heat sinking and eliminates the use of a socket, ic sockets co ntribute inter-lead capacitance which limits device bandwidth and should be avoided. for the pdip, pin 6 can be tied to either supply, grounded, or simply not used. but to optimize device performance and improve isolation, it is recomm ended that this pin be grounded. other considerations are pr oper power supply bypassing and keeping the input and output connections as short as possible which minimizes distributed capacitance and reduces board space. power supply decoupling for optimum device performanc e, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. ceramic capacitors ranging in value from 0.01 f to 0.1 f will minimize high frequency variations in supply voltage. solid tantalum capacitors 1 f or larger will optimize low frequency performance. it is also recommended that the bypass capacitors be connected close to the HA-5033 (preferably directly to the supply pins). figure 5 is based on: where: t jmax = maximum junction temperature of the device t a = ambient temperature ja = junction to ambient thermal resistance p dmax t jmax t a ? ja ------------------------------ - = maximum total power dissipation (w) pdip can quiescent p d = 0.72w at v s = 12v, i cc = 30ma 0.6 0.4 0.2 0 25 45 65 85 105 125 temperature ( o c) 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 figure 5. maximum power dissipation vs temperature typical applications (also see application note an548) figure 6. video coaxial line driver 50 ? system figure 7. video gain block r l rg -58 50 ? r m r s -12v +12v v in 5 12 10 0.1 f 0.1 f 11 50 ? 75 ? video 75 ? output HA-5033 900 ? v- v+ ha-2539 v- v+ 100 ? 15 ? 60 ? r 2 r 1 video signal input + - HA-5033
6 positive pulse response negative pulse response typical applications (also see application note an548) (continued) v out v in 0v 0v t a = 25 o c, r s = 50 ? , r m = r l = 50 ? v o v in r l r l r m + ---------------------- 1 2 -- - v in == v out v in 0v 0v t a = 25 o c, r s = 50 ? , r m = r l = 50 ? v o v in r l r l r m + ---------------------- 1 2 -- - v in == typical performance curves figure 8. input offset voltage vs temperature figure 9. input bias current vs temperature figure 10. supply current vs temperature figure 11. slew rate vs temperature 8 7 6 5 4 -80 40 160 temperature ( o c) offset voltage (mv) 3 2 1 120 80 -40 0 v s = 12v v s = 15v v s = 10v v s = 5v 40 30 20 -55 75 125 temperature ( o c) input bias current ( a) 10 0 -25 25 v s = 15v v s = 12v v s = 5v v s = 10v 30 20 10 0 -55 25 125 temperature ( o c) supply current (ma) 75 -25 v s = 15v v s = 12v v s = 10v v s = 5v temperature ( o c) 3000 2000 1000 slew rate (v/ s) v s = 15v, v in = 10v -55 75 125 -25 25 fall (r l = 1k ? ) fall (r l = 100 ? ) rise (r l = 1k ? ) rise (r l = 100 ? ) HA-5033
7 figure 12. slew rate vs load capacitance figure 13. slew rate vs load capacitance figure 14. gain error vs input voltage figure 15. gain error vs input voltage figure 16. gain error vs temperature figure 17. v in - v out vs i out typical performance curves (continued) capacitance (pf) 5000 10,000 1000 100 0 slew rate (v/ s) 2400 2200 2000 1800 200 400 600 800 1000 1200 1400 1600 v s = 15v, r l = 1k ? t a = 25 o c, v in = 10v fall rise capacitance (pf) 5000 10,000 1000 100 0 slew rate (v/ s) 1400 1300 1200 1100 200 400 500 600 700 800 900 1000 100 v s = 15v, r l = 100 ? t a = 25 o c, v in = 10v fall rise 300 input voltage (v) 0+2+4+6+8+10 -4 -8 -10 output input v os (mv) -80 -40 0 40 80 -6 -2 v s = 15v, t a = 25 o c r l = 10k ? r l = 1k ? 60 20 -20 -60 r l = 10k ? r l = 1k ? input voltage (v) 0 +2+4+6+8+10 -4 -8 -10 output input v os (mv) -900 -500 0 300 900 -6 -2 v s = 15v, t a = 25 o c r l = 50 ? r l = 100 ? r l = 100 ? r l = 50 ? 500 100 -100 -700 -300 700 r l = 1k ? v s = 15v, v o = 10v 160 140 120 100 80 -55 25 125 temperature ( o c) 60 40 20 75 -25 output input v os (mv) 800 700 600 500 200 0 10 80 90 100 i out (ma) v out = -10 v in - v out (mv) 20 30 40 50 60 70 v out = +10 v out = 0 sinking current v out = 0 sourcing current v s = 15, t a = 25 o c 400 300 100 110 120 HA-5033
8 figure 18. y - parameters phase vs frequency figure 19. y - parameter magnitude vs frequency figure 20. power supply rejection ratio vs frequency figure 21. total harmonic distortion vs frequency figure 22. total harmonic distortion vs input voltage figure 23. output voltage swing vs load resistance typical performance curves (continued) 10 6 180 135 90 45 0 -45 -90 -135 -180 phase angle (degrees) frequency (hz) y 12 10 7 10 8 10 9 y 21 y 11 y 22 magnitude (s) 1 10 -1 10 -2 10 -3 10 -4 10 -5 10 6 y 21 , y 22 y 11 y 11 y 12 10 8 10 7 frequency (hz) 10 9 y 12 y 22 y 21 frequency (hz) 1k 10k 100k 1m 10m 10 20 30 40 50 60 70 power supply rejection ratio (db) v s = 12v, t a = 25 o c v s = 12v, r l = 100 ? v in = 1v rms frequency (hz) 100k 10k 1k 100 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 total harmonic distortion (%) input voltage (rms) 0123 0.01 0.1 1.0 total harmonic distortion (%) v = 12v, r l = 100 ? v s = 12v r l = 100 ? f = 100khz 28 24 20 16 12 0 300 600 load resistance ( ? ) peak to peak output voltage (v) 8 4 500 400 100 200 700 800 900 1k t a = 25 o c v s = 15v v s = 12v v s = 10v v s = 5v HA-5033
9 figure 24. output swing vs frequency (note) figure 25. output swing vs frequency (note) note: this curve was obtained by noting the output voltage necessary to produce an observable distortion for a given frequency. if hi gher distortion is acceptable, then a higher output voltage for a given frequency ca n be obtained. however, operating the HA-5033 with increased d istortion (to the right of curve shown), will al so be accompanied by an increase in supply current . the resulting increase in chip temperature mu st be considered and heat sinking will be necessary to prevent thermal runaway. this characteristic is the result of the output transistor opera tion. if the signal amplitude or signal frequency or both ar e increased beyond the curve shown, th e npn, pnp output transistor s will approach a condition of being simultaneously on. under this condition, thermal runaway can occur. typical performance curves (continued) frequency (hz) 10k 100k 1m 10m 0.5 3.5 4.0 4.5 5.0 5.5 6.0 output voltage (v rms ) 100m 1g 3.0 2.5 2.0 1.5 1.0 0 v s = 15v, r l = 100 ? no heat sink in free air frequency (hz) 10k 100k 1m 10m 0.5 3.5 4.0 4.5 5.0 5.5 6.0 output voltage (v rms ) v s = 15v, r l = 1k ? 100m 1g no heat sink in free air 3.0 2.5 2.0 1.5 1.0 0 HA-5033
10 die characteristics die dimensions: 51 mils x 67 mils x 19 mils 1300 m x 1700 m x 483 m metallization: type: al, 1% cu thickness: 16k ? 2k ? passivation: type: nitride (si 3 n 4 ) over silox (sio 2 , 5% phos.) silox thickness: 12k ? 2k ? nitride thickness: 3.5k ? 1.5k ? substrate potential (powered up): unbiased transistor count: 20 process: bipolar dielectric isolation metallization mask layout HA-5033 v+ out v- in HA-5033
11 HA-5033 metal can packages (can) notes: 1. the reference, base, and seatin g planes are the same for this variation. 2. measured from maximum diameter of the product. 3. n is the maximum number of terminal positions. 4. dimensioning and tolerancing per ansi y14.5m - 1982. 5. controlling dimension: inch. ?d ?d1 a l a a reference plane f e k k1 ?b2 ?b base metal lead finish section a-a e 1 1 2 n t12.c 12 lead metal can package symbol inches millimeters notes min max min max a 0.130 0.150 3.30 3.81 - ?b 0.016 0.019 0.41 0.48 - ?b2 0.016 0.021 0.41 0.53 - ?d 0.585 0.615 14.86 15.62 - ?d1 0.540 0.560 13.72 14.22 - e 0.400 bsc 10.16 bsc - e1 0.100 bsc 2.54 bsc - f 0.020 0.040 0.51 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 l 0.500 0.560 12.70 14.22 - n12 123 rev. 0 5/18/94
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HA-5033 dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93


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