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[ak4709] ms1319- e -00 2011/07 - 1 - general description the ak4709 is an i 2 c controlled audio and video switch which has a matrix designed architecture for digital tv and set-top-box applications. the ak4709 offe rs the ideal features for digital set-top-box systems. the ak4709 includes audio switches, video switches, and video filters. the integrated audio driver supports ground referenced outputs, eliminating the need for large ac-coupling capacitors, reducing cost and saving board spac e. the ak4709 is housed in a s pace saving small 48-pin lqfp package. features analog switches for scart audio section ? thd+n: ? 95db (@2vrms) ? dynamic range: 99db (@2vrms), (a-weighted) ? stereo analog volume with pop- noise free circuit (+6db to ?60db & mute) ? analog inputs one full differential stereo input or single-ended input for decoder dac two stereo input (tv & vcr scart) ? analog outputs two stereo outputs (tv & vcr scart) ? ground-referenced outputs eliminate dc-blocking capacitor video section ? integrated lpf: ? 40db@27mhz ? 75ohm driver ? 6db gain for outputs ? four cvbs/y inputs (encx2, tv, vcr) , two cvbs/y outputs (tv, vcr) ? three r/c inputs (encx2, vcr), two r/c output (tv, vcr) ? two g and b inputs (enc, vcr), one g and b outputs (tv) ? bi-directional control for vcr-red/chroma ? y/pb/pr option (to 6mhz) tv/vcr input monitor loop-through mode for standby auto-startup mode for power saving scart pin#16 (fast blanking), pi n#8 (slow blanking) control power supply ? 3.3v+/ ? 5% and 12v+/ ? 10% ? low power dissipation / low power standby mode package ? small 48pin lqfp low power av scart switch ak4709
[ak4709] ms1319- e -00 2011/07 - 2 - block diagram tvoutl tvoutr vcroutl vcroutr tvinl tvinr vcrinl vcrinr ainl+ ainl- ainr- ainr+ bias tv1-0 mono scl sda register control pdn vd1 vcr1-0 vmono amp vss1 volume #0 +6 to -60db (2db/step) vo lum e #1 -6db to +24db (3db/step) cp cn vee vss2 charge pump vd2 audio block
[ak4709] ms1319- e -00 2011/07 - 3 - enc c tvrc enc g/cvbs vcr g tvg enc b/pb vcr b/pb tvb enc y tvvout 6db enc r/c/pr vcrvout vcrc vcr cvbs/y tv cvbs vcr r/c/pr enc cvbs/y encc encg vcrg encb vcrb ency encrc vcrvin tvvin vcrrc encv ( typical connection ) tv scart vcr scart ( typical connection ) vvd2 vss3 vvd1 monitor 6db 6db 6db 6db 6db video block
[ak4709] ms1319- e -00 2011/07 - 4 - monitor vcr fb tvfb 6db 0v 3.0v tvsb vcrsb 0/ 6/ 12v 0/ 6/ 12v vcrfb ( typical connection ) tv scart vcr scart ( typical connection ) int vp fb [1:0] sbt [1:0] sbv [1:0] video blanking block
[ak4709] ms1319- e -00 2011/07 - 5 - ordering guide AK4709EQ -10 +70 c 48pin lqfp (0.5mm pitch) akd4709 evaluation board for ak4709 pin layout a inl- 37 scl 36 38 vee 39 cn 40 cp 41 vss2 42 43 vd2 44 int 45 sda 46 pdn 47 a inr+ 35 34 33 32 31 30 29 28 27 26 vc rc 1 vss3 2 tvvout 3 vvd2 4 tvr c 5 tv g 6 tvb 7 vvd1 8 encb 9 encg 10 encrc 11 23 22 21 20 19 18 17 16 15 14 13 vc rfb vc rvin tvvin top view vc rvout 48 encc 12 24 25 tvfb ainl+ AK4709EQ vcrg vcrr c vp vcrb tvsb vc rsb vss1 en cv en cy vcroutl vcroutr tvinl tvinr vcr inl vcr inr vd1 a inr- tvoutl tvoutr
[ak4709] ms1319- e -00 2011/07 - 6 - pin/function no. pin name i/o function 1 vcrc o chrominance output pin for vcr 2 vss3 - video ground pin , 0v 3 tvvout o composite/luminance output pin for tv 4 vvd2 - video power supply pin #2: 3.13v ~ 3.47v normally connected to vss3 with a 0.1 f ceramic capacitor in parallel with a 4.7 f electrolytic capacitor. 5 tvrc o red/chrominance output pin for tv 6 tvg o green output pin for tv 7 tvb o blue output pin for tv 8 vvd1 - video power supply pin #1: 3.13v ~ 3.47v normally connected to vss3 with a 0.1 f ceramic capacitor in parallel with a 4.7 f electrolytic capacitor. 9 encb i blue input pin for encoder 10 encg i green input pin for encoder 11 encrc i red/chrominance input pin #1 for encoder 12 encc i chrominance input pin #2 for encoder 13 encv i composite/luminance input pin #1 for encoder 14 ency i composite/luminance input pin #2 for encoder 15 tvvin i composite/luminance input pin for tv 16 vcrvin i composite/luminance input pin for vcr 17 vcrfb i fast blanking input pin for vcr 18 vcrrc i red/chrominance input pin for vcr 19 vcrg i green input pin for vcr 20 vcrb i blue input pin for vcr 21 vp - blanking power supply pin, 10.8v ~ 13.2v the vp pin must be connected to the analogue 12v power supply via a 10ohm resistor and with a 0.1f ceramic capacitor in parallel with a 1f electrolytic capacitor to vss1, as shown in figure 20 . 22 vcrsb i/o slow blanking input/output pin for vcr, refer to table 20 . a 470ohm 5% resistor must be connected between the vcrsb pin and scart connector. 23 tvsb o slow blanking output pin for tv a 470ohm 5% resistor must be connected between the tvsb pin and scart connector. 24 vss1 - audio ground pin , 0v 25 vd1 - audio power supply pin: 3.13v ~ 3.47v normally connected to vss1 with a 0.1 f ceramic capacitor in parallel with a 4.7 f electrolytic capacitor. 26 vcrinr i rch vcr audio input pin 27 vcrinl i lch vcr audio input pin 28 tvinr i rch tv audio input pin 29 tvinl i lch tv audio input pin 30 vcroutr o rch analog output pin #1 31 vcroutl o lch analog output pin #1 32 tvoutr o rch anal og output pin #2 33 tvoutl o lch analog output pin #2
[ak4709] ms1319- e -00 2011/07 - 7 - no. pin name i/o function 34 ainrn i rch negative analog input pin 35 ainrp i rch positive analog input pin 36 ainln i lch negative analog input pin 37 ainlp i lch positive analog input pin 38 vee o negative voltage output pin connect to vss2 with a 1.0 f capacitor that should have the low esr ( equivalent series resistance ) over all temperature range. when this capacitor has the polarity, the positive polarity pin should be connected to the vss2 pin. non polarity capacitors can also be used. 39 cn i negative charge pump capacitor terminal pin connect to cp with a 1.0 f capacitor that should have the low esr (equivalent series resistance) over all temperature range. when this capacitor has the polarity, the positive polarity pin should be connected to the cp pin. non polarity capacitors can also be used. 40 cp i positive charge pump capacitor terminal pin connect to cn with a 1.0 f capacitor that should have the low esr (equivalent series resistance) over all temperature range. when this capacitor has the polarity, the positive polarity pin should be connected to the cp pin. non polarity capacitors can also be used. 41 vss2 - charge pump ground pin , 0v 42 vd2 - charge pump power supply pin: 3.13v ~ 3.47v normally connected to vss2 with a 0.1 f ceramic capacitor in parallel with a 4.7 f electrolytic cap. 43 int o interrupt pin for video blanking normally connected to vvd1(3.3v) through 10k resistor externally. 44 scl i i 2 c control data clock pin 45 sda i/o i 2 c control data pin 46 pdn i power-down mode pin when at ?l?, the ak4709 is in the power-down mode and is held in reset. the ak4709 should always be reset upon power-up. 47 vcrvout o composite/luminance output pin for vcr 48 tvfb o fast blanking output pin for tv note: scl, sda, pdn pins should not be left floating.
[ak4709] ms1319- e -00 2011/07 - 8 - absolute maximum ratings (vss1 =vss2 =vss3 = 0v; note 1 ) parameter symbol min max units power supply ( note 2 ) vd1 vd2 vvd1 vvd2 vp ? 0.3 -0.3 ? 0.3 ? 0.3 ? 0.3 4.0 4.0 4.0 4.0 14 v v v v v input current (any pins except for supplies) iin - 10 ma digital input voltage(pdn pin) vind1 ? 0.3 vvd1+0.3 v digital input voltage(scl, sda pins) vind2 ? 0.3 4.0 v video input voltage vinv ? 0.3 vvd1+0.3 v audio input voltage ( note 3 ) vina vee-0.3 vd1+0.3 v ambient operating temperature ta ? 10 70 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. vss1, vss2 and vss3 must be connected to the same analog ground plane. note 3. vee: vee pin voltage. the internal negative power supply generating circuit provides negative power supply(vee). the pdn pin, auto bit, mute bit, stby bit and amp bit control operation mode as shown in table 2 and table 3 . mode vee pin voltage 0 full power-down no video input 0v 1 auto startup mode (power-on default) video input -vd2+0.2v 2 standby & mute 0v 3 standby -vd2+0.2v 4 mute 0v no video input 0v 5 normal operation video input -vd2+0.2v table 1. vee pin voltage warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes.
[ak4709] ms1319-j-00 2011/07 - 9 - recommended operating conditions (vss1 =vss2 =vss3 = 0v; note 1 ) parameter symbol min typ max units power supply ( note 4 ) vd1 vd2 vvd1 vvd2 vp 3.13 3.13 3.13 3.13 10.8 3.3 3.3 3.3 3.3 12 3.47 3.47 3.47 3.47 13.2 v v v v v note 1. all voltages with respect to ground. note 4. vvd1 and vvd2 must be connected to the same voltage. *akm assumes no responsibility for the usage beyond recommended operating conditions in this datasheet. electrical characteristics (ta = 25 c; vp = 12v, vd1 = vd2 = vvd1 = vvd2 = 3.3v) power supplies min typ max units power supply current normal operation (pdn = ?h?) vd1+vd2+vvd1+vvd2 (no load, note 5 ) vd1+vd2+vvd1+vvd2 (with load, note 6 ) vp power-down mode (pdn = ?l?) ( note7 ) vd1+vd2 vvd1+vvd2 vp 0.49 85 80 0 0 80 0.74 120 10 10 120 ma ma a a a a note 5. stby bit = ?0?, all video outputs active. no signal, no load for a/v switches. note 6. all video outputs active. audio output: 1khz 2vrms output with 4.5k load at all audio output pins. video output: 100% color bar output with 150 load at all video output pins. slow blanking (default setting): sbio1-0 bits= ?00?, sbt1-0 bits= ?00?, sbv1-0 bits= ?00? note7. all digital inputs are held at vvd1 or vss3. no signal, no load for a/v switches. digital characteristics (ta = 25 c; vd1 = vd2 = vvd1 = vvd2 = 3.13 3.47v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%vvd1 - - - - 30%vvd1 v v low-level output voltage (sda pin: iout= 3ma, int pin: iout= 1ma) vol - - 0.4 v input leakage current iin - - 10 a
[ak4709] ms1319- e -00 2011/07 - 10 - analog characteristics (audio) (ta=25 c; vp=12v, vd1=vd2=vvd1=vvd2=3 .3v; signal frequency=1khz; measurement frequency=20hz 20khz; r l 4.5k ; 0db=2vrms output; volume#0=volume#1=0db, unless otherwise specified) parameter min typ max units analog input: (tvinl/tvinr/vcrinl/vcrinr pins) analog input characteristics input voltage ( note 6 ) 2.0 vrms input resistance 100 150 - k analog input: (ainl+/ainl-/ainr-/ainr+ pins) analog input characteristics input voltage (ain+) ? (ain ? ), ( note 6 ) 2.0 vrms input resistance 80 125 k stereo/mono output: (tvoutl/tvoutr/vcroutl/vcrout r pins) ( note 7 ) analog output characteristics volume#0 step width 2.3 3.0 3.7 db volume#1 step width (+6db to ?12db) (-12db to ?40db) (-40db to ?60db) 1.6 0.5 0.1 2 2 2 2.4 3.5 3.9 db db db thd+n (at 2vrms, note 9 , note 10 , note 11 ) ? 95 ? 84 db dynamic range ( ? 60db output, a-weighted, note 9 ) 92 99 db s/n (a-weighted) (2vrms output , vo1#0=vo1#1=0db, note 9 , note 13 ) 92 99 db interchannel isolation ( note 9 , note 12 ) 80 110 db interchannel gain mismatch ( note 9 , note 12 ) -0.5 0 +0.5 db dc offset ( note 14 ) -5 0 +5 mv gain drift - 200 - ppm/ c load resistance tvoutl/r, vcroutl/r 4.5 k load capacitance tvoutl/r, vcroutl/r 20 pf output voltage ( note 8 ) 1.85 2 2.15 vrms power supply rejection (psr) ( note 15 ) - 50 db note 6. f = 1khz, thd+n < -80db, gain = 0db(volume#0=volume#1=0db) note 7. measured by audio precision system two cascade. note 8. the output level of the internal amp with volume #0 should be less than 2vrms. the output level must be adjust ed by the volume #1 when output level of the ak4709 exceeds 2vrms. the audio output must not exceed 2.15vrms. note 9. analog in to tvout/vcrout. path: ainl+/- tvoutl, ainr+/- tvoutr, ainl+/- vcroutl, ainr+/- vcroutr volume#0=volume#1=0db. note 10. differential input. -86db(typ) at vd= 3.13v when single-ended input,-90db(typ) at f = 1khz. -75db(typ) at f = 10khz note 11. -78db (typ) referred to 0.5vrms output level at volume#0=+24db, volume#1= 0db. -80db (typ) reffered to 0.5vrms output level at volume#0 = +21db, volume#1=0db path: ainl+/- tvoutl, ainr+/- tvoutr, ainl+/- vcroutl, ainr+/- vcroutr note 12. between tvoutl and tvoutr with analog inputs ainl+/ ? , ainl/r+/ ? , 1khz/0db. note 13. analog in to tvout/vcrout. path: ainl+/- tvoutl, ainr+/- tvoutr, ainl+/- vcroutl, ainr+/- vcroutr 81db (typ) volume#0 = +24db, volume#1= 0db 83db (typ) volume#0 = +21db, volume#1= 0db note 14. analog in to tvout. volume#0=volume#1=0db path: ainl+/- tvoutl, ainr+/- tvoutr, vcrinl tvoutl, vcrinr tvoutr note 15. the psr is applied to vd1 and vd2 with 1khz, 100mv.
[ak4709] ms1319- e -00 2011/07 - 11 - analog characteristics (video) (ta = 25 c; vp = 12v, vd1=vd2= vvd1 = vvd2 = 3.3v; unless otherwise specified.) parameter conditions min typ max units sync tip clamp voltage at output pin. 0.24 v r/g/b clamp voltage at output pin. 0.24 v pb/pr clamp voltage at output pin. 1.49 v chrominance bias voltage at output pin. 1.49 v gain input = 0.3vp-p, 100khz 5.5 6 6.5 db interchannel gain mismatch1 tvrc, tvg, tvb. input = 0.3vp-p, 100khz. -0.5 - 0.5 db interchannel gain mismatch2 vcrc, vcrgo, vcrbo. input = 0.3vp-p, 100khz. -0.5 - 0.5 db frequency response input=0.3vp-p, c1=c2=0pf. 100khz to 6mhz. at 10mhz. at 27mhz. -1.0 -3 -40 0.5 -20 db db db group delay distortion at 4.43mhz with respect to 1mhz. 20 ns input impedance chrominance input (internally biased) 40 60 - k input signal f = 100khz, maximum with distortion < 1.0%, gain = 6db. - - 1.25 vpp load resistance ( figure 1 ) 150 - - load capacitance c1 ( figure 1 ) c2 ( figure 1 ) 400 15 pf pf dynamic output signal f = 100khz, maximum with distortion < 1.0% - - 2.5 vpp y/c crosstalk f = 4.43mhz, 1vp-p input. among tvvout, tvrc and vcrvout outputs. - ? 50 - db s/n reference level = 0.7vp-p, ccir 567 weighting. bw = 15khz to 5mhz. - 74 - db differential gain 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - 0.6 - % differential phase 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - 0.8 - degree video signal output 75 ohm 75 ohm max: 400pf c1 r1 r2 max: 15pf c2 figure 1. load resistance r1+r2 and load capacitance c1/c2.
[ak4709] ms1319- e -00 2011/07 - 12 - switching characteristics (ta = 25 c; vp = 10.8 13.2v, vd1=vd2= vvd1 = vvd2 = 3.13 3.47v) parameter symbol min typ max units control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 16 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf reset timing pdn pulse width ( note 17 ) tpd 150 ns note 16. data must be held for sufficient tim e to bridge the 300 ns transition time of scl. note 17. the ak4709 should be reset once by bringing the pdn pin = ?l? after all power supplies are supplied. note 18. i 2 c-bus is a trademark of nxp b.v.
[ak4709] ms1319- e -00 2011/07 - 13 - timing diagram thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing tpd vil pdn power-down timing
[ak4709] ms1319- e -00 2011/07 - 14 - operation overview 1. system reset and power-down options the ak4709 should be reset once by bringing pdn pin = ?l? after all power supplies are supplied. the ak4709 has several operation modes. the pdn pin, auto bit, mute bit, stby bit and amp bit control operation mode as shown in table 2 and table 3 . system reset and full power-down mode the ak4709 should be reset once by bringing pdn pin = ?l? after all power supplies are supplied. pdn pin: power down pin l: full power-down mode. power-down, reset and initializes the control register. h: device active. auto startup mode after the pdn pin is set to ?h?, the ak4709 is in the auto startup mode. in this mode, all blocks except for the video detection circuit are powered down (low power mode). on ce the video detection circuit detects video signal from tvvin pin or vcrvin pin, the ak4709 goes to the stand-by mode automatically and sends ?l? pulse via int pin. the sources of tvoutl/r are fixed to vcrinl/r, the sources of vcroutl/r are fixed to tvinl/r respectively. the source of dc- restore circuit is vcrvin pin. to exit the auto startup mode, set the auto bit to ?0?. auto bit (00h d3): auto startup bit 0: auto startup disable. (manual startup) 1: auto startup enable. (default) mute mode when the mute bit = ?1? and auto bit= ?0?, the audio outputs settle to vss(0v, typ) and the charge pump circuit is in power down mode. mute bit (00h d1): audio output control 0: normal operation. 1: all audio outputs to gnd (default) standby mode when the auto bit = mute bit = ?0? and the stby bit = ?1?, the ak4709 is forced into tv-vcr loop through mode. in this mode, the sources of tvoutl/r pins are fixed to vcrinl/r pins; the sources of vcroutl/r are fixed to tvinl/r pins respectively. all register va lues are not changed by stby bit = ?1?. stby bit (00h d0): standby bit 0: normal operation. 1: standby mode. (default)
[ak4709] ms1319- e -00 2011/07 - 15 - mode pdn pin auto bit stby bit mute bit mode 0 ?l? x x x full power-down 1 ?h? 1 x x auto startup mode (power-on default) 2 ?h? 0 1 1 standby & mute 3 ?h? 0 1 0 standby 4 ?h? 0 0 1 mute ( note 19 ) (amp power down) 5 ?h? 0 0 0 normal operation (amp operation) note 19. tvoutl/r are muted by mute bit in the default state. table 2. operation mode settings (x: don?t care) mode register control audio charge pump video output tvfb vcrsb tvsb power consumption 0 full power-down not available 1mw (typ) no video input power down hi-z hi-z pull -down ( note 20 ) 2.5mw(typ) 1 auto startup mode (power-on default) video input ( note 21 ) active active ( note 22 ) 290mw(typ) ( note 23 ) hi-z 2.5mw(typ) ( note 24 ) 2 standby & mute power down active ( note 25 ) 260mw (typ) ( note 23 ) hi-z 2.5mw (typ) ( note 24 ) 3 standby active active ( note 25 ) 290mw(typ) ( note 23 ) hi-z 2.5mw(typ) ( note 24 ) 4 mute (amp power down) power down active ( note 25 ) 260mw (typ) ( note 23 ) no video input power down hi-z 2.5mw(typ) hi-z 2.5mw(typ) 5 normal operation (amp operation) video input available active active ( note 25 ) active active 290mw(typ) ( note 23 ) note 20. internally pulled down by 120k (typ) resistor. note 21. video input to tvvin or vcrvin. note 22. vcrc output 0v for termination. note 23. all video outputs active. audio output: 1khz 2vrms output, video output: 100% color bar output. slow blanking (default setting): sbio1-0 bits= ?00?, sbt1-0 bits= ?00?, sbv1-0 bits= ?00? note 24. all video amp power down. note 25. the video output status is hi-z (default) when output enable register (05h) is ?0?, and it is active when output enable register (05h) is ?1?. table 3. status of each operation mode
[ak4709] ms1319- e -00 2011/07 - 16 - typical operation sequence (auto setup mode) the figure 2 shows an example of the system timing at auto startup mode. auto startup enable pdn pin a udio out (dc) tvvout, vcrvout active (loop-through) tvvin signal in no signal don?t care signal in no signal don?t care vcrvin signal in no signal don?t care don?t care active (loop-through) hi-z hi-z active (loop-through) (gnd) active (loop- through) no signal no signal hi-z low power mode low power mode low power mode a uto bit ?1?(default) charge pump video detect 50ms(max) 50ms(max) 125ms(max) 125ms(max) figure 2. auto startup mode sequence typical operation sequence (except auto setup mode) figure 3 shows an example of the system timing at normal operation mode. pdn p in stby bit ?0? ?1? ?1? (default) mute bit ?0? ?stand-by? ?1? ?0? ?mute? tvoutl/r amp tv-source select vcr in vcr in vcr in vcr in fixed to vcr in(loop-through) ?1? (default) a uto bit ?0? amp amp fixed to vcr in(loop-through) ?1? charge pump ?normal? ?normal? ?stand-by? ?stand-by & ?stand-by & vcr in vcr in 50ms(max) 50ms(max) (note26) video detect ?1? ( default ) video signal signal in no signal no signal 125ms(max) video output hi-z active hi-z (note26) 50ms(max) (gnd) 50ms(max) note 26. mute the analog outputs externally if click noise affects the system. figure 3. typical operating sequence
[ak4709] ms1319- e -00 2011/07 - 17 - 2. audio block switch control the ak4709 has switch matrixes designed primarily for scart routing. those are controlled via the control register as shown in table 4 and table 5 (please refer to the block diagram). (01h: d1-d0) tv1 tv0 source of tvoutl/r 0 0 amp 0 1 vcrin (default) 1 0 mute 1 1 (reserved) table 4. tvout switch configuration (01h: d5-d4) vcr1 vcr0 source of vcroutl/r 0 0 amp 0 1 tvin (default) 1 0 mute 1 1 volume#1 output table 5. vcrout switch configuration volume control #0 (11-level volume) the ak4709 has a 11-level volume control (volume #0) as shown in table 6 . the volume reflects the change of register value immediately. figure 4. volume #0(volume gain=0db: default), full differential stereo input (0dh: d6-d3) vol3 vol2 vol1 vol0 volume #0 gain output level (typ) 1 1 x x na - 1 0 1 1 +24db 2vrms (with 0.13vrms differential input) 1 0 1 0 +21db - 1 0 0 1 +18db 2vrms (with 0.25vrms differential input) 1 0 0 0 +15db - 0 1 1 1 +12db 2vrms (with 0.5vrms differential input) 0 1 1 0 +9db - 0 1 0 1 +6db 2vrms (with 1vrms differential input) 0 1 0 0 +3db - 0 0 1 1 0db 2vrms (with 2vrms differential input: default) 0 0 1 0 -3db - 0 0 0 1 -6db 1vrms (with 2vrms differential input) 0 0 0 0 mute - note: volume #1=0db (x: don?t care) table 6. volume #0, full differential stereo input 2vrms differential input tvoutl/r (vcroutl/r) ainl/r+ ainl/r- volume gain 0db vol ume #0 1vrms 1vrms 2vrms 0.47 0.47 300 300
[ak4709] ms1319- e -00 2011/07 - 18 - figure 5. volume #0(volume gain=0db:default), single-ended input (0dh: d6-d3) vol3 vol2 vol1 vol0 volume #0 gain output level (typ) 1 1 x x na - 1 0 1 1 +24db 2vrms (with 0.13vrms input) 1 0 1 0 +21db - 1 0 0 1 +18db 2vrms (with 0.25vrms input) 1 0 0 0 +15db - 0 1 1 1 +12db 2vrms (with 0.5vrms input) 0 1 1 0 +9db - 0 1 0 1 +6db 2vrms (with 1vrms input) 0 1 0 0 +3db - 0 0 1 1 0db 2vrms (with 2vrms input: default) 0 0 1 0 -3db - 0 0 0 1 -6db 1vrms (with 2vrms input) 0 0 0 0 mute - note: volume #1=0db (x: don?t care) table 7. volume #0, single-ended input ainl/r+ a inl/r- tvoutl/r (vcroutl/r) vo lume ga in 0 db volume #0 2vrms 2vrms 0.47 0.47 300 300
[ak4709] ms1319- e -00 2011/07 - 19 - volume control #1 (main volume) the ak4709 has main volume control (volume #1) as shown in table 8 . (02h: d5-d0) l5 l4 l3 l2 l1 l0 gain 1 0 0 0 1 0 +6db 1 0 0 0 0 1 +4db 1 0 0 0 0 0 +2db 0 1 1 1 1 1 0db (default) ? ? ? ? ? ? ? 0 0 0 0 0 1 -60db 0 0 0 0 0 0 mute note: the output must not exceed 2.15vrms. table 8. volume #1 when the mod bit = ?1?(default), changing volume levels doe s not cause pop noise. mdt1-0 bits select the transition time ( table 9 ). when the new gain value 1eh(-2db) is written to gain resistor while the actual (stable) gain is 1fh(0db), the gain changes to 1eh(-2db) within the transition time selected by mdt1-0 bits. the built-in volume controller compares the actual gain to the value of gain register after finishing the transition time, and re-changes the actual gain to new resister value within the transition time if the register value is different from the actual gain when compared. when the mod bit = ?0? then there is no transition time and the gain changes immediately. this change may cause a click noise. a ctual gain gain register transition time (5.3ms to 42.7ms pop free.) 1fh 1eh 1dh 1eh 1fh 1dh wr [gain=1eh] wr [gain=1ch] wr [gain=1dh] 1ch 1ch compare compare compare (to 1eh) (to 1dh) (to 1ch) figure 6. volume change operation (mod bit = ?1?) mdt1 mdt0 transition time 0 0 5.3ms 0 1 10.7ms 1 0 21.3ms 1 1 42.7ms (default) table 9. volume transition time (typ.)
[ak4709] ms1319- e -00 2011/07 - 20 - analog output block the ak4709 has chargepump circuit generating negative power supply rail from a 3.3v(typ) power supply. ( figure 7 ) it allows the ak4709 to output audio signal centered at vss (0v, typ) as shown in figure 8 . negative power generating circuit ( figure 7 ) needs 1.0uf capacitors (ca, cb) with low esr (equi valent series resistance). when using capacitors with a polarity, the positive side should be connected to cp and vss2 for capacitor ca and cb, respectively. when the mute bit = ?1?, the charge pump circuit is in power down mode and its analog outputs become vss (0v, typ). vd charge pump cp cn vss2 vee 1uf 1uf negative power a k4709 (+) cb ca (+) figure 7. negative power generate circuit tvoutr/tvoutl a k4709 (vcroutr/vcroutl) 0v 2vrms figure 8. audio signal output
[ak4709] ms1319- e -00 2011/07 - 21 - 3. video block video switch control the ak4709 has switches for tv and vcr. each switch can be controlled via the register s independently. when auto bit = ?1? or stby bit = ?1?, these switches setting is ignored and set to fixed confi guration (loop-through mode). please refer the auto startup mode and standby mode. (04h: d2-d0) mode vtv2-0 bit source of tvvout pin source of tvrc pin source of tvg pin source of tvb pin shutdown 000 (hi-z) (hi-z) (hi-z) (hi-z) encoder cvbs+rgb or encoder ypbpr 001 encv pin (encoder cvbs or y) encrc pin (encoder red,c or pb) encg pin (encoder green or y) encb pin (encoder blue or pr) encoder y/c 1 010 encv pin (encoder y) encrc pin (encoder c) (hi-z) (hi-z) encoder y/c 2 011 ency pin (encoder y) encc pin (encoder c) (hi-z) (hi-z) vcr (default) 100 vcrvin pin (vcr cvbs or y) vcrrc pin (vcr red,c or pb) vcrg pin (vcr green or y) vcrb pin (vcr blue or pr) tv cvbs 101 tvvin pin (tv cvbs) (hi-z) (hi-z) (hi-z) (reserved) 110 - - - - (reserved) 111 - - - - table 10. tv video output ( note 27 ) (04h: d5-d3) mode vvcr2-0 bit source of vcrvout pin source of vcrc pin shutdown 000 (hi-z) (hi-z) encoder cvbs or y/c 1 001 encv pin (encoder cvbs or y) encrc pin (encoder c) encoder cvbs or y/c 2 010 ency pin (encoder cvbs or y) encc pin (encoder c) tv cvbs (default) 011 tvvin pin (tv cvbs) (hi-z) vcr 100 vcrvin pin (vcr cvbs) vcrrc pin (vcr red, c) (reserved) 101 - - (reserved) 110 - - (reserved) 111 - - table 11. vcr video output (refer note 27 ) note 27. when input the video signal via encrc pi n or vcrrc pin, set clamp1-0 bits respectively.
[ak4709] ms1319- e -00 2011/07 - 22 - video output control (05h: d6-d0,) each video output can be set to hi-z i ndividually via the control re gisters. these settings are ignored when the auto bit = ?1?. tvv: tvvout output control tvr: tvrcout output control tvg: tvgout output control tvb: tvbout output control vcrv: vcrvout output control vcrc: vcrc output control tvfb: tvfb output control 0: hi-z. (default) 1: active. rgb/chroma bi-directional control for vcr scart (05h: d7, d5) the ak4709 supports the bi-directional rgb/chroma signal on the vcr scart. (ak4709) vcrrc pin vcrc pin vcr scart 75 0.1u (cio bit & vcrc bit) #15 pin figure 9. vcr red/chroma bi-directional control cio vcrc state of vcrc pin 0 0 hi-z (default) 0 1 active 1 0 connected to gnd 1 1 connected to gnd table 12. vcr red/chroma bi-directional control
[ak4709] ms1319- e -00 2011/07 - 23 - clamp and dc-restore circuit control (06h: d7-d2) each cvbs and y input has the sync tip clamp circuit. th e dc-restore circuit has two clamp voltages 0.24v(typ) and 1.49v(typ) to support both rgb and yp bpr signal. they correspond to 0.12v (typ) and 0.75v(typ) at the scart connector when matched by 75 resistors. the clamp1, clamp0 and clam pb bits select the input circuit for encrc pin (encoder red/chroma), encb pin (encoder bl ue), vcrrc pin (vcr red/chroma) and vcrb pin (vcr blue) respectively. vclp2-0 bits select th e sync source of dc- restore circuit. clampb clamp0 vcrrc input circuit vcrb input circuit note 0 0 dc restore clamp active (0.24v at sync timing/output pin) dc restore clamp active (0.24v at sync timing/output pin) for rgb 0 1 biased (1.49v at sync timing/output pin) (dc restore clamp active) (0.24v at sync timing output pin) for y/c (default) 1 0 dc restore clamp active (1.49v at sync timing/output pin) dc restore clamp active (1.49v at sync timing/output pin) for y/pb/pr 1 1 (reserved) (reserved) table 13. dc-restore control for vcr input clampb clamp1 encrc input circ uit encb input circuit note 0 0 dc restore clamp active (0.24v at sync timing/output pin) dc restore clamp active (0.24v at sync timing/output pin) for rgb (default) 0 1 biased (1.49v at sync timing/output pin) dc restore clamp active (0.24v at sync timing output pin) for y/c 1 0 dc restore clamp active (1.49v at sync timing/output pin) dc restore clamp active (1.49v at sync timing/output pin) for y/pb/pr 1 1 (reserved) (reserved) table 14. dc-restore c ontrol for encoder input clamp2 encg input circuit note 0 dc restore clamp active (0.24v at sync timing/output pin) for rgb (default) 1 sync tip clamp active (0.24v at sync timing/output pin) for y/pb/pr note: when the vtv2-0 bits = ?001? (source for tv = en coder cvbs /rgb), tvg bit = ?1? (tvg = active) and vclp1-0 bits = ?11? (dc restore source = encg), the sync tip is selected even if the clamp2 bit = ?0?. table 15. dc-restore control for encoder green/y input vclp2-0: dc restore source control vclp2 vclp1 vclp0 sync source of dc restore 0 0 0 encv (default) 0 0 1 ency 0 1 0 vcrvin 0 1 1 encg 1 0 0 vcrg 1 0 1 (reserved) 1 1 0 (reserved) 1 1 1 (reserved) note: when the auto bit = ?1?, the source is fixed to vcrvin. table 16. dc-restore source control
[ak4709] ms1319- e -00 2011/07 - 24 - 4. blanking control the ak4709 supports fast blanking signa ls and slow blanking (function sw itching) signals for tv/vcr scart. input/output control for fast/slow blanking fb1-0: tv fast blanking output control (07h: d1-d0) fb1 bit fb0 bit tvfb pin output level 0 0 0v (default) 0 1 2v< 3.0v(typ) at 150 load 1 0 same as vcr fb input (2.5v/0v) 1 1 (reserved) table 17. tv fast blanking output (note: minimum load is 150 ) sbt1-0: tv slow blanking output control (07h: d3-d2) sbt1 bit sbt0 bit tvsb pin output level 0 0 < 2v (default) 0 1 4.73v <, < 7v 1 0 (reserved) 1 1 10v < table 18. tv slow blanking output (note: minimum load is 10k ) sbv1-0: vcr slow blanking output control (07h: d5-d4) sbv1 bit sbv0 bit vcrsb pin output level 0 0 < 2v (default) 0 1 4.73v <, < 7v 1 0 (reserved) 1 1 10v < table 19. vcr slow blanking output (note: minimum load is 10k ) sbio1-0: tv/vcr slow blanki ng i/o control (07h: d7-d6) sbio1 bit sbio0 bit vcrsb pin direction tvsb pin direction 0 0 output (controlled by sbv1-0 bits) output (controlled by sbt1-0 bits) (default) 0 1 (reserved) (reserved) 1 0 input (stored in svcr1-0 bits) output (controlled by sbt1-0 bits) 1 1 input (stored in svcr1-0 bits) output (same output as vcr sb) table 20. tv/vcr slow blanking i/o control
[ak4709] ms1319- e -00 2011/07 - 25 - 5. monitor options and int function monitor options (08h: d4-d0) the ak4709 has several detection functi ons. svcr1-0 bits, fvcr bit, vcmon bit and tvmon bit reflect the input dc level of vcr slow blanking, the input dc level of vcr fast blanking and si gnals input to tvvin or vcrvin pins. svcr1-0: vcr slow bla nking status monitor svcr1-0 bits reflect the voltage at vcrsb pin only when the vcrsb is in the input mode. when the vcrsb is in the output mode, svcr1-0 bits hold previous value. vcrsb pin input level svcr1 bit svcr0 bit < 2v 0 0 4.5 to 7v 0 1 (reserved) 1 0 9.5 < 1 1 table 21. vcr slow blanking monitor fvcr: vcr fast blanki ng input level monitor this bit is enable d when tvfb bit = ?1?. vcrfb pin input level fvcr bit < 0.4v 0 1v < 1 table 22. vcr fast blanking monit or (typical threshold is 0.7v) vcmon: vcrvin pin video input monitor (mcomn bit = ?1?), tvvin pin or vcrvin pin video input monitor (mcomn bit = ?0?) 0: no video signal detected. 1: detects video signal. tvmon: tvvin pin video input mon itor (active when mcomn bit = ?1?) 0: no video signal detected. 1: detects video signal. auto (00h d3) mcomn (09h d7) tvvin signal vcrvin signal tvmon (08h d4) vcmon (08h d3) 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 1 1 1 1 x 0 0 0 0 1 x 0 1 0 1 1 x 1 0 0 1 1 x 1 1 0 1 (x: don?t care) note 28. tvvin/vcrvin signal: signal 0 = no signal applied, signal 1 = signal applied table 23. tv/vcr monitor function
[ak4709] ms1319- e -00 2011/07 - 26 - int function and mask options (09h: d3-d1) changes of the 08h status can be monitored via the int pin. the int pin is an ope n drain output and goes ?l? for 2 s (typ.) when the status of 08h is changed. th is pin should be tied to vvd1 (typ. 3.3v) via 10k resistor or lower voltage through 10k resistor. mtv bit, mvc bit, mcom n bit, mfvcr bit and msvcr bit control the reflection of the status change of these monitors onto the int pin from report to prevent to masks each monitor. ak4709 r=10k ? int 3.3v up figure 10. int pin mvc: vcmon mask. refer table 25 . mtv: tvmon mask. refer table 24 . mcomn: refer table 23 auto (00h d3) tvmon (08h d4) mtv (09h d4) int 0 no change 0 hi-z 0 no change 1 hi-z 0 change 0 generates ?l? pulse 0 change 1 hi-z 1 no change 0 hi-z 1 no change 1 hi-z note 29. when the stby bit = ?0?, th e tv monitor mask function is enabled. note 30. when auto bit = ?1?, tvmon does not change table 24. tv monitor mask auto (00h d3) vcmon (08h d3) mvc (09h d3) int 0 no change 0 hi-z 0 no change 1 hi-z 0 change 0 generates ?l? pulse 0 change 1 hi-z 1 no change 0 hi-z 1 no change 1 hi-z 1 change 0 generates ?l? pulse 1 change 1 generates ?l? pulse note 31. when the stby bit = ?0?, th e vcr monitor mask function is enabled. table 25. vcr monitor mask mfvcr: fvcr monitor mask. 0: change of fvcr is reflected to int pin. (default) 1: change of fvcr is not reflected to int pin. msvcr: svcr1-0 monitor mask 0: change of svcr1-0 is reflect ed to int pin. (default) 1: change of svcr1-0 is not reflected to int pin.
[ak4709] ms1319- e -00 2011/07 - 27 - 6. control interface (i 2 c-bus control) 1. write operations figure 11 shows the data transfer sequence in i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 17 ). after the start condition, a slave address is sent. this address is 7bits long followed by the eighth bit th at is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010001?. if the slave address match that of the ak4709, the ak4709 generates the acknowledge and the opera tion is executed. the master must generate the acknowledge-related clock pul se and release the sda line (high) during the acknowledge clock pulse ( figure 19 ). a ?1? for r/w bit indicates that the read operation is to be ex ecuted. a ?0? indicates that the write operation is to be executed. the second byte consists of th e address for control registers of the ak4709. the format is msb first, and those most significant 3-bits are fixed to zeros ( figure 13 ). the data after the second byte contain control data. the format is msb first, 8bits ( figure 14 ). the ak4709 generates an acknowledge after each by te has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 17 ). the ak4709 can execute multiple one byte write operations in a sequence. after receipt of the third byte, the ak4709 generates an acknowledge, and awaits the next data again. the master can tr ansmit more than one byte instead of terminating the write cycle after the first data byte is tr ansferred. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 0dh prior to generating the stop condition, the addre ss counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high pe riod of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low ( figure 19 ) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k figure 11. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 0 1 r/w figure 12. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 13. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 14. byte structure after the second byte
[ak4709] ms1319- e -00 2011/07 - 28 - 2. read operations set r/w bit = ?1? for read operations. after transmission of da ta, the master can read the next address?s data by generating an acknowledge instead of termina ting the write cycle after the receipt th e first data word. after the receipt of each data, the internal address counter is incremented by one, a nd the next data is taken into next address automatically. if the address exceeds 09h prior to generati ng the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the ak4709 supports two basic read operations : current address read and random read. 2-1. current address read the ak4709 contains an internal address counter that mainta ins the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the ak4709 generates an acknowledge, transmits 1byte data which address is set by th e internal address counter and increments the internal address counter by 1. if the master does not ge nerate an acknowledge to the data but generate the stop condition, the ak4709 discontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n+1) p s t o p data(n+x) a c k data(n+2) a c k r/w= ?1? a c k data(n) figure 15. current address read 2-2. random read random read operation allows the master to access any mem ory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write ope ration. the master issues a start condition, slave address (r/w bit = ?0?) and then th e register address to read. after the re gister address is acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit se t to ?1?. then the ak4709 generates an acknowledge, 1-byte data and increments the internal addre ss counter by 1. if the mast er does not generate an acknowledge to the data but generate the stop condition, the ak4709 discontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k sub a ddress(n) s t a r t a c k s slave a ddress r/w= ?1? figure 16. random address read
[ak4709] ms1319- e -00 2011/07 - 29 - scl sda stop condition start condition s p figure 17. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 18. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 19. bit transfer on the i 2 c-bus
[ak4709] ms1319- e -00 2011/07 - 30 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 0 0 0 0 auto 0 mute stby 01h switch vmute 0 vcr1 vcr0 mono 1 tv1 tv0 02h main volume 0 0 l5 l4 l3 l2 l1 l0 03h zerocross 0 vmono cal 0 0 mod mdt1 mdt0 04h video switch 0 0 vvcr2 vv cr1 vvcr0 vtv2 vtv1 vtv0 05h video output enable cio tvfb vcrc vcrv tvb tvg tvr tvv 06h video volume/clamp clampb vclp 1 vclp0 clamp2 clamp1 clamp0 0 0 07h s/f blanking control sbio1 sbio0 sbv1 sbv0 sbt1 sbt0 fb1 fb0 08h s/f blanking monitor 0 0 fvcr1 tvmon vcmon fvcr0 svcr1 svcr0 09h monitor mask mcomn 0 0 mtv mvc mfvcr msvcr 0 0ah dc restore 0 0 0 0 vclp2 0 1 1 0bh reserved 0 0 0 0 0 0 0 0 0ch reserved 0 0 0 0 0 0 0 0 0dh volume 0 vol3 vol2 vol1 vol0 1 1 1 when the pdn pin goes ?l?, the registers are initialized to their default values. while the pdn pin = ?h?, all registers can be accessed. do not write any data to the register over 0dh. register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 0 0 0 0 auto 0 mute stby r/w r/w default 0 0 0 0 1 0 1 1 stby: standby control 0: normal operation 1: standby mode (default). a ll registers are not initialized. amp: powered down and timings are reset. source of tvout: fixed to vcrin. source of vcrout: fixed to tvin. source of tvvout: fixed to vcrvin (or hi-z). source of tvrc: fixed to vcrrc (or hi-z). source of tvg: fixed to vcrg (or hi-z). source of tvb: fixed to vcrb (or hi-z). source of vcrvout: fixed to tvvin (or hi-z). source of vcrc: fixed to hi-z. mute: audio output control 0: normal operation 1: all audio outputs to gnd (default) auto: auto startup bit 0: auto startup disa ble (manual startup). 1: auto startup enable (default). note: when the sbio1 bit = ?1?(de fault = ?0?), the change of auto bit may cause a ?l? pulse on int pin.
[ak4709] ms1319- e -00 2011/07 - 31 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h switch vmute 0 vcr1 vcr0 mono 1 tv1 tv0 r/w r/w default 1 0 0 1 0 1 0 1 tv1-0: tvoutl/r pins source switch 00: amp 01: vcrinl/r pins (default) 10: mute 11: reserved mono: mono select for tvoutl/r pins 0: stereo. (default) 1: mono. (l+r)/2 vcr1-0: vcroutl/r pins source switch 00: amp 01: tvinl/r pins (default) 10: mute 11: volume#1 output vmute: mute switch for volume #1 0: normal operation 1: mute the volume #1 (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h main volume 0 0 l5 l4 l3 l2 l1 l0 r/w r/w default 0 0 0 1 1 1 1 1 l5-0: volume #1 control those registers control both lch and rch of volume #1. 111111 to 100011: (reserved) 100010: volume gain = +6db 100001: volume gain = +4db 100000: volume gain = +2db 011111: volume gain = +0db (default) 011110: volume gain = -2db ... 000011: volume gain = -56db 000010: volume gain = -58db 000001: volume gain = -60db 000000: volume gain = mute
[ak4709] ms1319- e -00 2011/07 - 32 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h volume control 0 vmono cal 0 0 mod mdt1 mdt0 r/w r/w default 0 0 1 0 0 1 1 1 mdt1-0: the time length control of volume transition time 00: typ. 5.3 ms 01: typ. 10.7 ms 10: typ. 21.3 ms 11: typ. 42.7 ms (default) mod: soft transition en able for volume #1 control 0: disable the volume value changes imme diately without soft transition. 1: enable (default) the volume value changes with soft transition. this function is disabled when stby bit = ?1?. cal: offset calibration enable 0: offset calibration disable. 1: offset calibration enable (default) vmono: mono select for vcroutl/r pins 0: stereo. (default) 1: mono. (l+r)/2
[ak4709] ms1319- e -00 2011/07 - 33 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h video switch 0 0 vvcr2 vvcr1 vvcr0 vtv2 vtv1 vtv0 r/w r/w default 0 0 0 1 1 1 0 0 vtv2-0: selector for tv video output refer table 10 . vvcr2-0: selector for vcr video output refer table 11 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h output enable cio tvfb vcrc vcrv tvb tvg tvr tvv r/w r/w default 0 0 0 0 0 0 0 0 tvv: tvvout out put control tvr: tvrcout output control tvg: tvgout out put control tvb: tvbout output control vcrv: vcrvout output control vcrc: vcrc output control tvfb: tvfb output control 0: hi-z (default) 1: active. cio: vcr rgb i/o control for vcr scart refer table 12 .
[ak4709] ms1319- e -00 2011/07 - 34 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h video volume clampb vclp1 vclp0 clamp2 clamp1 clamp0 0 0 r/w r/w default 0 0 0 0 0 1 0 0 clampb, clamp2-0: clamp control. refer table 13 , table 14 and table 15 . vclp1-0: dc restore source control 00: encv pin (default) 01: ency pin 10: vcrvin pin 11: (reserved) when the auto bit = ?1?, the source is fixed to vcrvin pin. addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h s/f blanking sbio1 sbio0 sbv1 sbv0 sbt1 sbt0 fb1 fb0 r/w r/w default 0 0 0 0 0 0 0 0 fb1-0: tv fast blanking out put control (for tvfb pin) 00: 0v (default) 01: 2v<, 2.5v(typ) at 150 load 10: follow vcr fb input (2.5v/0v) 11: (reserved) sbt1-0: tv slow blanking output control (for tvsb pi n. minimum load is 10k .) 00: < 2v (default) 01: 4.73v <, < 7v 10: (reserved) 11: 10v < sbv1-0: vcr slow blanking output control (for vcrsb pi n. minimum load is 10k .) 00: < 2v (default) 01: 4.73v <, < 7v 10: (reserved) 11: 10v < sbio1-0: tv/vcr slow bl anking i/o control refer table 20 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h monitor 0 0 fvcr1 tvmon vcmon fvcr0 svcr1 svcr0 r/w read default 0 0 0 0 0 0 0 0 svcr1-0, fvcr1-0: vcr fast bl anking/slow bl anking monitor refer table 21 , table 22 . vcmon, tvmon: vcr/tv video input monitor refer table 23 .
[ak4709] ms1319- e -00 2011/07 - 35 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h monitor mask mcomn 0 0 mtv mvc mfvcr msvcr 0 r/w r/w default 0 0 0 0 1 0 0 0 msvcr: svcr1-0 bits monitor mask 0: the int pin reflects the change of svcr1-0 bit. (default) 1: the int pin does not reflect the change of svcr1-0 bits. mfvcr: fvcr monitor mask 0: the int pin reflects the change of mfvcr bit. (default) 1: the int pin does not reflect the change of mfvcr bit. mvc: vcr input monitor mask refer table 25 . mtv: tv input monitor mask refer table 24 . mcomn: monitor mask option refer table 23 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah dc restore 0 0 0 0 vclp2 0 1 1 r/w r/w default 0 0 0 0 0 0 1 1 vclp2: dc restore source control refer table 16 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh main volume 0 vol3 vol2 vol1 vol0 1 1 1 r/w r/w default 0 0 0 1 1 1 1 1 vol3-0: volume #0 control those registers control both lch and rch of volume #0. 1011: volume gain = +24db 1010: volume gain = +21db 1001: volume gain = +18db 1000: volume gain = +15db 0111: volume gain = +12db 0110: volume gain = +9db 0101: volume gain = +6db 0100: volume gain = +3db 0011: volume gain = +0db (default) 0010: volume gain = -3db 0001: volume gain = -6db 0000: mute
[ak4709] ms1319- e -00 2011/07 - 36 - system design figure 20 shows the system connection diagram example. the evaluation board akd4709 de monstrates application circuits, the optimum layout, power suppl y arrangements and measurement results. tvfb 1 vvd1 2 vss3 3 tvvout 4 vvd2 5 tvrc 6 7 tvg 8 tvb 9 encb 10 encg 11 vcrvout int vd2 vss2 cp cn vee ainl+ 13 14 15 16 17 18 19 20 21 22 23 ak4709 encrc 12 encv ency tvvin vcrvin vcrfb vcrrc vcrg vcrb vp vcrsb tvsb vss1 24 35 34 33 32 31 30 29 28 27 26 25 36 ainr- tvoutl vcroutr tvinl tvinr tvoutr vcroutl vcrinl vcrinr ainr+ 48 47 46 45 44 43 42 41 40 39 38 37 encc 75 75 75 video 3.3v 0.1u 0.1u 0.1u 0.1u video encoder 0.1u 75 4.7u 0.1u + + mpeg micro controller 4.7u 0.1u a udio 3.3v decoder dacl dacr analog 12 v tv scart 0.47u 300 0.47u 300 0.47u 300 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u vcr scart 470 470 75 75 75 75 75 75 75 75 a nalog ground digital ground ainl- vd1 0.1u vcrc 75 pdn sd a scl 4.7u + analog 3.3 v 1.0uf 1.0uf 10 0.47u 300 75 75 300 300 300 300 0.1u 1u + 0.47u 300 0.47u 300 0.47u 300 0.47u 300 4.7u 0.1u + figure 20. typical connection diagram
[ak4709] ms1319- e -00 2011/07 - 37 - grounding and power supply decoupling vd1, vd2, vp, vvd1, vvd2, vss1, vss2 and vss3 should be supplied from analog supply unit with low impedance and be separated from system digital supply. an electrolytic capacitor 4.7 f parallel with a 0.1 f ceramic capacitor should be attached to vd1, vd2, vvd1, vvd2, vss1, vss2 a nd vss3 pin to eliminate the effects of high frequency noise. the 0.1 f ceramic capacitor should be placed as n ear to vd1 (vd2, vvd1, vvd2) as possible. the vp pin must be connected to the analogue 12v pow er supply via a 10ohm resistor and with a 0.1f ceramic capacitor in parallel with a 1f electrol ytic capacitor to vss1, as shown in figure 20 . analog audio outputs the analog outputs are also single-ende d and centered on 0v(typ.). the output signal range is typically 2vrms . slow blanking pins the slow blanking pin must have a 470ohm 5% series resistor.
[ak4709] ms1319- e -00 2011/07 - 38 - external circuit example the analog audio input pin must have 300ohm series re sistor and 0.47uf capacitor. analog audio input pin tvinl/r vcrinl/r 0.47 f 300 (cable) analog audio input pin ainr+ ainr- ainl+ ainl- 0.47 f 300 analog audio output pin tvoutl/r vcroutl/r 300 total > 4.5k (cable) analog video input pin encv, ency, vcrvin, tvvin, encrc, encc, vcrrc, encg, vcrg, encb, vcrb 0.1 f 75 (cable) 75 analog video output pin tvvout, tvrc tvg, tvr, tvb, vcrvout,vcrc max 400pf 75 75 max 15pf (cable)
[ak4709] ms1319- e -00 2011/07 - 39 - slow blanking pin tvsb vcrsb max 3nf (with 470 ) 470 5% min: 10k (cable) fast blanking input pin vcrfb 75 (cable) 75 fast blanking output pin tvfb 75 75 (cable)
[ak4709] ms1319- e -00 2011/07 - 40 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48pin lqfp (unit: mm) 0.10 37 24 25 36 0.09 0.20 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 m 0.3 0.75 0.5 s s package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
[ak4709] ms1319- e -00 2011/07 - 41 - marking a k4709eq xxxxxxx 1 xxxxxxx: date code date (yy/mm/dd) revision reason page contents 11/07/28 00 first edition revision history
[ak4709] ms1319- e -00 2011/07 - 42 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these products , please make inquiries the sales office of asahi kasei microdevices corporation (akm) or au thorized distributors as to current status of the products. z descriptions of external circuits, app lication circuits, software and other related informa tion contained in this document are provided only to illustrate the operation and application examples of th e semiconductor products. you are fully responsible for the incorporation of these external circ uits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein . akm assumes no liability for infringement of any patent, intellectual property, or other right s in the application or use of su ch information c ontained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to cu stoms and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by re presentative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very hi gh standards of performance and reliability. note2 ) a hazard related device or system is one designe d or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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