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rev.1.00 2004.6.10 page 1 of 37 rej09b0176-0100z m16c/26 group single-chip 16-bit cmos microcomputer rej09b0176-0100z rev.1.00 2004.6.10 1. overview the m16c/26 group of single-chip microcomputers are built using the high-performance silicon gate cmos process using a m16c/60 series cpu core and are packaged in a 48-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, they are capable of executing instructions at high speed. in addition, this microcomputer contains a multiplier and dmac which combined with fast instruction process- ing capability, makes it suitable for control of various oa, communication, and industrial equipment which requires high-speed arithmetic/logic operations. 1.1 applications audio, cameras, office/communications/portable/industrial equipment, etc specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition.
m16c/26 group 1. overview rev.1.00 2004.6.10 page 2 of 37 rej09b0176-0100z item performance number of basic instructions 91 instructions shortest instruction execution time 50 ns (f(bclk)= 20mh z , v cc1 = 3.0v to 5.5v) 100 ns (f(bclk)= 10mh z , v cc1 = 2.7v to 5.5v) memory rom (see the product list) capacity ram (see the product list) i/o port p1 5 to p1 7 , p6, p7, p8 0 to p8 3 , 8bit x 3, 7bit x 1, 4bit x 1, 3bit x 1 p8 5 to p8 7 , p9 0 to p9 3 , p10 multifunction timer timer a:16 bits x 5 channels (ta0, ta1, ta2, ta3, ta4) timer b:16 bits x 3 channels (tb0, tb1, tb2) three-phase motor control timer serial i/o 2 channels (uart0, uart1) uart, clock synchronous 1 channels (uart2) uart, clock synchronous, i 2 c bus 1 , or iebus 2 a/d converter 10 bits x 8 channels dmac 2 channels (trigger: 20 sources) watchdog timer 15 bits x 1 (with prescaler) interrupt 20 internal and 7 external sources, 4 software sources, 7 levels clock generation circuit 3 circuits ? main clock ? sub-clock ? on-chip oscillator (main-clock oscillation stop detect function) power supply voltage v cc =3.0v to 5.5v (f(bclk)=20mh z ) v cc =2.7v to 5.5v (f(bclk)=10mh z ) flash memory program/erase voltage v cc =2.7v to 5.5v number of program/erase 100 times (all area) 1000times (program area) /10000 times 3 (data area) power consumption 16ma (v cc =3v, f(bclk)=20mh z ) 25 a (f(bclk)=f(x cin )=32kh z on ram) 1.8 a (v cc =3v, f(x cin )=32kh z , when wait mode) 0.7 a (v cc =3v, when stop mode) i/o i/o withstand voltage 5.0v characteristics output current 5ma operating ambient temperature -20 to 85 c -40 to 85 c 3 device configuration cmos high performance silicon gate package 48-pin plastic mold qfp notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n.v. 2. iebus is a trademark of nec electronics corporation. 3. see table 1.3 for the number of program/erase and the operating ambient temperatue. table 1.1. performance outline of m16c/26 group 1.2 performance outline table 1.1 lists performance outline of m16c/26 group. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (these circuits contain a built-in feedback resistor and external ceramic/quartz oscillator)
m16c/26 group 1. overview rev.1.00 2004.6.10 page 3 of 37 rej09b0176-0100z 1.3 block diagram figure 1.1 is a block diagram of the m16c/26 group. timer (16-bit) output (timer a): 5 input (timer b): 3 internal peripheral functions watchdog timer (15 bits) dmac (2 channels) a/d converter (10 bits x 8 channels ) uart or clock synchronous serial i/o (8 bits x 3 channels) system clock generator x in -x out x cin -x cout on-chip oscillator m16c/60 series16-bit cpu core port p1 3 port p10 8 memory rom (note 1) ram (note 2) note 1: rom size depends on microcomputer type. note 2: ram size depends on microcomputer type. r0l r0h r1h r1l r2 r3 sb flg usp isp intb pc multiplier three-phase motor control circuit a0 a1 fb 8 port p6 8 port p7 7 port p8 4 port p9 figure 1.1. block diagram
m16c/26 group 1. overview rev.1.00 2004.6.10 page 4 of 37 rej09b0176-0100z 1.4 product list table 1.2 lists the m16c/26 group products, figure 1.2 shows the type numbers, memory sizes and pack- ages, table 1.3 lists the product code, and figure 1.3 shows the marking. table 1.2. product list type no. rom capacity ram capacity package type remarks m30262f3gp 24k + 4k byte 1k byte m30262f4gp 32k + 4k byte 1k byte m30262f6gp 48k + 4k byte 2k byte m30262f8gp 64k + 4k byte 2k byte as of may 2004 48p6q-a flash rom version product code: refer to table 1.3 package type: gp : package 48p6q-a rom capacity: 3: (24k + 4k) bytes 4: (32k + 4k) bytes 6: (48k + 4k) bytes 8: (64k + 4k) bytes memory type: f: flash memory version type no. m 3 0 2 6 2 f 4 gp C d3 m16c/26 group m16c family shows ram capacity, pin count, etc (the value itself has no specific meaning) figure 1.2. type no., memory size, and package
m16c/26 group 1. overview rev.1.00 2004.6.10 page 5 of 37 rej09b0176-0100z table 1.3. product code product code package internal rom (program area) program and erase endurance temperature range internal rom (data area) operating ambient temperature temperature range lead-free lead-included d3 d5 d7 d9 u3 u5 u7 u9 100 1,000 100 1,000 0c to 60c 100 10,000 100 10,000 0c to 60c 0c to 60c -40c to 85c -20c to 85c -40c to 85c -20c to 85c -40c to 85c -20c to 85c -40c to 85c -20c to 85c -40c to 85c -20c to 85c -40c to 85c -20c to 85c program and erase endurance figure 1.3. marking diagram of flash memory versionfor m16c/26 (top view) 0262f8 a d3 xxxxx type no. (see figure 1.3 type no., memory size, and package ) chip version and product code a : shows chip version. first version is blank. henceforth, whenever it changes a version, it continues with a, b, and c. d3 : shows product code. (see table 1.3 product code ) data code five digits
m16c/26 group 1. overview rev.1.00 2004.6.10 page 6 of 37 rej09b0176-0100z 1.5 pin configuration figures 1.4 showd the pin configurations (top view). figure 1.4. pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 p9 2 /tb 2in p9 1 /tb 1in cnv ss iv cc (note 2) p1 7 /int 5 p1 6 /int 4 p1 5 /int 3 /ad trg p10 7 /an 7 /ki 3 p7 0 /ta 0out /txd 2 /sda (note 1) x out v ss x in p8 5 /nmi/sd v cc p6 7 /txd 1 p6 6 /rxd 1 p6 5 /clk 1 reset p7 1 /ta 0in /rxd 2 /scl(note 1) p7 2 /clk 2 /ta 1out /v p7 3 /cts 2 /rts 2 /ta 1in /v p7 4 /ta 2out /w p7 5 /ta 2in /w p7 6 /ta 3out p7 7 /ta 3in p8 0 /ta 4out /u p8 1 /ta 4in /u p8 2 /int 0 p8 3 /int 1 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p6 3 /txd 0 p6 2 /rxd 0 p6 1 /clk 0 p6 0 /cts 0 /rts 0 p9 0 /tb 0in p8 7 /x cin p8 6 /x cout p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4 /ki 0 p10 3 /an 3 p10 2 /an 2 p10 1 /an 1 av ss p10 0 /an 0 v ref av cc p9 3 pin configuration (top view) note 1. this pin is n channel open-drain output pins. note 2. leave this pin open. package: 48p6q
m16c/26 group 1. overview rev.1.00 2004.6.10 page 7 of 37 rej09b0176-0100z 1.6 pin description table 1.4 and 1.5 describe the available pins. table 1.4. pin description(1) pin name signal name i/o type function v cc ,v ss power supply apply 2.7v to 5.5v to the v cc pin, and 0v to the vss pin. input cnv ss cnv ss input connect this pin to vss. iv cc iv cc leave this pin open. ____________ reset reset input input "l" on this input resets the microcomputer. x in clock input input these pins are provided for the main clock generating circuit input/output. x out clock output output connect a ceramic resonator or crystal between the x in and the x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. av cc analog power this pin is a power supply input for the a/d converter. connect this supply input pin to v cc . av ss analog power this pin is a power supply input for the a/d converter. connect this supply input pin to v ss . v ref reference input this pin is a reference voltage input for the a/d converter. voltage input p1 5 ~p1 7 i/o port p1 input/ this is an 3-bit cmos i/o port. it has an input/output port direction output register that allows the user to set each pin for input or output individually. when used for input, a pull-up resister option can be selected for the entire group of three pins. additional software selectable secondary ______ functions are: 1) p1 5 to p1 7 can be configured as external int interrupt pins, and; 2) p1 5 can input a trigger for the a/d converter. p6 0 ~p6 7 i/o port p6 input/ this is an 8-bit cmos i/o port. it has an input/output port direction output register that allows the user to set each pin for input or output individually. when used for input, a pull-up resister option can be selected for the entire group of four pins. pins in this port also function as uart0 and uart1 i/o. p7 0 ~p7 7 i/o port p7 input/ this is an 8-bit i/o port equivalent to p6. (p7 0 and p7 1 are n channel output open-drain output) p7 can also function as i/o for timer a0 to a3, as selected by software. additional programming options are: p7 0 to p7 3 can assume uart2 i/o capabilities, and p7 2 to p7 5 can function as output pins for the three-phase motor control timer. p8 0 ~p8 3 , i/o port p8 input/ p8 0 to p8 3 and p8 5 to p8 7 are an 7-bit i/o port equivalent to p6.when p8 5 ~p8 7 output used for input, a pull-up resister option can be selected for the entire group of four pins or three pins. additional software-selectable secondary functions are: 1) p8 0 and p8 1 can act as either i/o for timer a4, or as output pins for the three-phase motor control timer; 2) p8 2 to p8 3 can be ______ _______ _____ configured as external int interrupt pins; 3) p8 5 can be used as nmi/sd. p8 5 can not be used as i/o port while the three-phase motor control is enabled. apply a stable "h" to p8 5 after setting the direction register for p8 5 to "0" when the three-phase motor control is enabled, and; 4) p8 6 and p8 7 can serve as i/o pins for the sub-clock generation circuit. in this latter case, a quartzoscillator must be connented between p8 6 (x cout pin) and p8 7 (x cin pin).
m16c/26 group 1. overview rev.1.00 2004.6.10 page 8 of 37 rej09b0176-0100z table 1.7. pin description(2) pin name signal name i/o type function p9 0 ~p9 3 i/o port p9 input/ this is an 4-bit i/o port equivalent to p6. additional software-selectable output secondary functions are: 1) p9 0 to p9 2 can act as timer b0~b2 input pins. p10 0 ~p10 7 i/o port p10 input/ this is an 8-bit i/o port equivalent to p6. this port can also function as output a/d converter input pins, as selected by software. furthermore, p10 4 to p10 7 can also function as input pins for the key input interrupt function.
m16c/26 group 2. cpu rev.1.00 2004.6.10 page 9 of 37 rej09b0176-0100z 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. figure 2.1. central processing unit register 2.1 data registers (r0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32-bit data register (r2r0). r3r1 is the same as r2r0. 2.2 address registers (a0 and a1) the register a0 consists of 16 bits, and is used for address register indirect addressing and address regis- ter relative addressing. they also are used for transfers and logic/logic operations. a1 is the same as a0. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). data registers (note) address registers (note) frame base registers (note) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register note: these registers comprise a register bank. there are two register banks. r0h(r0's high bits) b15 b8 b7 b0 r3 intbh usp isp sb aa aa aa aa aa aa a a aaaaaaa aaaaaaa aa aa a a aa aa aa aa aa aa c d z s b o i u ipl r0l(r0's low bits) r1h(r1's high bits) r1l(r1's low bits) r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level the upper 4 bits of intb are intbh and the lower 16 bits of intb are intbl.
m16c/26 group 2. cpu rev.1.00 2004.6.10 page 10 of 37 rej09b0176-0100z 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to 0. 2.8.3 zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0. 2.8.4 sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0. 2.8.5 register bank select flag (b flag) register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. 2.8.6 overflow flag (o flag) this flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0. 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabled when the i flag is 0, and are enabled when the i flag is 1. the i flag is cleared to 0 when the interrupt request is accepted. 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is 0; usp is selected when the u flag is 1. the u flag is cleared to 0 when a hardware interrupt request is accepted or an int instruction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. 2.8.10 reserved area when write to this bit, write "0". when read, its content is indeterminate.
m16c/26 group 3. memory rev.1.00 2004.6.10 page 11 of 37 rej09b0176-0100z 3. memory figure 3.1 is a memory map of the m16c/26 group. the address space extends the 1m bytes from address 00000 16 to fffff 16 . the internal rom is allocated in a lower address direction beginning with address fffff 16 . for example, a 32-kbyte internal rom is allocated to the addresses from f8000 16 to fffff 16 . the fixed interrupt vector table is allocated to the addresses from fffdc 16 to fffff 16 . therefore, store the start address of each interrupt routine here. the internal ram is allocated in an upper address direction beginning with address 00400 16 . for example, a 1-kbytes internal ram is allocated to the addresses from 00400 16 to 007ff 16 . in addition to storing data, the internal ram also stores the stack used when calling subroutines and when interrupts are generated. the srf is allocated to the addresses from 00000 16 to 003ff 16 . peripheral function control registers are located here. of the sfr, any area which has no functions allocated is reserved for future use and cannot be used by users. the special page vector table is allocated to the addresses from ffe00 16 to fffdb 16 . this vector is used by the jmps or jsrs instruction. for details, refer to the m16c/60 and m16c/20 series software manual. figure 3.1. memory map 00000 16 xxxxx 16 internal rom (data area) internal rom (program area) sfr internal ram reserved area ffe00 16 fffdc 16 fffff 16 note 1: shown here is a block a (2k bytes) and block b (2k bytes). undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc nmi 1k bytes 007ff 16 00bff 16 address xxxxx 16 2k bytes size address yyyyy 16 size f8000 16 f4000 16 fa000 16 48k bytes 24k bytes 32k bytes reserved area 00400 16 0f000 16 0ffff 16 yyyyy 16 fffff 16 (note 1) f0000 16 64k bytes internal ram internal rom
m16c/26 group 4. special function register (sfr) map rev.1.00 2004.6.10 page 12 of 37 rej09b0176-0100z 4. special function register (sfr) map processor mode register 0 (note 2) pm0 00 16 processor mode register 1 pm1 00001000 2 system clock control register 0 cm0 01001000 2 system clock control register 1 cm1 00100000 2 address match interrupt enable register aier xxxxxx00 2 protect register prcr xx000000 2 oscillation stop detection register (note 3) cm2 0x000000 2 watchdog timer start register wdts xx 16 watchdog timer control register wdc 00xxxxxx 2 (note 4) address match interrupt register 0 rmad0 00 16 00 16 x0 16 address match interrupt register 1 rmad1 00 16 00 16 x0 16 voltage detection register 1 (note 5) vcr1 00001000 2 voltage detection register 2 (note 5) vcr2 00 16 processor mode register 2 pm2 xxx00000 2 voltage down detection interrupt register d4int 00 16 dma0 source pointer sar0 xx 16 xx 16 xx 16 dma0 destination pointer dar0 xx 16 xx 16 xx 16 dma0 transfer counter tcr0 xx 16 xx 16 dma0 control register dm0con 00000x00 2 dma1 source pointer sar1 xx 16 xx 16 xx 16 dma1 destination pointer dar1 xx 16 xx 16 xx 16 dma1 transfer counter tcr1 xx 16 xx 16 dma1 control register dm1con 00000x00 2 note 1: the blank areas are reserved and cannot be accessed by users. note 2: the pm00 and pm01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. note 3: the cm20, cm21, and cm27 bits do not change at oscillation stop detection reset. note 4: the wdc5 bit is 0 (cold start) immediately after power-on. it can only be set to 1 in a program. it is set to 0 w hen the input voltage at the v cc1 pin drops to vdet2 or less while the vc25 bit in the vcr2 register is set to 1 (ram retention limit detection circuit enable). x : nothing is mapped to this bit 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 address register symbol after reset
m16c/26 group 4. special function register (sfr) map rev.1.00 2004.6.10 page 13 of 37 rej09b0176-0100z int3 interrupt control register int3ic xx00x000 2 int5 interrupt control register int5ic xx00x000 2 int4 interrupt control register int4ic xx00x000 2 uart2 bus collision detection interrupt control register bcnic xxxxx000 2 dma0 interrupt control register dm0ic xxxxx000 2 dma1 interrupt control register dm1ic xxxxx000 2 key input interrupt control register kupic xxxxx000 2 a/d conversion interrupt control register adic xxxxx000 2 uart2 transmit interrupt control register s2tic xxxxx000 2 uart2 receive interrupt control register s2ric xxxxx000 2 uart0 transmit interrupt control register s0tic xxxxx000 2 uart0 receive interrupt control register s0ric xxxxx000 2 uart1 transmit interrupt control register s1tic xxxxx000 2 uart1 receive interrupt control register s1ric xxxxx000 2 timer a0 interrupt control register ta0ic xxxxx000 2 timer a1 interrupt control register ta1ic xxxxx000 2 timer a2 interrupt control register ta2ic xxxxx000 2 timer a3 interrupt control register ta3ic xxxxx000 2 timer a4 interrupt control register ta4ic xxxxx000 2 timer b0 interrupt control register tb0ic xxxxx000 2 timer b1 interrupt control register tb1ic xxxxx000 2 timer b2 interrupt control register tb2ic xxxxx000 2 int0 interrupt control register int0ic xx00x000 2 int1 interrupt control register int1ic xx00x000 2 note :the blank areas are reserved and cannot be accessed by users. x : nothing is mapped to this bit 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 address register symbol after reset
m16c/26 group 4. special function register (sfr) map rev.1.00 2004.6.10 page 14 of 37 rej09b0176-0100z 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 01b0 16 01b1 16 01b2 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 01b8 16 01b9 16 01ba 16 01bb 16 01bc 16 01bd 16 01be 16 01bf 16 0250 16 0251 16 0252 16 0253 16 0254 16 0255 16 0256 16 0257 16 0258 16 0259 16 025a 16 025b 16 025c 16 025d 16 025e 16 025f 16 0330 16 0331 16 0332 16 0333 16 0334 16 0335 16 0336 16 0337 16 0338 16 0339 16 033a 16 033b 16 033c 16 033d 16 033e 16 033f 16 note 1: the blank areas are reserved and cannot be accessed by users. note 2: this register is included in the flash memory version. x : nothing is mapped to this bit peripheral clock select register pclkr 00000011 2 address register symbol after reset ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ flash memory control register 4 (note 2) fmr4 01000000 2 flash memory control register 1 (note 2) fmr1 0100xx0x 2 flash memory control register 0 (note 2) fmr0 xx000001 2
m16c/26 group 4. special function register (sfr) map rev.1.00 2004.6.10 page 15 of 37 rej09b0176-0100z address register symbol after reset 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 timer a1-1 register ta11 xx 16 xx 16 timer a2-1 register ta21 xx 16 xx 16 timer a4-1 register ta41 xx 16 xx 16 three-phase pwm control register 0 invc0 00 16 three-phase pwm control register 1 invc1 00 16 three-phase output buffer register 0 idb0 00 16 three-phase output buffer register 1 idb1 00 16 dead time timer dtt xx 16 timer b2 interrupt occurrence frequency set counter ictb2 xx 16 interrupt cause select register ifsr 00 16 note : the blank areas are reserved and cannot be accessed by users. x : nothing is mapped to this bit uart2 special mode register 4 u2smr4 00 16 uart2 special mode register 3 u2smr3 000x0x0x 2 uart2 special mode register 2 u2smr2 x0000000 2 uart2 special mode register u2smr x0000000 2 uart2 transmit/receive mode register u2mr 00 16 uart2 bit rate generator u2brg xx 16 uart2 transmit buffer register u2tb xxxxxxxx 2 xxxxxxxx 2 uart2 transmit/receive control register 0 u2c0 00001000 2 uart2 transmit/receive control register 1 u2c1 00000010 2 uart2 receive buffer register u2rb xxxxxxxx 2 xxxxxxxx 2
m16c/26 group 4. special function register (sfr) map rev.1.00 2004.6.10 page 16 of 37 rej09b0176-0100z 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 count start flag tabsr 00 16 clock prescaler reset flag cpsrf 0xxxxxxx 2 one-shot start flag onsf 00 16 trigger select register trgsr 00 16 up-down flag udf 00 16 timer a0 register ta0 xx 16 xx 16 timer a1 register ta1 xx 16 xx 16 timer a2 register ta2 xx 16 xx 16 timer a3 register ta3 xx 16 xx 16 timer a4 register ta4 xx 16 xx 16 timer b0 register tb0 xx 16 xx 16 timer b1 register tb1 xx 16 xx 16 timer b2 register tb2 xx 16 xx 16 timer a0 mode register ta0mr 00 16 timer a1 mode register ta1mr 00 16 timer a2 mode register ta2mr 00 16 timer a3 mode register ta3mr 00 16 timer a4 mode register ta4mr 00 16 timer b0 mode register tb0mr 00xx0000 2 timer b1 mode register tb1mr 00xx0000 2 timer b2 mode register tb2mr 00xx0000 2 timer b2 special mode register tb2sc xxxxxx00 2 uart0 transmit/receive mode register u0mr 00 16 uart0 bit rate generator u0brg xx 16 uart0 transmit buffer register u0tb xxxxxxxx 2 xxxxxxxx 2 uart0 transmit/receive control register 0 u0c0 00001000 2 uart0 transmit/receive control register 1 u0c1 00000010 2 uart0 receive buffer register u0rb xxxxxxxx 2 xxxxxxxx 2 uart1 transmit/receive mode register u1mr 00 16 uart1 bit rate generator u1brg xx 16 uart1 transmit buffer register u1tb xxxxxxxx 2 xxxxxxxx 2 uart1 transmit/receive control register 0 u1c0 00001000 2 uart1 transmit/receive control register 1 u1c1 00000010 2 uart1 receive buffer register u1rb xxxxxxxx 2 xxxxxxxx 2 uart transmit/receive control register 2 ucon x0000000 2 dma0 request cause select register dm0sl 00 16 dma1 request cause select register dm1sl 00 16 note : the blank areas are reserved and cannot be accessed by users. x : nothing is mapped to this bit address register symbol after reset
m16c/26 group 4. special function register (sfr) map rev.1.00 2004.6.10 page 17 of 37 rej09b0176-0100z 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 note 1: the blank areas are reserved and cannot be accessed by users. x : nothing is mapped to this bit a/d register 0 ad0 xxxxxxxx 2 xxxxxxxx 2 a/d register 1 ad1 xxxxxxxx 2 xxxxxxxx 2 a/d register 2 ad2 xxxxxxxx 2 xxxxxxxx 2 a/d register 3 ad3 xxxxxxxx 2 xxxxxxxx 2 a/d register 4 ad4 xxxxxxxx 2 xxxxxxxx 2 a/d register 5 ad5 xxxxxxxx 2 xxxxxxxx 2 a/d register 6 ad6 xxxxxxxx 2 xxxxxxxx 2 a/d register 7 ad7 xxxxxxxx 2 xxxxxxxx 2 a/d control register 2 adcon2 00 16 a/d control register 0 adcon0 00000xxx 2 a/d control register 1 adcon1 00 16 port p1 register p1 xx 16 port p1 direction register pd1 00 16 port p6 register p6 xx 16 port p7 register p7 xx 16 port p6 direction register pd6 00 16 port p7 direction register pd7 00 16 port p8 register p8 xx 16 port p9 register p9 xx 16 port p8 direction register pd8 00x00000 2 port p9 direction register pd9 00 16 port p10 register p10 xx 16 port p10 direction register pd10 00 16 pull-up control register 0 pur0 00 16 pull-up control register 1 pur1 00 16 pull-up control register 2 pur2 00 16 port control register pcr 00 16 register symbol after reset address
m16c/26 group 5. electrical characteristics (v cc =5v) rev.1.00 2004.6.10 page 18 of 37 rej09b0176-0100z table 16.1. absolute maximum ratings operating ambient temperature parameter unit input voltage analog supply voltage supply voltage output voltage v o -0.3 to v cc +0.3 -0.3 to v cc +0.3 p d power dissipation storage temperature rated value v v v condition v i av cc v cc t stg t opr symbol mw p7 0 , p7 1 p7 0 , p7 1 -0.3 to 6.5 v v reset, cnv ss , p1 5 to p1 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 3 , p8 5 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 , v ref , x in v cc =av cc v cc =av cc -0.3 to 6.5 v -0.3 to 6.5 -65 to 150 300 -20 to 85 / -40 to 85 -0.3 to 6.5 c topr=25 c c p1 5 to p1 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 3 , p8 5 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 , x out 5. electrical characteristics 5.1 absolute maximum ratings
m16c/26 group 5. electrical characteristics (v cc =5v) rev.1.00 2004.6.10 page 19 of 37 rej09b0176-0100z 2 . 75 . 5 t y p .m a x . unit p a r a m e t e r v c c s u p p l y v o l t a g e s y m b o l m i n . standard analog supply voltage v cc avcc v v 0 0 analog supply voltage s u p p l y v o l t a g e v i h i o h ( a v g ) h i g h a v e r a g e o u t p u t c u r r e n t m a ma v s s avss 0 . 8 v c c v v v v c c 0 . 2 v c c 0 l o w i n p u t v o l t a g e i o h ( p e a k ) h i g h p e a k o u t p u t c u r r e n t h i g h i n p u t v o l t a g e - 5 . 0 - 1 0 . 0 l o w p e a k o u t p u t c u r r e n t 1 0 . 0 5 . 0 m a f (x in ) m a i n c l o c k i n p u t o s c i l l a t i o n f r e q u e n c y ( n o t e 4 ) l o w a v e r a g e o u t p u t c u r r e n t i o l ( p e a k ) m a i o l ( a v g ) v p 7 0 , p 7 1 0 . 8 v c c 6 . 5 v v i l 3 3 . 3 3 x v c c - 8 0 v cc =3.0 to 5.5v v cc =2.7 to 3.0v 0 0 mhz mhz 20 f (x cin ) sub-clock oscillation frequency k h z 5 0 3 2 . 7 6 8 note 1: referenced to v cc = 2.7 to 5.5v at topr = -20 to 85 c / -40 to 85 c unless otherwise specified. note 2: the mean output current is the mean value within 100ms. note 3: the total i ol (peak) for all ports must be 80ma max. the total i ol (peak) for all ports must be -80ma max. note 4: relationshi p between main clock oscillation fre q uenc y and su pp l y volta g e. f (ring) on-chip oscillation frequency mhz 1 f (bclk) cpu operation clock 0 m h z 20 reset, cnv ss , x in , p1 5 to p1 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 3 , p8 5 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 r e s e t , c n v s s , x i n , p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 3 , p 8 5 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 3 , p 8 5 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 3 , p 8 5 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 3 , p 8 5 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 3 , p 8 5 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 main clock input oscillation frequency 20.0 0.0 f(x in ) operating maximum frequency [mh z ] v cc [v] (main clock: no division) 5.5 3.0 10.0 2.7 aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa 33.33 x v cc -80mh z table 1.26.2. recommended operating conditions (note 1) 5.2 recommended operating conditions
m16c/26 group 5. electrical characteristics (v cc =5v) rev.1.00 2004.6.10 page 20 of 37 rej09b0176-0100z 5.3 a/d conversion characteristics s t a n d a r d m i n .typ.m a x . C i n l r e s o l u t i o n i n t e g r a l n o n - l i n e a r i t y e r r o r b i t s v r e f = v c c 1 0 symbol parameter m e a s u r i n g c o n d i t i o nunit an 0 to an 7 input v r e f = v c c = 5 v l s b 3 l s b v ref =v cc =3.3v 8 b i t 2 r l a d d e r t c o n v l a d d e r r e s i s t a n c e c o n v e r s i o n t i m e ( 1 0 b i t ) , s a m p l e & h o l d f u n c t i o n a v a i l a b l e r e f e r e n c e v o l t a g e a n a l o g i n p u t v o l t a g e k ? s v v i a v r e f v 0 2.0 10 v cc v ref 4 0 3 . 3 c o n v e r s i o n t i m e ( 8 b i t ) , s a m p l e & h o l d f u n c t i o n a v a i l a b l e s 2 . 8 t conv t s a m p sampling time 0.3 s v ref =v cc v ref =v cc =5v, ? ad =10mhz v ref =v cc =5v, ? ad =10mhz d n l d i f f e r e n t i a l n o n - l i n e a r i t y e r r o r o f f s e t e r r o r g a i n e r r o r C C l s b l s b l s b 1 3 3 note 1: referenced to v cc =av cc =v ref =3.3 to 5.5v, v ss =av ss =0v at topr = -20 to 85 c / -40 to 85 c unless otherwise specified. note 2: ad operation clock frequency (? ad frequency) must be 10 mhz or less. and divide the f ad if v cc is less than 4.2v, and make ? ad frequency equal to or lower than f ad /2. note 3: a case without sample & hold function turn ? ad frequency into 250 khz or more in addition to a limit of note 2. a case with sample & hold function turn ? ad frequency into 1mhz or more in addition to a limit of note 2. 1 0 b i t an 0 to an 7 input v ref =v cc =3.3v l s b 5 an 0 to an 7 input v ref =v cc =5v l s b 3 l s b v ref =v cc =3.3v 8 bit 2 1 0 b i t an 0 to an 7 input v ref =v cc =3.3v l s b 5 C a b s o l u t e a c c u r a c y table 16.3. a/d conversion characteristics (note 1)
m16c/26 group 5. electrical characteristics (v cc =5v) rev.1.00 2004.6.10 page 21 of 37 rej09b0176-0100z 5.4 flash memory version electrical characteristics note 1: when not otherwise specified, vcc = 2.7 to5.5v; topr = 0 to 60 c. note 2: vcc = 5v; topr = 25 c. note 3: definition of e/w cycle: each block may be written to a variable number of times - up to a maximum of the total number of distinct word addresses - for every block erase. performing multiple writes to the same address before an erase operation is prohibited. note 4: maximum number of e/w cycles for which opration is guaranteed. note 5: topr = 55c. note 6: when not otherwise specified, vcc = 2.7 to 5.5v; topr = -40 to 85c (d7, u7) / -20 to 85c (d9, u9). note 7: table18.5 applies for block a or b e/w cycles > 1000. otherwise, use table 18.4. note 8: to reduce the number of e/w cycles, a block erase should ideally be performed after writing as many different word addresses (only one time each) as possible. it is important to track the total number of block erases. note 9: should erase error occur during block erase, attempt to execute clear status register command, then clock erase command at least three times until erase error disappears. note 10: when block a or b e/w cycles exceed 100 (d7, d9, u7, u9), select one wait state per block access. when fmr 17 is set to "1", one wait state is inserted per access to block a or b - regardless of the value of pm17. wait sta te insertion during access to all other blocks, as well as to internal ram, is controlled by pm17 - regardless of the setting of fmr17. note 11: customers desiring e/w failure rate information should contact their renesas technical support representative. w o r d p r o g r a m t i m e ( v c c = 5 . 0 v , t o p r = 2 5 c ) block erase time 75 0.2 60 0 9 s s p a r a m e t e r standard m i n . t y p . ( n o t e 2 ) m a x u n i t s y m b o l C C 0 . 49s 0.7 9 s 1 . 29s 2 k b y t e b l o c k 8k b y t e b l o c k 1 6k b y t e b l o c k 3 2 k b y t e b l o c k C e r a s e / w r i t e c y c l e ( n o t e 3 ) 1 0 0 ( n o t e 4 ) c y c l e t d ( s r - e s ) C t i m e d e l a y f r o m s u s p e n d r e q u e s t u n t i l e r a s e s u s p e n d data retention time (note 5) m s y e a r 8 20 w o r d p r o g r a m t i m e ( v c c = 5 . 0 v , t o p r = 2 5 c ) b l o c k e r a s e t i m e ( v c c = 5 . 0 v , t o p r = 2 5 c ) 100 s p a r a m e t e r standard min. t y p . ( n o t e 2 ) m a x unit s y m b o l C C 0 . 3 s ( 2 k b y t e b l o c k ) C erase/write cycle (note 3, 8, 9) 10000 (note 4,10) c y c l e td(sr-es) t i m e d e l a y f r o m s u s p e n d r e q u e s t u n t i l e r a s e s u s p e n d ms 8 table 16.4. flash memory version electrical characteristics (note 1) 100e/w cycle products (d3, d5, u3, u5)) table 16.5. flash memory version electrical characteristics (note 6) 10000 e/w cycle products (d7, d9, u7, u9) [blocka and block b(note 7)] erase suspend request (interrupt request) fmr46 td(sr-es) flash program, erase voltage flash read operation voltage v cc = 2.7 v to 5.5 v v cc =2.7 to 5.5 v table 16.6. flash memory version program/erase voltage and read operation voltage characteristics (at topr = 0 to 60 o c)
m16c/26 group 5. electrical characteristics (v cc =5v) rev.1.00 2004.6.10 page 22 of 37 rej09b0176-0100z table 16.7. low voltage detection circuit electrical characteristics (note 1, note 4 ) s y m b o l s t a n d a r d t y p . unit measuring condition m i n .m a x . p a r a m e t e r v d e t 4 vo l t a g e d o w n d e t e c t i o n v o l t a g e ( n o t e 1 ) v 3 . 84 . 4 v c c 1 = 0 . 8 t o 5 . 5 v n o t e 1 : v d e t 4 > v d e t 3 n o t e 2 : w h e r e r e s e t l e v e l d e t e c t i o n v o l t a g e i s l e s s t h a n 2 . 7 v , i f t h e s u p p l y p o w e r v o l t a g e i s g r e a t e r t h a n t h e r e s e t l e v e l d e t e c t i o n v o l t a g e , t h e o p e r a t i o n a t f ( b c l k ) 1 0 m h z i s g u a r a n t e e d . n o t e 3 : v d e t 3 r > v d e t 3 i s n o t g u a r a n t e e d . n o t e 4 : t h e l o w v o l t a g e d e t e c t i o n c i r c u i t i s d e s i g n e d t o u s e w h e n v c c i s s e t t o 5 v . 3 . 3 v d e t 3 r e s e t l e v e l d e t e c t i o n v o l t a g e ( n o t e s 1 , 2 ) v 2 . 83 . 6 2 . 2 v 0 . 8 2 . 94 . 0 s y m b o l s t a n d a r d t y p . unit measuring condition m i n .m a x . p a r a m e t e r 2 v cc1 =2.7 to 5.5v n o t e : w h e n v c c = 5 v 150 6 (note) 50 t d ( r - s ) stop release time 2 0 t d ( m - l ) time for internal power supply stabilization when main clock oscillation starts 2 0 t d ( s - r ) h a r d w a r e r e s e t 2 r e l e a s e w a i t t i m e s m s v d e t 3 s l o w v o l t a g e r e s e t r e t e n t i o n v o l t a g e v d e t 3 r l o w v o l t a g e r e s e t r e l e a s e v o l t a g e ( n o t e 3 ) 2 . 2 v t d ( p - r )t i m e f o r i n t e r n a l p o w e r s u p p l y s t a b i l i z a t i o n d u r i n g p o w e r i n g - o n t d ( e - a ) l o w v o l t a g e d e t e c t i o n c i r c u i t o p e r a t i o n s t a r t t i m e s s ms v cc1 =2.7 to 5.5v v c c 1 = v d e t 3 r t o 5 . 5 v t d ( w - s ) low power dissipation mode wait mode release time 150 s interrupt for stop mode release cpu clock td(r-s) td(s-r) vdet3r v cc table 16.8. power supply circuit timing characteristics 5.5 low voltage detection circuit electrical charactristics
m16c/26 group 5. electrical characteristics (v cc =5v) rev.1.00 2004.6.10 page 23 of 37 rej09b0176-0100z v cc = 5v table 16.9. electrical characteristics (note 1 ) s y m b o l v o h v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e v o l v o l h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e s t a n d a r d t y p . u n i t measuring condition v v v x o u t v 2 . 0 0.45 v v x o u t 2 . 0 2 . 0 min. m a x . p a r a m e t e r i o h = - 1 m a i o h = - 0 . 5 m a i o l = 1 m a i o l = 0 . 5 m a p1 5 to p1 7 , p6 0 to p6 7 ,p7 2 to p7 7 ,p8 0 to p8 3 , p8 5 to p8 7 ,p9 0 to p9 3 , p10 0 to p10 7 highpower lowpower highpower l o w p o w e r highpower lowpower h i g h o u t p u t v o l t a g e x c o u t w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d 2 . 5 1 . 6 v hysteresis h y s t e r e s i s high input current i ih l o w i n p u t c u r r e n t i i l v ram ram retention voltage v t + - v t - v t + - v t - 0 . 2 1 . 0v 0 . 22 . 5v 5.0 a a at stop mode 2.0 v r e s e t v i =5v v i =0v - 5 . 0 r f x i n r fxcin f e e d b a c k r e s i s t a n c ex i n feedback resistance x cin 15 1 . 5m ? m ? p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 3 , p8 5 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7, x in , reset, cnvss r pullup p u l l - u p r e s i s t a n c e 50 k ? v x cout 0 0 w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d h i g h p o w e r l o w p o w e r v i = 0 v 30 170 t a 0 i n t o t a 4 i n , t b 0 i n t o t b 2 i n , i n t 0 t o i n t 1 , i n t 3 t o i n t 5 , n m i , a d t r g , s c l , s d a , r x d 0 t o r x d 2 , c t s 0 t o c t s 2 , c l k 0 t o c l k 2 , t a 2 o u t t o t a 4 o u t , k i 0 t o k i 3 v cc -2.0 v cc -2.0 n o t e 1 : r e f e r e n c e d t o v c c = 4 . 2 t o 5 . 5 v , v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( b c l k ) = 2 0 m h z u n l e s s o t h e r w i s e s p e c i f i e d . i o h = - 5 m a i o h = - 2 0 0 a v cc -2.0 v cc -0.3 v cc v cc v c c v c c i o l = 5 m a i o l = 2 0 0 a l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 3 , p 8 5 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 p1 5 to p1 7 , p6 0 to p6 7 ,p7 2 to p7 7 ,p8 0 to p8 3 , p8 5 to p8 7 ,p9 0 to p9 3 , p10 0 to p10 7 p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 3 , p 8 5 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 3 , p 8 5 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 , x i n , r e s e t , c n v s s p1 5 to p1 7 , p6 0 to p6 7 ,p7 2 to p7 7 ,p8 0 to p8 3 , p8 5 to p8 7 ,p9 0 to p9 3 , p10 0 to p10 7 5.6 electrical charactristics (v cc =5v)
m16c/26 group 5. electrical characteristics (v cc =5v) rev.1.00 2004.6.10 page 24 of 37 rej09b0176-0100z v cc = 5v table 16.10. electrical characteristics (2) (note 1 ) s y m b o l s t a n d a r d t y p . u n i t measuring condition m i n .max. p a r a m e t e r i cc p o w e r s u p p l y c u r r e n t ( v c c = 3 . 0 t o 5 . 5 v ) no division m a i n s i n g l e - c h i p m o d e , t h e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e v s s 1 61 9 f ( b c l k ) = 2 0 m h z , m a s k r o m t . b . dm a f l a s h m e m o r y p rogram v c c = 5 . 0 v f ( b c l k ) = 1 0 m h z , t . b . dm a f l a s h m e m o r y e r a s e v c c = 5 . 0 v f ( b c l k ) = 1 0 m h z , t opr =25 c 3.0 a stop mode, f(bclk)=32khz, wait mode (note 2), oscillation capacity high 7.5 a 0.8 2.0 a fl as h memory n o t e 1 : r e f e r e n c e d t o v c c = = 4 . 2 t o 5 . 5 v , v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( b c l k ) = 2 0 m h z u n l e s s o t h e r w i s e s p e c i f i e d . n o t e 2 : w i t h o n e t i m e r o p e r a t e d u s i n g f c 3 2 . n o t e 3 : t h i s i n d i c a t e s t h e m e m o r y i n w h i c h t h e p r o g r a m t o b e e x e c u t e d e x i s t s . wait mode a l o w p o w e r d i s s i p a t i o n m o d e , r a m ( n o t e 3 ) f(bclk)=32khz 4 2 0a low power dissipation mode, flash memory(note 3) f ( b c l k ) = 3 2 k h z , a f l a s h m e m o r y 2 5 on-chip oscillation, t . b . d m a t . b . d n o d i v i s i o n , o n - c h i p o s c i l l a t i o n f(bclk)=32khz, wait mode(note 2), oscillation capacity low
m16c/26 group 5. electrical characteristics (v cc =5v) rev.1.00 2004.6.10 page 25 of 37 rej09b0176-0100z v cc = 5v 5.7 timing requirements (v cc =5v) (v cc = 5v, v ss = 0v, at topr = ?20 to 85 o c / ?40 to 85 o c unless otherwise specified) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 50 25 25 15 15 table 16.11. external clock input (x in input)
m16c/26 group 5. electrical characteristics (v cc =5v) rev.1.00 2004.6.10 page 26 of 37 rej09b0176-0100z v cc = 5v timing requirements (v cc = 5v, v ss = 0v, at topr = ?20 to 85 o c / ?40 to 85 o c unless otherwise specified) table 16.12. timer a input (counter input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 40 100 40 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 400 200 200 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 200 100 100 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 100 100 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 2000 1000 1000 400 400 standard max. min. ns ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 800 200 200 table 16.13. timer a input (gating input in timer mode) table 16.14. timer a input (external trigger input in one-shot timer mode) table 16.15. timer a input (external trigger input in pulse width modulation mode) table 16.16. timer a input (counter increment/decrement input in event counter mode) table 16.17. timer a input (two-phase pulse input in event counter mode)
m16c/26 group 5. electrical characteristics (v cc =5v) rev.1.00 2004.6.10 page 27 of 37 rej09b0176-0100z table 16.18. timer b input (counter input in event counter mode) table 16.19. timer b input (pulse period measurement mode) table 16.20. timer b input (pulse width measurement mode) table 16.21. a/d trigger input table 16.22. serial i/o _______ table 16.23. external interrupt inti input v cc = 5v ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 1000 125 250 250 200 100 100 0 30 90 80 timing requirements (v cc = 5v, v ss = 0v, at topr = ?20 to 85 o c / ?40 to 85 o c unless otherwise specified)
m16c/26 group 5. timing (v cc =5v) rev.1.00 2004.6.10 page 28 of 37 rej09b0176-0100z tai in input tai out input during event counter mode t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in Cup) t su(upCt in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) tbi in input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) ad trg input t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) t su(ta out -ta in ) two-phase pulse input in event counter mode tai in input tai out input t su(ta in -ta out ) figure 16.1. timing diagram (1) v cc = 5v
m16c/26 group 5. timing (v cc =5v) rev.1.00 2004.6.10 page 29 of 37 rej09b0176-0100z figure 16.2. timing diagram (2) t su(dCc) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(cCq) t h(cCd) t h(cCq) inti input v cc = 5v
m16c/26 group 5. electrical characteristics (v cc =3v) v cc = 3v rev.1.00 2004.6.10 page 30 of 37 rej09b0176-0100z table 16.24. electrical characteristics ( note) s y m b o l v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e v o l h i g h o u t p u t v o l t a g e s t a n d a r d t y p . unit m e a s u r i n g c o n d i t i o n v v x o u t v v x o u t 0 . 5 0 . 5 m i n .max. v c c - 0 . 5 p a r a m e t e r i oh = - 1ma i oh = - 0.1ma i oh = - 50 a i ol =1ma i ol =0.1ma i ol =50 a p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 3 , p 8 5 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 h i g h p o w e r l o w p o w e r h i g h p o w e r l o w p o w e r h i g h p o w e r l o w p o w e r x c o u t with no load applied with no load applied 2.5 1 . 6 v h y s t e r e s i s h y s t e r e s i s h i g h i n p u t c u r r e n t i i h low input current i il v ram ram retention voltage v t + - v t - v t + - v t - 0.2 0 . 8v 0.2 1 . 8v 4.0 a a at stop mode 2.0 v r e s e t v i =3v v i =0v - 4.0 r fxin r fxcin feedback resistance x in feedback resistance x cin 25 3.0 m ? m ? r p u l l u p pull-up resistance 100 k ? v x c o u t 0 0 with no load applied with no load applied h i g h p o w e r l o w p o w e r v i =0v 50 5 0 0 v c c - 0 . 5 v c c - 0 . 5 note 1 : referenced to v cc =2.7 to 3.3v, v ss =0v at topr = -20 to 85 c / -40 to 85 c, f(bclk)=10mhz unless otherwise specified. v c c v c c v c c 0 . 5 h i g h o u t p u t v o l t a g e l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 3 , p 8 5 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 t a 0 i n t o t a 4 i n , t b 0 i n t o t b 2 i n , i n t 0 t o i n t 1 , i n t 3 t o i n t 5 , n m i , a d t r g , s c l , s d a , r x d 0 t o r x d 2 , c t s 0 t o c t s 2 , c l k 0 t o c l k 2 , t a 2 o u t t o t a 4 o u t , k i 0 t o k i 3 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 3 , p8 5 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7, x in , reset, cnvss p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 3 , p8 5 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7, x in , reset, cnvss p1 5 to p1 7 , p6 0 to p6 7 ,p7 2 to p7 7 ,p8 0 to p8 3 , p8 5 to p8 7 ,p9 0 to p9 3 , p10 0 to p10 7 5.8 electrical charactristics (v cc =3v)
m16c/26 group 5. electrical characteristics (v cc =3v) v cc = 3v rev.1.00 2004.6.10 page 31 of 37 rej09b0176-0100z table 16.25. electrical characteristics (2) ( note 1) s y m b o l s t a n d a r d t y p . u n i t m e a s u r i n g c o n d i t i o n min. m a x . p a r a m e t e r i n s i n g l e - c h i p m o d e , t h e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e v s s no division f ( b c l k ) = 1 0 m h z , 1 3 f l a s h m e m o r y ma t . b . d i c c p o w e r s u p p l y c u r r e n t ( v c c = 2 . 7 t o 3 . 6 v ) t opr =25 c 3 . 0 a s t o p m o d e , f(bclk)=32khz, w a i t m o d e ( n o t e 2 ) , o s c i l l a t i o n c a p a c i t y h i g h 6 . 0 a 0.7 1.8 a fl as h memory note 1: referenced to v cc =2.7 to 3.3v, v ss =0v at topr = -20 to 85 c / -40 to 85 c, f(bclk)=10mhz unless otherwise specified. note 2: with one timer operated using f c32 . note 3: this indicates the memory in which the program to be executed exists. wait mode a low power dissipation mode, ram(note 3) f(bclk)=32khz, 4 2 0 a low power dissipation mode, flash memory(note 3) f(bclk)=32khz, a f l a s h m e m o r y 2 5 on-chip oscillation, f(bclk)=32khz, wait mode (note 2), oscillation capacity low n o d i v i s i o n , o n - c h i p o s c i l l a t i o n 8 v c c 1 = 3 . 0 v ma fl as h memory f ( b c l k ) = 1 0 m h z , p rogram v c c 1 = 3 . 0 v ma fl as h memory f ( b c l k ) = 1 0 m h z , e rase m a t . b . d t . b . d t . b . d
m16c/26 group 5. electrical characteristics (v cc =3v) v cc = 3v rev.1.00 2004.6.10 page 32 of 37 rej09b0176-0100z 5.9 timing requirements (v cc =3v) timing requirements (v cc = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 16.26. external clock input (x in input) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 100 40 40 18 18
m16c/26 group 5. electrical characteristics (v cc =3v) v cc = 3v rev.1.00 2004.6.10 page 33 of 37 rej09b0176-0100z timing requirements (v cc = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 16.27. timer a input (counter input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 60 150 60 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 600 300 300 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 300 150 150 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 150 150 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 3000 1500 1500 600 600 standard max. min. s ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 2 500 500 table 16.28. timer a input (gating input in timer mode) table 16.29. timer a input (external trigger input in one-shot timer mode) table 16.30. timer a input (external trigger input in pulse width modulation mode) table 16.31. timer a input (counter increment/decrement input in event counter mode) table 1.6.32. timer a input (two-phase pulse input in event counter mode)
m16c/26 group 5. electrical characteristics (v cc =3v) v cc = 3v rev.1.00 2004.6.10 page 34 of 37 rej09b0176-0100z table 16.33. timer b input (counter input in event counter mode) table 16.34. timer b input (pulse period measurement mode) table 16.35. timer b input (pulse width measurement mode) table 16.36. a/d trigger input table 16.37. serial i/o _______ table 16.38. external interrupt inti input ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 150 60 60 120 120 300 600 300 300 600 300 300 1500 200 380 380 300 150 150 0 50 90 160 timing requirements (v cc = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified)
m16c/26 group 5. timing (v cc =3v) v cc = 3v rev.1.00 2004.6.10 page 35 of 37 rej09b0176-0100z figure 16.3. timing diagram (1) tai in input tai out input during event counter mode tbi in input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(t in Cup) t su(upCt in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) ad trg input t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) t su(ta out -ta in ) two-phase pulse input in event counter mode tai in input tai out input t su(ta in -ta out )
m16c/26 group 5. timing (v cc =3v) v cc = 3v rev.1.00 2004.6.10 page 36 of 37 rej09b0176-0100z figure 16.4. timing diagram (2) t su(dCc) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(cCq) t h(cCd) t h(cCq) inti input
m16c/26 group 6. package rev.1.00 2004.6.10 page 37 of 37 rej09b0176-0100z 6. package lqfp48-p-77-0.50 weight(g) jedec code eiaj package code lead material cu alloy 48p6q-a plastic 48pin 7 ? 7mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 1.0 m d 7.4 m e 7.4 8 0 0.1 1.0 0.65 0.5 0.35 9.2 9.0 8.8 9.2 9.0 8.8 0.5 7.1 7.0 6.9 7.1 7.0 6.9 0.175 0.125 0.105 0.27 0.22 0.17 1.4 0 1.7 e e e h e 1 48 37 24 25 36 12 13 h d d m d m e a f y b 2 i 2 recommended mount pad a 1 a 2 l 1 l detail f lp a3 c lp 0.45 0.6 0.25 0.75 0.08 x a3 e b x m recommended
revision history m16c/26 hardware manual rev. date description page summary c-1 1.00 jun/10/ 04 - first edition
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