HC2509C march 1999 1 HC2509C features l phase - locked loop clock distribution for synchronous dram applications l supports pc - 100 and meets ? pc100 sdram registered dimm specification rev. 1.2 ? l distrib utes one clock input to one bank of five and one bank of four outputs l no external rc network required l external feedback (fbin) pin is used to synchronize the outputs to the clock input l separate output enable for each output bank l operates at 3.3 v v cc l 125 mhz maximum frequency l on - chip series damping resistors l support spread spectrum clock(ssc) synthesizers l esd protection exceeds 3000 v per mil - std - 883, method 3015 ; exceeds 350 v using machine model ( c = 200 pf, r = 0 ) l latch - up performance exceeds 40 0 ma per jesd 17 l packaged in plastic 24 - pin thin shrink small - outline package pin configuration general description the HC2509C is a low - skew, low jitter, phase - locked loop(pll) clock driver, distributing high frequency clock signals for sdram. the h c2509c operates at 3.3v v cc and provides integrated series - damping resistors that make it ideal for driving point - to - point loads. the propagation delay from the clk input to any clock output is nearly zero. one bank of five outputs and one bank of four ou tputs provide nine low - skew and low - jitter clocks. each bank of outputs can be enabled or disabled separately via the control inputs (1g and 2g). output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at clk. the HC2509C is sp ecially designed to interface with high speed sdram applications in the range of 25mhz to 125mhz and includes an internal rc network which provides excellent jitter characteristics and eliminates the needs for external components. for the test purpose, the pll can be bypassed by strapping av cc to ground. the HC2509C is characterized for operation from 0 c to 85 c. function table inputs outputs 1y 2y 1g 2g clk (0:4) (0:3) fbout x x l l l l l l h l l h l h h l h h h l h h l h h h h h h h tssop 24 package (top view) agnd vcc 1y0 1y1 1y2 gnd gnd 1y3 1y4 vcc 1g fbout clk avcc vcc 2y0 2y1 gnd gnd 2y2 2y3 vcc 2g fbin 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
HC2509C march 1999 2 functional block diagram 11 14 24 13 23 3 4 5 8 9 21 20 17 16 12 pll 1g 2g clk fbin avcc 1y1 1y2 1y4 2y1 2y2 2y3 fbout 1y0 1y3 2y0
HC2509C march 1999 3 table 1. pin description pin name pin no. type functional description clk 24 i clock input. clk provides the reference signal to the internal pll. fbin 13 i feedback input. fbin provides the feedback signal to th e internal pll. ig 11 i output bank enable. when 1g is high, all outputs 1y(0:4) are enabled. when 1g is low, outputs 1y(0:4) are disabled to a logic - low state. 2g 14 i output bank enable. when 2g is high, all outputs 2y(0:3) are enabled. when 2g is low, outputs 2y(0:3) are disabled to a logic - low state. fbout 12 o feedback output. fbout completes the feedback loop of the pll by being wired to fbin. 1y(0:4) 3,4,5,8,9 o clock outputs. these outputs provide low - skew copies of clkin. each output has an emb edded series - damping resistor. 2y(0:3) 16,17, 20,21 o clock outputs. these outputs provide low - skew copies of clkin. each output has an embedded series - damping resistor. av cc 23 power analog power supply. av cc provides the power reference for the analog circuitry. av cc can be also used to bypass the pll for the test purpose. when av cc is strapped to ground, pll is bypassed and clk is buffered directly to the device outputs. agnd 1 ground analog ground. agnd provides the ground reference for the analog c ircuitry. v cc 2,10,15,22 power power supply gnd 6,7,18,19 ground ground table 2. absolute maximum ratings over operating free - air temperature range symbols parameter value unit conditions v cc supply voltage range - 0.5 to 4.6 v v i input voltage ran ge - 0.5 to 6.5 v v o voltage range applied to any input in the high or low state - 0.5 to vcc + 0.5 v i ik input clamp current 50 ma v i <0 or v i >0 i ok output clamp current 50 ma v o <0 or v o > v cc i o continuous output current 50 ma v o =0 to v cc p max maxi mum power dissipaiton 0.7 w t stg storage temperature range - 65 to 150 c
HC2509C march 1999 4 table 3. recommended operating conditions value symbol parameter min max unit condition av cc supply voltage 3 3.6 v v ih high - level input voltage 2 v v il low - level input voltage 0.8 v v i input voltage 0 v cc v i oh high - level output current - 12 ma i ol low - level output current 12 ma t a operating free - air temperature 0 85 c table 4. electrical characteristics over recommended operating free - air temperat ure range value symbol min typ max unit v cc (v) test conditions v ik - 1.2 v 3 i i = - 18ma v cc - 0.2 min to max i oh = - 100 m a 2.1 3 i oh = - 12 ma v oh 2.4 v 3 i oh = - 6 ma 0.2 min to max i ol = 100 m a 0.8 3 i ol = 12 ma v ol 0.5 5 v 3 i ol = 6 ma i i 5 m a 3.6 v i =v cc or gnd i cc 10 m a 3.6 v i =v cc or gnd, i o = 0 ouputs: low or high c 500 m a 3.3 to 3.6 one input at v cc - 0.6v, other inputs at v cc or gnd c i 4 pf 3.3 v i = v cc or gnd c o 6 pf 3.3 v o = v cc or gnd table 5.timing requirements over recommended ranges of supply voltage and operating free - air temperature value symbol parameter min max unit f clock clock frequency 25 125 mhz input clock duty cycle 40 60 % stabilization time 1 ms time to obtain phase lock of its feedback signal to it s reference signal.
HC2509C march 1999 5 table 6. switching characteristics over recommended ranges of supply voltage and operating free - air temperature.(c l =30pf) (see figure1 and 2) = vcc = 3.3 v 0.165v vcc = 3.3v 0.3v parameter from(input) to(output) min typ max min typ max unit 66mhz < clkin - < 100mhz fbin - - 150 - 150 ps t phase error (normalized) clkin - = 100mhz fbin - - 50 50 ps t sk any y of fbout any y or fbout 200 ps jitter (pk - pk) clkin > 66mhz a ny y or fbout - 100 100 ps duty cycle clkin > 66mhz any y or fbout 45 55 % t r any y or fbout 1.3 1.9 0.8 2.1 ns t f any y or fbout 1.7 2.5 1.2 2.7 ns = these parameters are not production tested. phase error does not include jitter . figure 1. load circuit and voltage waveforms notes: 1. all input pulses are supplied by generators having the following characteristics : prr 100mhz, z o =50 w , t r =1.2ns, t f =1.2ns 2.the outputs are measured one at a time with one transition per measurement. 30pf 500 ? from output under test input output 50% v cc 50% v cc 3v 0v v oh v ol t pd 0.4v 0.4v t r t f 2v 2v load circuit for outputs voltage waveforms propagation delay times
HC2509C march 1999 6 figure 2. phase error and skew calcu lations any y any y t sk fbout any y t sk clkin fbin phase error t
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