a plus make your product a-plus ASM2506C data sheet a plus integrated circuits inc. address: 3 f-10, no. 32, sec. 1, chenggung rd., taipei, taiwan 115, r.o.c. (115) ???^?? 32 ? 3 ? 10. tel: 886-2-2782-9266 fax: 886-2-2782-9255 website : http: //www.aplusinc.com.tw sales e-mail: sales@aplusinc.com.tw technology e-mail: service@aplusinc.com.tw
ASM2506C rev 1.0 2002/5/22 1 ASM2506C ? very low-cost voice synthesizer with 4-bit microprocessor 1.0 general description the ASM2506C is very low cost voice synthesizer with 4-bit microprocessor. it has various features including 4-bit alu, rom, ram, i/o ports, timers, clock generator, watchdog timer(wdt), voice synthesizer, etc. it consists of 22 instructions in the device. with cmos technology and halt function can minimize power dissipation. its architecture is similar to risc, with two stages of instruction pipeline. it allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles). 1.1 feature single power supply can opera te from 2.4v through 5v internal program rom: 4k x 10-bit 1 sets of 17-bit dpr can access up to 80k x 10 bits data memory space data registers: ? 64 x 4-bit data ram (00-1fh plus 40h-5fh) ? unbanked special function registers (sfr) range: 20h-3fh i/o ports: ? pra: 4-bit i/o port a (2bh) ? prb: 2-bit output port b (2dh) on-chip clock generator: resistive clock drive ( rm) timer: 1 ? timer0: a 9-bit auto-reload timer/counter stack: 2-level subroutine nesting halt and release from halt function to reduce power consumption watch dog timer ( wdt ) instruction: 1-cycle instruction except for table read and program branches which are 2-cycles number of instruction: 22 the voice function can be implemented by microprocessor instruction ? one 8-bit cout output for ASM2506C
ASM2506C rev 1.0 2002/5/22 2 figure 1.1 : block diagram of ASM2506C cout osc vdd/gnd rom 1 pc[11:0] rom latch instruction latch instruction decoder 0 pch(8) pcl(4) pclatch(8) dpr3,2,1 program dlatch(10) clock generator power on reset test select p1,p2,p3,p4 enter test mode timer0(9) reset chip stack ( 12 ) data bus [ 3:0 ] instruction bus [9:0] rom_addr[16:0] rom_data[9:0] data bus[3:0] control signal addr[16:0] =00000b (addr[16:12]) prasl(4) weak or strong pull-low for pra, (data) instruction bus [9:0] instruction bus [9:0] ( voice synthesizer ) one-channel sram (64 x 4) 40h-5fh (2-level) alu(4) register(4) accumlator ( 4 ) immediate ( 4 ) dpr[16:0] reset pin reset chip pra0 00h-1fh pra(4) prb(2) prb, prc cout
ASM2506C rev 1.0 2002/5/22 3 figure 1.2 : external rom map of ASM2506C data rom 12bit x 2 stack reset vector 13fffh(80kx10-bits) 00fffh(4k) 00000h-00fffh pro g ram and data rom 17-bit data pointer pc[11:0] 00000h-13fffh reserved for testing 00080h-003ffh 00400h 00000h 00080h
ASM2506C rev 1.0 2002/5/22 4 1.2 pin-out ASM2506C pin-out vdd i - power supply during operation pra3-1 i/o sti std./o.d. i/o port with programmable strong pull-low or weak pull-low or fix-input-floating capability output type with standard or open-drain output pra0/reset i/o sti std./o.d. i/o port with programmable strong pull-low or weak pull-low or fix-input-floating capability output type with standard or open-drain output mask option selected as an external reset pin with weak pull-low capability osc i - rm mode oscillator input cout o - current output of audio gnd i - circuit ground potential test o - enter test mode. ( test = high ) prb0-1 o std./o.d. output type with standard or open-drain output 1.3 application circuit
ASM2506C rev 1.0 2002/5/22 5 1.4 bonding diagram substrate must be connected to gnd. ASM2506C pad location chip size: x= 1550+120(um) , y= 1770+120(um) pad # pad name x y pad # pad name x y 1 ra3 -664.92 -476.16 7 test_pad 105.44 -800.84 2 ra2 -664.92 -604.28 8 cout 303.96 -800.84 3 ra1 -662.64 -800.84 9 vdd 683.04 -800.84 4 ra0 -468.24 -800.84 10 rb0 664.92 -599.84 5 osc -281.04 -800.84 11 rb1 664.92 -481.44 6 gnd -111.72 -800.84 ASM2506C chip size: x= 1550+120(um) , y= 1770+120(um) 80k x 10 bit rom 6 7 8 9 5 4 1 2 3 10 11
ASM2506C rev 1.0 2002/5/22 6 1.5 dc characteristics for ASM2506C symbol parameter vdd min. typ. max. unit condition vdd operating voltage 2.4 3 5.5 v depending on freq. 3 1 isb standby 5 1 ua 4mhz, rm in halt mode 3 2 iop supply current operating 5 7 ma 4mhz, rm io floating 3 3 5 9 iih input current /internal pull low 5 -5.2 ua 4mhz, rm in halt mode (io ports with weak pull-high pull-low) 3 -3 ioh output high current 5 -8 3 7 iol output low current 5 20 ma 4mhz, rm (io ports) df/f frequency stability -10 10 % fosc(3v- 2.4v) fosc (3v) df/f fosc variation -20 20 % vdd=3v, rosc=1m, 4mhz figure 1.3 : frequency range for rosc in rm mode resistor(k ohm) 1200 1000 620 470 3v freq.(mhz) 3.27 4.11 6.28 7.84 rosc & freq. 3.27 4.11 6.28 7.84 0 2 4 6 8 10 0 200 400 600 800 1000 1200 1400 rosc k ohm freq. mhz
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