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d a t a sh eet product speci?cation file under integrated circuits, ic18 1999 may 10 integrated circuits UAA1570HL global positioning system (gps) front-end receiver circuit
1999 may 10 2 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL contents 1 features 2 general description 3 ordering information 4 quick reference data 5 block diagram 6 pinning information 7 functional description 7.1 low noise amplifiers lna1 and lna2 7.1.1 lna1in 7.1.2 lna1out 7.1.3 lna2in 7.1.4 lna2out 7.1.5 mx1in 7.1.6 general remarks and results 7.2 correlation of the UAA1570HL data sheet, application and test boards 7.3 rf mixer with preamplifier 7.4 vco 7.5 first if filter 7.6 second if mixer 7.7 second if filter 7.8 time and amplitude quantization 7.8.1 clock inputs 7.8.2 cmos to ecl sample clock squaring circuit 7.8.3 time quantization (sampler) 7.8.4 ttl output stage 7.8.5 1-bit delays 7.9 programmable synthesizer 7.9.1 vco prescaler 7.9.2 main synthesizer dividers (n-path) 7.9.3 second local oscillator dividers (l-path) 7.9.4 reference dividers (r-path) 7.10 serial interface 7.10.1 p0 and p1 7.10.2 r5 7.10.3 r0, r1, r2, r3 and r4 7.10.4 n7 7.10.5 n0, n1, n2, n3, n4, n5 and n6 7.10.6 l0, l1, l2 and l3 7.11 the serial interface word 7.12 the default frequency plan 7.13 phase detector, charge pump and loop filter 8 operating mode selection tables 8.1 manual selection operating modes 9 limiting values 10 thermal characteristics 11 dc characteristics 12 ac characteristics 13 characterization test circuit 14 default application and demonstration board 15 internal circuitry 16 package outline 17 soldering 17.1 introduction to soldering surface mount packages 17.2 reflow soldering 17.3 wave soldering 17.4 manual soldering 17.5 suitability of surface mount ic packages for wave and reflow soldering methods 18 definitions 19 life support applications
1999 may 10 3 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 1 features complete single-chip programmable double-superheterodyne c/a-code gps receiver programmable high if frequencies supporting wideband/p-code gps and global navigation satellite system (glonass) applications supports frequency plans with a 2nd if of 4 f 0 (1.023 mhz) = 4.092 mhz 48-pin lqfp package - 40 to +85 c operating temperature range 2.7 v minimum supply voltage low dc power consumption [57 ma typical with both low-noise amplifiers (lnas) active] power-down mode (<900 m a) typical receiver noise figure at 1.57542 ghz: 4.5 db typical phase noise - 72 dbc/hz at 10 khz offset simple microstrip lna1/2 and first mixer matching single pin vco with external varactor and resonator digital phase locked loop (dpll) synthesizer with programmable vco, 2nd local oscillator (lo) and reference dividers 3-bit synthesizer and power-down control input reference and independent sample clock input with internal squaring 1-bit amplitude quantized and time sampled ttl/cmos compatible output driver high active gain supporting saw filter applications configurable for external first lna applications. 2 general description the UAA1570HL is a complete single-chip double-superheterodyne receiver front-end intended for gps and glonass navigation systems. the ic includes a programmable on-chip dpll synthesizer, vco with external varactor and resonator, a 1-bit amplitude quantizer and a time sampled ttl/cmos compatible sign output bit driver. it can be used with either an active or passive antenna system by disabling or enabling the on-chip lnas and is ideally suited for low power gps receiver applications because of its 3 v supply and the power management features through control pins. programmable prescaler controls provide the flexibility of using different frequency schemes. the UAA1570HL is optimized to provide sign bit data to the companion philips part, the saa1575hl baseband digital signal processor. the saa1575hl can provide the sample clock input to the UAA1570HL by dividing a ttl/cmos level reference clock signal down to a programmable sampling clock output frequency. both ics can also be used independently. the UAA1570HL is supplied in a low profile, 48-pin lqfp package for excellent radio frequency (rf) performance and small size. 3 ordering information type number package name description version UAA1570HL lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2
1999 may 10 4 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 4 quick reference data v cca =v ddd =3v; t amb =25 2 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit v cca analog supply voltage 2.7 3 5 v v ddd digital supply voltage 2.7 3 5 v i vcca + i vddd analog supply current plus digital supply current v cca and v ddd = 2.7 v - 55.1 62.3 ma v cca and v ddd =5v - 61 69.3 ma g rf available rf power gain lnas at 1.57542 ghz - 31 - db g if1 available 1st mixer power gain mx1 at 1.57542 ghz - 17.7 - db g if2 available 2nd mixer power gain mx2 at 41.8 mhz - 21.4 - db g v(lim) limiter voltage gain to 1st latch limiter at 3.48 mhz - 78 - dbv d v lim(m) differential limiter sensitivity (peak value) f = 3.48 mhz - 100 -m v f rx receiver noise ?gure f = 1.57542 ghz - 4.5 5.2 db t amb operating ambient temperature v cca and v ddd = 3.3 to 5 v - 40 +25 +85 c v cca and v ddd =3to5v - 30 +25 +85 c v cca and v ddd = 2.7 to 5 v 0 +25 +85 c
1999 may 10 5 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 5 block diagram fig.1 block diagram. shaded blocks are not active during synthesizer state. (1) the default values are: l = 10, n = 71 and r = 4. handbook, full pagewidth mhb269 UAA1570HL divide-by-1 or 2 divide-by-r (1) (4 to 31) divide-by-1 or 2 divide-by-2 divide-by-n (1) (64 to 127) divide-by-2 divide-by-2 divide-by-l (1) (4 to 15) divide-by-3 vco 9 10 11 12 13 14 15 16 17 18 48 47 46 45 44 43 19 20 21 22 24 23 lna2 4 3 2 1 5 6 data register for programming 28 36 35 33 31 32 quantizer 29 30 34 27 26 25 squaring circuit squaring circuit 8 7 to data register mixer 2 mixer 1 40 42 41 39 38 lna1 phase frequency detector 37 to data register v cca(lna2) lna2gnd1 lna2in biasgnd2 lna2gnd2 lna2out refin v cca(vco) vcognd p12gnd clock tank v cca(pll) dgnd sign v ddd v cca(lim) bfcp liminp liminn bfcn limgnd if2n data mx1in mx1gnd v cca(mx1p) if1p if1n v cca(mx2) mx2gnd if2inp strobe if2p mxpgnd if2inn lna1gnd2 biasgnd1 lna1in lna1gnd1 v cca(lna1) p42gnd comp p39gnd pllgnd sclk lna1out p41gnd
1999 may 10 6 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 6 pinning information symbol pin pin voltage typical values (v) description v cc = 2.7 v v cc =5v v cca(lna2) 1 2.7 5 lna2 power supply: dc operation range 2.7 to 5 v; use close proximity rf decoupling to pins 2, 4 and 5 lna2gnd1 2 0 0 lna2 ground 1: minimize rf ground inductance lna2in 3 0.815 0.807 lna2 input: use external rf ac coupling biasgnd2 4 0 0 lna2 bias circuit ground: minimize rf ground inductance lna2gnd2 5 0 0 lna2 ground 2: minimize rf ground inductance lna2out 6 1.48 3.629 lna2 output: use external rf ac coupling. the dc voltage is approximately 1.3 v below the v cca(lna2) supply on pin 1. clock 7 cmos level cmos level serial interface clock input: this dc coupled cmos clock input moves 20-bit programming words into the synthesizer data input register while the strobe is low. a dc short-circuit to ground is recommended with the default frequency plan. refin 8 1.69 3.99 reference input: use external ac coupling. the dc voltage is approximately 1 v below the v cca(pll) supply on pin 36. v cca(vco) 9 2.7 5 vco power supply: dc operation range 2.7 to 5 v; use critical close proximity rf decoupling to pin 11 tank 10 1.92 1.92 vco negative impedance resonator port: use the absolute minimum trace lengths and widths and keep the loop to the vco ground pin 11 as short as possible, while centring the comp output voltage at pin 40 within the charge pump output voltage range given in chapter 11 by adjusting the resonator inductance and/or required ac coupling component. vcognd 11 0 0 vco ground: minimize rf ground inductance; use critical close proximity rf decoupling to vco supply pin 9 p12gnd 12 0 0 this pin provides additional rf shielding and has to be connected to ground mxpgnd 13 0 0 rf mixer preampli?er ground: minimize rf ground inductance mx1in 14 0.82 0.81 rf mixer preampli?er input: use external ac coupling and rf matching mx1gnd 15 0 0 rf mixer ground: minimize rf ground inductance; use critical close proximity rf decoupling to v cca(mx1p) supply pin 16 v cca(mx1p) 16 2.7 5 rf preampli?er/mixer power supply: dc operation range 2.7 to 5 v; use critical close proximity rf decoupling to pin 15 if1p 17 2.7 5 rf mixer if positive output: dc couple this output pin to the v cca(mx1p) supply through ?rst if ?lter inductors or rf chokes. capacitively decouple the supply near the output inductors. balanced ?rst mixer if1 outputs are recommended. prevent externally squared reference harmonics from entering the ?rst if signal path or components.
1999 may 10 7 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL if1n 18 2.7 5 rf mixer if negative output: dc couple this output pin to the v cca(mx1p) supply through ?rst if ?lter inductors or rf chokes. capacitively decouple the supply near the output inductors. balanced ?rst mixer if1 outputs are recommended. prevent externally squared reference harmonics from entering the ?rst if signal path or components. v cca(mx2) 19 2.7 5 if mixer power supply: if present, decouple the common v cc line sourcing the ?rst and second mixer by placing a large decoupling capacitor between the two mx2gnd 20 0 0 if mixer ground: minimize if ground inductance; use close proximity if decoupling to the v cca(mx2) supply pin 19 if2inn 21 0.983 0.98 if mixer negative input: use external ac coupling. balanced if1 second mixer inputs are recommended. prevent externally squared reference harmonics from entering the ?rst if signal path or components. if2inp 22 0.983 0.98 if mixer positive input: use external ac coupling. balanced if1 second mixer inputs are recommended. prevent externally squared reference harmonics from entering the ?rst if signal path or components. strobe 23 cmos level cmos level serial interface strobe input: a low level on this dc-coupled cmos strobe input enables the clock input to load the 20-bit programming word into the synthesizer input data register. a mandatory dc short-circuit to ground is required to ensure that the default frequency plan is invoked on power-up. if2p 24 2.7 5 if mixer second if positive output: dc couple this output pin to the v cca(mx2) supply through second if ?lter inductors or rf chokes. capacitively decouple the supply near the output inductors. balanced second mixer if2 outputs are optional for many applications. short the unused if2p or if2n output directly to the supply in single-ended applications. if2n 25 2.7 5 if mixer second if negative output: dc couple this output pin to the v cca(mx2) supply through second if ?lter inductors or rf chokes. capacitively decouple the supply near the output inductors. balanced second mixer if2 outputs are optional for many applications. short the unused if2p or if2n output directly to the supply in single-ended applications. limgnd 26 0 0 limiter ground: minimize ground inductance bfcn 27 1.696 3.999 negative limiter input dc feedback loop decoupling: ac couple this pin to ground in close proximity to the pin. the dc voltage is approximately 1 v below the v cca(lim) supply on pin 31. no dc coupling. liminn 28 1.696 3.999 negative limiter input: ac couple this pin to the second if ?lter output or to ground if unused with single-ended ?lter applications. the dc voltage is approximately 1 v below the v cca(lim) supply on pin 31. no dc coupling. symbol pin pin voltage typical values (v) description v cc = 2.7 v v cc =5v
1999 may 10 8 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL liminp 29 1.696 3.999 positive limiter input: ac couple this pin to the second if ?lter output or to ground if unused with single-ended ?lter applications. the dc voltage is approximately 1 v below the v cca(lim) supply on pin 31. no dc coupling. bfcp 30 1.696 3.999 positive limiter input dc feedback loop decoupling: ac couple this pin to ground in close proximity to the pin. the dc voltage is approximately 1 v below the v cca(lim) supply on pin 31. no dc coupling. v cca(lim) 31 2.7 5 limiter, sample clock squaring and sampler emitter coupled logic (ecl) circuits power supply: decouple in close proximity to pins 26 and 31. if present, isolate from the common v cc line sourcing the ?rst and second mixer by placing a large decoupling capacitor between this block and the mixers. data 32 cmos level cmos level serial interface data input: this dc-coupled cmos data input accepts 20-bit programming words into the synthesizer data input register, while the strobe is low, on the rising edge of the clock input. a dc short-circuit to ground is recommended with the default frequency plan. v ddd 33 2.7 (independent of v cc level) 5 (independent of v cc level) sign bit ttl output driver power supply: critically isolate and separately decouple this digital v ddd supply from all other analog (v cca ) supplies. maintain minimum trace lengths to decoupling components. particular attention should be applied to prevent coupling into v cca(lim) pin 31. if saa1575hl is used, use the digital supply from the back-end. sign 34 ttl output ttl output amplitude and time quantized second if output signal: extreme care should be taken to isolate this sampled ttl output signal from all analog traces and components, particularly the second if ?lter components at the limiter input. avoid coupling into the reference oscillator signal trace. dgnd 35 0 0 sign bit ttl output driver sink ground: critically isolate this digital supply ground from all other analog supplies and grounds. maintain minimum trace lengths to decoupling components. v cca(pll) 36 2.7 5 synthesizer power supply: decouple in close proximity to pin 38 sclk 37 1.34 2.5 sample clock squaring input: accepts low-level ac coupled sample clock inputs directly from the pll reference oscillator or dc-coupled externally squared digital clocks derived from the pll reference oscillator after external frequency division. the maximum dc-coupled input level at pin 37 should not exceed 75% of the v cca(lim) supply value. the threshold level is set at half the supply value on v cca(lim) pin 31. pllgnd 38 0 0 pll ground: minimize ground inductance; use close proximity decoupling to the v cca(pll) supply pin 36 p39gnd 39 0 0 this pin provides additional rf/if shielding and has to be connected to ground symbol pin pin voltage typical values (v) description v cc = 2.7 v v cc =5v
1999 may 10 9 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL comp 40 depends on vco application depends on vco application charge pump phase frequency detector output: the pll loop ?lter is connected in shunt and close proximity to this pin. the pll loop ?lter tuning control voltage should be routed to the external vco varactor circuit using minimal trace lengths in complete isolation from all potential coupling sources. p41gnd 41 0 0 this pin provides additional rf/if shielding and has to be connected to ground p42gnd 42 0 0 this pin provides additional rf/if shielding and has to be connected to ground v cca(lna1) 43 2.7 5 lna1 power supply: dc operation range 2.7 to 5 v; use close proximity rf decoupling to pins 44, 46 and 47. lna1gnd1 44 0 0 lna1 ground 1: minimize rf ground inductance lna1in 45 0.815 0.807 lna1 input: use external rf ac coupling biasgnd1 46 0 0 lna1 bias circuit ground: minimize rf ground inductance lna1gnd2 47 0 0 lna1 ground 2: minimize rf ground inductance lna1out 48 1.48 3.629 lna1 output: use external rf ac coupling. the dc voltage is approximately 1.3 v below the v cca(lna1) supply on pin 43. symbol pin pin voltage typical values (v) description v cc = 2.7 v v cc =5v
1999 may 10 10 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.2 pin configuration. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 12 24 37 25 UAA1570HL mhb270 v cca(pll) dgnd sign v ddd v cca(lim) bfcp liminp liminn bfcn limgnd if2n data lna1gnd2 biasgnd1 lna1in lna1gnd1 v cca(lna1) p42gnd comp p39gnd pllgnd sclk lna1out p41gnd v cca(lna2) lna2gnd1 lna2in biasgnd2 lna2gnd2 lna2out refin v cca(vco) vcognd p12gnd clock tank mx1in mx1gnd v cca(mx1p) if1p if1n v cca(mx2) mx2gnd if2inp strobe if2p mxpgnd if2inn
1999 may 10 11 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7 functional description the programmability of the UAA1570HL and flexible interface definitions allow the device to be configured for a wide range of applications. to restrict the content of this document the functional description of the device will generally concentrate on the c/a-code application circuit based on the default frequency plan. the application circuit does not allow easy measurement, calibration and documentation of the many sub-block characteristics which ensure good system performance. therefore, test boards have been developed which allow direct measurement of the sub-block characteristics. the tables and graphs reflect the UAA1570HL specification as derived from simulation and measured results in these characterization board environments. the tables and graphs do not directly specify application board expectations. the functional description however, focuses on the default application. the rf system diagram (see fig.3) illustrates the default application of the UAA1570HL in the philips gps demonstration board. in this application the UAA1570HL is intended to be operated directly from a passive gps antenna through a very short antenna cable. any cable loss in this demonstrator adds directly to the system noise figure and should therefore be minimized. lna1 can be powered down in the UAA1570HL to accommodate applications built around external lnas, typically where long antenna cable runs are required. the first lna is assumed to be matched with a 2nd-order band-pass structure to provide some input selectivity, since no dielectric or saw filter has been used in the demonstration board. it should be noted that low loss rf saw filters now make it possible to significantly improve the jam immunity of this amplifier, by placing a saw filter at the output of the antenna. on the demonstration board the first lna is followed by a low loss rf saw filter (<2.4 db). on the demonstration board the second lna has been matched to 50 w using a simple transmission line structure. finally, another identical rf saw filter follows the second lna into the first mixer.
1999 may 10 12 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.3 UAA1570HL rf system diagram (default application). mhb271 handbook, full pagewidth 38 48 47 46 45 44 43 42 41 40 39 37 23 13 14 15 16 17 18 19 20 21 22 24 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 UAA1570HL c311 c312 c303 r301/c301 c309 c310 c301 c304 c302 r323 c336 r305 l302 c317 c318 c314 c319 c332 c316 c315 r306 r322 r314 r310 r311 l304 l303 l301 l309 l308 l307 l306 c345 c308 c322 c306 c320 c331 c347 c337 c334 c324 c346 c335 vrf c327 c328 c321 c305 l305 c338 c339 c313 c340 c330 data r307 refin vrf r319 r315 c341 vrf refin vrf clock v ddd c329 r316 d301 strobe sign sclk isolate these digital signals, supplies, and grounds from all analog rf functions. optimum performance requires that the gps digital baseband, supply regulators, and other sources of digital noise be placed in this relative orientation to the UAA1570HL. l = 386 mils w = 6 mils 100 w l = 217 mils w = 33 mils 50 w line stretcher l = 376 mils w = 33 mils 50 w line stretcher l = 412 mils w = 6 mils 100 w c323 c325 c307 l = 286 mils w = 6 mils 100 w l = 355 mils w = 6 mils 100 w saw bpf301 saw bpf302 v tune vrf l = 315 mils w = 6 mils 100 w l = 1020 mils w = 8.8 mils l = 900 mils w = 8.8 mils c326 j301 isolate the reference input and its harmonics from the first if and its filtering components v tune analog ground digital ground
1999 may 10 13 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.1 low noise ampli?ers lna1 and lna2 two identical lnas are provided on the ic although lna1 need not be biased, if sufficient external gain is provided by an external lna. the input stage of each amplifier consists of an unbalanced common emitter and a cascode stage. the ac-coupled output stage is a compound feedback bootstrap amplifier. each stage is independently biased and regulated. lna1 can be disabled by connecting the respective supply (pin 43) to ground. lna2 has to be powered-up even if not used. each lna can supply a power matched gain of approximately 15.5 db with an associated noise figure of 3.7 db. both lnas have - 1 db input compression points of approximately - 22 dbm from a 3 v supply. the 2nd and 3rd-order input intercepts are approximately - 7.9 and - 13 dbm, respectively, in a power matched environment. the rf match impedances at l1 (1.57542 ghz) are provided in table 1 for all rf inputs and outputs. table 1 rf matching impedances pin real part ( w ) imaginary part ( w ) function 45 31 - j32 lna1 input 48 77.5 +j6 lna1 output 324 - j25 lna2 input 6 74.5 - j0.5 lna2 output 14 33.5 - j25.5 1st mixer input these rf port impedances are marked on the following smith charts (see figs 4 to 8; normalized to 50 w ) and suggested matching structure netlists are provided. they contain transmission lines defined by their characteristic impedance z (in ohms), their electrical length e (in degrees) and the operating frequency f (in ghz). capacitors c are given in pf. tlin is a series transmission line and tloc is an open-circuit stub transmission line. node 1 is the UAA1570HL rf port being matched and node 0 is ground. these matching networks are structurally identical to those illustrated on the gps application block diagram, however, the component values in the application diagram are somewhat different to account for stray capacitances and other real world influences. the netlists are derived from eezmatch software (besser associates, los altos, ca, usa). generally, we assume a minimum shunt capacitance, due to the ic pin pad and adjacent pin strays, of approximately 0.25 pf as an initial stray element in the netlist below, that will always be present in the matching structure design. this value should be re-estimated and matched if the layout introduces significant additional strays at the pin pads.
1999 may 10 14 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.1.1 lna1in cap10c= 0.25 ! c1 c = pf tlin12z= 97.0 e = 34.5 f = 1.57542 ! tl1 z = oh, e = deg, f = ghz cap 2 0 c = 2.0 ! c3 c = pf alternatively the 2 pf shunt capacitance at the input of the 97 w matching line above might be replaced with a 25 w microstrip open stub if space permits. tloc20z= 25.0 e = 26.1 f = 1.57542 fig.4 lna1 input impedance and matching network. handbook, full pagewidth mhb318 0.2 0.5 1 2 5 0.2 0.5 1 2 5 10 10 0 0.2 0.5 1 2 5 10 + j - j
1999 may 10 15 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.1.2 lna1out to facilitate matching of both lna outputs, a small shunt capacitance should be placed as close as possible to the output pin pad increasing the assumed 0.25 pf lumped pin capacitance by approximately 0.5 pf to 0.75 pf. this ensures that a simple, short, high impedance transmission line will provide a good 50 w match at high gain. a via to the opposite side of the board right at this output pin allows a stub or chip capacitance to be added without comprising the characteristics of the 97 w matching line. cap10c= 0.25 ! c22 c = pf ind128l=0.7!l7=nh cap280c= 7.1658792e - 1 ! c23 c = pf tlin 28 29 z = 97.0 e = 26.239010 f = 1.57542 ! tl15 if an open line stub is used, the latter components have to be replaced by: tloc 2 80z= 20.0 e = 8.0 f = 1.57542 ! otl7 z = oh, e = deg, f = ghz tlin 28 30 z = 97.0 e = 26.2 f = 1.57542 ! tl16 z = oh, e = deg, f = ghz fig.5 lna1 output impedance and matching network. handbook, full pagewidth mhb319 0.2 0.5 1 2 5 0.2 0.5 1 2 5 10 10 0 0.2 0.5 1 2 5 10 + j - j
1999 may 10 16 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.1.3 lna2in cap10c= 0.25 ! c13 c = pf tlin 1 14 z = 97.0 e = 30.0 f = 1.57542 ! tl9 z = oh, e = deg, f = ghz cap140c= 2.3309277 ! c14 c = pf fig.6 lna2 input impedance and matching network. handbook, full pagewidth mhb320 0.2 0.5 1 2 5 0.2 0.5 1 2 5 10 10 0 0.2 0.5 1 2 5 10 + j - j
1999 may 10 17 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.1.4 lna2out cap10c= 0.25 ! c22 c = pf ind131l=0.1!l8 l=nh cap310c=0.5!c24c=pf tlin 31 32 z = 97.0 e = 25.077020 f = 1.57542 ! tl17 z = oh, e = deg, f = ghz in the event that the second capacitor is replaced by an open line stub, the last two components have to be changed: tloc 3 10z= 20.0 e = 5.5 f = 1.57542 ! otl8 z = oh, e = deg, f = ghz tlin 31 33 z = 97.0 e = 24.460094 f = 1.57542 ! tl = 18 z = oh, e = deg, f = ghz fig.7 lna2 output impedance and matching network. handbook, full pagewidth mhb321 0.2 0.5 1 2 5 0.2 0.5 1 2 5 10 10 0 0.2 0.5 1 2 5 10 + j - j
1999 may 10 18 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.1.5 mx1in cap10c= 0.25!c5c=pf tlin 1 13 z = 100.0 e = 31.083933 f = 1.57542 ! tl9 z = oh, e = deg, f = ghz cap130c= 1.673902 ! c6 c = pf again an alternative open stub line is suggested which could be used to replace the 1.67 pf capacitance at this end of the previous netlist. tloc 1 30z= 25.0 e = 23.0 f = 1.57542 ! otl 5 z = oh, e = deg, f = ghz fig.8 mx1 input impedance and matching network. handbook, full pagewidth mhb322 0.2 0.5 1 2 5 0.2 0.5 1 2 5 10 10 0 0.2 0.5 1 2 5 10 + j - j
1999 may 10 19 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.1.6 g eneral remarks and results the rf match has an important effect on the gains, noise figure, and dynamic characteristics of the rf system blocks. reflection coefficients better than - 15 db are easily attainable and can be improved to better than - 25 db with attention to details. in the following graph (see fig.10) the solid trace g lna (db) represents the measured frequency response of the UAA1570HL lnas as measured on a spectrum analyzer, while the dotted and dashed results were obtained using a noise figure meter over a more restricted frequency range. fig.9 typical lna fundamental, 2nd and 3rd-order product output levels as a function of input level. (1) fundamental output. (2) 3rd-order product output. (3) 2nd-order product output. handbook, halfpage - 90 - 70 - 50 - 10 20 - 100 - 20 0 mhb272 - 30 - 40 - 60 - 80 output (dbm) input (dbm) (2) (3) (1) fig.10 typical lna gain and noise figure as a function of frequency (50 w power matched on the input and output). (1) lna gain (db). (2) power gain. (3) noise figure. handbook, halfpage mhb273 0 1000 2000 3000 30 20 - 10 10 0 g lna (db) f (mhz) (2) (3) (1) 15.3 3.68 1575.42
1999 may 10 20 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.2 correlation of the UAA1570HL data sheet, application and test boards the application circuit does not allow easy measurement, calibration and documentation of the many sub-block characteristics which ensure good system performance. therefore, test boards have been developed which allow direct measurement of the sub-block characteristics. these boards use a 1 : 16 w ratio rf transformer to transform 50 w to the more appropriate value of 800 w at if frequencies. the high-impedance side of these transformers is terminated with a physical resistor to adjust the UAA1570HL impedance at the port being measured, to approximately 800 w . this ensures that a calibrated signal is applied or received in the 50 w test environment. the transformer provides marginal performance at 41.8 mhz, so calibration results for this transformer are also included in this document. the 800 w impedance environment is somewhat less than that used in the application board. the UAA1570HL characteristic tables provided in this document are calibrated to this 800 w environment as quantified in the notes at the end of the table. the effects of the transformer and associated termination losses have also been removed to some extent, so that specifications reflect the performance of the ic. the measured graph results were all derived from the test boards and corrected to again reflect part performance as much as possible. however, this was not always possible, so some discussion concerning the measurement limitations is provided where appropriate. where possible, fundamental design relationships and limitations are indicated. the following two graphs (figs 11 and 12) reflect the measured performance of the 1 : 16 w ratio rf transformer used to test the if functions. two transformers were placed back-to-back to make these measurements. figure 11 represents the transmission function of just one of these transformers over frequency. figure 12 represents the associated return loss at one input with the second transformer terminated into 50 w . in the actual UAA1570HL test board a single transformer is terminated in 800 w . in addition to the direct effects of power losses introduced by the transformer (approximately - 1.3 db at 41.82 mhz), which are reflected in the measured s21 results, the test board results may also be impacted by deficiencies in the transformer 1 : 4 voltage step-up ratio at 41.8 mhz; however, this has not been quantified. an additional correction must be made to the current test results to compensate for internal 4 pf shunt capacitors on each collector output of the first mixer, which have not been resonated out in the testing. the first mixer measurements also include a 3 db loss due to the 800 w transformer termination. this loss is also removed from the specification result. the second mixer has similar 2.1 db input and 3 db output transformer termination losses removed from the specification. for measurements made at 3.48 mhz in the second if, 0.4 db must be added to the measured results to reflect transformer losses at if2, also. in summary the measured gain of the first mixer has been increased by 1.3 db (transformer il) + 1.4 db (capacitive roll-off effects) + 0.2 db (gain match) + 3 db (output transformer termination loss) or 5.9 db to calibrate out these losses in the specification. the measured gain of the second mixer has been increased by 1.3 db (input transformer il) + 1.7 db (input term loss) + 0.4 db (output transformer il) and + 3 db (output term loss) or 6.4 db to calibrate out these losses in the specification.
1999 may 10 21 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.11 s 21 for the test measurement transformer. (1) s 21 ; t amb = - 40 c. (2) s 21 ; t amb = +25 c. (3) s 21 ; t amb = +85 c. handbook, halfpage 0 100 0 - 5 s 21 (db) f (mhz) (2) (3) (1) - 4 mhb274 - 3 - 2 - 1 20 40 60 80 fig.12 s 11 for the test measurement transformer. (1) s 11 ; t amb = - 40 c. (2) s 11 ; t amb = +25 c. (3) s 11 ; t amb = +85 c. handbook, halfpage 0 100 20 - 30 s 11 (db) f (mhz) - 20 mhb275 - 10 0 10 20 40 60 80 (2) (3) (1)
1999 may 10 22 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.3 rf mixer with preampli?er the 1st mixer (the rf mixer) consists of an rf preamplifier followed by a gilbert cell mixer. the rf preamplifier consists of the same unbalanced common emitter and cascode stage as used in the lnas, but without the compound feedback bootstrap output stage. the cascode output is ac-coupled into one side of the lower tree of the gilbert cell mixer. the other side is internally ac-coupled to mixer ground via a 20 pf decoupling capacitor. the gilbert mixer rf input is degenerated with low loss inductive emitter feedback to increase the effective - 1 db compression point and intercept points. referenced to the preamplifier input, the - 1 db compression point and 3rd-order intercept point are - 25.4 dbm and - 16.3 dbm, respectively. another important first mixer parameter is its 2nd-order input intercept point, which will extrapolate to approximately 1.38 v (peak value) differential or +12.8 dbm in the 50 w mixer input environment. the differential output of the gilbert cell mixer is open-collector to allow optimization of conversion gain and matching to the first if filter over a wide range of frequencies and filter options. the total conversion gain is therefore determined by the real part of the effective output load, which is given by the if filter input impedance and loss and/or fixed filter input matching networks, if present. the voltage conversion gain can be estimated by multiplying the effective single-ended to differential transconductance value for the first mixer (0.0531 a/v) by the total effective differential output resistance. the total power conversion gain to a differential load can be estimated from the voltage conversion gain by subtracting . the total power delivered by the mixer to the output resistance is distributed between the fixed output termination, the if filter input impedance, as well as equivalent loss impedances associated with the finite q of filter components. the assumption has also been made that the output impedance which the mixer sees is real, at least in the if band. note : the open-collector outputs of the first mixer each include internal 4 pf capacitors to ground. these capacitors should be included in the design of the first if filter by removing 2 pf from the differential input capacitance for balanced filters and 4 pf from single-ended designs. 10 diff_load 50 w ---------------------- log therefore, the test circuit voltage conversion gain is estimated at 0.0531 a/v times the effective differential loading of approximately 440 w . this results in a voltage conversion gain of approximately 27.4 dbv. subtracting 9.4 db to convert from power in a 50 w environment to power into 440 w , we see that the first mixer delivers a total power conversion gain of approximately 18.0 db in the test circuit. it is important to note that approximately 3 db of this available power gain is lost in the test circuit output transformer termination and that much of this power can be recovered in application circuits. the peak differential output voltage swing of the mixer should be limited to less than approximately 1 v (peak value) or 2 v (p-p) differential or 0.5 v (peak value) single-ended to prevent clipping by the internal output esd protection diodes and to prevent mixer output saturation. this implies that effective differential output loads of approximately 2.5 k w could result in clipping at the output of the mixer. the first mixer output structure also supports single-ended first if filter applications. by taking one of the mixer outputs to the supply rail, the other can drive a single-ended first if filter, thereby reducing external component cost in some applications. maintaining the same single-ended loading impedance, as in the differential case (i.e. double the effective single-ended load) results in the same peak voltage across the same load, even with only half the transconductance 1 2 (0.0531 a/v) available. therefore the same power is delivered to the same filter load and the conversion gain remains the same. however, an effective load of 1.25 k w would also bring this single-ended mixer output to the same clipping point as the full differential equivalent load of 2.5 k w . the maximum recommended first mixer single-sided voltage conversion gain (input to one output) is therefore approximately 32 for both single-ended and differential output applications. the power matched double-side band (dsb) noise figure of the rf mixer with preamplifier is approximately 12 db at 1.57542 ghz from a 3 v supply.
1999 may 10 23 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.13 typical first mixer fundamental, 2nd and 3rd-order product output levels as a function of input level. (1) fundamental output. (2) 3rd-order product output. (3) 2nd-order product output. handbook, halfpage - 90 - 70 - 50 - 10 20 - 100 - 20 0 mhb276 - 30 - 40 - 60 - 80 output (dbm) input (dbm) (2) (3) (1) fig.14 typical rf mixer noise figure as a function of temperature and supply voltage (test board). (1) f dsb ; t amb = - 40 c. (2) f dsb ; t amb = +25 c. (3) f dsb ; t amb = +85 c. handbook, halfpage 2345 20 16 0 12 mhb277 8 4 f dsb (db) v cc (v) (2) (3) (1)
1999 may 10 24 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.4 vco the vco consists of a single transistor in common collector configuration with internal positive feedback realized by capacitors connected from emitter to ground and emitter to base. together with the external resonator/inductor, this is a typical colpitts circuit. with the transistors base connected to pin 10 (tank), the internal circuit arrangement produces a large negative input impedance at this pin. at v cca = 3 v and t amb =27 c the oscillator transistor is initially biased with approximately 1.5 ma of start-up current. this value is relatively constant varying from approximately 1.56 ma at t amb = +120 c to 1.4 ma at t amb = - 55 c. during operation, the average currents are higher due to the large amplitudes involved leading to recti?cation and bias point shifting. the vco operates as a negative impedance oscillator with a suitable external inductive resonator. series or parallel resonators can be used, while tuning is achieved by an external varactor diode. vco gain as well as the out-of-loop bandwidth phase noise are dependent on the choice of external elements used here. consequently, they should be selected with great care; their quality factor is especially important and should be as high as possible. finally, the vco is followed by a differential buffer stage with emitter follower inputs splitting the signal to the divider and lo driver stage path to increase isolation between mixer and synthesizer and their wanted or unwanted signals. this first buffer stage is followed by two other specialized buffer amplifier stages in the individual signal paths bringing the signal to the required levels for driving a mixer or a divider. fig.15 simulated vco small signal negative resistance (top diagram) and capacitance (below), without strays. (1) t amb = - 55 c. (2) t amb = +27 c. (3) t amb = +120 c. handbook, full pagewidth 3 0 0.5 1 1.5 2 2 4 0 0 100 - 100 2.5 mhb278 f (ghz) r ( w ) c (pf) (2) (3) (1) (2) (3) (1)
1999 may 10 25 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.16 magnitude of the reflection coefficient of vco negative resistance tank pin (measured). (1) corrected for strays. (2) raw data 3 v supply voltage. handbook, halfpage 2.4 0.4 mhb279 0.4 1 3 0.8 0.6 2 f (ghz) (2) (1) 0.8 1.2 1.6 2.0 fig.17 phase of the reflection coefficient of vco negative resistance tank pin (measured). (1) corrected for strays. (2) raw data 3 v supply voltage. handbook, halfpage 0 - 200 mhb280 0.4 1 3 0.8 0.6 2 f (deg) f (ghz) (2) (1) - 160 - 120 - 80 - 40
1999 may 10 26 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.5 first if ?lter the first if filter provides four functions: 1. it provides selectivity to protect the 2nd mixer (the if mixer) from high level spurious rf signals which pass through the wide band-pass envelope of the rf filters, typically 40 to 60 mhz. 2. the filter attenuates thermal noise and spurious signals in the 2nd mixer image band. 3. it can provide impedance matching/transformation from the rf mixer output to the if mixer input. 4. it can reject spurious common mode and/or differential signals generated by high level local sources such as harmonics of the reference clock or sample clock. the first if can be structured to support a wide range of single-ended or balanced filters including lc or saw realizations. high rf gain provides first if signal levels high enough to accommodate first if filter losses of 15 db with optimum rf matching and conversion gain in the first mixer. the philips application board uses a 6th-order coupled resonator filter based on the butterworth response. the design method is described in the handbook of filter synthesis by anatol zverev. the handbook tables formulate single-ended filter designs which we later convert to a balanced form. the initial centre frequency and bandwidth were 41.82 and 4.5 mhz, respectively. the following list illustrates the tabular design 3 db down k and q parameters from zverev that were developed for the initial single-ended structure. r s = 331.4 w r l = 689.6 w q 0 = 5.0; insertion loss = 4.742; q 1 = 0.8226; q n = 1.7115; k 12 = 0.6567; k 23 = 0.7060. this tabular listing was chosen based on the desired selectivity and minimal insertion loss, which could be realized with available surface mount inductors operating with quality factors (q) in the range of 40 to 50. the impedance level is determined by the choice of design inductance (165 nh), with foresight given to eventual balancing of the design. maximizing the load presented to the first mixer was also a consideration. with some frequency plans stability in both the first and second if will also need to be considered when choosing the impedance level of the design. the handbook calculations result in a preliminary single-ended three shunt tank structure with a coupling capacitor between each tank as follows: r s = 331 w tank 1 = 165 nh in parallel with 81.6 pf coupling capacitor 1 = 6.2 pf tank 2 = 165 nh in parallel with 74.9 pf coupling capacitor 2 = 6.7 pf tank 3 = 165 nh in parallel with 81.1 pf r l = 690 w . to convert this filter to a balanced design it can be mirrored in the ground plane which would result in the following balanced structure. it should be noted that the tank design inductances have doubled while the tank capacitances have halved, which can be seen by removing the virtual ground plane. the series elements remain unchanged in the balanced design, while the differential source and load have of course doubled. r s = 663 w tank 1 = 330 nh in parallel with 40.8 pf coupling capacitor 1 = 6.2 pf tank 2 = 330 nh in parallel with 37.5 pf coupling capacitor 2 = 6.7 pf tank 3 = 330 nh in parallel with 40.6 pf r l = 1380 w . to optimize the power developed by the first mixer its load was maximized by driving the 1380 w side of this filter. it was also decided to bias the output of the first mixer through tank 3 components by breaking the former differential 330 nh inductor back into two 165 nh inductors connected to the supply which also acts as a virtual ground. the filter was then resimulated in spice to optimize against available discrete surface mount component values with finite quality factors. all filters must be driven by their design impedances to produce their prescribed response. since the finite quality factors of the filter inductors emulate an equivalent shunting load of approximately 2 p f l q, the source and load terminating impedances can be increased to compensate for this parasitic element while maintaining ideal filter response and minimizing losses. in the default application, r322/306 in conjunction with the equivalent parallel resistance at the respective filter input and output give the desired terminating impedance.
1999 may 10 27 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL the limitation imposed by image noise is illustrated in fig.18 where the ideal calculated filter response is compared against the measured noise density at the output of the first if filter. the single sided fet probe measured result was corrected by +6 db to account for balanced processing and or - 11.2 db to accommodate power conversion losses. the if noise density selectivity is seen to be limited by the available rf gain and noise figure of the first mixer. at the image frequency, 34.86 mhz, the measured noise floor is approximately 13 db below the desired if level at 41.82 mhz. this will result in an image contribution to the noise figure of the system of approximately 0.2 db. 10 log 50 w 663 w ---------------- the in-band noise density can be estimated based on the single-ended voltage gain to the output of the if filter. with the antenna thermal input level at approximately - 174 dbm/hz, noise figure of approximately 4 db and voltage gain from the antenna to the if filter output of approximately 47 dbv (at 5 v supply voltage), we can expect the differential noise power density to be approximately - 174 dbm + 4 db + 47 dbv + 6 db (conversion to balanced) - or - 129 dbm/hz. the final term converts the measured power using a high impedance fet probe, calibrated to a 50 w environment, to the actual 663 w differential filter output environment. 10 log 663 w 50 w ---------------- fig.18 first if filter output noise power density (application board). (1) ideal calculated filter response. (2) measured filter noise density. handbook, halfpage 30 - 120 - 140 - 130 - 150 - 160 34 50 mhb281 38 42 46 n d (dbm/hz) f (mhz) (2) (1) 34.86 10 6 /sec 41.82 10 6 /sec
1999 may 10 28 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.6 second if mixer the second mixer is a standard gilbert cell mixer operating with a total tail current of 4.3 ma, which is proportional to absolute temperature (ptat). the rf input, or lower tree of the mixer, is not internally terminated other than by 5 k w biasing resistors to each input. with no significant emitter degeneration, the real part of the rf port input impedance is dominated by the two differential junction r p s in parallel with the bias elements. the differential output of the gilbert cell mixer is open-collector to allow the conversion gain and matching to the second if filter to be optimized over a wide range of frequencies and to many types of if filters. the conversion voltage gain is determined by the tuned real part of the effective output load. this load may consist of the if filter input impedance as well as fixed filter input matching compensation terminations and losses. the voltage conversion gain can be estimated by multiplying the effective differential conversion transconductance value (0.0294 a/v) by the total effective differential load at the output of the mixer. the conversion power gain is best described relative to specified mixer input and output impedance environments. the power conversion gain is calculated by subtracting from the dbv value of the voltage conversion gain of the mixer. it should be noted that differential second mixer input terminations may be dc-coupled. we can simplify and estimate the second mixer conversion gain in the default application by noting that the input impedance environment is approximately 663 w , while the output environment is approximately 1394 w . with effective output loading of 854 w (2.2 k w in parallel with 0.7 2 996 w ) the voltage conversion gain can therefore be expected to be approximately 25.1 v/v or 28 dbv. the power correction from 663 w at the input to 1394 w (0.7 2 996 w ) at the output is - 3.2 db, so the resulting power conversion gain is approximately 24.8 db. the factor of 0.7 in the calculation of the impedance level is explained in section 7.7. it should be noted that a balanced coupled k filter can be converted to a single-ended equivalent with a single-ended input impedance exactly equal to that of the full differential filter by keeping the same tank resonator components, but placing the series coupling capacitors in single-ended series (i.e. halving the differential value) and ac grounding one side of the tanks. 10 output resistance environment input resistance environment ------------------------------------------------------------------------------- - log the demonstration board was converted from a balanced second if filter in this manner. to optimize the noise figure of the second mixer the input termination admittance should be reduced. however, this will be at the expense of the mixers input compression and 3rd-order intercept characteristics. since the rf input of the if mixer is a simple differential stage, the input - 1db compression point and 3rd-order intercept points are relatively fixed at approximately 67 and 215 mv (peak value), respectively, in the second mixer. this results from noting that an undegenerated differential input can be expected to have an input - 1 db compression point of approximately 36.6 mv (peak value) differential. with a small additional extrinsic emitter degeneration the - 1db compression point is raised to approximately 67 mv (peak value) differential. this is approximately - 24.7 dbm in the 663 w second mixer gps application input environment with the 3rd-order intercept point being approximately 10 db higher at - 14.6 dbm. another important second mixer parameter is its 2nd-order input intercept point, which will extrapolate to approximately 79.8 v (peak value) differential or 36.8 dbm in the 663 w mixer input environment. the peak output voltage swing of the if mixer should be limited to a peak differential swing of less than approximately 1 v (peak value) or 2 v (p-p) differential to prevent clipping by the internal output esd protection diodes and to prevent mixer output saturation. this implies that an effective differential output load of approximately 3.2 k w could result in clipping at the output of the mixer. the if mixer supports single-ended first and second if filter applications. a single-ended input is implemented by ac bypassing one side of the if mixer input to ground and accepting an associated drop in mixer conversion voltage gain. it should be noted that single-ended input terminations can still be dc-coupled to the mixer input pins by using the above mentioned bypass capacitor. the if mixer output can be made single-ended by connecting the unused mixer output to the supply rail. extra care should be taken to characterize single-ended first if applications. using a single-ended second if filter in combination with a balanced first if filter may help reject common mode signals not rejected by the first if filter. however, it should be noted that the differential tank capacitors of the fully differential if filters can be replaced by common mode capacitors by doubling the differential value and connecting two of these capacitors to ground. any distribution between these two extremes is also acceptable.
1999 may 10 29 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL as with the rf mixer maintaining the same single-ended load as an effective differential load would result in the same voltage applied to the equivalent resistance. however, a single-ended effective load of 1.6 k w could also bring this mixer output to its clipping point. the maximum recommended second mixer single-sided voltage conversion gain (one input to one output) is therefore approximately 16 for both single-ended and differential output applications. the estimated single-side band (ssb) noise figure of the if mixer is approximately 7.5 db at t amb =27 c from a 3 v supply with an input termination matching resistor of 2k w . removing the termination results in an expected noise figure of 4.9 db from a 1 k w source. this degradation is distributed between the input termination input loss and approximately a 1.6 db increase in the actual mixer noise figure. the conversion gain is expected to be relatively supply independent, increasing by only approximately 0.5 db from a supply value of 2.7 to 5.5 v. the if mixer rf bandwidth is also expected to only increase by approximately 4%, while the mixer noise figure is expected to decrease by less than 0.1 db as the supply is increased over the same supply range. the if mixer rf bandwidth, if not resonated, is dominated by the mixer differential input capacitance of approximately 1 pf. with tuned inputs, the if mixer rf input bandwidth can be extended quite high, but practical consideration warrant that the rf filter terminating the input should provide band limiting, thereby restricting the rf high frequency roll-off to less than 200 mhz without special characterization efforts. this is also, generally, the upper limit that the programmable synthesizer supports. the noise figure of the if mixer as well as the limiter can be expected to degrade as the operating frequencies are increased. for example, at 200 mhz in a terminated 100 w system the dsb noise figure of the if mixer will increase by at least 10 db to approximately 18 db. if stability permits low impedance first if filters can be matched into the if mixer using step-up matching circuits such as baluns or transformer like tuned networks, to minimize the degradations. the input compression point and noise figure of the if mixer, as measured in the characterization test board, are plotted against temperature and supply voltage in figs 19 and 20. the characterization test board employs the 1 : 16 w ratio transformers to provide a 50 w match to the 800 w test environment. the losses of the input and output transformers, as well as transformer insertion losses at 41.82 and 3.48 mhz, have been removed before plotting. therefore, this graph correlates to specification and expected performance of the second mixer in the referenced 800 w environment. fig.19 if mixer - 1 db input compression point (800 w test circuit). (1) t amb = - 40 c. (2) t amb = +25 c. (3) t amb = +85 c. handbook, halfpage 2345 - 24 - 30 mhb282 - 26 - 28 cp - 1db (dbm) v cc (v) (2) (3) (1)
1999 may 10 30 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.20 if mixer dsb noise figure (800 w test circuit). (1) t amb = - 40 c. (2) t amb = +25 c. (3) t amb = +85 c. handbook, halfpage 2345 6 3 mhb283 5 4 f dsb (db) v cc (v) (2) (3) (1) fig.21 typical second mixer fundamental, 2nd and 3rd-order product output levels as a function of input level (800 w environment). (1) fundamental output. (2) 3rd-order product output. (3) 2nd-order product output. handbook, halfpage - 90 - 70 - 50 - 10 20 - 100 - 20 0 mhb284 - 30 - 40 - 60 - 80 output (dbm) input (dbm) (2) (3) (1)
1999 may 10 31 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.7 second if ?lter the second if filter provides five functions: 1. it provides selectivity to protect the limiter input from spurious signals which pass through the first if band-pass filter envelope, typically 5 mhz wide. 2. the filter attenuates undesired second mixer output products, such as the lo leak, to levels which will not block/capture the following limiter stage. 3. the filter defines and shapes the noise bandwidth to be amplitude quantized. 4. it can provide impedance matching/transformation from the if mixer output to the limiter input while maintaining stability. 5. it can reject spurious common mode and/or differential signals generated by high level local sources such as harmonics of the reference clock or sample clock and digital processing noise from associated devices such as the saa1575hl. the second if can be structured to support a wide range of single-ended or balanced filters including lc or ceramic realizations. the available system gain can provide second if signal levels sufficient to accommodate high second if filter losses. the philips application board again uses a 6th-order coupled resonator filter based on the butterworth response. the design method is described in the handbook of filter synthesis by anatol zverev. initially a skewed centre frequency and bandwidth were input at 3.1 and 1.75 mhz, respectively, to help overcome the asymmetry which is intrinsic in geometric low frequency band-pass filter designs as they approach dc. the following table design 3 db down k and q parameters were used: r s = 548 w r l = 996 w q 0 = 20.0; insertion loss = 0.958; q 1 = 0.8041; q n = 1.4156; k 12 = 0.7687; k 23 = 0.6582. this filter was originally mirrored by a virtual ground to convert it to a balanced form, but later the balanced components were converted back to a single-ended form (to reduce component count) simply by placing the balanced series capacitors in series on one side of the filter (effectively halving the capacitance value) and grounding the opposite side of the tanks where these series capacitors were removed. this effectively maintains the differential power gain while only using a single-sided output. the filter was then resimulated in pspice to optimize against available discrete surface mount component values. finally the filters input and output direction were reversed to ensure that the highest impedance side was placed at the mixer output to maximize the available power developed. a 909 w termination was used at the output of the filter to terminate the 4.87 k w limiter input. this effective 766 w termination is somewhat lower than the initial design value of 2 548 w or 1096 w and therefore develops approximately - 1.56 db less power with respect to second mixer loading. the reduction of the impedance level by 30% (or a factor of 0.7) was done in order to have a large safety margin against instability of the limiter/quantizer path. instability can be caused here by the large small-signal gain associated with this signal path in conjunction with the high signal levels present at the sign output. furthermore, due to the strong non-linearities present in this signal path, lo2 leakage in conjunction with the if2 itself can produce signals at the if1 frequency and thus enter the if1 filter together with the wanted signal. this impedance level reduction is passed through the second if filter and consequently lowers the mixer 2 conversion gain by approximately 30%, too. the filter design was determined to be sufficiently tolerant to this adjustment by observing the effect on the filters output noise response with respect to unstable peaking and maintaining the desired selectivity response. care must be taken not to induce instability while observing the if2 filter noise response by using a 10 : 1 divider in conjunction with a very low capacitance rf fet probe (<0.5 pf). in the default application, r323/305 in conjunction with the equivalent parallel resistance at the respective filter input and output give the desired terminating impedance. the frequency of the mixed down third harmonic of the reference oscillator is usually the most significant spurious product which is generated in the default frequency plan and must be kept at least 13 db below the integrated noise response of the filter. for example, typical true power noise densities (dn) for a nominal gps demonstration board operating at 3 v are expected to be approximately - 100 dbm/hz differential at the input of the limiter and reflect the importance of designing a well matched rf system. assuming that a somewhat lower gain variation has been realized with a noise density of approximately - 105 dbm/hz over an estimated 2 mhz noise equivalent bandwidth, it is possible to evaluate and measure the associated spurious product level that would result in a - 13 db jammer-to-noise (j/n) and 0.2 db system noise figure degradations as follows:
1999 may 10 32 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL the true power of a product at the output of the second if filter in a 1 k w environment should be no more than - 105 dbm/hz + 63 db - 13 db or approximately - 55 dbm. the equivalent single-sided measurement with a 50 w calibrated probe would be or - 44.6 dbm. figure 22 illustrates the true noise power density as measured points for this lower gain case. the filter response of the first if filter is translated to the second if and superimposed at the second if to show that the 3rd harmonic reference spur at 43.2 mhz, is not filtered by this response. 55 dbm C 10 log 548 50 --------- - + also shown is the second if filter response and the combined first and second if filter selectivities, which account for total observed selectivity noise response. for difficult applications which require higher losses in the if filters, self jamming can be minimized by choosing a reference and frequency plan which places the harmonics of the reference exactly at the second lo frequency, where they are benign. fig.22 second if filter output noise density frequency response on the application board. (1) if1 filter response superimposed on if2 filter response. (2) if2 filter response (calculated). (3) if2 filter noise density (measured). (4) if1 filter response translated to if2 frequency. handbook, halfpage 048 16 n d (dbm/hz) f (mhz) - 90 - 130 - 150 - 110 mhb285 12 (2) (3) (4) (1) 3.48 x 10 6 /sec 4.86 x 10 6 /sec
1999 may 10 33 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.8 time and amplitude quantization after frequency conversion in the double-superheterodyne portion of the UAA1570HL and filtering to approximately a 2 mhz bandwidth in the second and final if filter, the frequency translated thermal noise from the gps pass-band around the l1 carrier is ready to be converted to a digital signal for processing by the companion gps chip-set part (saa1575hl). first the thermal noises sign is determined by amplitude quantization in a 1-bit hard limiter. this asynchronous information is then time quantized by latching in a master/slave d-flip-flop to complete the analog-to-digital conversion process. finally, this ecl digital sign bit data is translated to ttl levels and sent to the saa1575hl. four differential stages are used to hard limit the thermal noise in the final if. the total gain is approximately 63.9 dbv with a bandwidth of roughly 66 mhz and a noise figure of approximately 11.3 db in a 1 k w environment. the parallel equivalent differential input impedance of the limiter is 4.87 k w in parallel with 0.3 pf. offset control is provided through 42.5 k w feedback resistors from each balanced output back to the inputs. external decoupling capacitors cut the feedback loop for ac signals. limiter inputs as low as 25 m v (peak value differential) are resolved at the output master flip-flop dff1 in its transparent mode. as the master flip-flop is latched positive feedback resolves metastable states. while the master flip-flop is in its transparent state the positive feedback in the slave flip-flop will resolve the remaining metastable states as it is latched. three forms of lo leakage can block the limiter if they capture the device. the first is lo leakage from the first mixer output which will couple into the package die pad through internal 4 pf common mode capacitors at the output of the 1st mixer. this leakage signal is effectively filtered at the 2nd if filter output, but reappears internally on all down-bonded grounds. it appears at a level of approximately 0.5 mv (peak value differential) across the limiter input transistor bases with an assumed 1st mixer input rf offset of approximately 1 mv. the second is lo leakage from the second mixer. assuming 1.5 mv rf input offset, the leakage at the output of the second if filter is expected to be approximately 500 m v (peak value differential) ( - 69 dbm into 1 k w ) and sets the worst case nominal process blocking level. with a nominal - 50 dbm if thermal level at this point there is a 19 db margin to blocking. to prevent blocking, if filter losses should be minimized and the selectivity of the single-ended or differential second if filter has to be designed and characterized to maintain this leakage product at least 11 db below the integrated second if filter thermal noise signal. the third form of blocking can occur if lo1 leakage is sufficiently high (greater than 15 mv (peak value) on the die pad) to be injected into the 2nd mixer regulators and all down-bonded if grounds. this results in burst of lo1 leakage at the 2nd mixer lo2 zero transition points which increase lo2 leakage peaks by factors of 10. the gain response of the limiter from a low impedance source with no input strays is illustrated from the input to the output of each stage in fig.23.
1999 may 10 34 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.23 limiter input, 1st, 2nd and 3rd stage gain response as a function of frequency (simulated). (1) limiter input. (2) 1st stage gain response. (3) 2nd stage gain response. (4) 3rd stage gain response. handbook, full pagewidth 80 - 160 0 - 80 mhb286 10 - 2 10 - 1 11010 2 10 3 10 4 g (db) f (mhz) (2) (3) (4) (1)
1999 may 10 35 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.24 limiter differential input resistance as a function of frequency (simulated). (1) t amb = - 55 c. (2) t amb = +27 c. (3) t amb = +120 c. handbook, full pagewidth 8 2 0 6 4 mhb287 r i(diff) (k w ) 10 - 2 10 - 1 11010 2 10 3 10 4 f (mhz) (2) (3) (1) 7.8.1 c lock inputs both the reference and the sample clock input can be driven by a temperature compensated crystal oscillator (tcxo). typical tcxos produce 0.5 to 1.0 v (p-p) clipped sine wave outputs. the drive capability is typically 20 k w in parallel with 5 pf or 10 k w in parallel with 10 pf. some tcxos are even capable of driving loads as low as 1 k w without buffering. alternatively, cost can be reduced by designing a simple discrete crystal oscillator reference, paying careful attention to temperature tolerance ( 6 ppm) as well as shock and vibration characteristics. both UAA1570HL clock inputs, the synthesizer reference input refin (pin 8), and the sample clock input sclk (pin 37), accept low level inputs and provide internal gain/squaring circuits. the reference clock input has a high impedance with 20 k w in parallel with 0.07 pf. a high stability, low phase noise crystal reference source should be ac-coupled to this port. reference inputs up to 35 mhz and levels between 50 to 500 mv (peak value) are acceptable. this source can be externally squared and attenuated before being applied. direct sinusoidal inputs should be as large as possible within the prescribed range to optimize phase noise performance. the sample clock input also features a high impedance of 23.3 k w . the sample clock input can be ac-coupled directly to the reference if the system sampling objectives are met. alternatively, the tcxo/xo reference can be externally squared to cmos input levels and applied to the saa1575hl rclk input (pin 98) and divided under firmware control to produce a signal commensurate with the sampling objective. due to the wide range of programmable frequency plans and sampling rates supported by the UAA1570HL, it is not possible to predict the frequencies and levels of the associated spurious products that will be generated. one significant source of potential spurs are the harmonics of the reference and sampling signals. the availability of on-chip squaring circuits provide some freedom to minimize large digital signal effects in sensitive rf circuit areas. in most cases digital sampling signal levels are acceptable as long as careful attention is paid to avoid injecting these signals or their harmonics into the pass bands of the if filters.
1999 may 10 36 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL the sclk input of the UAA1570HL is self-biased at 50% of the analog supply voltage (v cca ) near the internal threshold level. it is therefore possible to operate this input with levels as low as 10 mv (peak value) in order to avoid large digital signal flow on the printed-circuit board (pcb) runners. this is done in the default application with a 6.8 and 3.9 k w resistive divider followed by a 10 pf ac coupling series capacitor in between the saa1575hl and the UAA1570HL. however, when it is nevertheless intended to use full cmos or ttl levels, some attenuation is required so that the peak sample clock input does not exceed 75% of the UAA1570HL analog supply voltage. this is especially important while the UAA1570HL is operating from a lower supply (3 v) than the saa1575hl (5 v). a resistive divider can help in these cases, but the ac coupling method described above should be preferred. 7.8.2 cmos to ecl sample clock squaring circuit the UAA1570HL internal sample clock squaring circuit allows single-ended sinusoidal clock inputs as low as 10 mv (peak value) over a frequency range from 5 to 35 mhz. the rise time of the clock output should be in the order of 25% of the maximum sampling frequency to ensure that aperture losses are less than approximately 1 db (0.91 db). the period of a 35 mhz clock is 28.57 ns. to keep the sampling aperture on the order of one fourth this period implies a rise time of 5.7 ns is required and should also be kept with lower sampling clock rates. using a 14.4 mhz sampling rate test signal into the sclk input results in good ttl eye pattern characteristics over a measured input range down to at least - 25 dbm. at - 35 dbm the effects of slew rate limiting begin to appear with the eye pattern closing beyond - 40 dbm. 7.8.3 t ime quantization ( sampler ) two clocked d flip-flops are connected in a master/slave configuration to implement the sampling function of the 1-bit sampler. with the internal dff clock (clk) low the master flip-flop dff1 is in its transparent mode and continuously follows the amplitude quantized limiter output. as the clock (clk) goes high the data is latched in the master flip-flop and the slave dff2 becomes transparent to the latched output from the master flip-flop. the falling edge of the clk signal latches the slave and again loads the limiter output into the master flip-flop. these stages also provide additional limiting gain for marginal input signals from the limiter. 28.57 ns 41.25 ---------------------- - ? ?? since the ttl/cmos output stage is transparent the sign bit output is updated on the rising edge of the clk with the master latched and the slave transparent. this implies the dsp can expect sign bit data to be latched on the low clk state. 7.8.4 ttl output stage the ttl output stage is a variation of a totem pole modified to operate from an independent isolated supply voltage from 2.7 to 5.5 v. this supply voltage is also independent of other supply voltages used in the UAA1570HL. circuits to minimize cross-conductance and short-circuit currents are provided. operating from a 2.7 v supply, v ol and v oh are nominally 132 mv and 1.95 v, respectively. operating from a 5.5 v supply, v ol and v oh are nominally 195 mv and 4.6 v, respectively. typical rise times of 8 ns and fall times of 10 ns can be expected from this output driving cmos loads. 7.8.5 1- bit delays the rise and fall times of the ttl output with a 15 pf load are approximately 8 ns and are relatively independent of supply and temperature. a small decrease (1 to 2 ns) in rise and fall times is seen at t amb = - 55 c and a small increase at t amb = 120 c (2 to 4 ns). typical propagation delay times through the time quantization circuitry while switching amplitude quantization states from a 5.5 v supply are: sclk input to ttl sign output 16 ns (rising edge) sclk input to ttl sign output 17.6 ns (falling edge). 7.9 programmable synthesizer the UAA1570HL includes a programmable synthesizer allowing the main, second lo and reference dividers to be programmed under external control via a three-wire serial control bus. alternatively, a low on the strobe input on power-up will load a 20-bit default frequency plan word and power-on options into the synthesizer registers. frequency plans with a 2nd if of 4 f 0 (1.023 mhz) = 4.092 mhz can be implemented. 7.9.1 vco prescaler after the vco signal leaves its single-ended-to-balanced cascode buffer it is again amplified on its way to a high speed fixed divide-by-2 prescaler using a super buffer such as that described for the first mixer (see section 7.3).
1999 may 10 37 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 7.9.2 m ain synthesizer dividers (n- path ) the main synthesizer divider path includes an additional fixed divide-by-3 prescaler preceding a programmable variable n-divider which can be programmed over a range from 64 to 127. the output of the programmable divider passes through a fixed divide-by-2 and finally an optional divide-by-1 or divide-by-2 before being applied to the phase frequency detector. 7.9.3 s econd local oscillator dividers (l- path ) the second lo signal is divided down from the vco prescaler output, first by a programmable l-divider and then by a fixed divide-by-2 before being buffered and applied to the second mixer. 7.9.4 r eference dividers (r- path ) after squaring (limiting), the reference signal is divided down first by a variable r-divider. the divide ratio ranges from 4 to 31. the variable divider is followed by an optional divide-by-1 or divide-by-2 before being applied to the phase/frequency detector. 7.10 serial interface the three-wire serial bus consists of dc-coupled data, clock and strobe cmos level inputs. the data input loads serial 20-bit programming words into the synthesizer data input register on each rising edge of the clock input, while the strobe line is held low. the clock signal should be set-up high for at least 30 ns before the strobe state is changed. each data bit should be set-up for at least 30 ns before being clocked into the register and then held for at least 30 ns. the clock rate should not exceed 10 mhz and the clock pulse width should be at least 30 ns. the 20-bit data word definition follows in the order in which they are to be read (clocked) into the data register. 7.10.1 p0 and p1 the first bit read into the synthesizer should be the power-down bit, p1, which enables one of two power-down states if set high. the second bit read into the register, p0, defines the type of power-down. a complete power-down of the UAA1570HL is performed if this bit is set high and a partial power-down with the synthesizer remaining on if this bit is set low. for normal operation of the UAA1570HL both of these bits are set low, which are also the default values for p0,p1 = 0,0. the final p0,p1 = 1,0 state is undefined. 7.10.2 r5 next a post reference scaler bit, r5, is set to program a divide-by-1 or divide-by-2 following the variable reference divider. with this bit set low the divide-by-2 post scaler is enabled and the phase frequency detector receives equal mark/space ratio reference port signals. this is the default state for this bit (r5 = 0). in the high state the mark/space ratio is a function of the variable reference divider value, and the range of the reference divider is extended to lower division ratios. 7.10.3 r0, r1, r2, r3 and r4 the next five bits clocked into the data register are the binary equivalent value of the variable reference divider ratio. the programmable range of this divider is 4to31 , continuous . the default value is set to 4 (r0, r1, r2, r3, r4 = 0, 0, 1, 0, 0) with the most significant bit (msb) clocked into the data register first. the total reference division ratio is set by these five bits if r5 is set to the high state. the range can be optionally doubled to even values from 8 to 62 if r5 is set low. this option is set in the default case, resulting in equal mark/space ratios as described above. the total default reference division ratio is therefore 8 with (r0, r1, r2, r3, r4, r5 = 0, 0, 1, 0, 0, 0). 7.10.4 n7 as in the reference divider case the main synthesizer divider includes an optional post scaler divider following the main programmable divider. this divide-by-1 or divide-by-2 is controlled by program word bit n7. with this bit set low the divide-by-2 post scaler is enabled and the phase frequency detector receives equal mark/space ratio signals at its main synthesizer port. the default state for this bit is (n7 = 1) which does not double the total main synthesizer divide ratio as described below. 7.10.5 n0, n1, n2, n3, n4, n5 and n6 the next seven bits clocked into the data register are the binary equivalent value of the variable main synthesizer divider ratio. the programmable range of this divider is 64 to 127 , continuous . the default value is set to 71 (n0, n1, n2, n3, n4, n5, n6 = 1, 1, 1, 0, 0, 0, 1) with the msb clocked into the data register first. the output of the main programmable divider includes a fixed divide-by-2 which modifies the previous range to all even values from 128 to 254 , inclusive. the programmable portion of the main synthesizer division ratio is set by these seven bits if n7 is set to the high state as described above for the default case.
1999 may 10 38 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL this ratio can again be optionally doubled by setting n7 low . the range is then extended to values from 256 to 508 , inclusive, in increments of 4 . equal mark/space-ratio signals are always fed to the main synthesizer port of the phase frequency detector since the fixed divide-by-2 post scaler is always present. the main synthesizer path divisions ratio range, including the fixed divide-by-2 and divide-by-3 prescalers, is increased by a factor of 6 from 768 to 1524 in increments of 12 when n7 is set high or from 1536 to 3048 in increments of 24 if n7 is set low . the total default main synthesizer path division ratio from the vco is 12 71 or 852 with (n0, n1, n2, n3, n4, n5, n6, n7 = 1, 1, 1, 0, 0, 0, 1, 1). 7.10.6 l0, l1, l2 and l3 the last four bits clocked into the data register set the programmable division ratio for the 2nd local oscillator. again the msb is read in first with the binary word set to a number between 4 and 15. the default values are set to 10 (l0, l1, l2, l3 = 0, 1, 0, 1). again a post scaler is provided with a fixed divide-by-2 value to ensure that the lo signal exhibits equal mark/space ratios driving the second mixer. the programmable divider and fixed post scaler provide division between 8 and 30 in even increments. since the 2nd local oscillator path from the vco includes the divide-by-2 prescaler common to both the l-divider and n-divider paths, the total programmable 2nd local oscillator division range, relative to the vco, is 16 to 60 in increments of 4. with the 20-bit programming word completely clocked into the data register the strobe signal is returned to a high state after a minimum delay of 30 ns to latch and effect the parallel loading of the programmed word states. 7.11 the serial interface word the complete default program word once serially loaded or loaded by default on power-up with the strobe held low realizes the following frequency plan in the UAA1570HL. it should be noted that the msb for the complete 20-bit program word is l0 and the least significant bit (lsb) is p1 with the latter the first loaded into the data register. this is in contrast to the sequence in which the different bits determining the individual divider ratios are structured. the resulting default 20-bit word is: l0, l1, l2, l3, n0, n1, n2, n3, n4, n5, n6, n7, r0, r1, r2, r3, r4, r5, p0, p1 = 0, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0. 7.12 the default frequency plan the default synthesizer programming produces the following frequency plan: table 2 frequency plan 7.13 phase detector, charge pump and loop ?lter the phase detector is of a phase and frequency sensitive digital type. in conjunction with the charge pump, it operates without a dead zone. the charge pump itself has a single-ended output delivering or sinking current pulses with a maximum amplitude of 240 m a into the external loop filter. the layout for the connection between the loop filter and the vco input should be made with utmost care in order to avoid other signals entering this path. the loop filter as chosen on the demonstration board yields a loop bandwidth of approximately 100 khz, with a damping constant of 1. it consists of a 3.9 nf capacitor and a series resistor of 20 k w , both in parallel with a 150 pf capacitor. parameter value rf input frequency 1.57542 ghz vco frequency 1.5336 ghz rf image frequency 1.49178 ghz first if frequency 41.82 mhz second lo division ratio 2 10 2=40 second lo frequency 38.34 mhz second image frequency 34.86 hz second if frequency 3.48 mhz reference frequency 14.4 mhz total main synthesizer division ratio 2 3 71 2 = 852 total reference division ratio 2 4=8 phase comparison frequency 1.8 mhz
1999 may 10 39 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 8 operating mode selection tables table 3 programmable operating modes 8.1 manual selection operating modes some applications of the UAA1570HL may require the use of an external lna. since lna1 is self contained and includes independent bias circuitry, it can be powered down simply by not connecting the respective supply pin or tying it to ground. some considerations apply to optimize performance when using an external lna. generally the UAA1570HL has been optimized with approximately 15 db of gain in the first lna. to prevent degradation of the system noise figure or dynamic range in subsequent system functions, such as the first mixer or synthesizer, some limitations on the nominal effective gain and noise figure of external devices should be taken into account. the following values are not specified, since exceeding the recommended ranges may still result in adequate dynamic performance in some 1-bit gps system applications. note : lna2 has to be powered-up under all circumstances, i.e. its supply pin has to be connected to v cc under all circumstances due to biasing constraints. table 4 operation with external lnas notes 1. the maximum external noise figure listed is that which will produce approximately a 1 db degradation in system noise figure using the minimum recommended external gain. the maximum recommended external gain listed results in approximately 1 db compression in the second mixer input with an in-band continuous wave jammer present (j/s = 35 db) for nominal processed parts. 2. if a high gain external lna is used, both lna1 and lna2 should be removed from the signal path. however, the lna2 supply pin has to be connected to v cc to retain power to the first mixer. mode p0 p1 lna1 lna2 vco mx1, mx2, 1-bit 2nd lo dpll normal 0 0 yes yes yes yes yes yes partial power-down 0 1 no no yes no no yes unde?ned 1 0 ------ complete power-down 1 1 no no no no no no mode v cc(lna1) v cc(lna2) maximum recommended external gain including cable and filter losses minimum recommended external gain including cable and filter losses maximum recommended external noise figure including cable and filter losses internal current reduction normal yes yes 10 db - 3.5 db 3.5 db - lna1 replacement; note 1 no yes 25 db 8 db 4 db 6.5 ma lna1/lna2 replacement; notes 1 and 2 no yes 41 db 21 db 4 db 6.5 ma
1999 may 10 40 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 9 limiting values in accordance with the absolute maximum rating system (iec 134). all ground pins are tied together. note 1. human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. 10 thermal characteristics 11 dc characteristics t amb =25 2 c; test circuit see fig.25; unless otherwise speci?ed. symbol parameter conditions min. max. unit v max maximum voltage at any pin with respect to ground - 0.5 v cc + 0.5 v v cca analog supply voltage - 0.5 +5.5 v v ddd digital supply voltage - 0.5 +5.5 v t stg storage temperature - 65 +150 c t j junction temperature - 150 c t amb operating ambient temperature v cca =v ddd =5v - 40 +85 c v es electrostatic handling note 1 - 2000 +2000 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 74 k/w symbol parameter conditions min. typ. max. unit supplies i cca(lna1) lna1 analog supply current v cca = 2.7 v 4.27 6.4 8.23 ma v cca = 3 v 4.79 6.54 8.04 ma v cca = 5 v 5.3 7.15 8.73 ma i cca(lna2) lna2 analog supply current v cca = 2.7 v 5 7.1 8.9 ma v cca = 3 v 5.22 7.26 9.01 ma v cca = 5 v 5.68 7.92 9.83 ma i cca(vco) vco analog supply current v cca = 2.7 v 2.85 3.74 4.64 ma v cca = 3 v 2.86 3.77 4.69 ma v cca = 5 v 2.89 3.82 4.76 ma i bias(mx1) mx1 bias current v cca = 2.7 v 5.18 7.49 9.03 ma v cca = 3 v 5.36 7.63 9.13 ma v cca = 5 v 5.61 8.02 9.63 ma i o(mx1) mx1 output current (pins 17 and 18) v cca = 2.7 v 3.84 4.97 5.77 ma v cca = 3 v 3.89 5.06 5.9 ma v cca = 5 v 4.06 5.39 6.33 ma i bias(mx2) mx2 bias current v cca = 2.7 v 1.67 2.36 2.88 ma v cca = 3 v 1.69 2.39 2.92 ma v cca = 5 v 1.71 2.44 2.98 ma
1999 may 10 41 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL i o(mx2) mx2 output current (pins 24 and 25) v cca = 2.7 v 2.41 3.73 4.56 ma v cca = 3 v 2.46 3.79 4.62 ma v cca = 5 v 2.53 3.93 4.81 ma i cca(lim) lim analog supply current v cca = 2.7 v 0.9 1.31 1.53 ma v cca = 3 v 0.97 1.41 1.65 ma v cca = 5 v 1.39 2 2.34 ma i cca(pll) pll analog supply current v cca = 2.7 v 11.45 14.3 16.07 ma v cca = 3 v 11.67 14.98 17.06 ma v cca = 5 v 12.2 15.85 18.13 ma i dddl low ttl digital current 5 k w dc load; v ddd = 2.7 v 2.9 3.75 4.6 ma 5k w dc load; v ddd = 3 v 3.02 3.9 4.77 ma 5k w dc load; v ddd = 5 v 3.49 4.58 5.94 ma i dddh high ttl digital current 5 k w dc load; v ddd = 2.7 v 0.13 0.44 0.65 ma 5k w dc load; v ddd = 3 v 0.2 0.5 0.7 ma 5k w dc load; v ddd = 5 v 0.47 0.88 1.15 ma i tot(wake) total current (wake state) v cca =v ddd = 2.7 v 46.36 55.1 62.3 ma v cca =v ddd = 3 v 47.54 56.66 64.26 ma v cca =v ddd = 5 v 51.04 61.02 69.33 ma i tot(sleep) total current (sleep state) v cca =v ddd = 2.7 v - 116.2 223.5 m a v cca =v ddd =3v - 182.7 323.2 m a v cca =v ddd =5v - 648.4 900.9 m a i tot(synth) total current (synthesizer state) v cca =v ddd = 2.7 v 14.36 18.08 20.4 ma v cca =v ddd = 3 v 14.98 19.02 21.54 ma v cca =v ddd = 5 v 15.72 20.37 23.27 ma lna1 and lna2 v lnain dc operating point lna1in and lna2in (pins 45 and 3) v cca =v ddd = 2.7 v 781 815 856 mv v cca =v ddd = 3 v 784 811 843 mv v cca =v ddd = 5 v 780 807 839 mv v lnaout dc operating point lna1out and lna2out (pins 48 and 6) v cca =v ddd = 2.7 v 1.02 1.48 1.71 v v cca =v ddd = 3 v 1.284 1.75 1.983 v v cca =v ddd = 5 v 3.115 3.629 3.886 v reference input; pin 8 v refin dc operating point refin v cca = 2.7 v 1.56 1.69 1.87 v v cca = 3 v 1.87 1.99 2.15 v v cca = 5 v 3.84 3.99 4.19 v symbol parameter conditions min. typ. max. unit
1999 may 10 42 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL vco; pin 10 v tank dc operating point tank v cca = 2.7 v 1.825 1.918 2.01 v v cca = 3 v 1.822 1.916 2.011 v v cca = 5 v 1.818 1.918 2.018 v mixer 1; pin 14 v mx1in dc operating point mx1in v cca = 2.7 v 800 818 846 mv v cca = 3 v 797 814 839 mv v cca = 5 v 792 810 837 mv mixer 2; pins 21 and 22 v if2in dc operating point if2inn and if2inp v cca = 2.7 v 939 983 1011 mv v cca = 3 v 937 981 1009 mv v cca = 5 v 936 980 1008 mv limiter v bfc dc operating point bfcn and bfcp (pins 27 and 30) v cca = 2.7 v 1.276 1.696 1.831 v v cca = 3 v 1.578 1.998 2.133 v v cca = 5 v 3.579 3.999 4.134 v v limin dc operating point liminn and liminp (pins 28 and 29) v cca = 2.7 v 1.276 1.696 1.831 v v cca = 3 v 1.578 1.998 2.133 v v cca = 5 v 3.579 3.999 4.134 v sign bit output (ttl); pin 34 v ol(sign) low-level dc operating point output sign 5k w dc load; v cca = 2.7 v 45 130.6 160.8 mv 5k w dc load; v cca = 3 v 42 127 157 mv 5k w dc load; v cca =5v - 71.8 - mv v oh(sign) high-level dc operating point output sign 5k w dc load; v cca = 2.7 v 1.589 1.876 1.956 v 5k w dc load; v cca = 3 v 1.794 2.168 2.273 v 5k w dc load; v cca = 5 v 3.566 4.1 4.251 v sclk input (cmos to ecl); pin 37 v th(sclk) dc operating point sclk threshold [0.5 v cca(lim) (pin 31)] v cca =v ddd = 2.7 v 1.329 1.341 1.353 v v cca =v ddd = 3 v 1.479 1.491 1.503 v v cca =v ddd = 5 v 2.478 2.499 2.519 v comp; pin 40 v o(comp) charge pump output voltage swing v cca = 2.7 v 0.2 - 2.1 v v cca =3v 0.2 - 2.4 v v cca =5v 0.2 - 4.4 v i cp(max) maximum current sinked or sourced by the charge pump v cca = 2.7 v - 240 -m a v cca =3v - 240 -m a v cca =5v - 240 -m a symbol parameter conditions min. typ. max. unit
1999 may 10 43 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 12 ac characteristics t amb =25 2 c; default frequency plan; test circuit see fig.25; unless otherwise speci?ed. s-parameters given below (s11, s22 and s12) are design goals which should be achieved in order to reach the other given values. they are depending on application. symbol parameter conditions min. typ. max. unit system performance f rx receiver noise ?gure (lna1 input to sign bit output) f = 1.57542 ghz; v cca = 3 v; note 1 3.8 4.5 5.2 db s sensitivity - 3 db; note 2 - 103 - 106 - 109 dbm lna 1; note 3 s21 lna1 power gain 50 w matched input and output v cca = 2.7 v 12.3 15.4 18.1 db v cca = 3 v 12.4 15.7 18.5 db v cca = 5 v 12.9 16.6 19.7 db s11 lna1 input re?ection coef?cient 50 w matched input and output v cca = 2.7 v -- 18 - 16.3 db v cca =3v -- 18 - 16.2 db v cca =5v -- 18 - 16.2 db s12 lna1 reverse isolation 50 w matched input and output v cca = 2.7 v -- 38.9 - 29.9 db v cca =3v -- 38 - 29 db v cca =5v -- 35.6 - 26.6 db s22 lna1 output re?ection coef?cient 50 w matched input and output v cca = 2.7 v -- 21.2 - 12.7 db v cca =3v -- 18 - 13.4 db v cca =5v -- 10.8 - 8.7 db ip3 lna1 3rd-order input intercept point 50 w matched input and output v cca = 2.7 v - 17 - 13.4 - dbm v cca =3v - 16.8 - 13.2 - dbm v cca =5v - 16.6 - 12.6 - dbm ip2 lna1 2nd-order input intercept point 50 w matched input and output v cca = 2.7 v - 7.7 - dbm v cca =3v - 7.9 - dbm v cca =5v - 8.6 - dbm
1999 may 10 44 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL cp - 1db(lna1) - 1 db input compression point 50 w matched input and output v cca = 2.7 v - 26.6 - 22.2 - dbm v cca =3v - 26.6 - 22.2 - dbm v cca =5v - 28.2 - 22 - dbm f lna1 noise ?gure lna1 50 w matched input and output v cca = 2.7 v - 3.6 4.7 db v cca =3v - 3.6 4.3 db v cca =5v - 3.6 4.2 db lna 2; note 3 s21 lna2 power gain 50 w matched input and output v cca = 2.7 v 11.4 14.8 18.2 db v cca = 3 v 12.1 15.3 18.5 db v cca = 5 v 11.6 15.9 20.3 db s11 lna2 input re?ection coef?cient 50 w matched input and output v cca = 2.7 v -- 18.5 - 14.2 db v cca =3v -- 18 - 13.5 db v cca =5v -- 17.1 - 12.6 db s12 lna2 reverse isolation 50 w matched input and output v cca = 2.7 v -- 35.8 - 26.8 db v cca =3v -- 34.9 - 25.9 db v cca =5v -- 32.5 - 23.5 db s22 lna2 output re?ection coef?cient 50 w matched input and output v cca = 2.7 v -- 18.4 - 14.9 db v cca =3v -- 18 - 15 db v cca =5v -- 15.7 - 14.1 db ip3 lna2 3rd-order input intercept point 50 w matched input and output v cca = 2.7 v - 28.6 - 13.5 - dbm v cca =3v - 16.9 - 12.8 - dbm v cca =5v - 16.3 - 12 - dbm ip2 lna2 2nd-order input intercept point 50 w matched input and output v cca = 2.7 v - 7.7 - dbm v cca =3v - 7.9 - dbm v cca =5v - 8.6 - dbm symbol parameter conditions min. typ. max. unit
1999 may 10 45 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL cp - 1db(lna2) - 1 db input compression point 50 w matched input and output v cca = 2.7 v - 28.1 - 22.4 - dbm v cca =3v - 27.1 - 22.6 - dbm v cca =5v - 26.6 - 22.2 - dbm f lna2 noise ?gure lna2 50 w matched input and output v cca = 2.7 v - 3.7 4.4 db v cca =3v - 3.7 4.3 db v cca =5v - 3.8 6.3 db mixer 1 y21 mx1 conversion transconductance 50 w matched input and 800 w matched output; note 4 v cca = 2.7 v 0.032 0.0513 0.0813 a/v v cca = 3 v 0.0334 0.0531 0.0837 a/v v cca = 5 v 0.0403 0.0593 0.0889 a/v g conv(v) voltage conversion gain 50 w matched input and output; note 5 v cca = 2.7 v 23.9 27.1 32.1 dbv v cca = 3 v 24.3 27.5 32.4 dbv v cca = 5 v 25.7 28.4 32.7 dbv g conv(p) power conversion gain 50 w matched input and 800 w matched output; note 6 v cca = 2.7 v 14.5 17.7 22.6 db v cca = 3 v 14.8 18 22.9 db v cca = 5 v 16.2 18.9 23.2 db s11 mx1 input re?ection coef?cient 50 w matched input and 800 w matched output v cca = 2.7 v -- 17.8 - 15.9 db v cca =3v -- 18 - 16.2 db v cca =5v -- 18.9 - 16.6 db cp - 1db(mx1) - 1 db input compression point 50 w matched input and 800 w matched output; note 6 v cca = 2.7 v - 29.7 - 25.4 - dbm v cca =3v - 31.2 - 25.4 - dbm v cca =5v - 31 - 25.4 - dbm symbol parameter conditions min. typ. max. unit
1999 may 10 46 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL f dsb(mx1) double-side band noise ?gure mx1 50 w matched input and 800 w matched output; note 6 v cca = 2.7 v - 12.8 16.8 db v cca =3v - 12 15.8 db v cca =5v - 10 12.7 db mixer 2 y21 mx2 conversion transconductance 800 w matched input and output; note 7 v cca = 2.7 v 0.0252 0.0293 0.0344 a/v v cca = 3 v 0.0171 0.0294 0.0438 a/v v cca = 5 v 0.0258 0.03 0.0352 a/v g conv(v) voltage conversion gain 800 w matched input and output; note 8 v cca = 2.7 v 17.8 21.4 25.5 dbv v cca = 3 v 17.8 21.4 25.6 dbv v cca = 5 v 18 21.6 25.8 dbv g conv(p) power conversion gain 800 w matched input and output; note 9 v cca = 2.7 v 17.8 21.4 25.6 db v cca = 3 v 17.8 21.4 25.6 db v cca = 5 v 18 21.6 25.8 db r i(dif) differential input resistance note 10 v cca = 2.7 v 1.6 2.05 2.45 k w v cca = 3 v 1.6 2.05 2.45 k w v cca = 5 v 1.6 2.05 2.45 k w c i(dif) differential input capacitance note 10 v cca = 2.7 v 0.9 1 1.1 pf v cca = 3 v 0.9 1 1.1 pf v cca = 5 v 0.9 1 1.1 pf cp - 1db(mx2)(m) - 1 db differential input compression point 800 w matched input and output (peak value); note 9 v cca = 2.7 v 50 67.2 84.3 mv v cca = 3 v 44 67.2 90.3 mv v cca = 5 v 44.6 67.2 89.8 mv f dsb(mx2) double-side band noise ?gure mx2 800 w matched input and output; note 9 v cca = 2.7 v - 4.8 6.1 db v cca =3v - 4.8 5.5 db v cca =5v - 4.8 7 db symbol parameter conditions min. typ. max. unit
1999 may 10 47 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL limiter g v(lim) small signal limiting voltage gain 800 w matched limiter input to internal limiter output v cca = 2.7 v - 64.5 - db v cca = 3 v 61.8 65.7 69.5 db v cca =5v - 66.0 - db r i(dif) differential input resistance note 10 v cca = 2.7 v 4.10 4.85 6.67 k w v cca = 3 v 4.11 4.87 6.69 k w v cca = 5 v 4.15 4.92 6.76 k w c i(dif) differential input capacitance note 10 0.25 0.28 0.31 pf f lim limiter noise ?gure referred to 800 w 800 w matched source; note 11 v cca = 2.7 v - 16.5 - db v cca = 3 v 12.0 15.0 17.0 db v cca =5v - 11.0 - db s lim(m) differential limiter sensitivity 800 w matched source (peak value); note 11 v cca = 2.7 v 46 100 154 m v v cca = 3 v 68.8 100 131.2 m v v cca = 5 v 46 100 154 m v sclk (sample clock conditioning) g v(sclk) small signal voltage gain 50 w terminated sclk input to internal dff clock input v cca = 2.7 v - 38.9 - db v cca =3v - 39.0 - db v cca =5v - 39.6 - db r i(sclk) input resistance note 10 v cca = 2.7 v - 23.2 - k w v cca =3v - 23.4 - k w v cca =5v - 23.7 - k w c i(sclk) input capacitance note 10 v cca = 2.7 v - 0.86 - pf v cca =3v - 0.84 - pf v cca =5v - 0.74 - pf b sclk small signal bandwidth 50 w terminated source - 42.5 - mhz symbol parameter conditions min. typ. max. unit
1999 may 10 48 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL s sclk(m) sclk sensitivity 50 w terminated source (peak value) v cca = 2.7 v 10 -- mv v cca =3v 10 -- mv v cca =5v 10 -- mv vco r i(1.4ghz)(seqn) series equivalent negative resistance at 1.4 ghz (only for reference) v cca = 2.7 v -- 14.5 -w v cca =3v -- 14.7 -w v cca =5v -- 15.0 -w c i(1.4ghz)(seq) series equivalent capacitance at 1.4 ghz (only for reference) v cca = 2.7 v - 2.61 - pf v cca =3v - 2.56 - pf v cca =5v - 2.47 - pf r i(1.5ghz)(seqn) series equivalent negative resistance at 1.5 ghz (only for reference) v cca = 2.7 v -- 12.1 -w v cca =3v -- 12.3 -w v cca =5v -- 12.6 -w c i(1.5ghz)(seq) series equivalent capacitance at 1.5 ghz (only for reference) v cca = 2.7 v - 3.06 - pf v cca =3v - 3.00 - pf v cca =5v - 2.90 - pf r i(1.6ghz)(seqn) series equivalent negative resistance at 1.6 ghz (only for reference) v cca = 2.7 v -- 10.4 -w v cca =3v -- 10.7 -w v cca =5v -- 11.0 -w c i(1.6ghz)(seq) series equivalent capacitance at 1.6 ghz (only for reference) v cca = 2.7 v - 2.94 - pf v cca =3v - 2.89 - pf v cca =5v - 2.78 - pf v vco(m) ?rst lo signal level (peak value) note 12 v cca = 2.7 v -- 0.9 v v cca =3v -- 0.9 v v cca =5v -- 0.9 v k vco(av) average vco gain in typical application v cca = 2.7 v - 84.84 - mhz/v v cca = 3 v 61.7 96.62 101 mhz/v v cca =5v - 67.15 - mhz/v synthesizer f i(ref) reference input frequency 1 14.4 35 mhz p i(ref) reference input level relative to 50 w- 32.27 +5 +9.75 dbm z i(ref) reference input impedance - 20 - k w pn 10khz pll phase noise 10 khz offset note 12 v cca = 2.7 v - 72 - dbc/hz v cca =3v - 72 - dbc/hz v cca =5v - 72 - dbc/hz symbol parameter conditions min. typ. max. unit
1999 may 10 49 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL notes 1. the noise figure of the gps application board is estimated from the - 3 db sensitivity testing by substitution using a 10 db external lna with a noise figure of less than 2 db. 2. the sensitivity of the gps application board is measured by recording the rf level required to observe a 3 db drop in the sampled l1 signal, after sampling to 1.32 mhz product [3.48 mhz(if2) - 4.8 mhz (f sample )] in the sign bit output. 3. at l1 (1.57542 ghz) with a - 35 dbm input with matching components tuned at 3 v at t amb =25 c. 4. from the matched single-ended rf mixer preamplifier input to the differential if output of mx1. 5. from the matched single-ended rf mixer preamplifier input to the differential if output of mx1 across an equivalent 400 w loading of an 800 w termination and transformer differential load (4 : 1 ratio to a 50 w measurement termination). 6. from the matched single-ended rf input to the differential if output of mx1 into an equivalent 400 w differential load. half of the delivered conversion gain power is delivered to an 800 w termination, with the remaining power transformed (z-ratio 16 : 1) down and delivered to a 50 w termination. the available tabulated power is 3 db higher than the power delivered to the 50 w termination. 7. from the differential transformer matched rf input to the differential if output of mx2. 8. from the differential transformer matched rf input to the differential if output of mx2 across an equivalent 400 w loading of an 800 w termination and transformer differential load (4 : 1 ratio to a 50 w measurement termination). 9. from the differential transformer matched rf input to the differential if output of mx2 into an equivalent 400 w differential load. half of the delivered conversion gain power is delivered to an 800 w termination, with the remaining power transformed (z-ratio 16 : 1) down and delivered to a 50 w termination. the available tabulated power is 3 db higher than the power delivered to the 50 w termination. the back-to-back 50 w : 800 w : 800 w :50 w response characteristics of mini circuits rf transformer t16-6t are provided in fig.11. 10. simulated values without external pin strays. 11. due to test time constraints the sensitivity of the limiter is measured indirectly in the current ate test definition. bench characterization using a 1 : 16 w ratio transformer established - 3 db limiting sensitivity at 100 m v (peak value) across the 800 w terminated transformer output at the limiter input. this sensitivity is not due to gain limitations, but rather intrinsic complex broadband noise characteristics over an estimated 800 mhz equivalent sampled spectral bandwidth. however, the measured - 82 dbm sensitivity of the device in an 800 w operating environment defines the minimum level which can be detected in the sampling quantizer. the ate test method results perform about 8.2 dbv better than bench characterization using conventional - 3 db limiting. the specification results represent the ate results degraded by 8.2 db. the limiter noise figure test is being degraded by 800 w transformer termination loss. only a weak and remote correlation exist between highly non-linear noise figure measurements made on a time sampled quantizer output and linear simulation results. 12. the peak vco tank swing and phase noise are measured in the default application board. with high q resonators the peak voltage swing at the resonator pin should be limited to <0.8 v (peak value). a de-biasing resistor can be added from the tank pin to ground.
1999 may 10 50 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 13 characterization test circuit mhb288 b ook, full pagewidth 38 48 47 46 45 44 43 42 41 40 39 37 23 13 14 15 johnstech international jti-ts048qfp07-0.50 giga 3 socket 16 17 18 19 20 21 22 24 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 UAA1570HL r6 820 w r2 10 w l6 3.9 nh c14 1.0 pf c21 1 nf c22 0.01 m f c23 100 pf 100 pf c13 select c100 l7 33 nh c25 1 nf c53 1.2 pf c2 100 pf c1 0.01 m f c50 c26 0.01 m f c27 100 pf 220 nh l8 220 nh l11 c16 0.01 m f c15 100 pf l9 0 nh l10 220 nh c20 0.01 m f c28 c24 c19 c17 r7 c18 z y trace y trace x trace x trace trace x trace mixin j6 sma lna1out j14 sma r8 1.2 k w r9 820 w 5.1 k w z trace z trace y trace r18 5.1 k w c46 0.047 m f c47 100 pf c7 0.01 m f if1p j7 sma r11 length (mils) 4 layer fr4 board 125 mils thick 50 w coplanar microstrip h = 12 mils w = 20 mils g = 10 mils 62 w coplanar microstrip h = 12 mils w = 12 mils g = 11.5 mils lna1in lna1out lna2in lna2out mix1in x 1500 1261 586 345 1565 y (50 w ) (via) (62 w ) 894 568 932 1005 311 125 125 125 125 125 z 75 45 89 85 69 c30 mix2in j9 sma c31 0.01 m f 0.01 m f 0.1 m f 0.1 m f t2 t16-6t t1 t16-6t r15 r16 r12 r13 820 w r14 c34 r1 51 w c37 100 pf c41 2.2 m f c12 4.7 pf c11 100 nf c38 0.01 m f c33 c35 c36 0.01 m f c42 100 pf c43 c32 liminp j10 sma r17 51 w sign j11 sma agnd r3 10 k w sclk j12 sma t4 t16-6t r10 c29 220 nh l12 220 nh l14 33 nh l1 l4 33 nh l5 5.6 nh 33 nh l13 4.7 nh l17 lna2in j1 sma 4.7 nh l2 x trace z trace y trace clock lna2out j2 sma l3 0 nh ext refin j3 sma x trace z trace y trace c51 1.2 pf c52 lna1in j13 sma 5.6 nh l16 l15 33 nh c40 0.01 m f c48 100 pf c49 0.01 m f c39 100 pf c44 0.1 m f c45 agnd if2p j8 sma t3 t16-6t strobe data v ddd post c57 2.2 m f v cc c8 100 pf c9 0.01 m f c10 15 pf c4 1.5 pf c3 c6 1.2 pf c5 v tune j4 jumper r4 2.4 k w r5 2.4 k w vr1 smv1204-133 v tune tcxo gv cc g out txs1134m c54 10 pf c55 10 pf c56 10 pf j5 3wb r19 100 w r20 100 w r21 100 w strobe data clock fig.25 characterization test circuit.
1999 may 10 51 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL table 5 component list for fig.25 component component characteristics value tolerance package c1, c7, c9, c16, c20, c22, c26, c31, c36, c38, c40, c42 and c49 0.01 m f 10% 603 c2, c8, c15, c19, c23, c27, c37, c39, c43, c47 and c48 100 pf 5% 603 c3, c5, c50 and c100 not loaded -- c4 1.5 pf 0.25 pf 805 c6, c51 and c53 1.2 pf 0.25 pf 805 c10 15 pf 5% 603 c11 (1) not loaded -- c12 4.7 pf 0.25 pf 603 c13 short -- c14 1.0 pf 0.25 pf 805 c17, c18, c24, c28, c29 and c30 not loaded -- c21 and c25 1000 pf 5% 603 c32, c35 and c45 0.1 m f 10% 603 c33, c34 and c44 not loaded -- c41 and c57 (2) 2.2 m f 10% - c46 0.047 m f 10% 603 c52 not loaded -- c54 to c56 (3) 10 pf 5% 603 r1 and r17 51 w 1% 603 r2 (4) not loaded -- r3 10 k w 1% 603 r4 and r5 2.4 k w 1% 603 r6, r9 and r13 820 w 1% 603 r7, r10 and r11 not loaded -- r8 1.2 k w 1% 603 r12 not loaded -- r14 not loaded -- r15 not loaded -- r16 (5) 5.1 k w 1% 603 r18 5.1 k w 1% 603 r19, r20 and r21 100 w 5% 603 l1, l4, l7, l13 and l15 33 nh 10% 805 (coilcraft) l2 and l17 4.7 nh 0.3 nh 805 (toko) l3 short -- l5 5.6 nh 0.3 nh 603 (toko) l6 3.9 nh 0.3 nh 805 (toko) l8, l10, l11, l12 and l14 220 nh 10% 805 (coilcraft) l9 short --
1999 may 10 52 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL notes 1. 0.1 m f, 10%, 603 if used. 2. 16 v voltage rating. 3. for default frequency plan: short. 4. 10 w , 5%, 603 if used. 5. for ac characterization, terminate with 50 w to ground and use a 50 w input test instrument. 6. txs1134mtew if used. l16 5.6 nh 0.3 nh 805 (toko) vr1 smv1204-133 low capacitance varactor (alpha) t1 to t4 transformer mini circuits t16-6t-kk81/w38, 16 : 1 impedance ratio tcxo (6) not loaded -- component component characteristics value tolerance package
1999 may 10 53 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 14 default application and demonstration board fig.26 overall schematic. handbook, full pagewidth mhb492 digital processor rclk sclk sign rfdata rfclk rfle rf front-end rclk sclk sign rfdata power supply vrtc v bb batt_on batt_off vrtc v bb batt_on batt_off rfclk rfle
1999 may 10 54 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.27 baseband circuitry (continued in fig.28). mhb290 handbook, full pagewidth 44 73 47 46 45 41 40 74 14 15 52 76 wrl wrh a1 tp1 pmcs dmcs rd 39 35 34 33 32 36 29 28 a6 a7 a8 a9 a2 a3 a4 a5 27 a10 24 22 21 20 19 23 18 11 a15 a16 a17 a18 a11 a12 a13 a14 10 a19 70 68 67 64 63 69 62 59 d4 d5 d6 d7 d0 d1 d2 d3 58 d8 57 55 54 53 56 d13 d9 d10 d11 d12 49 48 d14 d15 89 rfdat 90 91 rfclk rfle 16 25 37 51 61 86 v cc(p) v cc(p) v cc(p) v cc(p) v cc(p) v cc(p) v cc1 v cc2 v cc3 v cc4 v cc5 v cc6 12 30 66 v cc(core) v cc(core) v cc(core) v dd1 v dd2 v dd3 72 80 v cc(b) v cc(r) vrtc1 v bb1 xtal2 xtal3 pwrfail pwrdn xtal1 75 83 84 81 82 4 txd1 rxd1 tp4 xtal4 txd0 rxd0 42 96 95 94 gpio1 gpio2 tp2 gpio0 88 87 5 6 gpio7 gpio6 gpio3 gpio4 7 gpio5 8 9 n.c. n.c. u204 saa1575hl r207 470 w r206 10 k w d201 bas16 rclk sclk sign batt_on batt_off rclk sclk sign batt_on batt_off v cc v cc v cc v cc r205 10 k w r204 1 m w v cc 10 pf c207 c208 180 w r203 v cc v cc 1 jp202 header 10 2 3 4 5 6 7 9 8 10 10 pf jp201 jmp3 tp218 tp216 tp225 tp219 tp220 tp221 tp211 tp210 tp209 tp208 98 1 rclk sclk tp201 tp202 93 92 3 if1 if2 tp3 tp203 2 t1s tp204 v cc v cc 77 78 43 rstime pwrb pwrm sign t1s_out batt_on batt_off 13 v ss 17 v ss 26 v ss 31 v ss 38 v ss 50 v ss 60 v ss 65 v ss 71 v ss 79 v ss 85 v ss tp205 tp206 97 99 100 test1 test2 n.c. tp207 tp222 tp223 tp224 1 23 v cc out gnd u207 zm33164 tp217 tp229 1 23 v cc out gnd u206 zm33064 c209 10 m f (6.3 v) y201 30 mhz r202 10 m w 27 pf c205 c206 0 w r201 27 pf tp212 tp213 tp214 tp215 tp230 y202 32.678 khz gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v cc c224 33 nf c223 33 nf c222 33 nf c221 33 nf v cc6 c220 33 nf v cc5 c219 33 nf v cc4 c218 33 nf v cc3 c217 33 nf v cc2 c216 33 nf v cc1 c215 33 nf vrtc1 c214 33 nf v bb1 c213 33 nf v dd3 c212 33 nf v dd2 c211 33 nf v dd1 c210 33 nf gnd
1999 may 10 55 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.28 baseband circuitry (continued from fig.27). mhb291 handbook, full pagewidth r224 220 w r210 open r223 220 w r209 open r222 220 w r208 open rfle rfclk rfdata rfle rfclk rfdata rfl rfc rfd tp227 tp226 tp228 gnd v cc1 v cc v cc2 v cc3 v cc4 v cc5 v cc6 c225 47 m f (6.3 v) 1 w r216 v dd1 v dd v dd2 v dd3 vrtc1 v bb1 c226 47 m f (6.3 v) 1 w r213 vrtc 1 w r212 v bb 1 w r211 gnd gnd 11 13 15 16 17 12 18 19 10 8 7 6 5 9 4 3 d4 d5 d6 d7 d0 d1 d2 d3 d12 d13 d14 d15 d8 d9 d10 d11 a5 a6 a7 a8 a1 a2 a3 a4 a4 a5 a6 a7 a0 a1 a2 a3 25 21 23 2 26 24 1 20 a13 a14 a15 /dmcs a9 a10 a11 a12 a12 a13 a14 /ce a8 a9 a10 a11 22 /rd /oe 28 v bb 14 gnd 27 /wrh /we u202 m5m5256bvp 11 13 15 16 17 12 18 19 10 8 7 6 5 9 4 3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 a5 a6 a7 a8 a1 a2 a3 a4 a4 a5 a6 a7 a0 a1 a2 a3 25 21 23 2 26 24 1 20 a13 a14 a15 /dmcs a9 a10 a11 a12 a12 a13 a14 /ce a8 a9 a10 a11 22 /rd /oe 27 /wrl /we u203 m5m5256bvp 21 19 18 17 16 20 15 14 24 26 27 28 29 25 30 31 d4 d5 d6 d7 d0 d1 d2 d3 11 9 8 7 6 10 5 4 d13 d14 d15 d16 d8 d9 d11 d12 2 43 v pp v cc v cc /pgm a5 a6 a7 a8 a1 a2 a3 a4 a4 a5 a6 a7 a0 a1 a2 a3 32 36 37 38 39 35 40 a13 a14 a15 a9 a10 a11 a12 a12 a13 a14 a8 a9 a10 a11 41 42 44 a16 a17 a15 a16 3 /ce 22 /pmcs /oe u205 27c202 gnd 13 7 6 20 21 17 8 5 12 15 16 2 3 14 1 28 /t3in /t4in r1out r2out v + v - /t1in /t2in rxd0 rxd1 txd0 txd1 26 22 19 24 25 r4out r5out en /shdn r3out t1out t2out t3out t4out c1 + c1 - c2 + c2 - 9 27 23 18 4 /r5in /r1in /r2in /r3in /r4in u201 j201 db9 db9 j202 max213eai v cc v cc v cc v cc 3 7 2 6 1 5 9 4 8 3 7 2 6 1 5 9 4 8 c203 100 nf (50 v) c204 100 nf (50 v) 100 nf (50 v) 100 nf (50 v) c202 c201 gnd gnd 28 v bb 14 gnd 12 34 gnd
1999 may 10 56 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.29 rf front-end circuit (continued in fig.30). mhb292 handbook, full pagewidth r315 2.7 k w r314 2.7 k w r313 6.8 k w r320 2.21 k w r321 2.21 k w c346 33 nf c333 33 nf v cc v cca c344 10 nf (50 v) c339 4.7 pf c340 150 pf c341 3.9 nf c342 4700 pf c337 33 nf c336 33 nf c335 33 nf c338 15 pf c348 10 pf c343 4700 pf vrf vrf vrf vrf l305 6.8 nh r326 10 k w r327 10 k w r319 20 k w r316 10 k w r312 3.9 k w r318 10 k w r317 10 k w 5 4 5 6 7 8 1 2 3 8 39 12 10 32 40 7 8 14 6 x301 tco-987q - + 2 1 3 d301 smv1233-004 rfdata 7 rfclk 23 rfle 34 sign r310 18 w r311 18 w 37 30 29 28 27 c334 33 nf r309 open r325 1 w c347 open c330 33 nf 1 36 31 33 c332 33 nf c329 33 nf 19 16 c331 33 nf 9 41 43 sclk liminn bfcn v cca(lna1) v cca(lna2) v cca(pll) v cca(lim) v cca(mx2) v cca(mx1p) v cca(vco) p41gnd v ddd liminp sclk bfcp refin p39gnd comp p12gnd tank data clock strobe sign vrf v ddd v ccd rclk u302 max903esa dgnd agnd agnd agnd agnd agnd agnd dgnd agnd r322 r324 open 12 k w c345 1 m f (16 v) c308 open vrf m1biasp m1biasn l306 180 nh l307 180 nh r323 r304 0 w 2.21 k w vrf m2biasp m2biasn l308 27 m h l309 open agnd agnd agnd agnd agnd agnd agnd agnd UAA1570HL
1999 may 10 57 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.30 rf front-end circuit (continued from fig.29). mhb293 handbook, full pagewidth r306 909 w r303 9 w r307 9 w c315 6.8 pf c316 6.8 pf c317 8.2 pf c318 8.2 pf c325 27 pf c328 33 nf (50 v) c327 10 pf (50 v) c324 1.5 pf c326 0.56 pf l303 330 nh l304 330 nh 45 lna1in 48 3 lna1out lna2in lna2out UAA1570HL vrf l = 367 mils (9.3 mm) w = 33 mils 50 w w = 6 mils 100 w c321 0.27 pf c307 open c305 open c323 2.2 pf l = 355 mils (9 mm) w = 6 mils 100 w l = 286 mils (7.3 mm) w = 6 mils 100 w l = 386 mils (10 mm) l = 1020 mils w = 8.8 mils l = 900 mils w = 8.8 mils l = 315 mils (8.1 mm) w = 6 mils 100 w j301 sma-f 1 25 346 bpf301 mf1012s-1 i/o i/o 6 14 mx1in 17 if1p m1biasp 18 if1n 21 if2inn 22 if2inp 24 if2p 25 if2n liminp liminn m1biasn m2biasp m2biasn c320 1.2 pf c313 36 pf c314 36 pf c319 39 pf r305 820 w r302 0 w 0 w r301 c302 47 pf c304 open c303 47 pf c312 1000 pf c311 1000 pf l301 22 m h l302 22 m h 44 lna1gnd1 46 biasgnd1 47 lna1gnd2 5 lna2gnd2 4 biasgnd2 2 lna2gnd1 42 p42gnd 38 pllgnd 26 limgnd 20 mx2gnd 13 mxpgnd 35 dgnd 15 mx1gnd 11 vcognd c301 82 pf c309 18 pf c310 68 pf c306 0.47 pf c322 2.2 pf l = 412 mils (10.5 mm) w = 6 mils 100 w l = 217 mils (5.5 mm) w = 33 mils 50 w 1 25 346 bpf302 mf1012s-1 i/o i/o dgnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd
1999 may 10 58 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.31 power supply circuitry. handbook, full pagewidth mhb294 gnd v bat r117 1 k w b101 3 v 170 mah c114 22 m f (6.3 v) v103 bc858 v105 bc858 gnd gnd v cc v cc v bat r113 47 k w r109 470 w r110 1 m w r112 1 m w r115 10 m w batt_on batt_off v bb c113 22 m f (6.3 v) v104 bc858 v102 bc848 v101 bc848 v106 bc858 gnd gnd v dd v bat r114 47 k w r116 10 m w vrtc r111 1 m w c112 470 nf gnd u103 lp2951cm in 8 sd 3 6 vtap 2 snse 1 out fb 7 4 c105 100 nf tp103 v dd(in) v dd v cc c106 100 nf c111 10 m f (6.3 v) r106 18 k w r108 12 k w r103 1 w gnd gnd gnd gnd gnd gnd gnd 5 err u101 pl101 jmp3 in 2 out 3 adj 1 c101 1 nf d102 ll4007 tp101 v cc v cc d101 ll4007 c109 10 m f (10 v) c107 1 m f (20 v) c102 1 nf c108 22 m f (5 v) r118 270 w r119 820 w r101 1 w gnd gnd gnd gnd gnd gnd gnd u102 lm317t(3) lm317t(3) in 2 out 3 adj 1 3 v/5 v jp101 1 2 c103 1 nf d104 ll4007 tp102 vrf vrf d103 ll4007 c116 10 m f (10 v) c115 1 m f (20 v) c104 1 nf c110 22 m f (5 v) r120 240 w r121 390 w r122 330 w r102 1 w
1999 may 10 59 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL the gps system application demonstration board consists of 6 layers with a total final thickness of 1.5 mm. the pcb material is fr4. fig.32 demonstration board top layer plus components (real size 88.9 mm 88.9 mm). mhb295 handbook, full pagewidth c326 bpf302 l303 * * d301 l304 r314 r316 r325 r309 r306 r319 r310 r311 r305 r301 c310 c303 r216 c220 r211 c213 r302 l305 l302 l301 c322 c311 c312 c301 u301 c325 c324 c314 c317 c305 c319 c302 c309 c341 jp202 c318 c334 c320 c338 c306 c327 c328 c329 pmcs wrh c217 dmcs pwrfail c211 wrl rd pwrdn ptest vrf in x301 rs232 #0 u204 c216 c213 c219 c215 c210 r206 pl101 c103 r120 r121 r102 c101 c107 c109 u101 r103 u102 c116 c115 r122 r303 r307 1 batt_off u201 r326 r327 u206 c209 r212 c212 gnd/v cc v cc in v dd in r118 + + r119 c102 r101 jp101 1 batt_on rxd1 txd1 txd0 rxd0 rfclk rfdata rfle sign dac rclk sclk t1s_out 1 c223 u205 3 v/170 mah r205 u207 r224 r210 r223 r209 r222 r208 r213 c214 rs232 #1 gps demo board version 1.3
1999 may 10 60 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.33 demonstration board 2nd layer. mhb296 handbook, full pagewidth
1999 may 10 61 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.34 demonstration board 3rd layer. mhb297 handbook, full pagewidth
1999 may 10 62 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.35 demonstration board 4th layer. mhb298 handbook, full pagewidth
1999 may 10 63 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.36 demonstration board 5th layer. mhb299 handbook, full pagewidth
1999 may 10 64 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL fig.37 demonstration board bottom layer plus components. mhb300 handbook, full pagewidth c326 bpf302 l303 * * d301 l304 r314 r316 r325 r309 r306 r319 r310 r311 r305 r301 c310 c303 r216 c220 r211 c213 r302 l305 l302 l301 c322 c311 c312 c301 u301 c325 c324 c314 c317 c305 c319 c302 c309 c341 jp202 c318 c334 c320 c338 c306 c327 c328 c329 pmcs wrh c217 dmcs pwrfail c211 wrl rd pwrdn ptest vrf in x301 rs232 #0 u204 c216 c213 c219 c215 c210 r206 pl101 c103 r120 r121 r102 c101 c107 c109 u101 r103 u102 c116 c115 r122 r303 r307 1 batt_off u201 r326 r327 u206 c209 r212 c212 gnd/v cc v cc in v dd in r118 + + r119 c102 r101 jp101 1 batt_on rxd1 txd1 txd0 rxd0 rfclk rfdata rfle sign dac rclk sclk t1s_out 1 c223 u205 3 v/170 mah r205 u207 r224 r210 r223 r209 r222 r208 r213 c214 rs232 #1 gps demo board version 1.3
1999 may 10 65 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL table 6 component list for gps demonstration board component type component characteristics value tolerance package b101 lithium battery 3 v/170 mah - cr1/3 c101 to c104, c311 and c312 ceramic capacitor 1 nf/50 v 10% 603 c105, c106, c201 to c204 ceramic capacitor 100 nf/50 v 20% 603 c107 and c115 ceramic capacitor 1 m f/63 v 20% 1210 c108 and c110 tantalum capacitor 22 m f/16 v 20% - c109 and c116 tantalum capacitor 10 m f/16 v 20% - c111 and c209 tantalum capacitor 10 m f/6.3 v 20% - c112 ceramic capacitor 470 nf/63 v 20% 1206 c113 and c114 tantalum capacitor 22 m f/6.3 v 20% - c205, c206 and c325 ceramic capacitor 27 pf/50 v 5% 603 c207, c208, c327 and c348 ceramic capacitor 10 pf/50 v 5% 603 c210 to c224, c328 to c337 and c346 ceramic capacitor 33 nf/63 v 10% 603 c225 and c226 tantalum capacitor 47 m f/6.3 v 20% - c301 ceramic capacitor 82 pf/50 v 5% 603 c302 and c303 ceramic capacitor 47 pf/50 v 5% 603 c304, c305, c307, c308 and c347 - not loaded -- c306 ceramic capacitor 0.47 pf/50 v 0.1 pf 603 c309 ceramic capacitor 18 pf/50 v 5% 603 c310 ceramic capacitor 68 pf/50 v 5% 603 c313 and c314 ceramic capacitor 36 pf/50 v 5% 603 c315 and c316 ceramic capacitor 6.8 pf/50 v 0.25 pf 603 c317 and c318 ceramic capacitor 8.2 pf/50 v 0.25 pf 603 c319 ceramic capacitor 39 pf/50 v 5% 603 c320 ceramic capacitor 1.2 pf/50 v 0.25 pf 603 c321 ceramic capacitor 0.27 pf/50 v 0.1 pf 603 c322 and c323 ceramic capacitor 2.2 pf/50 v 0.25 pf 603 c324 ceramic capacitor 1.5 pf/50 v 0.25 pf 603 c326 ceramic capacitor 0.56 pf/50 v 0.1 pf 603 c338 ceramic capacitor 15 pf/50 v 5% 603 c339 ceramic capacitor 4.7 pf/50 v 0.25 pf 603 c340 ceramic capacitor 150 pf/50 v 5% 603 c341 ceramic capacitor 3.9 nf/50 v 10% 603 c342 and c343 ceramic capacitor 4.7 nf/50 v 5% 603 c344 ceramic capacitor 10 nf/50 v 10% 603 c345 tantalum capacitor 1 m f/16 v 20% - d101 to d104 ll4007 diode, equivalent to 1n4007 --- d201 smd diode bas 16 -- sot23
1999 may 10 66 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL d301 alpha smv1204-133 varactor -- sot23 l301 and l302 smd inductor 22 m h 5% 1008 l303 and l304 smd inductor 330 nh 5% 1008 l305 smd inductor 6.8 nh 5% 603 l306 and l307 smd inductor 180 nh 5% 1008 l308 smd inductor 27 m h 5% 1008 l309 - not loaded -- r101, r102, r103, r211, r212, r213, r216 and r325 smd resistor 1 w 5% 603 r106 smd resistor 18 k w 5% 603 r108 and r322 smd resistor 12 k w 1% 603 r109 and r207 smd resistor 470 w 1% 603 r110, r111, r112 and r204 smd resistor 1 m w 1% 603 r113 and r114 smd resistor 47 k w 1% 603 r115, r116 and r202 smd resistor 10 m w 1% 603 r117 smd resistor 1 k w 1% 603 r118 smd resistor 270 w 1% 603 r119 and r305 smd resistor 820 w 1% 603 r120 smd resistor 240 w 1% 603 r121 smd resistor 390 w 1% 603 r122 smd resistor 330 w 1% 603 r201, r301, r302 and r304 smd resistor 0 w- 603 r203 smd resistor 180 w 5% 603 r205, r206, r316, r317, r318, r326 and r327 smd resistor 10 k w 1% 603 r208, r209, r210, r309 and r324 - not loaded -- r222 to r224 smd resistor 220 w 5% 603 r303 and r307 smd resistor 9.1 w 5% 603 r306 smd resistor 910 w 1% 603 r310 and r311 smd resistor 18 w 1% 603 r312 smd resistor 3.9 k w 1% 603 r313 smd resistor 6.8 k w 1% 603 r314 and r315 smd resistor 2.7 k w 1% 603 r319 smd resistor 20 k w 5% 603 r320, r321 and r323 smd resistor 2.2 k w 1% 603 u101 and u102 (1) lm317t voltage regulator -- to220 u103 lp2951cm voltage regulator (national) -- so8 component type component characteristics value tolerance package
1999 may 10 67 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL note 1. with heat sink depending on input voltage. u201 max213eairs2312 transceiver (maxim) -- ssop28 u202 and u203 sram m5m5256bfp-70ll 32k 8 (mitsubishi) -- so28 u205 27c202 eprom -- plcc44 u206 zm33064 power monitor --- u207 zm33164 power monitor --- u302 max903esa comparator (maxim) -- so8 v101 and v102 bc848 or bc847c npn transistor -- sot23 v103 to v106 bc858 pnp transistor -- sot23 x301 tcxo tco-987q --- y201 30 mhz crystal, 16 pf load capacitance --- y202 smd crystal 32.768 khz 30 ppm - bpf301 and bpf302 mf1012s-1 saw ?lter --- component type component characteristics value tolerance package
1999 may 10 68 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 15 internal circuitry pin symbol pin voltage typical values (v) equivalent circuit without esd protection circuits v cc = 2.7 v v cc =5v 1v cca(lna2) 2.7 5 2 lna2gnd1 0 0 3 lna2in 0.815 0.807 4 biasgnd2 0 0 5 lna2gnd2 0 0 6 lna2out 1.48 3.629 7 clock cmos level cmos level 8 refin 1.69 3.99 9v cca(vco) 2.7 5 10 tank 1.92 1.92 3 2 mhb301 6 5 mhb302 7 mhb303 8 mhb304 10 11 mhb305
1999 may 10 69 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 11 vcognd 0 0 12 p12gnd 0 0 13 mxpgnd 0 0 14 mx1in 0.82 0.81 15 mx1gnd 0 0 16 v cca(mx1p) 2.7 5 17 if1p 2.7 5 18 if1n 2.7 5 19 v cca(mx2) 2.7 5 20 mx2gnd 0 0 21 if2inn 0.983 0.98 22 if2inp 0.983 0.98 23 strobe cmos level cmos level 24 if2p 2.7 5 25 if2n 2.7 5 26 limgnd 0 0 pin symbol pin voltage typical values (v) equivalent circuit without esd protection circuits v cc = 2.7 v v cc =5v 14 13 mhb306 17 18 mhb307 21 22 mhb308 23 mhb309 24 25 mhb310
1999 may 10 70 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 27 bfcn 1.696 3.999 28 liminn 1.696 3.999 29 liminp 1.696 3.999 30 bfcp 1.696 3.999 31 v cca(lim) 2.7 5 32 data cmos level cmos level 33 v ddd 2.7 (independent of v cc level) 5 (independent of v cc level) 34 sign ttl output ttl output 35 dgnd 0 0 36 v cca(pll) 2.7 5 37 sclk 1.34 2.5 38 pllgnd 0 0 39 p39gnd 0 0 pin symbol pin voltage typical values (v) equivalent circuit without esd protection circuits v cc = 2.7 v v cc =5v 28 27 30 29 mhb311 32 mhb312 34 mhb313 37 mhb314
1999 may 10 71 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 40 comp depends on vco application depends on vco application 41 p41gnd 0 0 42 p42gnd 0 0 43 v cca(lna1) 2.7 5 44 lna1gnd1 0 0 45 lna1in 0.815 0.807 46 biasgnd1 0 0 47 lna1gnd2 0 0 48 lna1out 1.48 3.629 pin symbol pin voltage typical values (v) equivalent circuit without esd protection circuits v cc = 2.7 v v cc =5v 40 mhb315 45 44 mhb316 48 47 mhb317
1999 may 10 72 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 16 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 94-12-19 97-08-01 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
1999 may 10 73 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 17 soldering 17.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 17.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 17.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1999 may 10 74 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL 17.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 18 definitions 19 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. package soldering method wave reflow (1) hlqfp, hsqfp, hsop, sms not suitable (2) suitable plcc (3) , so suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable sqfp not suitable suitable ssop, tssop, vso not recommended (5) suitable data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1999 may 10 75 philips semiconductors product speci?cation global positioning system (gps) front-end receiver circuit UAA1570HL notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 64 philips semiconductors C a worldwide company netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero 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& sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. 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philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy printed in the netherlands 285002/00/01/pp76 date of release: 1999 may 10 document order number: 9397 750 04463

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