d2408 ms pc 20081030-s00001 no.a1360-1/10 specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. LV5654T overview the LV5654T is a 4-channel switching regulator controller. features ? low-voltage (3v) operation. ? reference voltage precision : 1%. ? independent standby functions for each of the four channels. ? is capable of driving mos transistors. ? synchronous rectification : channel 1 and channel 2. ? supports inverting step-up operation (channel 3). specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage 1 v cc max v cc pin -0.3 to 16 v maximum supply voltage 2 vbvias max vbias pin -0.3 to 18 v maximum clock input voltage vc lkin max clkin pin 5.5 v allowable power dissipation pd max independent ic 0.4 w operating temperature topr -30 to +85 c storage temperature tstg -55 to +125 c recommended operating conditions at ta = 25 c parameter symbol conditions ratings unit supply voltage 1 v cc v cc pin 3 to 15 v supply voltage 2 vbias vbias pin 3 to 15 v clock input voltage vc lkin clkin pin 5 v timing resistor rt 7 to 30 k ? timing capacitor ct 100 to 1000 pf triangle wave frequency f osc 0.1 to 1.3 mhz bi-cmos ic 4-channel switching regulator controller orderin g numbe r : ena1360
LV5654T no.a1360-2/10 electrical characteristics at ta = 25c, v cc = vbias = 3.6v, scp = 0v ratings parameter symbol conditions min typ max unit error amplifier 1 in + pin internal bias voltage vb value added to the error amplifier offset at the error amplifier + side voltage 0.504 0.51 0.516 v output low voltage ch1 to ch4 v low fb in - = 2.0v, ifb = 20 a 0.2 v output high voltage ch1 to ch4 v hi fb in - = 0v ifb1 = -20 a 2.0 v error amplifier 2 in3 - re pin offset voltage vof -6 6 mv output low voltage v low fb3re in3 - re = 2.0v, ifb = 20 a 0.2 v output high voltage v hi fb3re in3 - re = -10mv, ifb = 500 a 2.0 v protection circuit threshold voltage v scp 1.1 1.25 1.4 v scp pin current i scp 4 a short circuit detection signal pin vscpout open collector iscpout = 100 a 0.2 v software start block (ch1 to ch4) soft start current ch1 to ch4 i sf csoft = 0v 3.2 4 4.8 a soft start resistance ch1 to ch4 r sf 160 200 240 k ? fixed duty maximum on duty 1-2 ch1 to ch2 duty max 1-2 out monitor, in - = 0v 100 % maximum on duty 3 ch3 duty max 3 out monitor, in - = 0v 80 85 90 % maximum on duty 4 ch4 duty max 4 out monitor, in - = 0v 80 85 90 % output block 1 to 6 out pin high side on resistance r out sour i o = 10ma 25 ? out pin high side on resistance r out sink i o = 10ma 10 ? triangle wave oscillator block current setting pin voltage vt rt rt = 10k ? 0.57 v output current i oh ct 190 a output current ratio ? i o ct ct pin, rise/fall 2.5 oscillation frequency f osc 1 rt = 10k ? , ct = 270pf 510 khz reference voltage block reference voltage vref 1.240 v line regulation v ln ref v cc = 3v to 15v 10 mv control circuit on state voltage v on ctl 2.0 v off state voltage v off ctl 0.6 v pin input current i in ctl 60 a standby circuit on voltage v on stby 2.0 v off voltage v off stby 0.6 v pin input current i in stby vstby = 2v 60 a all circuits v cc current consumption i cc in1 - to in4 - = 1v 4 5 ma standby mode current consumption i off vstby = vctl = 0v i off = i cc + i bias 1 a
LV5654T no.a1360-3/10 package dimensions unit : mm (typ) 3253b pin assignment sanyo : tssop36(275mil) 7.6 5.6 (0.5) (1.0) 9.75 0.5 0.15 1 18 36 19 0.18 (0.63) 0.08 1.2max 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 out2 out2n gnd_p (vs) out1 out1n csoft1 csoft2 csoft3 csoft4 v cc in1 - fb1 in2 - fb2 vref ct rt gnd_s vbias out3 out4 scpout clkin stby4 stby3 stby2 stby1 scp ctl in4 - fb4 in3 + re in3 - re fb3re fb3 in3 - LV5654T top view
LV5654T no.a1360-4/10 block diagram and sample application circuit the clkin pin must be connected to gnd, when the external clock synchronization (clkin) is not used. v cc signal system power supply vbias fb1a step-down (down) v o 1 3.3v/100m a v o 4 6v/100ma out1 out1n pre-output stage power supply + - - fb1a in1 - fb1 csoft1 ct ctl rt stby1 stby2 stby3 stby4 scp_out scp gnd_p (vs) gnd_s clkin fb4a v o 3 -4v/100ma fb3a inversion (invert) in4 - fb4 csoft4 fb4a out3 out4 + - - + + - + + - on/off setting step-up (up) stby osc in3 - re in3 + re fb3r in3 - fb3 csoft3 + - - fb3a + - + + - v o 2 3.3v/100m a fb2a step-down (down) out2 out2n + - - fb2a in2 - fb2 csoft2 + + - vref
LV5654T no.a1360-5/10 pin function block pin no. pin name functions 9 stby1 standby input. h/ch1 ; on, l/ch1 ; off. 26 in1 - error amplifier inverting input. 25 fb1 error amplifier output. 31 csoft1 soft start setting capacitor con nection. connect to gnd through a capacitor. 33 out1 output. external transistor p-channel gate connection. ch1 down (step-down) 32 out1n output. external transistor n-channel gate connection. 8 stby2 standby input. h/ch2 ; on, l/ch2 ; off. 24 in2 - error amplifier inverting input. 23 fb2 error amplifier output. 30 csoft2 soft start setting capacitor con nection. connect to gnd through a capacitor. 36 out2 output. external transistor p-channel gate connection. ch2 down (step-down) 35 out2n output. external transistor n-channel gate connection. 7 stby3 standby input. h/ch3 ; on, l/ch3 ; off. 14 in3 + re inversion amplifier, + (noninverting) input. 15 in3 - re inversion amplifier, - (inverting) input. 16 fb3re inversion amplifier output. 18 in3 - error amplifier, - (inverting) input. 17 fb3 error amplifier output. 29 csoft3 soft start setting capacitor con nection. connect to gnd through a capacitor. ch3 (inversion) 2 out3 output. external transistor p-channel gate connection. 6 stby4 standby input. h/ch4 ; on, l/ch4 ; off. 12 in4 - error amplifier inverting input. 13 fb4 error amplifier output. 28 csoft4 soft start setting capacitor con nection. connect to gnd through a capacitor. ch4 step-up (up) 3 out4 output. external transistor n-channel gate connection. 27 v cc power supply input (signal system). 1 vbias power supply input (pre-output stage). 19 gnd_s ground (signal system). 34 gnd_p (vs) ground (pre-output stage). power 22 vref reference voltage output. 11 ctl output control. 10 scp connection pin for the delay time setting capacitor of short circuit detection circuit. control 4 scpout scp_out pin (scp output). 21 ct triangle wave oscillation fr equency setting capacitor connection. 20 rt triangle wave oscillation frequency setting resistor connection. osc 5 clkin external clock input.
LV5654T no.a1360-6/10 equivalent circuits pin no. pin name equivalent circuit 11 9 8 7 6 ctl stby1 stby2 stby3 stby4 120k ? ctrl/stby* gnd_s 30k ? 26 24 18 12 in1 - in2 - in3 - in4 - vreg (internal constant voltage) in* - 500 ? 5k ? 5k ? gnd_s 25 23 17 13 fb1 fb2 fb3 fb4 vreg (internal constant voltage) fb* 500 ? 20 ? gnd_s 14 15 in3 + re in3 - re vreg (internal constant voltage) in3 - re 500 ? 500 ? 5k ? 5k ? gnd_s in3 + re 16 fb3r vreg (internal constant voltage) fb3r gnd_s 31 30 29 28 csoft1 csoft2 csoft3 csoft4 vreg (internal constant voltage) gnd_s 500 ? 10k ? 200k ? csoft* continued on next page.
LV5654T no.a1360-7/10 continued from preceding page. pin no. pin name equivalent circuit 33 32 36 35 2 3 out1 out1n out2 out2n out3 out4 v out * v out *n gnd_p (vs) vbias 20 rt vreg (internal constant voltage) 500 ? 500 ? rt gnd_s 21 ct vreg (internal constant voltage) ct gnd_s 10 scp vreg (internal constant voltage) scp gnd_s 13k ? 1.5k ? 4 scp_out vreg (internal constant voltage) scp_out gnd_s continued on next page.
LV5654T no.a1360-8/10 continued from preceding page. pin no. pin name equivalent circuit 22 vref vreg (internal constant voltage) vref gnd_s 14.8k ? 5 clkin vreg (internal constant voltage) 300 ? clkin gnd_s 27 v cc v cc 1 vbias vbias 19 gnd_s gnd_s 34 gnd_p (vs) gnd_p (vs)
LV5654T no.a1360-9/10 notes (1) soft start time setting method the soft start time is set with the capac itor connected between csoft* and gnd_s. this ic has an independent soft start function for each chan nel, so a capacitor must be connected for each channel to set the soft start (time). (description of soft start operation) (outline of soft start pin) (2) setting the oscillation frequency the internal oscillation frequency is set by the resistor conn ected to the rt pin and the capacitor connected to the ct pin. the waveform generated on ct is a triangular wave with the charging/discharging waveform determined by rt and ct. f osc = 1.32 1 ct rt [hz] the actual internal oscillation frequency deviates from the calculated value due to overshoot, undershoot and other factors, so the frequency should be confirmed in an actual set. (3) external input clk function (clk_in) switching operation can be synchronized with external clock input (clk_in) by using the clk_in pin. ? external clock (clk_in) frequency and input level when using external clock (clk_in) input, input a frequency equal to the internal oscillation frequency +20% or more to clk_in. in addition, the clk_in configuration is shown in the figure ?clk_in (input) equivalent circuit (outline)? below. the 0.8v reference voltage and clk_in are compared to determine the edges, so input a signal of 0.8v or more (v cc voltage or less) as the external clock (clk_in). ? external/internal clock switching set the ctl pin low before switching between the external clock and the internal clock. switching clocks when running may give rise to output voltage fluctuations. ? maximum on duty the maximum on duty (duty_max*) of channel 3 to channel 4 is the 85% (typ.) setting. when using the external clock (clk_in), the maximum on duty (duty_max*) becomes smaller, so care must be taken for the set output voltage. (clk_in (input) equivalent circuit (outline)) clk_in 0.8v csoft* [v] csoft* voltage vreg (internal constant voltage) t [s] vb (typ, 0.515 [v]) 200k ? csoft* gnd_s vb (= 0.515 [v] (typ)) csoft pin charging starts the output voltage reaches the set voltage (output voltage constant) soft start time (tsoft [s])
LV5654T ps no.a1360-10/10 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. (4) scp function ? description of operation when any one of fb1 to fb4 goes high due to the load being shorted or other reason, charging to the scp pin starts. if output does not recover during the set time tscp and the scp pin voltage exceeds the threshold voltage, the protection circuit (scp) operates, and all channel outputs are turned off. the scp_out pin set from high to low. all outputs are latched off by the protection circuit (scp). this latched state (output off) is canceled by setting the ctl pin low or by turning the power supply off. when not using the protection function (scp), the scp pin must be shorted to gnd_s with a line that is as short as possible. ? scp_out the scp_out pin functions to notify an external microcontroller or other component of the output status (low when scp operates). the output configuration is an open drain output, and a pull-up resistor is used. when not used, leave this pin open. ? switching time the scp_out switching time is set by the capacitor connected to the scp pin. (scp charging operation) (scp and scp_out operation) this catalog provides information as of december, 2008. specifications and inform ation herein are subject to change without notice. scp [v] scp ctl ? when stby* is regarded as high (the output is turned on by setting ctl low to high). scp_out t [s] tscp scp operation charging with iscp = 4 [ a] threshold voltage 1.25v (typ) capacitor charging starts with the load being shorted output short circuit 1.25 [v] (typ)
|
