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this is information on a product in full production. may 2012 doc id 018957 rev 3 1/21 21 STGIPN3H60 sllimm?-nano (small low-loss intelligent molded module) ipm, 3 a - 600 v 3-phase igbt inverter bridge datasheet ? production data features ipm 3 a, 600 v, 3-phase igbt inverter bridge including control ics for gate driving and freewheeling diodes optimized for low electromagnetic interference v ce(sat) negative temperature coefficient 3.3 v, 5 v, 15 v cmos/ttl inputs comparators with hysteresis and pull down/pull up resistors undervoltage lockout internal bootstrap diode interlocking function smart shutdown function comparator for fault protection against overtemperature and overcurrent op amp for advanced current sensing optimized pinout for easy board layout applications 3-phase inverters for motor drives dish washers, refrigerator compressors, heating systems, air-conditioning fans, draining and recirculation pumps description this intelligent power module implements a compact, high performance ac motor drive in a simple, rugged design. it is composed of six igbts with freewheeling diodes and three half- bridge hvics for gate driving, providing low electromagnetic interference (emi) characteristics with optimized switching speed. the package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. this ipm includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. sllimm? is a trademark of stmicroelectronics. ndip-26l table 1. device summary order code marking package packaging STGIPN3H60 gipn3h60 ndip-26l tube www.st.com
contents STGIPN3H60 2/21 doc id 018957 rev 3 contents 1 internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . 3 2 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STGIPN3H60 internal schematic diagram and pin configuration doc id 018957 rev 3 3/21 1 internal schematic diagram and pin configuration figure 1. internal schematic diagram gnd vcc hin vboot lvg out hvg cin gnd vcc hin sd-od lin vboot lvg out hvg gnd opout op- vcc hin vboot lvg out hvg op+ lin u sd-od hin u vcc u cin lin v hin v vcc v op- opout op+ lin w hin w vcc w sd-od gnd n w w, out w vboot w n v v, out v p vboot v n u u,out u vboot u pin 1 pin 16 pin 17 pin 26 sd-od lin sd-od lin am09916v1
internal schematic diagram and pin configuration STGIPN3H60 4/21 doc id 018957 rev 3 table 2. pin description pin symbol description 1 gnd ground 2sd / od shut down logic input (active low) / open drain (comparator output) 3v cc w low voltage power supply w phase 4 hin w high side logic input for w phase 5lin w low side logic input for w phase 6 op+ op amp non inverting input 7op out op amp output 8 op- op amp inverting input 9v cc v low voltage power supply v phase 10 hin v high side logic input for v phase 11 lin v low side logic input for v phase 12 cin comparator input 13 v cc u low voltage power supply for u phase 14 hin u high side logic input for u phase 15 sd / od shut down logic input (active low) / open drain (comparator output) 16 lin u low side logic input for u phase 17 v boot u bootstrap voltage for u phase 18 p positive dc input 19 u, out u u phase output 20 n u negative dc input for u phase 21 v boot v bootstrap voltage for v phase 22 v, out v v phase output 23 n v negative dc input for v phase 24 v boot w bootstrap voltage for w phase 25 w, out w w phase output 26 n w negative dc input for w phase
STGIPN3H60 internal schematic diagram and pin configuration doc id 018957 rev 3 5/21 figure 2. pin layout (top view) (*) dummy pin internally connec ted to p (positive dc input).
electrical ratings STGIPN3H60 6/21 doc id 018957 rev 3 2 electrical ratings 2.1 absolute maximum ratings table 3. inverter part symbol parameter value unit v ces each igbt collector emitter voltage (v in (1) = 0) 1. applied between hin i , lin i and gnd for i = u, v, w 600 v i c (2) 2. calculated according to the iterative formula: each igbt continuous collector current at t c = 25c 3a i cp (3) 3. pulse width limited by max junction temperature each igbt pulsed collector current 18 a p tot each igbt total dissipation at t c = 25c 8 w table 4. control part symbol parameter min. max. unit v out output voltage applied between out u , out v , out w - gnd v boot - 21 v boot + 0.3 v v cc low voltage power supply - 0.3 21 v v cin comparator input voltage - 0.3 v cc +0.3 v v op+ opamp non-inverting input - 0.3 v cc +0.3 v v op- opamp inverting input - 0.3 v cc +0.3 v v boot bootstrap voltage - 0.3 620 v v in logic input voltage applied between hin, lin and gnd - 0.3 15 v v sd /od open drain voltage - 0.3 15 v v out/ d t allowed output slew rate 50 v/ns table 5. total system symbol parameter value unit v iso isolation withstand voltage applied between each pin and heatsink plate (ac voltage, t = 60 sec.) 1000 v t j power chips operating junction temperature -40 to 150 c t c module case operation temperature -40 to 125 c i c t c () t jmax () t c ? r thj c ? v ce sat () max () t jmax () i c t c () , () ------------------------------------------------------------------------------------------------------- =
STGIPN3H60 electrical ratings doc id 018957 rev 3 7/21 2.2 thermal data table 6. thermal data symbol parameter value unit r thja thermal resistance junction-ambient 50 c/w
electrical characteristics STGIPN3H60 8/21 doc id 018957 rev 3 3 electrical characteristics t j = 25 c unless otherwise specified. note: t on and t off include the propagation delay time of the internal drive. t c(on) and t c(off) are the switching time of igbt itself under the internally given gate driving condition. figure 3. switching time test circuit table 7. inverter part symbol parameter test conditions min. typ. max. unit v ce(sat) collector-emitter saturation voltage v cc = v boot = 15 v, v in (1) = 0 - 5 v, i c = 1 a - 2.15 2.6 v v cc = v boot = 15 v, v in (1) = 0 - 5 v, i c = 1 a, t j = 125 c -1.65 i ces collector-cut off current (v in (1) = 0 ?logic state?) v ce = 550 v, v cc = v boot = 15 v - 250 a v f diode forward voltage v in (1) = 0 ?logic state?, i c = 1 a - 1.7 v inductive load switching time and energy t on tu r n - o n t i m e v dd = 300 v, v cc = v boot = 15 v, v in (1) = 0 - 5 v, i c = 1 a (see figure 4 ) -275 ns t c(on) crossover time (on) - 90 t off turn-off time - 890 t c(off) crossover time (off) - 125 t rr reverse recovery time - 50 e on turn-on switching losses - 18 j e off turn-off switching losses - 13 1. applied between hin i , lin i and gnd for i = u, v, w (lin inputs are active-low).
STGIPN3H60 electrical characteristics doc id 018957 rev 3 9/21 note: figure 4 ?switching time definition? refers to hin inputs (active high). for lin inputs (active low), vin polarity must be inverted for turn-on and turn-off. 3.1 control part figure 4. switching time definition v ce i c i c v in t on t c(on) v in(on) 10% i c 90% i c 10% v ce ( a ) t u rn-on ( b ) t u rn-off t rr 100% i c 100% i c v in v ce t off t c(off) v in(off) 10% v ce 10% i c am0922 3 v1 table 8. low voltage power supply (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v cc_hys v cc uv hysteresis 1.2 1.5 1.8 v v cc_thon v cc uv turn on threshold 11.5 12 12.5 v v cc_thoff v cc uv turn off threshold 10 10.5 11 v i qccu undervoltage quiescent supply current v cc = 10 v sd /od = 5 v; lin = 5 v; hin = 0, cin = 0 150 a i qcc quiescent current v cc = 15 v sd /od = 5 v; lin = 5 v hin = 0, cin = 0 1ma v ref internal comparator (cin) reference voltage 0.5 0.54 0.58 v
electrical characteristics STGIPN3H60 10/21 doc id 018957 rev 3 table 9. bootstrapped voltage (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v bs_hys v bs uv hysteresis 1.2 1.5 1.8 v v bs_thon v bs uv turn on threshold 10.6 11.5 12.4 v v bs_thoff v bs uv turn off threshold 9.1 10 10.9 v i qbsu undervoltage v bs quiescent current v bs < 9 v sd /od = 5 v; lin and hin = 5 v; cin = 0 70 110 a i qbs v bs quiescent current v bs = 15 v sd /od = 5 v; lin and hin = 5 v; cin = 0 150 210 a r ds(on) bootstrap driver on resistance lvg on 120 table 10. logic inputs (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v il low logic level voltage 0.8 v v ih high logic level voltage 2.25 v i hinh hin logic ?1? input bias current hin = 15 v 110 175 260 a i hinl hin logic ?0? input bias current hin = 0 v 1 a i linl lin logic ?1? input bias current lin = 0 v 3 6 20 a i linh lin logic ?0? input bias current lin = 15 v 1 a i sdh sd logic ?0? input bias current sd = 15 v 30 120 300 a i sdl sd logic ?1? input bias current sd = 0 v 3 a dt dead time see figure 5 180 ns
STGIPN3H60 electrical characteristics doc id 018957 rev 3 11/21 table 11. opamp characteristics (v cc = 15 v unless otherwise specified) symbol parameter test condition min. typ. max. unit v io input offset voltage v ic = 0 v, v o = 7.5 v 6 mv i io input offset current v ic = 0 v, v o = 7.5 v 440na i ib input bias current (1) 100 200 na v icm input common mode voltage range 0v v ol low level output voltage r l = 10 k to v cc 75 150 mv v oh high level output voltage r l = 10 k to gnd 14 14.7 v i o output short circuit current source, v id = +1; v o = 0 v 16 30 ma sink, v id = -1; v o = v cc 50 80 ma sr slew rate v i = 1 - 4 v; c l = 100 pf; unity gain 2.5 3.8 v/ s gbwp gain bandwidth product v o = 7.5 v 8 12 mhz a vd large signal voltage gain r l = 2 k 70 85 db svr supply voltage rejection ratio vs. v cc 60 75 db cmrr common mode rejection ratio 55 70 db 1. the direction of input current is out of the ic. table 12. sense comparator characteristics (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit i ib input bias current v cp+ = 1 v 3 a v ol open drain low level output voltage i od = 3 ma 0.5 v t d_comp comparator delay sd /od pulled to 5 v through 100 k resistor 90 130 ns sr slew rate c l = 180 pf; r pu = 5 k 60 v/sec t sd shutdown to high / low side driver propagation delay v out = 0, v boot = v cc , v in = 0 to 3.3 v 50 125 200 ns t isd comparator triggering to high / low side driver turn-off propagation delay measured applying a voltage step from 0 v to 3.3 v to pin cin i 50 200 250
electrical characteristics STGIPN3H60 12/21 doc id 018957 rev 3 note: x: don?t care table 13. truth table condition logic input (v i ) output sd /od lin hin lvg hvg shutdown enable half-bridge tri-state lxxll interlocking half-bridge tri-state hlhll 0 ?logic state? half-bridge tri-state hhl l l 1 ?logic state? low side direct driving hllhl 1 ?logic state? high side direct driving hhhlh
STGIPN3H60 electrical characteristics doc id 018957 rev 3 13/21 3.2 waveform definitions figure 5. dead time and interlocking waveform definitions lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg dt lh dt hl dt lh dt hl dt lh dt hl dt lh dt hl gate driver outputs off (half-bridge tri-state) interlocking interlocking control signal edges overlapped: interlocking + dead time control signals edges synchronous (*): dead time control signals edges not overlapped, but inside the dead time: dead time control signals edges not overlapped, outside the dead time: direct driving (*) hin and lin can be connected together and driven by just one control signal interlocking interlocking g gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state)
smart shutdown function STGIPN3H60 14/21 doc id 018957 rev 3 4 smart shutdown function the STGIPN3H60 integrates a comparator for fault sensing purposes. the comparator non- inverting input (cin) can be connected to an external shunt resistor in order to implement a simple overcurrent protection function. when the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the half bridge in 3-state. in the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a rc network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. the time delay between the fault and the outputs turn-off is no more dependent on the rc values of the external network connected to the shutdown pin. at the same time the internal logic turns on the open-drain output and holds it on until the shutdown voltage goes below the logic input lower threshold. finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external rc network. figure 6. smart shutdown timing waveforms please refer to table 12 for internal propagation delay time details. hin/lin hvg/lvg sd/od open drain gate (internal) upper threshold lower threshold comp vref cp+ protection fast shut down: the driver outputs are set in sd state immediately after the comparator triggering even if the sd signal has not yet reach the lower input threshold real disable time 2 1 1 2 = (r on_od // r sd ) c sd = r sd c sd sd/od from/to controller v bias smart sd logic c sd r sd r on_od shut down circuit time constants
STGIPN3H60 application information doc id 018957 rev 3 15/21 5 application information figure 7. typical application circuit
application information STGIPN3H60 16/21 doc id 018957 rev 3 5.1 recommendations input signal hin is active high logic. an 85 k (typ.) pull-down resistor is built-in for each high side input. if an external rc filter is used for noise immunity, attention should be given to the variation of the input signal level. input signal lin is active low logic. a 720 k (typ.) pull-up resistor, connected to an internal 5 v regulator through a diode, is built-in for each low side input. to prevent input signal oscillation, the wiring of each input should be as short as possible. by integrating an application-specific type hvic inside the module, direct coupling to the mcu terminals without an opto-coupler is possible. each capacitor should be located as close as possible to the pins of the ipm. low inductance shunt resistors should be used for phase leg current sensing. electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. additional high frequency ceramic capacitors mounted close to the module pins will further improve performance. the sd /od signal should be pulled up to 5 v / 3.3 v with an external resistor (see section 4: smart shutdown function for detailed info). note: for further details refer to an4043. table 14. recommended operating conditions symbol parameter test conditions min. typ. max. unit v pn supply voltage applied between p-nu, nv, nw 300 500 v v cc control supply voltage applied between v cc - gnd 13.5 15 18 v v bs high side bias voltage applied between v booti - out i for i = u, v, w 13 18 v t dead blanking time to prevent arm-short for each input signal 1.5 s f pwm pwm input signal -40c < t c < 100c -40c < t j < 125c 25 khz t c case operation temperature 100 c
STGIPN3H60 package mechanical data doc id 018957 rev 3 17/21 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 15. ndip-26l mechanical data dim. mm. min. typ. max. a 4.40 a1 0.80 1.00 1.20 a2 3.00 3.10 3.20 a3 1.70 1.80 1.90 a4 5.70 5.90 6.10 b 0.53 0.72 b1 0.52 0.60 0.68 b2 0.83 1.02 b3 0.82 0.90 0.98 c 0.46 0.59 c1 0.45 0.50 0.55 d 29.05 29.15 29.25 d1 0.50 d2 0.35 d3 29.55 e 12.35 12.45 12.55 e 1.70 1.80 1.90 e1 2.40 2.50 2.60 eb1 16.10 16.40 16.70 eb2 21.18 21.48 21.78 l 1.24 1.39 1.54
package mechanical data STGIPN3H60 18/21 doc id 018957 rev 3 figure 8. ndip-26l package dimensions b1,b3 b,b2 c c1 d e eb1 eb2 e b d1 a3 e1 d2 a1 a4 l a a2 b2 d3 0.075 0.075 8278949_a
STGIPN3H60 package mechanical data doc id 018957 rev 3 19/21 figure 9. ndip-26l tube dimensions (dimensions are in mm.) note: base quantity 17 pcs, bulk quantity 476 pcs. antistatic s 03 pvc am10474v1 8313150_a
revision history STGIPN3H60 20/21 doc id 018957 rev 3 7 revision history table 16. document revision history date revision changes 23-jun-2011 1 initial release. 23-dec-2011 2 document status promoted from preliminary data to datasheet. added figure 9 on page 19 . 02-may-2012 3 modified: min. and max. value table 4 on page 6 . added: table 14 on page 16 .
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