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hb52r168db-f 128 mb unbuffered sdram s.o.dimm 16-mword 64-bit, 66 mhz memory bus, 1-bank module (16 pcs of 16 m 4 components) ade-203-1098a (z) rev. 1.0 jan. 24, 2000 description the hb52r168db is a 16m 64 1 bank synchronous dynamic ram small outline dual in-line memory module (s.o.dimm), mounted 16 pieces of 64-mbit sdram (hm5264405ftb) sealed in tcp package and 1 piece of serial eeprom (2-kbit) for presence detect (pd). an outline of the hb52r168db is 144-pin zig zag dual tabs socket type compact and thin package. therefore, the hb52r168db makes high density mounting possible without surface mount technology. the hb52r168db provides common data inputs and outputs. decoupling capacitors are mounted beside tcp on the module board. note: do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. features fully compatible with jedec standard outline 8-byte s.o.dimm 144-pin zig zag dual tabs socket type ? outline: 67.60 mm (length) 25.40 mm (height) 3.80 mm (thickness) ? lead pitch: 0.80 mm 3.3 v power supply clock frequency: 66 mhz lvttl interface data bus width: 64 non parity single pulsed ras 4 banks can operates simultaneously and independently burst read/write operation and burst read/single write operation capability programmable burst length : 1/2/4/8/full page
hb52r168db-f 2 2 variations of burst sequence ? sequential (bl = 1/2/4/8/full page) ? interleave (bl = 1/2/4/8) programmable ce latency: 2/3 byte control by dqmb refresh cycles: 4096 refresh cycles/64 ms 2 variations of refresh ? auto refresh ? self refresh low self refresh current: HB52R168DB-10FL (l-version) full page burst length capability ? sequential burst ? burst stop capability ordering information type no. frequency ce latency package contact pad hb52r168db-10f HB52R168DB-10FL 66 mhz 66 mhz 2/3 2/3 small outline dimm (144-pin) gold pin arrangement front side back side 2pin 60pin 62pin 144pin 1pin 59pin 61pin 143pin
hb52r168db-f 3 pin arrangement (cont.) front side back side pin no. signal n ame pin no. signal n ame pin no. signal n ame pin no. signal n ame 1v ss 73 nc 2 v ss 74 ck1 3 dq0 75 v ss 4 dq32 76 v ss 5 dq1 77 nc 6 dq33 78 nc 7 dq2 79 nc 8 dq34 80 nc 9 dq3 81 v cc 10 dq35 82 v cc 11 v cc 83 dq16 12 v cc 84 dq48 13 dq4 85 dq17 14 dq36 86 dq49 15 dq5 87 dq18 16 dq37 88 dq50 17 dq6 89 dq19 18 dq38 90 dq51 19 dq7 91 v ss 20 dq39 92 v ss 21 v ss 93 dq20 22 v ss 94 dq52 23 dqmb0 95 dq21 24 dqmb4 96 dq53 25 dqmb1 97 dq22 26 dqmb5 98 dq54 27 v cc 99 dq23 28 v cc 100 dq55 29 a0 101 v cc 30 a3 102 v cc 31 a1 103 a6 32 a4 104 a7 33 a2 105 a8 34 a5 106 a13 (ba0) 35 v ss 107 v ss 36 v ss 108 v ss 37 dq8 109 a9 38 dq40 110 a12 (ba1) 39 dq9 111 a10 (ap) 40 dq41 112 a11 41 dq10 113 v cc 42 dq42 114 v cc 43 dq11 115 dqmb2 44 dq43 116 dqmb6 45 v cc 117 dqmb3 46 v cc 118 dqmb7 47 dq12 119 v ss 48 dq44 120 v ss 49 dq13 121 dq24 50 dq45 122 dq56 51 dq14 123 dq25 52 dq46 124 dq57 53 dq15 125 dq26 54 dq47 126 dq58 55 v ss 127 dq27 56 v ss 128 dq59 57 nc 129 v cc 58 nc 130 v cc 59 nc 131 dq28 60 nc 132 dq60 61 ck0 133 dq29 62 cke0 134 dq61 63 v cc 135 dq30 64 v cc 136 dq62 65 re 137 dq31 66 ce 138 dq63
hb52r168db-f 4 front side back side pin no. signal n ame pin no. signal n ame pin no. signal n ame pin no. signal n ame 67 w 139 v ss 68 nc 140 v ss 69 s0 141 sda 70 nc 142 scl 71 nc 143 v cc 72 nc 144 v cc pin description pin name function a0 to?11 address input ? row address a0 to a11 ? column address a0 to a9 a12/a13 bank select address ba1, ba0 dq0 to dq63 data-input/output s0 chip select re row address asserted bank enable ce column address asserted w write enable dqmb0 to dqmb7 byte input/output mask ck0/ck1 clock input cke0 clock enable sda data-input/output for serial pd scl clock input for serial pd v cc power supply v ss ground nc no connection
hb52r168db-f 5 serial pd matrix * 1 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of bytes used by module manufacturer 1000000080 128 1 total spd memory size 0000100008 256 byte 2 memory type 0000010004 sdram 3 number of row addresses bits 000011000c 12 4 number of column addresses bits 000010100a 10 5 number of banks 0000000101 1 6 module data width 0100000040 64 7 module data width (continued) 0000000000 0 (+) 8 module interface signal levels 0000000101 lvttl 9 sdram cycle time (highest ce latency) 15 ns 11110000f0 cl = 3 10 sdram access from clock (highest ce latency) 9 ns 1001000090 11 module configuration type 0000000000 non parity 12 refresh rate/type 1000000080 normal (15.625 m s) self refresh 13 sdram width 0000010004 16m 4 14 error checking sdram width 0000000000 15 sdram device attributes: minimum clock delay for back- to-back random column addresses 0000000101 1 clk 16 sdram device attributes: burst lengths supported 100011118f 1, 2, 4, 8, full page 17 sdram device attributes: number of banks on sdram device 0000010004 4 18 sdram device attributes: ce latency 0000011006 2, 3 19 sdram device attributes: s latency 0000000101 0 20 sdram device attributes: w latency 0000000101 0 21 sdram module attributes 0000000000 non buffer
hb52r168db-f 6 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 22 sdram device attributes: general 000011100e v cc 10% 23 sdram cycle time (2nd highest ce latency) 15 ns 11110000f0 cl = 2 24 sdram access from clock (2nd highest ce latency) 9 ns 1001000090 25 sdram cycle time (3rd highest ce latency) undefined 0000000000 26 sdram access from clock (3rd highest ce latency) undefined 0000000000 27 minimum row precharge time 000111101e 30 ns 28 row active to row active min 0001010014 20 ns 29 re to ce delay min 000111101e 30 ns 30 minimum re pulse width 001111003c 60 ns 31 density of each bank on module 0010000020 128m byte 32 address and command signal input setup time 0011000030 3 ns 33 address and command signal input hold time 0001010115 1.5 ns 34 data signal input setup time 0011000030 3 ns 35 data signal input hold time 0001010115 1.5 ns 36 to 61 superset information 0000000000 future use 62 spd data revision code 0001001012 rev. 1.2a 63 checksum for bytes 0 to 62 010110105a 90 64 manuf a c t ur er ? s j edec id c ode 0000011107 hitachi 65 to 71 manuf a c t ur er ? s j edec id c ode 0000000000 72 manufacturing location * 3 (ascii- 8bit code) 73 manufacturer? part number 0100100048 h 74 manufacturer? part number 0100001042 b 75 manufacturer? part number 0011010135 5 76 manufacturer? part number 0011001032 2 77 manufacturer? part number 0101001052 r
hb52r168db-f 7 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 78 manufacturer? part number 0011000131 1 79 manufacturer? part number 0011011036 6 80 manufacturer? part number 0011100038 8 81 manufacturer? part number 0100010044 d 82 manufacturer? part number 0100001042 b 83 manufacturer? part number 001011012d 84 manufacturer? part number 0011000131 1 85 manufacturer? part number 0011000030 0 86 manufacture? part number 0100011046 f 87 manufacturer? part number (l-version) 010011004c l manufacturer? part number 0010000020 (space) 88 manufacturer? part number 0010000020 (space) 89 manufacturer? part number 0010000020 (space) 90 manufacturer? part number 0010000020 (space) 91 revision code 0011000030 initial 92 revision code 0010000020 (space) 93 manufacturing date year code (bcd)* 4 94 manufacturing date week code (bcd)* 4 95 to 98 assembly serial number * 6 99 to 125 manufacturer specific data * 5 126 intel specification frequency 0110011066 66 mhz 127 intel specification ce # latency support 0000011006 cl = 2, 3 notes: 1. all serial pd data are not protected. 0: serial data, ?riven low? 1: serial data, ?riven high these spd are based on intel specification (rev.1.2a). 2. regarding byte32 to 35, based on jedec committee ballot jc42.5-97-119. 3. byte72 is manufacturing location code. (ex: in case of japan, byte72 is 4ah. 4ah shows ??on ascii code.) 4. regarding byte93 and 94, based on jedec committee ballot jc42.5-97-135. bcd is ?inary coded decimal? 5. all bits of 99 through 125 are not defined (??or ??. 6. bytes 95 through 98 are assembly serial number.
hb52r168db-f 8 block diagram dqmb0 dq0 to dq7 * d0 to d15: hm5264405 u0: 2-kbit eeprom c0 to c15: 0.1 f n0 to n31: network resistors (10 w ) ras (d0 to d15) cas (d0 to d15) a0 to a11 a0 to a11(d0 to d15) cke0 cke (d0 to d15) ba0 a13 (d0 to d15) ba1 a12 (d0 to d15) v cc v cc (d0 to d15, u0) v ss v ss (d0 to d15, u0) serial pd sda a0 a1 a2 v ss scl u0 sda scl notes: 1. the sda pull-up resistor is required due to the open-drain/open-collector output. 2. the scl pull-up resistor is recommended because of the normal scl line inacitve "high" state. ck0 clk (d0, d1, d2, d3) 8 n0 to n3 n4 to n7 n8 to n11 n12 to n15 n16 to n19 n20 to n23 n24 to n27 n28 to n31 clk (d8, d9, d10, d11) c0-c15 d0 i/o0 to i/o3 i/o0 to i/o3 dqm dqm d1 ck1 clk (d4, d5, d6, d7) clk (d12, d13, d14, d15) re ce s0 w we cs we cs dqmb4 dq32 to dq39 8 d8 i/o0 to i/o3 i/o0 to i/o3 dqm dqm d9 we cs we cs dqmb1 dq8 to dq15 8 d2 i/o0 to i/o3 i/o0 to i/o3 dqm dqm d3 we cs we cs dqmb5 dq40 to dq47 8 d10 i/o0 to i/o3 i/o0 to i/o3 dqm dqm d11 we cs we cs dqmb2 dq16 to dq23 8 d4 i/o0 to i/o3 i/o0 to i/o3 dqm dqm d5 we cs we cs dqmb6 dq48 to dq55 8 d12 i/o0 to i/o3 i/o0 to i/o3 dqm dqm d13 we cs we cs dqmb3 dq24 to dq31 8 d6 i/o0 to i/o3 i/o0 to i/o3 dqm dqm d7 we cs we cs dqmb7 dq56 to dq63 8 d14 i/o0 to i/o3 i/o0 to i/o3 dqm dqm d15 we cs we cs
hb52r168db-f 9 absolute maximum ratings parameter symbol value unit note voltage on any pin relative to v ss v t ?.5 to v cc + 0.5 ( 4.6 (max)) v1 supply voltage relative to v ss v cc ?.5 to +4.6 v 1 short circuit output current iout 50 ma power dissipation p t 16 w operating temperature topr 0 to +65 c storage temperature tstg ?5 to +125 c note: 1. respect to v ss . dc operating conditions (ta = 0 to +65 c) parameter symbol min typ max unit notes supply voltage v cc 3.0 3.3 3.6 v 1, 2 v ss 000 v3 input high voltage v ih 2.0 v cc + 0.3 v 1, 4, 5 input low voltage v il ?.3 0.8 v 1, 6 ambient illuminance 100 lx notes: 1. all voltage referred to v ss 2. the supply voltage with all v cc pins must be on the same level. 3. the supply voltage with all v ss pins must be on the same level. 4. ck, cke, s , dqmb, dq pins: v ih (max) = v cc + 0.5 v for pulse width 5 ns at v cc . 5. others: v ih (max) = 4.6 v for pulse width 5 ns at v cc . 6. v il (min) = ?.0 v for pulse width 5 ns at v ss .
hb52r168db-f 10 dc characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) hb52r168db -10f/10fl parameter symbol min max unit test conditions notes operating current ( ce latency = 2) i cc1 960 ma burst length = 1 t rc = min 1, 2, 3 ( ce latency = 3) i cc1 960 ma standby current in power down i cc2p 24 ma cke0 = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 16 ma cke0 = v il , ck0/ck1 = v il or v ih fixed 7 standby current in non power down i cc2n 160 ma cke0, s = v ih , t ck = 12 ns 4 active standby current in power down i cc3p 64 ma cke0, s = v ih , t ck = 12 ns 1, 2, 6 active standby current in non power down i cc3n 288 ma cke0, s = v ih , t ck = 12 ns 1, 2, 4 burst operating current ( ce latency = 2) i cc4 880 ma t ck = min, bl = 4 1, 2, 5 ( ce latency = 3) i cc4 880 ma refresh current i cc5 1760 ma t rc = min 3 self refresh current i cc6 ?6mav ih 3 v cc ?0.2 v v il 0.2 v 8 self refresh current (l-version) i cc6 6.4 ma v ih 3 v cc ?0.2 v v il 0.2 v input leakage current i li ?0 10 m a0 vin v cc output leakage current i lo ?0 10 m a0 vout v cc dq = disable output high voltage v oh 2.4 v i oh = ? ma output low voltage v ol 0.4 v i ol = 2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, ck0/ck1 operating current. 7. after power down mode, no ck0/ck1 operating current. 8. after self refresh mode set, self refresh current.
hb52r168db-f 11 capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) parameter symbol max unit notes input capacitance (address) c in 90 pf 1, 2, 4 input capacitance ( re , ce , w , s , cke) c in 90 pf 1, 2, 4 input capacitance (ck) c in 60 pf 1, 2, 4 input capacitance (dqmb) c in 20 pf 1, 2, 4 input/output capacitance (dq) c i/o 20 pf 1, 2, 3, 4 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. measurement condition: f = 1 mhz, 1.4 v bias, 200 mv swing. 3. dqmb = v ih to disable data-out. 4. this parameter is sampled and not 100% tested. ac characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) hb52r168db -10f/10fl parameter symbol min max unit notes system clock cycle time ( ce latency = 2) t ck 15 ns 1 ( ce latency = 3) t ck 15 ck0/ck1 high pulse width t ckh 5 ns 1 ck0/ck1 low pulse width t ckl 5 ns 1 access time from ck0/ck1 ( ce latency = 2) t ac 9 ns 1, 2 ( ce latency = 3) t ac ? data-out hold time t oh 2.5 ns 1, 2 ck0/ck1 to data-out low impedance t lz 2 ns 1, 2, 3 ck0/ck1 to data-out high impedance t hz 7 ns 1, 4 data-in setup time t ds 3 ns 1 data in hold time t dh 1.5 ns 1 address setup time t as 3 ns 1 address hold time t ah 1.5 ns 1 cke0 setup time t ces 3 ns 1, 5 cke0 setup time for power down exit t cesp 3 ns 1 cke0 hold time t ceh 1.5 ns 1
hb52r168db-f 12 ac characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (cont) hb52r168db -10f/10fl parameter symbol min max unit notes command ( s0 , re , ce , w , dqmb) setup time t cs 3 ns 1 command ( s0 , re , ce , w , dqmb) hold time t ch 1.5 ns 1 ref/active to ref/active command period t rc 105 ns 1 active to precharge command period t ras 60 120000 ns 1 active command to column command (same bank) t rcd 30 ns 1 precharge to active command period t rp 30 ns 1 write recovery or data in to precharge lead time t dpl 30 ns 1 active (a) to active (b) command period t rrd 20 ns 1 transition time (rise and fall) t t 15ns refresh period t ref ?4ms notes: 1. ac measurement assumes t t = 1 ns. reference level for timing of input signals is 1.4 v. 2. access time is measured at 1.4 v. load condition is c l = 50 pf with current source. 3. t lz (min) defines the time at which the outputs achieves the low impedance state. 4. t hz (max) defines the time at which the outputs achieves the high impedance state. 5. t ces defines cke0 setup time to ck rising edge except power down exit command. test conditions input and output timing reference levels: 1.4 v input waveform and output load: see following figures ambient illuminance: under 100 lx t t 2.8 v v ss input 80% 20% t t 50 w +1.4 v dq cl
hb52r168db-f 13 relationship between frequency and minimum latency hb52r168db parameter -10f/10fl frequency (mhz) 66 t ck (ns) symbol 15 notes active command to column command (same bank) i rcd 21 active command to active command (same bank) ( ce latency = 2) i rc 7 = [i ras + i rp ] 1 ( ce latency = 3) i rc 8 active command to precharge command (same bank) ( ce latency = 2) i ras 4 1 ( ce latency = 3) i ras 5 precharge command to active command (same bank) i rp 31 write recovery or data input to precharge command (same bank) i dpl 21 active command to active command (different bank) i rrd 21 self refresh exit time i srex 22 last data in to active command (auto precharge, same bank) i apw 5 = [i dpl + i rp ] self refresh exit to command input i sec 7 = [i rc ] 3 precharge command to high impedance ( ce latency = 2) i hzp 2 ( ce latency = 3) i hzp 3 last data out to active command (auto precharge) (same bank) i apr 1 last data out to precharge (early precharge) ( ce latency = 2) i ep ? ( ce latency = 3) i ep ? column command to column command i ccd 1 write command to data in latency i wcd 0 dqmb to data in i did 0 dqmb to data out ( ce latency = 2) i dod 2 ( ce latency = 3) i dod 3 cke0 to ck0/ck1 disable i cle 1
hb52r168db-f 14 relationship between frequency and minimum latency (cont) hb52r168db parameter -10f/10fl frequency (mhz) 66 t ck (ns) symbol 15 notes register set to active command t rsa 3 s0 to command disable i cdd 0 power down exit to command input i pec 1 burst stop to output valid data hold ( ce latency = 2) i bsr 1 ( ce latency = 3) i bsr 2 burst stop to output high impedance ( ce latency = 2) i bsh 2 ( ce latency = 3) i bsh 3 burst stop to write data ignore i bsw 0 notes: 1. t rcd to t rrd are recommended value. 2. be valid [dsel] or [nop] at next command of self refresh exit. 3. except [dsel] and [nop]
hb52r168db-f 15 pin functions ck0/ck1 (input pin): ck is the master clock input to this pin. the other input signals are referred at ck rising edge. s0 (input pin): when s is low, the command input cycle becomes valid. when s is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. re , ce and w (input pins): although these pin names are the same as those of conventional dram modules, they function in a different way. these pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. for details, refer to the command operation section. a0 to a11 (input pins): row address (ax0 to ax11) is determined by a0 to a11 level at the bank active command cycle ck rising edge. column address (ay0 to ay9) is determined by a0 to a9 level at the read or write command cycle ck rising edge. and this column address becomes burst access start address. a10 defines the precharge mode. when a10 = high at the precharge command cycle, both banks are precharged. but when a10 = low at the precharge command cycle, only the bank that is selected by a12/a13 (ba) is precharged. a12/a13 (input pin): a12/a13 is a bank select signal (ba). the memory array of the hb52r168db is divided into bank0, bank1, bank2 and bank3, if a12 is low and a13 is low, bank0 is selected. if a12 is high and a13 is low, bank1 is selected. if a12 is low and a13 is high, bank2 is selected. if a12 is high and a13 is high, bank3 is selected. cke0 (input pin): this pin determines whether or not the next ck is valid. if cke is high, the next ck rising edge is valid. if cke is low, the next ck rising edge is invalid. this pin is used for power-down and clock suspend modes. dqmb0 to dqmb7 (input pins): read operation: if dqmb is high, the output buffer becomes high-z. if the dqmb is low, the output buffer becomes low-z. write operation: if dqmb is high, the previous data is held (the new data is not written). if dqmb is low, the data is written. dq0 to dq63 (dq pins): data is input to and output from these pins. v cc (power supply pins): 3.3 v is applied. v ss (power supply pins): ground is connected.
hb52r168db-f 16 command operation command truth table the sdram module recognizes the following commands specified by the s , re , ce , w and address pins. cke command symbol n - 1 n s recew a12/ a13 a10 a0 to a11 ignore command desl h h no operation nop h l hhh burst stop in full page bst h l hhl column address and read command read h lhlhvlv read with auto-precharge read a h lhlhvhv column address and write command writ h lhllvlv write with auto-precharge writ a h lhllvhv row address strobe and bank act. actv h l l hhvvv precharge select bank pre h llhlvl precharge all bank pall h llhl h refresh ref/self h v lllh mode register set mrs h llllvvv note: h: v ih . l: v il . : v ih or v il . v: valid address input ignore command [desl]: when this command is set ( s is high), the sdram module ignore command input at the clock. however, the internal status is held. no operation [nop]: this command is not an execution command. however, the internal operations continue. burst stop in full-page [bst]: this command stops a full-page burst operation (burst length = full-page), and is illegal otherwise. when data input/output is completed for a full page of data, it automatically returns to the start address, and input/output is performed repeatedly. column address strobe and read command [read]: this command starts a read operation. in addition, the start address of burst read is determined by the column address and the bank select address (ba). after the read operation, the output buffer becomes high-z. read with auto-precharge [read a]: this command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4, or 8. when the burst length is full-page, this command is illegal.
hb52r168db-f 17 column address strobe and write command [writ]: this command starts a write operation. when the burst write mode is selected, the column address and the bank select address (ba) become the burst write start address. when the single write mode is selected, data is only written to the location specified by the column address and the bank select address (ba). write with auto-precharge [writ a]: this command automatically performs a precharge operation after a burst write with a length of 1, 2, 4, or 8, or after a single write operation. when the burst length is full-page, this command is illegal. row address strobe and bank activate [actv]: this command activates the bank that is selected by bank select address (ba) and determines the row address (ax0 to ax11). when a12 and a13 are low, bank0 is activated. when a12 is high and a13 is low, bank1 is activated. when a12 is low and a13 is high, bank2 is activated. when a12 and a13 are high, bank3 is activated. precharge selected bank [pre]: this command starts precharge operation for the bank selected by a12/a13. if a12 and a13 are low, bank0 is selected. if a12 is high and a13 is low, bank1 is selected. if a12 is low and a13 is high, bank2 is selected. if a12 and a13 are high, bank3 is selected. precharge all banks [pall]: this command starts a precharge operation for all banks. refresh [ref/self]: this command starts the refresh operation. there are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. for details, refer to the cke0 truth table section. mode register set [mrs]: the sdram module has a mode register that defines how it operates. the mode register is specified by the address pins (a0 to a13) at the mode register set cycle. for details, refer to the mode register configuration. after power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. dqmb truth table cke command symbol n - 1 n dqmb write enable/output enable enb h l write inhibit/output disable mask h h note: h: v ih . l: v il . : v ih or v il . read: i dod is needed. write: i dod is needed. the sdram module can mask input/output data by means of dqmb during reading, the output buffer is set to low-z by setting dqmb to low, enabling data output. on the other hand, when dqmb is set to high, the output buffer becomes high-z, disabling data output. during writing, data is written by setting dqmb to low. when dqmb is set to high, the previous data is held (the new data is not written). desired data can be masked during burst read or burst write by setting dqmb. for details, refer to the dqmb control section of the sdram module operating instructions.
hb52r168db-f 18 cke truth table cke current state command n-1 n s recew address active clock suspend mode entry h l any clock suspend l l clock suspend clock suspend mode exit l h idle auto refresh command ref h h l l l h idle self refresh entry self h l l l l h idle power down entry h l l h h h hlh self-refresh self refresh exit selfx l h l h h h lhh power down power down exit l h l h h h lhh note: h: v ih . l: v il . : v ih or v il . clock suspend mode entry: the sdram module enters clock suspend mode from active mode by setting cke to low. if command is input in the clock suspend mode entry cycle, the command is valid. the clock suspend mode changes depending on the current status (1 clock before) as shown below. active clock suspend: this suspend mode ignores inputs after the next clock by internally maintaining the bank active status. read suspend and read with auto-precharge suspend: the data being output is held (and continues to be output). write suspend and writ with auto-precharge suspend: in this mode, external signals are not accepted. however, the internal state is held. clock suspend: during clock suspend mode, keep the cke to low. clock suspend mode exit: the sdram module exits from clock suspend mode by setting cke to high during the clock suspend state. idle: in this state, all banks are not selected, and completed precharge operation. auto refresh command [ref]: when this command is input from the idle state, the sdram module starts auto refresh operation. (the auto refresh is the same as the cbr refresh of conventional dram module.) during the auto refresh operation, refresh address and bank select address are generated inside the sdram module. for every auto refresh cycle, the internal address counter is updated. accordingly, 4096 times are required to refresh the entire memory. before executing the auto refresh command, all the banks must be in the idle state. in addition, since the precharge for all banks is automatically performed after auto refresh, no precharge command is required after auto refresh.
hb52r168db-f 19 self refresh entry [self]: when this command is input during the idle state, the sdram module starts self refresh operation. after the execution of this command, self refresh continues while cke0 is low. since self refresh is performed internally and automatically, external refresh operations are unnecessary. power down mode entry: when this command is executed during the idle state, the sdram module enters power down mode. in power down mode, power consumption is suppressed by cutting off the initial input circuit. self refresh exit: when this command is executed during self refresh mode, the sdram module can exit from self refresh mode. after exiting from self refresh mode, the sdram module enters the idle state. power down exit: when this command is executed at the power down mode, the sdram module can exit from power down mode. after exiting from power down mode, the sdram module enters the idle state. function truth table the following table shows the operations that are performed when each command is issued in each mode of the sdram module. the following table assumes that cke is high. current state srecew address command operation precharge h desl enter idle after t rp lhhh nop enter idle after t rp lhhl bst nop l h l h ba, ca, a10 read/read a illegal l h l l ba, ca, a10 writ/writ a illegal l l h h ba, ra actv illegal l l h l ba, a10 pre, pall nop lllh ref, self illegal l l l l mode mrs illegal idle h desl nop lhhh nop nop lhhl bst nop l h l h ba, ca, a10 read/read a illegal l h l l ba, ca, a10 writ/writ a illegal l l h h ba, ra actv bank and row active l l h l ba, a10 pre, pall nop lllh ref, self refresh l l l l mode mrs mode register set
hb52r168db-f 20 current state srecew address command operation row active h desl nop lhhh nop nop lhhl bst nop l h l h ba, ca, a10 read/read a begin read l h l l ba, ca, a10 writ/writ a begin write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall precharge lllh ref, self illegal l l l l mode mrs illegal read h desl continue burst to end lhhh nop continue burst to end lhhl bst burst stop to full page l h l h ba, ca, a10 read/read a continue burst read to ce latency and new read l h l l ba, ca, a10 writ/writ a term burst read/start write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall term burst read and precharge lllh ref, self illegal l l l l mode mrs illegal read with auto-precharge h desl continue burst to end and precharge lhhh nop continue burst to end and precharge lhhl bst illegal l h l h ba, ca, a10 read/read a illegal l h l l ba, ca, a10 writ/writ a illegal l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall illegal lllh ref, self illegal l l l l mode mrs illegal
hb52r168db-f 21 current state srecew address command operation write h desl continue burst to end lhhh nop continue burst to end lhhl bst burst stop on full page l h l h ba, ca, a10 read/read a term burst and new read l h l l ba, ca, a10 writ/writ a term burst and new write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall term burst write and precharge* 2 lllh ref, self illegal l l l l mode mrs illegal write with auto-precharge h desl continue burst to end and precharge lhhh nop continue burst to end and precharge lhhl bst illegal l h l h ba, ca, a10 read/read a illegal l h l l ba, ca, a10 writ/writ a illegal l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall illegal lllh ref, self illegal l l l l mode mrs illegal refresh (auto refresh) h desl enter idle after t rc lhhh nop enter idle after t rc lhhl bst enter idle after t rc l h l h ba, ca, a10 read/read a illegal l h l l ba, ca, a10 writ/writ a illegal l l h h ba, ra actv illegal l l h l ba, a10 pre, pall illegal lllh ref, self illegal l l l l mode mrs illegal notes: 1. h: v ih . l: v il . : v ih or v il . the other combinations are inhibit. 2. an interval of t dpl is required between the final valid data input and the precharge command. 3. if t rrd is not satisfied, this operation is illegal.
hb52r168db-f 22 from precharge state, command operation to [desl], [nor] or [bst]: when these commands are executed, the sdram module enters the idle state after t rp has elapsed from the completion of precharge. from idle state, command operation to [desl], [nop], [bst], [pre] or [pall]: these commands result in no operation. to [actv]: the bank specified by the address pins and the row address is activated. to [ref], [self]: the sdram module enters refresh mode (auto refresh or self refresh). to [mrs]: the sdram module enters the mode register set cycle. from row active state, command operation to [desl], [nop] or [bst]: these commands result in no operation. to [read], [read a]: a read operation starts. (however, an interval of t rcd is required.) to [writ], [writ a]: a write operation starts. (however, an interval of t rcd is required.) to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands set the sdram module to precharge mode. (however, an interval of t ras is required.) from read state, command operation to [desl], [nop]: these commands continue read operations until the burst operation is completed. to [bst]: this command stops a full-page burst. to [read], [read a]: data output by the previous read command continues to be output. a f t e r ce latency, the data output resulting from the next command will start. to [writ], [writ a]: these commands stop a burst read, and start a write cycle. to [actv]: this command makes other banks bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop a burst read, and the sdram module enters precharge mode.
hb52r168db-f 23 from read with auto precharge state, command operation to [desl], [nop]: these commands continue read operations until the burst operation is completed, and the sdram module then enters precharge mode. to [actv]: this command makes other banks bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. from write state, command operation to [desl], [nop]: these commands continue write operations until the burst operation is completed. to [bst]: this command stops a full-page burst. to [read], [read a]: these commands stop a burst and start a read cycle. to [writ], [writ a]: these commands stop a burst and start the next write cycle. to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop burst write and the sdram module then enters precharge mode. from write with auto-precharge state, command operation to [desl], [nop]: these commands continue write operations until the burst is completed, and the sdram module enters precharge mode. to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. from refresh state, command operation to [desl], [nop], [bst]: after an auto-refresh cycle (after t rc ), the sdram module automatically enters the idle state.
hb52r168db-f 24 simplified state diagram precharge write suspend read suspend row active idle idle power down auto refresh self refresh mode register set power on writea writea suspend reada reada suspend active clock suspend sr entry sr exit mrs refresh cke cke_ active write read write with ap read with ap power applied cke cke_ cke cke_ cke cke_ cke cke_ cke cke_ precharge ap read write write with ap read with read with ap write with ap precharge precharge precharge bst (on full page) bst (on full page) *1 read read write write automatic transition after completion of command. transition resulting from command input. note: 1. after the auto-refresh operation, precharge operation is performed automatically and enter the idle state.
hb52r168db-f 25 mode register configuration the mode register is set by the input to the address pins (a0 to a13) during mode register set cycles. the mode register consists of five sections, each of which is assigned to address pins. a13, a12, a11, a10, a9, a8: (opcode): the sdram module has two types of write modes. one is the burst write mode, and the other is the single write mode. these bits specify write mode. burst read and burst write: burst write is performed for the specified burst length starting from the column address specified in the write cycle. burst read and single write: data is only written to the column address specified during the write cycle, regardless of the burst length. a7: keep this bit low at the mode register set cycle. if this pin is high, the vender test mode is set. a6, a5, a4: (lmode): these pins specify the ce latency. a3: (bt): a burst type is specified. when full-page burst is performed, only ?equential?can be selected. a2, a1, a0: (bl): these pins specify the burst length. a2 a1 a0 burst length 00 0 1 00 1 2 01 0 4 01 1 8 1 1 1 f.p. bt=0 bt=1 10 0 r 11 0 r 1 2 4 8 r r r a3 0 sequential 1 interleave burst type a6 a5 a4 cas latency 00 0 r 00 1 r 01 0 2 01 1 3 1xx r a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 opcode 0 lmode bt bl a9 0 0r write mode a8 0 1 burst read and burst write 1 burst read and single write 0 1r 1 10 1 r r f.p. = full page r is reserved (inhibit) x: 0 or 1 a11 a10 a10 x x x a11 x x x 00 a12 a13 a13 x x x 0 a12 x x x 0
hb52r168db-f 26 burst sequence a2 a1 a0 addressing(decimal) 00 0 00 1 01 0 01 1 11 1 interleave sequential 10 0 11 0 10 1 starting ad. 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 7, 0, 0, 1, 0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 7, 6, 4, 5, 6, 5, 4, 0, 1, 2, 3, 6, 1, 0, 3, 2, 4, 5, 2, 3, 0, 1, 6, 5, 4, 3, 2, 1, 0, burst length = 8 a1 a0 addressing(decimal) 00 01 10 11 interleave sequential starting ad. 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, burst length = 4 a0 addressing(decimal) 0 1 interleave sequential starting ad. 0, 1, 1, 0, 0, 1, 1, 0, burst length = 2
hb52r168db-f 27 operation of the sdram module read/write operations bank active: before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (actv) command. bank0, bank1, bank2 or bank3 is activated according to the status of the bank select address pin, and the row address (ax0 to ax11) is activated by the a0 to a11 pins at the bank active command cycle. an interval of t rcd is required between the bank active command input and the following read/write command input. read operation: a read operation starts when a read command is input. output buffer becomes low-z in the ( ce latency-1) cycle after read command set. the sdram module can perform a burst read operation. the burst length can be set to 1, 2, 4, 8 or full-page. the start address for a burst read is specified by the column address and the bank select address (ba) at the read command set cycle. in a read operation, data output starts after the number of clocks specified by the ce latency. the ce latency can be set to 2 or 3. when the burst length is 1, 2, 4, or 8, full-page, the dout buffer automatically becomes high-z at the next clock after the successive burst-length data has been output. the ce latency and burst length must be specified at the mode register. ce latency read ck command dout actv row column address cl = 2 cl = 3 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 t rcd cl = ce latency burst length = 4
hb52r168db-f 28 burst length read ck command dout actv row column out 0 out 6 out 7 out 8 address out 0 out 1 out 4 out 5 out 0 out 1 out 2 out 3 bl = 1 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 6 out 7 out 4 out 5 out 0-1 out 0 out 1 bl = 2 bl = 4 bl = 8 bl = full page t rcd bl : burst length cas latency = 2 write operation: burst write or single write mode is selected by the opcode (a13, a12, a11, a10, a9, a8) of the mode register. burst write a burst write operation is enabled by setting opcode (a9, a8) to (0, 0). a burst write starts in the same clock as a write command set. (the latency of data input is 0 clock.) the burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. the write start address is specified by the column address and the bank select address (ba) at the write command set cycle. writ ck command din actv row column in 0 in 6 in 7 in 8 address in 1 in 4 in 5 in 3 bl = 1 in 6 in 7 in 4 in 5 in 0-1 in 0 in 1 bl = 2 bl = 4 bl = 8 bl = full page t rcd in 0 in 0 in 0 in 0 in 1 in 1 in 1 in 2 in 2 in 2 in 3 in 3 ce latency = 2, 3
hb52r168db-f 29 single write a single write operation is enabled by setting opcode (a9, a8) to (1, 0). in a single write operation, data is only written to the column address and the bank select address (ba) specified by the write command set cycle without regard to the burst length setting. (the latency of data input is 0 clock). writ ck command din actv row column in 0 address t rcd ce latency = 2, 3 burst length = 1, 2, 4, 8, full page auto precharge read with auto precharge: in this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. the command executed for the same bank after the execution of this command must be the bank active (actv) command. in addition, an interval defined by i apr is required before execution of the next command. ce latency precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output burst read (burst length = 4) ck l apr l ras l apr cl=2 command cl=3 command dout dout note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ". actv read a actv out3 out2 out1 out0 l ras actv read a actv out3 out2 out1 out0
hb52r168db-f 30 write with auto-precharge: in this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. the command executed for the same bank after the execution of this command must be the bank active (actv) command. in addition, an interval of l apw is required between the final valid data input and input of next command. burst write (burst length = 4) ck command din l apw i ras actv writ a in0 in1 in2 in3 actv note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ". single write ck command din l apw i ras actv writ a in actv note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ".
hb52r168db-f 31 full-page burst stop burst stop command during burst read: the burst stop (bst) command is used to stop data output during a full-page burst. the bst command sets the output buffer to high-z and stops the full-page burst read. the timing from command input to the last data changes depending on the ce latency setting. in addition, the bst command is valid only during full-page burst mode, and is invalid with burst lengths 1, 2, 4 and 8. ce latency bst to valid data bst to high impedance 21 2 32 3 ce latency = 2, burst length = full page l = 1 cycle bsr ck command dout out out out out l = 2 cycle bsh bst out out ce latency = 3, burst length = full page l = 2 cycle bsr ck command dout out out out out l = 3 cycle bsh bst out out out
hb52r168db-f 32 burst stop command at burst write: the burst stop command (bst command) is used to stop data input during a full-page burst write. no data is written in the same clock as the bst command and in subsequent clocks. in addition, the bst command is only valid during full-page burst mode, and is invalid with burst lengths of 1, 2, 4 and 8. and an interval of t dpl is required between last data-in and the next precharge command. burst length = full page t ck command din in dpl in pre/pall bst i = 0 cycle bsw
hb52r168db-f 33 command intervals read command to read command interval: 1. same bank, same row address : when another read command is executed at the same row address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. read to read command interval (same row address in same bank) ck command dout out b3 address out b1 out b2 ba actv row column a read read column b out a0 out b0 bank0 active column =a read column =b read column =a dout column =b dout ce latency = 3 burst length = 4 bank 0 2. same bank, different row address: when the row address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. 3. different bank: when the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. read to read command interval (different bank) ck command dout out b3 address out b1 out b2 ba actv row 0 row 1 actv read column a out a0 out b0 bank0 active bank3 active bank0 read bank3 read read column b bank0 dout bank3 dout ce latency = 3 burst length = 4
hb52r168db-f 34 write command to write command interval: 1. same bank, same row address: when another write command is executed at the same row address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. in the case of burst writes, the second write command has priority. write to write command interval (same row address in same bank) ck command din in b3 address in b1 in b2 ba actv row column a writ writ column b in a0 in b0 bank0 active column =a write column =b write burst write mode burst length = 4 bank 0 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. 3. different bank: when the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. in the case of burst write, the second write command has priority. write to write command interval (different bank) ck command din in b3 address in b1 in b2 ba actv row 0 row 1 actv writ column a in a0 in b0 bank0 active bank3 active bank0 write bank3 write writ column b burst write mode burst length = 4
hb52r168db-f 35 read command to write command interval: 1. same bank, same row address: when the write command is executed at the same row address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. however, dqmb must be set high so that the output buffer becomes high-z before data input. read to write command interval (1) ck command dout in b2 in b3 read writ in b0 in b1 high-z din cl=2 cl=3 dqmb burst length = 4 burst write read to write command interval (2) ck command dout read writ din cl=2 cl=3 dqmb high-z 2 clock high-z 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank- active command. 3. different bank: when the bank changes, the write command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. however, dqmb must be set high so that the output buffer becomes high-z before data input.
hb52r168db-f 36 write command to read command interval: 1. same bank, same row address: when the read command is executed at the same row address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. however, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. write to read command interval (1) ck command din writ read in a0 out b1 out b2 out b3 out b0 dout column = a write column = b read column = b dout ce latency dqmb burst write mode ce latency = 2 burst length = 4 bank 0 write to read command interval (2) ck command din writ read in a0 out b1 out b2 out b3 out b0 dout column = a write column = b read column = b dout ce latency in a1 dqmb burst write mode ce latency = 2 burst length = 4 bank 0 2. same bank, different row address: when the row address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank- active command. 3. different bank: when the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).
hb52r168db-f 37 read command to precharge command interval (same bank): when the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. however, since the output buffer then becomes high-z after the clocks defined by i hzp , there is a case of interruption to burst read data output will be interrupted, if the precharge command is input during burst read. to read all data by burst read, the clocks defined by i ep must be assured as an interval from the final data output to precharge command execution. read to precharge command interval (same bank): to output all data ce latency = 2, burst length = 4 ck command dout read pre/pall out a0 out a1 out a2 out a3 cl=2 l = -1 cycle ep ce latency = 3, burst length = 4 ck command dout read pre/pall out a0 out a1 out a2 out a3 cl=3 l = -2 cycle ep
hb52r168db-f 38 read to precharge command interval (same bank): to stop output data ce latency = 2, burst length = 1, 2, 4, 8, full page burst ck command dout read pre/pall out a0 high-z l hzp = 2 ce latency = 3, burst length = 1, 2, 4, 8, full page burst ck command dout read pre/pall out a0 high-z l hzp = 3
hb52r168db-f 39 write command to precharge command interval (same bank): when the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. however, if the burst write operation is unfinished, the input data must be masked by means of dqmb for assurance of the clock defined by t dpl . write to precharge command interval (same bank) burst length = 4 ( to stop write operation) ck command din writ pre/pall t dpl dqmb ck in a0 in a1 command din writ pre/pall dqmb t dpl burst length = 4 (to write all data) ck in a0 in a1 in a2 command din writ pre/pall in a3 dqmb t dpl
hb52r168db-f 40 bank active command interval: 1. same bank: the interval between the two bank-active commands must be no less than t rc . bank active to bank active for same bank ck command address ba bank 0 active actv row actv row bank 0 active t rc 2. in the case of different bank-active commands: the interval between the two bank-active commands must be no less than t rrd . bank active to bank active for different bank ck command address ba bank 0 active bank 3 active actv row:0 actv row:1 t rrd
hb52r168db-f 41 mode register set to bank-active command interval: the interval between setting the mode register and executing a bank-active command must be no less than l rsa . ck command address mode register set bank active mrs actv i rsa bs & row code
hb52r168db-f 42 dqmb control the dqmb mask the lower and upper bytes of the dq data, respectively. the timing of dqmb is different during reading and writing. reading: when data is read, the output buffer can be controlled by dqmb. by setting dqmb to low, the output buffer becomes low-z, enabling data output. by setting dqmb to high, the output buffer becomes high-z, and the corresponding data is not output. however, internal reading operations continue. the latency of dqmb during reading is 2 clocks. ck dout out 0 out 1 l = 2 latency out 3 dod dqmb high-z writing: input data can be masked by dqmb. by setting dqmb to low, data can be written. in addition, when dqmb is set to high, the corresponding data is not written, and the previous data is held. the latency of dqmb during writing is 0 clock. ck din in 0 in 1 l = 0 latency in 3 did dqmb
hb52r168db-f 43 refresh auto-refresh: all the banks must be precharged before executing an auto-refresh command. since the auto- refresh command updates the internal counter every time it is executed and determines the banks and the row addresses to be refreshed, external address specification is not required. the refresh cycle is 4096 cycles/64 ms. (4096 cycles are required to refresh all the row addresses.) the output buffer becomes high- z after auto-refresh start. in addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. self-refresh: after executing a self-refresh command, the self-refresh operation continues while cke is held low. during self-refresh operation, all row addresses are refreshed by the internal refresh timer. a self- refresh is terminated by a self-refresh exit command. before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below. (1) enter self-refresh mode within 15.6 m s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. (2) start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 m s after exiting from self-refresh mode. others power-down mode: the sdram module enters power-down mode when cke goes low in the idle state. in power down mode, power consumption is suppressed by deactivating the input initial circuit. power down mode continues while cke is held low. in addition, by setting cke to high, the sdram module exits from the power down mode, and command input is enabled from the next clock. in this mode, internal refresh is not performed. clock suspend mode: by driving cke to low during a bank-active or read/write operation, the sdram module enters clock suspend mode. during clock suspend mode, external input signals are ignored and the internal state is maintained. when cke is driven high, the sdram module terminates clock suspend mode, and command input is enabled from the next clock. for details, refer to the ?ke truth table? power-up sequence: the sdram module should be initialized by the following sequence with power up. the ck, cke, s , dqmb and dq pins keep low till power stabilizes. the ck pin is stabilized within 100 m s after power stabilizes before the following initialization sequence. the cke and dqmb is driven to high between power stabilizes and the initialization sequence. this sdram module has v cc clamp diodes for ck, cke, s dqmb and dq pins. if these pins go high before power up, the large current flows from these pins to v cc through the diodes. initialization sequence: when 200 m s or more has past after the above power on, all banks must be precharged using the precharge command (pall). after t rp delay, set 8 or more auto refresh commands (ref). set the mode register set command (mrs) to initialize the mode register. we recommend that by keeping dqm, dqmu/dqml to high, the output buffer becomes high-z during initialization sequence, to avoid dq bus contention on memory system formed with a number of device.
hb52r168db-f 44 v cc power up sequence initialization sequence 100 s 0 v low low low cke, dqmb ck s , dq 200 s power stabilize
hb52r168db-f 45 timing waveforms read cycle bank 0 active bank 0 read ck cke s t ras t rcd t ch t cs # #

0 1 8 9 0 1 8 9 3 : ; 3 : ;

1 8 9 1 8 9 ; < ; < re ce w ba + 2 3 : + 2 3 : ! " ) * 0 1 8 ! " ) * 0 1 8 ! " ) 0 1 8 ( / 7 ? : ( 0 7 ? ( 0 78 ? " * + 2 : 1 9 : a10 address dqmb din dout t ch t cs t ckh t t ck ckl t rp t rc ce latency = 2 burst length = 4 bank 0 access = v or v 1 9 t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as v ih ih il bank 0 precharge , 3 4 < 3 ; < ; t ac t ac t ac t oh t oh t oh t oh t ac 2 : ; t lz , - 4 t hz % , - 3 4 ; < c d k l ' / 6 7 > ? & ' . / 5 6 < = & ' . / 5 6 < = $ % , - 4 $ % , - 4
& - . 4 5 < % & - . 4 5 < % & - . 4 5 < " # + 6 > ? # $ + , # $ + , ( ( ' ' ' ? ?
$ % , 0 1 3 4 8 : ; # $ + 2 3 7 : ? ' / 6 7 > ?
hb52r168db-f 46 write cycle ck cke s t ras t rcd , - 4 5 < " # " #
$ + , 3 " # $ +
re ce w ba a10 address din dout t ch t cs t ckh t t ck t dh t dh ckl t dh t dh t ds t ds t ds t ds t rp t rc t dpl bank 0 write t ch t cs bank 0 active bank 0 precharge t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ah t as t ah t as t ah t as t ch t cs t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ch t cs t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ah t as " ) " ) * 1 2 8 9 & - ! " $ % ! " ( ) 0 1 8 8 ? . / 6 7 = > ' / ! ( /0
: ; $ % 0 8 ? % & , - 4 5 ; < 8 " & - . 5 6 < = & '

( / / 7 > ? $ % & - & v ih ce latency = 2 burst length = 4 bank 0 access = v or v ! " ih il dqmb
hb52r168db-f 47 mode register set cycle m n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ck cke s re ce w ba address dqmb din dout @ h i & ' / d m n h p & . / 7 & ' / $ % - . - 6 > g f g o p ; c d k l high-z b b+3 b? b?+1 b?+2 b?+3 l valid c: b? rsa code l rcd l rp precharge if needed mode register set bank 3 active bank 3 read h ? @ h i / 7 8 a & . / 7 8 ; d l m ' ( / 0 ( n 6 ? @ h - 6 ? g o p % & - . 7 & r: b c: b . 6 7 ? @ h p 4 5 < = f output mask v ih l = 3 ce latency = 3 burst length = 4 = v or v ih il rcd
hb52r168db-f 48 read cycle/write cycle 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 cke re s ce w address dqmb dout din ck ba = f o < = e < = e f f g o = e f r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3

h i
i a b j k 8 a j 7 8 @ a a b j 8 @ a j i j @ i i j @ i 9 : b 0 9 b ' 0 8 9 ' / 0 8 9 ' / 0 8 a ( 1 : ' ( 0 1 ' ( 0 ( 0 1 ' ( 0 5 > f g 4 5 = f + 4 5 = 5 = > f 4 5 = > f - 5 > + , 5 , 5 > , 5 > # , 5 $ % - #$ , # , $ - $ , %

( ! ( ) 1 2 ( ) 1 ( 1 ( k l b k l b j k 9 b j k j k k j k 9 a b j bank 0 active bank 0 read bank 3 active bank 3 read bank 3 read bank 3 read bank 0 precharge bank 3 precharge bank 0 active bank 0 write bank 3 active bank 3 write bank 3 write bank 3 write bank 0 precharge bank 3 precharge cke re s ce w address dqmb din dout ba high-z high-z 4 5 = e f $ % / 7 8 ? @ i 1 9 : b c v ih v ih read cycle re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il write cycle re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ! ih il
hb52r168db-f 49 read/single write cycle n e m n e n e m n f g o p = e f n o = f g n o = e f n 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 $ , # , ! * ! * r:a c:a r:b c:a' # , # , r:a c:a c:a $ - ! a a a a $ $

bank 0 active bank 0 read bank 3 active bank 0 write bank 0 precharge bank 3 precharge bank 0 active bank 0 read bank 0 write bank 0 precharge ) * 2 ) * 2 ) 2 ) < = e n r:b bank 3 active > f g p = > f g = > f 4 = > f + 4 = k l k l b j k 9 b j k $ % - 6 > $ % - 5 > $ ,- 5 > $ , 4 5 > # + , 4 5 8 9 a i j
9 a b i j
9 a b j k
9 b j k
b k l c:a bank 0 read a a+1 a+2 a+3

9 a b j k

% %

bank 0 write bank 0 write cke re s ce w address dqmb din dout ck ba cke re s ce w address dqmb ba ' ( 0 1 9 ( ) 0 1 9 : ) 2 : ; c l ) 1 2 9 : c ( ) 1 2 9 : c:b bc a+1 a+3 a+1 a+2 a+3 c:c ! " * + 2 3 ) ! * ! * 3 > f g o p # + , 3 4 < = ) 1 2 : & v ih v ih read/single write re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il din dout
hb52r168db-f 50 read/burst write cycle < d e n 2 ; < d < d e ; < d < e n 4 < = e f 3 4 < e 4 < = e * 3 4 < & / 0 7 8 ? @ i / 0 8 @ a i 0 8 9 @ a i j 0 8 9 a b i j & ' & ' 0 ' ( 0 ( ) 0 1 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 # r:a c:a r:b c:a' # r:a c:a c:a
j
a i j @ a i # a a+1 a+2 a+3 a+1 a a+1 a+2 a+3 h p

i h i ? h i ? h bank 0 active bank 0 read bank 0 write bank 0 precharge ' ( 0 1 ) & . / 7 8 ? @ * 2 3 < r:b bank 3 active 4 5 = + 4 5 = " + 4 " * + 4 " * + 9 b j k 9 a b j 8 9 a b j / 8 9 @ a / 7 8 @ a h i #$ , 5 # + , 5 " # + , " # + " # + cke re s ce w address dqmb ck ba cke re s ce w address dqmb ba a+1 a+2 a+3 a a+3 a
a i j ' ( 0 1 * 2 3 : ; c d " + 3 4 < & ' bank 0 active bank 0 read bank 3 active clock suspend bank 0 write bank 0 precharge bank 3 precharge & ' . / 6 7 @ " v ih read/burst write re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il din dout din dout
hb52r168db-f 51 full page read/write cycle high-z

z r:a c:a r:b
e o y d e n d e n o o y e n o r:a c:a r:b high-z
\ [ \ q z [ [ \ q [ \ \ ] h r \ h q r r \ h q r \ 2 < f o ; d e o 1 ; d e 2 < e o 2 ;< e o 2 3 < ( 12 ; ( 2 3 < ( 2 < ( 2 ; # # $ # $ . $ % . bank 0 active bank 0 read bank 3 active burst stop bank 3 precharge bank 0 active bank 0 write bank 3 active burst stop bank 3 precharge @ i j s ] ? @ i j r s ? @ h i r s 5 ? @ h i r 5 > ? h i r # , - 5 6 ? @ - 6 7 @ a j # - 6 7 ? @ j # , - 6 7 ? @ $ - . # $ - . # $ - s t ] ^ t ] ^ t ^ ^ ] " # , 5 6 ? * ) * 2 3 ( ) 2 3 ( ) 2 ( ) 2 ( 2 s t \ ] cke re s ce w address dqmb din dout ck ba cke re s ce w address dqmb ba ; d e n o x d m n v w a > h q r v ih v ih a a+1 a+2 a+3 read cycle re - ce delay = 3 ce latency = 3 burst length = full page = v or v ih il write cycle re - ce delay = 3 ce latency = 3 burst length = full page = v or v ih il a a+1 a+2 a+3 a+6 a+5 a+4 din dout
hb52r168db-f 52 auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ck cke s ce w ba address dqmb din dout ' ( / 0 7 8 @ a h i
m n % & / 8 @ a h i high-z rp ! ) * 1 2 : ; 1 : b c 8 @ a i j
/ 8 9 a " # + ? h i 4 5 = > ' = e f n ? h & ' / 0 8 precharge if needed auto refresh active bank 0 t rc t rc t auto refresh read bank 0 r:a c:a a10=1 re ! * 2 3 : ; d : c d l
a i j

$ , 5 = > b f j k o a a+1 v ih refresh cycle and read cycle re - ce delay = 2 ce latency = 2 burst length = 4 = v or v ih il self refresh cycle $ % - . 6 ck cke s re ce w ba address dqmb din dout
$ , 1 2 4 5 : ; = > b c f j k . 6 7 ? @ h . 7 8 ? @ h ) 2 : ; : b c l
: b c j k $ , 5 = > e f n ? h p 6 7 ? h p ' ( 5 = > $ , 5 precharge command if needed self refresh entry command auto refresh self refresh exit ignore command or no operation f g o p ' ( 0 1 7 ? @ h i ( n o ? h p n o cke low ! " ) * 2 7 : ; ? @ c h k l a10=1 rc t rp t # ,
#$ , 4 5 = > e f m n
#$ , 4 5 < = e f m n self refresh cycle re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il high-z next clock enable 5 > f g n o 5 = > f n o 4 5 = > e f n rc t next clock enable l srex self refresh entry command
hb52r168db-f 53 clock suspend mode 1 9 : b c ( ( ) ! ( ) ! ( ) 2 ( f n o ' ' 0 4 5 = f 5 = > f g 0 1 2 3 4 5 6 7 8 9 101112131415161718192021 ! ' / 0 & / $ ,- 5 > # + , 4 < = $ - 5 > r:a c:a r:b a a+1 a+2 a+3 b b+1 b+2 # , 4 5 & ' /
! r:a c:a r:b c:b
a a+1 a+2 b b+1 b+2 b+3 ' / 0 9 , 4 5 > & ' /
c:b bank0 active active clock suspend start active clock supend end bank0 read bank3 active read suspend end bank0 precharge bank3 read precharge bank0 write bank0 active active clock suspend start active clock suspend end bank3 active write suspend start write suspend end bank3 write bank0 precharge earliest bank3 precharge b+3 5 = > f 4 5 = > f ' ' ( 0 e f n o e f m n < e f m n < d e m n
a i j 8 @ a h i 8 @ a i j
a j k ( 1 2 9 : b k ( 0 1 9 : b ' ( 0 8 9
8 a i j ( 0 1 8 9 b ' ( / 0 8 & ' / cke re s ce w address dqmb ck ba cke re s ce w address dqmb ba a+3 high-z high-z
$ ,- 5 6 ? g 2 ; < c d l 0 8 9 a b i j & ' ' ( t ces t ceh t ces read cycle re - ce delay = 2 ce latency = 2 burst length = 4 = v or v ih il write cycle re - ce delay = 2 ce latency = 2 burst length = 4 = v or v ih il
a j k dout din dout din read suspend start earliest bank3
hb52r168db-f 54 power down mode ck cke s re ce w ba address dqmb din dout
$ , 4 5 = > e f n o & ' / 0 8 & ' / ! " . / 6 7 ? @ h p ! " + % - . 6 >? g o p ! % & $ % - 56 = > f g n o % precharge command if needed power down entry active bank 0 power down mode exit
8 a i j ' ( / 0 8 9 / 8 9 @ a h i j " # + / 7 8 ? @ h / 7 8 ? @ h i / 7 8 ? @ h i cke low r: a a10=1 rp t # high-z power down cycle re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il initialization sequence 78910 52 53 54 48 49 50 51 ! ( ) 1 2 : g o p auto refresh bank active if needed rc t rc t auto refresh valid c k l 0 123456 ck cke s re ce w address dqmb dq 8 9 a b j
a i j 7 @ a h i . 7 ? @ h t valid rsa t rp all banks precharge mode register set @ a i / 8 9 a v ih v ih ! * ! ! ) 55 high-z ' ( / 0 8 9 a 3 4 ; < d e m 4 < = d e m n / 7 8 a ) b c k 9 b c k 6 ? g p code
hb52r168db-f 55 physical outline 2 144 1.00 0.10 0.039 0.004 detail a 0.25 max. 0.010 max. 2.55 0.100 0.60 0.05 0.024 0.002 0.80 0.031 2-r2.00 2-r0.079 3.70 0.146 23.20 0.913 4.60 0.181 2.10 0.083 32.80 1.291 4.00 0.10 0.157 0.004 3.80max. 0.150max. (datum -a-) 1.50 0.10 0.059 0.004 4.00 0.10 0.157 0.004 (datum -a-) detail b r0.75 r0.030 2.5 0.098 2.00min. 0.079min. component area (back) 2r3.00min 2r0.118min. 4.00min. 0.157min. 3.20min. 0.126min. 1 143 3.30 0.130 23.20 0.913 4.60 0.181 2.50 0.098 32.80 1.291 (datum -a-) 25.40 1.000 20.00 0.787 67.60 2.661 a b component area (front) unit: mm inch
hb52r168db-f 56 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/index.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:
hb52r168db-f 57 revision record rev. date contents of modification drawn by approved by 0.0 sep. 3, 1999 initial issue (referred to hm5264165f/hm5264805f/hm5264405f rev 0.0) s. tsukui k. tsuneda 1.0 jan. 24, 2000 (referred to hm5264165f/hm5264805f/hm5264405f rev 0.0) cke truth table clock suspend mode entry ( s ): h to dc characteristics i cc1 max (cl = 2): 1120 ma to 960 ma i cc1 max (cl = 3): 1120 ma to 960 ma i cc2p max: 48 ma to 24 ma i cc2ps max: 32 ma to 16 ma i cc2n max: 256 ma to 160 ma i cc3n max: 320 ma to 288ma i cc4 max (cl = 2): 1120 ma to 880 ma i cc4 max (cl = 3): 1120 ma to 880 ma i cc5 max: 1840 ma to 1760 ma physical outline: correct error

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