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multichannel 96 khz codec ad1836a fea t ures 5 v m u ltichann el audio syst e m accepts 16-/18 - /20-/24-bit dat a supports 24-bit and 96 khz sa mple rate multibit -? m o dulators with data directed scrambling differentia l output for optimum performance adcs: C 92 db t h d + n, 105 db snr and dyna mic range dacs: C 95 db t h d + n, 108 db snr and dyna mic range on-chip volume control with "auto-ramp" function programmable gain amplifier for adc input hardware and software contr o llable clickles s mute digital de-emp hasis processing supports 256 f s , 512 f s , or 768 f s master clock power-down mode plus soft p o wer-down mode flexible seria l data port with right justified, l e ft justifie d, i 2 s compatible, and dsp serial port modes tdm interface mode supports 8 in/8 out usin g a single sharc? sport 52-lea d mqfp ( p qfp) plastic package a pplic a t io ns home theater s y stems automotive a u dio systems dvd r e co rders set-top boxes digital a u dio e ffects processors pr oduc t ov er vie w the ad1836a is a hig h p e r f o r ma nce , sin g le-chi p co dec tha t p r o v ides t h r e e st er e o d a cs and tw o s t er e o ad cs usin g ad i s pa t e n t ed m u l t i b i t - ? a r c h i t ec t u r e . an s p i? p o r t is in cl ude d , a l lo win g a m i cr o c o n t r ol ler t o ad j u st vol u m e and man y o t her p a ra m e ters. the ad1836a op er a t es f r o m a 5 v s u p p l y , wi th p r o v isio n fo r a s e p a ra t e o u t p ut su p p ly t o in t e r f a c e w i t h lo w v o l t a g e ext e r n al cir c ui tr y . th e ad1836a is a v a i l a b l e in a 52-lead mqf p ( p qf p ) p a ckage. func ti onal bl oc k di a g ram digital filter - ? dac dac1l dac1r clock mclk cout v ref control port cclk cdata clatch serial data i/o port digital filter - ? adc1l 48khz/96khz pga - ? adc2l 48khz digital filter 48khz dlrclk dbclk dsdata1 dsdata2 dsdata3 alrclk abclk asdata1 asdata2 capl1 capl2 capr1 capr2 pd/rst avdd agnd dvdd dgnd 2 432 mux pga - ? adc2r 48khz digital filter 48khz digital filter - ? dac dac2l dac2r volume digital filter - ? dac dac3l dac3r filtr adc1l adc1r adc2l1 adc2l2 adc2r1 adc2r2 mux volume volume volume volume volume filtd 48khz/96khz digital filter - ? adc1r 48khz/96khz 48khz/96khz fi g u r e 1 . in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . rev. 0
ad1836a table of contents ad1836a s p e cif i ca tion s ............................................................... 3 a b s o l u t e m a xim u m r a t i n g s ............................................................ 8 p i n c o nf igura t io n a n d pin f u nc t i o n al d e s c r i p t io n s .................. 9 f u n c t i o n al o v e r vie w ...................................................................... 11 ad cs ............................................................................................ 11 d a cs ............................................................................................ 11 c l o c k s i g n als ............................................................................... 11 res e t an d p o w e r - d o w n ............................................................. 12 s e r i al c o n t r o l p o r t ..................................................................... 12 p o w e r s u p pl y a nd v o l t a g e refe r e n c e . ...................................... 13 s e r i al d a t a p o r t sd a t a f o r m a t ............................................... 13 s p i c o n t r o l r e g i s t ers . ................................................................ 19 o u t l in e dim e n s io n s ....................................................................... 23 es d c a u t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 or der i n g g u ide . ......................................................................... 23 revisi on h i s t or y rev i s i o n 0: i n i t ial v e r s i o n rev. 0 | page 2 of 2 4
ad1836a ad1836aspecifications ta ble 1. tes t condi t i ons , u n le s s ot herwi s e not e d. perf orma n c e of a ll cha nne ls i s i d ent i ca l ( e xclus i ve of t h e int e rchannel g a i n mismatch an d in terchan n e l p h ase dev i ation sp ecification s ). p a r a m e t e r r a t i n g supply voltages (avdd, dvdd ) 5 v ambient temperature 25c master clock 12.288 mhz (48 khz f s , 256 f s mode) input signal 1.000 khz, 0 dbf s (full scale) input sample rate 48 khz measurement bandwidth 20 hz to 20 khz word width 24 bits load capacitance (digital output) 100 pf load impedance (digital outpu t ) 2.5 k? input voltage hi 2.4 v input voltage l o 0.8 v rev. 0 | page 3 of 2 4
ad1836a rev. 0 | page 4 of 24 table 2. analog performance parameter min typ max unit adc resolution (all adcs) 24 bits dynamic range (20 hz to 20 khz, C60 db input) 1, 2 no filter (rms), ad1836aas 97 102 db with a-weighted filter (rms), ad1836aas 100 105 db no filter (rms), ad1836acs 94 99 db with a-weighted filter (rms), ad1836acs 97 102 db total harmonic distortion + noise (C1 dbfs) 1 C92 C83 db full-scale input voltage (differentia l) 2.18 (6.16) v rms (v pp) gain error C5.0 +5.0 % interchannel gain mismatch C0.1 +0.1 db offset error C10 0 +10 mv gain drift 100 ppm/c interchannel isolation C110 db programmable input gain 12 db gain step size 3 db cmrr, direct input, 100 mv rms, 1 khz C77 C63 db cmrr, direct input, 100 mv rms, 20 khz C72 C60 db cmrr, pga differential input, 100 mv rms, 1 khz C57 C39 db cmrr, pga differential input, 100 mv rms, 20 khz C57 C39 db input resistance 10 k? input capacitance 15 pf analog-to-digital converters common-mode input volts 2.25 v dynamic range (20 hz to 20 khz, C60 db input) 1, 2 no filter (rms), ad1836aas 102 105 db with a-weighted filter (rms), ad1836aas 105 108 db no filter (rms), ad1836acs 99 102 db with a-weighted filter (rms), ad1836acs 102 105 db total harmonic distortion + noise (0 dbfs) 1 C95 C85 db full-scale output voltage (differential) 2.0 (5.6) v rms (v pp) gain error C6.0 +6.0 % interchannel gain mismatch C0.3 +0.3 db offset error 15 55 95 mv gain drift 150 ppm/c interchannel isolation C110 db interchannel phase deviation 0.1 degrees volume control step size (1023 linear steps) 0.098 % volume control range (max attenuation) 60 db max attenuation C100 db de-emphasis gain error 0.1 db output resistance at each pin 115 ? digital-to-analog converters v ref (filtr), common-mode output 2.2 2.25 2.3 v 1 total harmonic distortion + noise and dynamic range typical spec ifications are for two channels active, max/min are all channel s active. 2 measured with audio precision system two cascade in rms mode. averaging mode will show appr oximately 2 db better performance.
ad1836a table 3. digita l i/o p a r a m e t e r m i n t y p m a x u n i t input voltage hi (v ih ) 2 . 2 v input voltage l o (v il ) 0 . 8 v input leakage (i ih @ v ih = 2.4 v) 10 a input leakage (i il @ v il = 0.8 v) 10 a high level output voltage (v oh ) i oh = 2 ma odvdd C 0.4 v low level outp ut voltage (v ol ) i ol = 2 ma 0.5 v input capacitance 20 pf table 4. power supplies parameter m i n t y p m a x u n i t voltage, dvdd and avdd 4.75 5 5.25 v voltage, odvdd 3.0 3.3/5 5.25 v analog current 108 ma analog currentpower-down 47 ma digital current 78 ma supplies digital currentpower-down 1.5 ma operationbot h supplies 930 mw operationanalog suppli e s 540 mw operationdigital supplie s 390 mw dissip a tion power-down both supplie s 243 mw 1 khz 300 mv p- p signal at analog supply pins C60 db power supply rejection ratio 20 khz 300 mv p-p signal at analog supply pins C50 db table 5. tem p e r ature range p a r a m e t e r m i n t y p m a x u n i t specification s g u aranteed 25 c C 4 0 + 8 5 c a m b i e n t functionality guaranteed C 4 0 + 1 1 0 c c a s e s t o r a g e C 6 5 + 1 5 0 c table 6. digital filter @ 44.1 khz parameter m i n t y p m a x u n i t pass ba nd 20 khz pass-band ripple 0.0001 db transition ba nd 22 khz stop band 24 khz stop-band attenuation 120 db adc decim a ti on filter group delay 990.20 s pass ba nd 20 khz pass-b a nd rippl e 0.01 d b transition ba nd 22 khz stop band 24 khz stop-band attenuation 70 db dac interpola t ion fil t er group delay 446.35 s rev. 0 | page 5 of 2 4
ad1836a table 7. timing sp ecification s p a r a m e t e r c o m m e n t s m i n m a x u n i t t mh mclk high 512 f s mode 18 ns t ml mclk low 512 f s mode 18 ns t mclk mclk period 512 f s mode 36 ns f mclk mclk frequency 512 f s mode 27 mhz t pdr pd/rst low 5 n s maste r clock and res e t t pdr r pd/rst recovery reset to active output 4500 t mclk t chh c c l k h i g h 1 0 n s t chl c c l k l o w 1 0 n s t cds cdata setup to cclk rising 5 ns t cdh cdata hold from cclk rising 5 ns t cls clatch setup to cclk rising 5 ns t clh clatch hold from cclk falli ng 5 ns t code cout enable from cclk falli ng 10 ns t cod cout delay from cclk falli ng 10 ns t coh cout hold from cclk falli ng 0 ns spi port t cot s cout three-state from cclk falli ng 10 ns t dbh d b c l k h i g h 1 5 n s t dbl d b c l k l o w 1 5 n s f db dbclk frequen cy 64 f s n s t dls dlrclk setup to dbclk rising 0 ns t dlh dlrclk hold from dbclk rising 10 ns t dds dsdata se tup to dbclk rising 0 ns dac seria l po rt (normal modes ) t ddh dsdata hold from dbclk rising 20 ns t dbh d b c l k h i g h 1 5 n s t dbl d b c l k l o w 1 5 n s f db dbclk frequency 256 f s n s t dls dlrclk setup to dbclk rising 0 ns t dlh dlrclk hold from dbclk rising 10 ns t dds dsdata se tup to dbclk rising 0 ns dac seria l po rt (packed 128 mo de, packed 256 mode) t ddh dsdata hold from dbclk rising 20 ns t abd a b c l k d e l a y 1 5 n s from mclk transition, 256 f s mode from mclk rising, 512 f s mo de t als lrclk skew from abclk falling C2 +2 ns adc seria l po rt (normal modes ) t abdd asdata delay from abclk falling 5 ns t abd a b c l k d e l a y 1 5 n s from mclk transition, 256 f s mode from mclk rising, 512 f s mo de t als lrclk skew from abclk falling C2 +2 ns adc seria l po rt (packed 128 mo de, packed 256 mode) t abdd asdata delay from abclk falling 5 ns t abd a b c l k d e l a y 1 5 n s from mclk transition, 256 f s mode from mclk rising, 512 f s mode t als lrclk skew from abclk falling C2 +2 ns t abdd asdata delay from abclk falling 5 ns t dds dsdata1 hold to abclk rising 0 ns adc seria l po rt (tdm packed a u x) t ddh dsdata1 hold from abclk risi ng 7 ns t ax ds aauxdata set u p to auxbclk rising 7 ns t ax dh aauxdata hold from auxbclk rising 10 ns auxilia r y in te rface t dx dd dauxdata delay from auxbclk falling 25 ns rev. 0 | page 6 of 2 4
ad1836a t a l e t i i n s ec i ic a t io n c o n t i n u ed p a a e t e c o e n t m i n m a u n i t t xbd a u x b c l d e l a 1 n fo mcl tanition 6 s mode fo mcl riin 1 s mode auxilia r in te rface ma t e mode t xl s auxlrcl ske fo auxbcl fallin 3 3 n t xb h a u x b c l h i h 6 n t xbl a u x b c l l o 6 n xb auxbcl feuenc 6 s n t dls auxlrcl set u to auxbcl riin n auxilia r in te rface sl a e mode t dlh auxlrcl hold fo auxbcl riin 1 n re pae o
ad1836a absolute maximum ratings table 8. ad18 36a absolute maximum ratings p a r a m e t e r m i n m a x u n i t analog (avdd) C0.3 +6 v digital (dvdd) C0.3 +6 v input current ( e x c ept supply pins) 20 ma analog input voltage (signal pins) C0.3 avdd + 0.3 v digital input voltage ( s ignal pins) C0.3 dvdd + 0.3 v ambient temperature (operating) C40 +85 c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y ca us e p e r m an e n t da ma g e t o t h e de vice . this is a s t r e s s ra t i n g o n ly a nd f u n c t i o n al op era t io n o f t h e de v i ce a t t h es e o r an y o t her co ndi t i o n s ab o v e t h os e indic a te d i n t h e op era t io nal s e c t io n o f t h is s p e cif i ca tion is not i m pl i e d. e x p o su re to ab s o lute m a x i m u m r a t i ng c o n d i t i ons m a y af fe c t d e v i c e rel i a b i l i t y . table 9. packa g e characteristics p a r a m e t e r m i n t y p m a x u n i t ja (thermal res i s t ance [j unction to ambient]) 45 c / w jc (thermal res i s t ance [j unction to cas e ]) 18 c / w rev. 0 | page 8 of 2 4
ad1836a pin conf iguration and pi n functional descri ptions 52 51 50 49 48 43 42 41 40 47 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 13 12 pin 1 identifier 39 38 37 36 35 34 33 32 31 30 29 28 27 ad1836a agnd av dd adc1 inlp adc1 inln adc1 inrn adc2 inlp /cap l2 adc2 inln/cap l1 adc2 inl1 adc2 inl2 adc2 inr2 adc2 inr1 adc2 inrn/cap r1 dgnd cclk clatch cout as data2 as data1 odvdd mclk alrclk abclk ds data3 ds data2 dv dd dvdd cdata pd/rst outlp3 o utln3 outlp2 o utln2 outlp1 o utln1 avdd agnd filtd filtr dgnd dsdata1 dbclk dlrclk outrp3 outrn3 outrp2 outrn2 outrp1 outrn1 agnd agnd adc2inrp/capr2 adc1 inrp top view (not to scale) f i g u re 2. 52-l e ad m qfp table 10. pin function descri ptions52-lea d mqfp pin n o . in /ou t mnem o ni c descr i pt i o n 1 i dv dd digi tal powe r s u pply. connec t to dig i tal 5 v s u pply . 2 i cda t a serial con t r o l inp u t . 3 i pd/ r s t power-down res e t (ac t ive low ) . 4 o outl p3 d a c 3 l e ft p o sit i ve ou t p ut . 5 o outln3 dac 3 le ft ne gative o u tput. 6 o outl p2 d a c 2 l e ft p o sit i ve ou t p ut . 7 o outln2 dac 2 le ft ne gative o u tput. 8 o outl p1 d a c 1 l e ft p o sit i ve ou t p ut . 9 o outln1 dac 1 le ft ne gative o u tput. 10 i av dd analog powe r s u pply. connec t to analog 5 v. 1 1 i ag n d analog gro u n d . 12 i filtd filte r c a paci tor c o nnection . b y pas s with 1 0 f| | 1 0 0 nf to ag nd. 13 i fil t r volta g e re fer e nc e fil t er capac i to r connec t ion . b y p a ss with 1 0 f| | 1 00 n f to ag nd . 1 4 i ag n d analog gro u n d . 15 i avdd analog powe r supply. connec t to analog 5 v s u ppl y. 16 i adc 1 i n l p adc 1 lef t posi ti v e inp u t. 17 i adc 1 i n l n adc 1 lef t n e ga ti ve inp u t. 18 i adc 1 i n r p adc 1 ri ght pos i t i ve inpu t. 19 i adc 1 i n r n adc 1 ri ght neg a tive inp u t. 2 0 i a d c 2 i n l p / c a p l 2 adc2 left positive input (direct m o de)/ad c2 left d e coupling cap (mux/pg a and pga differential mode). 2 1 i a d c2 in ln /ca pl1 adc 2 lef t n e ga ti ve inp u t ( d irec t mod e )/ ad c2 le f t deco upling ca pacitor (m ux/ p g a a n d p g a di ffe ren t ial m o de ). 22 i adc 2 i n l 1 adc 2 lef t inp u t 1 (m ux/ p g a mo de )/le ft posit i ve i n put (p ga di f f er ential mo de ). 23 i adc 2 i n l 2 adc 2 lef t inp u t 2 (m ux/ p g a mo de )/ le ft nega tiv e inp u t (p ga d i f f e rent ial mo de ). 24 i adc 2 i n r 2 adc 2 ri ght inp u t 2 (mu x /pg a mode )/ri gh t ne ga tive inp u t (pg a d i ffe ren t ial mo de ). 25 i adc 2 i n r 1 adc 2 ri ght inp u t 1 (mu x /pg a mode )/ri gh t posi ti ve inp u t (pg a dif f eren tial mo de ). 2 6 i adc 2 i n r n /c ap r 1 adc 2 ri ght neg a tive inp u t ( d irec t mo de )/ad c2 ri ght de couplin g capacito r (m ux/ p g a a n d p g a di ffe ren t ial m o de ). rev. 0 | page 9 of 2 4
ad1836a pin n o . in /ou t mnem o ni c descr i pt i o n 2 7 i adc 2 i n r p /c ap r 2 a d c2 r i g h t p o sitive i n put (direct m o de )/ ad c2 ri g h t deco upling c a pacitor (m ux/ p g a a n d p g a di ffe ren t ial m o de ). 2 8 i ag n d analog gro u n d . 29 i ag nd analog gro u n d . 30 o out r n 1 dac 1 r i gh t ne g a tive o utp u t . 31 o out r p 1 dac 1 r i gh t posi tive o utp u t . 32 o out r n 2 dac 2 r i gh t ne g a tive o utp u t . 33 o out r p 2 dac 2 r i gh t posi tive o utp u t . 34 o out r n 3 dac 3 r i gh t ne g a tive o utp u t . 35 o out r p 3 dac 3 r i gh t posi tive o utp u t . 36 i/o dl rcl k lr clock for d a c s . 37 i/o dbclk bit clock for dacs. 38 i dsd a ta 1 dac inp u t 1 (i np ut to dac 1 l an d r). 3 9 i dg n d digi tal gro u n d . 40 i dv dd digi tal powe r s u pply. connec t to dig i tal 5 v s u pply . 41 i dsd a ta 2 dac inp u t 2 (i np ut to dac 2 l an d r). 42 i dsd a ta 3 dac inp u t 3 (i np ut to dac 3 l an d r). 43 o abclk bit clock for adcs. 44 o al rc lk lr clock for adc s . 45 i mc lk mas t er cl ock inp u t . 46 i odvd d digi tal ou tp ut d r iver power s u ppl y. connec t to 3. 3 v or 5 v log i c s u p p ly. 47 o asd a ta 1 adc se rial da ta outp ut 1 (a dc 1 l an d r). 48 o asd a ta 2 adc se rial da ta outp ut 2 (a dc 2 l an d r). 49 o cout outp u t for con t r o l da ta. 5 0 i cla t ch latch inpu t for c o ntrol da ta. 51 i cclk control clock inp u t fo r control da ta. 5 2 i dg n d digi tal gro u n d . rev. 0 | page 10 of 24
ad1836a rev. 0 | page 11 of 24 functional overview adcs there are four adc channels in the ad1836a configured as two independent stereo pairs. one stereo pair is the primary adc and has fully differential inputs. the second pair can be programmed to operate in one of three possible input modes (programmed via spi adc control register 3). the adc section may also operate at a sample rate of 96 khz with only the two primary channels active. the adcs include an on-board digital decimation filter with 120 db stop-band attenuation and linear phase response, operating at an over- sampling ratio of 128 (for 4-channel 48 khz operation) or 64 (for 2-channel 96 khz operation). the primary adc pair should be driven from a differential signal source for best performance. the input pins of the primary adc connect directly to the internal switched capacitors. to isolate the external driving op amp from the glitches caused by the internal switched capacitors, each input pin should be isolated by using a series-connected external 100 ? resistor together with a 1 nf capacitor connected from each input to ground. this capacitor must be of high quality, for example, ceramic npo or polypropylene film. the secondary input pair can operate in one of three modes: ? direct differential inputs (driven the same way as the primary adc inputs described above). ? pga mode with differential inputs. in this mode, the pga amplifier can be programmed using the spi port to give an input gain of 0 db to 12 db in steps of 3 db. external capacitors are used after the pga to supply filtering for the switched capacitor inputs. ? single-ended mux/pga mode. in this mode, two single- ended stereo inputs are provided that can be selected using the spi port. input gain can be programmed from 0 db to 12 db in steps of 3 db. external capacitors are used to supply filtering for the switched capacitor inputs. peak level information for each adc may be read from the spi port through registers 12 to 15. the data is supplied as a 10-bit word with a maximum range of 0 db to C60 db and a resolution of 1 db. the registers hold peak information until read; after reading, the registers are reset so that new peak information can be acquired. refer to the register descriptions for the details on this format. a digital high-pass filter can be switched in line with the adcs under spi control to remove residual dc offsets. it has a 1.3 hz, 6 db per octave cutoff at a 44.1 khz sample rate. the cutoff frequency will scale directly with sample frequency. note that it does not remove these offsets from the peak level measurement. the voltage at the v ref pin, filtr (~2.25 v), can be used to bias external op amps that buffer the input signals. see the power supply and voltage reference section. dacs the ad1836a has six dac channels arranged as three independent stereo pairs, with six fully differential analog outputs for improved noise and distortion performance. each channel has its own independently programmable attenuator, adjustable in 1024 linear steps. digital inputs are supplied through three serial data input pins (one for each stereo pair) and a common frame (dlrclk) and bit (dbclk) clock. alternatively, one of the packed data modes may be used to access all six channels on a single tdm data pin. each set of differential output pins sits at the dc level of v ref and swings 1.4 v for a 0 db digital input signal. a single op amp third order external low-pass filter is recommended to remove high frequency noise present on the output pins, as well as to provide differential-to-single-ended conversion. note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. the voltage at the v ref pin, filtr (~2.25 v), can be used to bias the external op amps that buffer the output signals. see the power supply and voltage reference section. clock signals the master clock frequency can be selected for 256, 512, or 768 times the sample rate. the default at power-up is 256 f s . for operation at 96 khz, the master clock frequency should stay at the same absolute frequency. for example, if the ad1836a is programmed in 256 f s , 48 khz mode, the frequency of the master clock would be 256 48 khz = 12.288 mhz. if the ad1836a is then switched to 96 khz operation (via writing to the spi port), the frequency of the master clock should remain at 12.288 mhz (which is now 128 f s ). the internal clock used in the ad1836a is 512 f s (48 khz mode) or 256 f s (96 khz mode). a clock doubler is used to generate this internal master clock from the external clock in the 256 f s and 768 f s modes. to maintain the highest performance possible, it is recom- mended that the clock jitter of the master clock signal be limited to less than 300 ps rms, measured using the edge-to- edge technique. even at these levels, extra noise or tones may appear in the dac outputs if the jitter spectrum contains large spectral peaks. it is highly recommended that an independent crystal oscillator generate the master clock. in addition, it is especially important that the clock signal should not be passed
ad1836a thr o ug h a n fp ga o r o t h e r la rg e dig i tal c h i p b e f o r e bein g a p p l ie d t o t h e ad1836a. i n m o s t cas e s, this wil l ind u ce c l o c k ji t t er d u e t o t h e fac t t h a t t h e clo c k sig n al is s h a r in g co mm on p o w e r a nd g r o u nd co n n e c t i on s wi t h o t h e r unr e la te d dig i t a l o u t p u t sig n als. the s i x d a c ch annel s u s e a c o mmon s e r i a l bi t cl o c k to cl o c k i n t h e s e r i a l da t a and a co m m on l e f t -r ig h t f r a m i n g clo c k. t h e fo ur ad c chan n e ls o u t p ut a co m m o n s e r i a l b i t clo c k an d a lef t -r ig h t f r a m in g c l o c k. the c l o c k sig n a l s a r e al l syn c hro n o u s wi t h the sa m p l e ra t e . reset and power-down res e t wi l l p o w e r do wn t h e chi p a nd s e t t h e con t r o l r e g i s t ers t o t h eir def a u l t s e t t in gs. af t e r r e s e t is de-a ss er t e d , a n in i t ia li za t i o n r o u t in e wil l r u n in side t h e ad1 836a t o c l ea r al l m e m o r i es t o zer o . this ini t ial i za tio n lasts f o r a p p r o x ima t e l y 4500 m c lks. the p o w e r - dow n b i t i n t h e d a c c o n t r o l reg i st er 1 a nd ad c c o n t r o l reg i st e r 1 wi l l p o w e r d o wn t h e r e sp e c t i v e dig i t a l s e c t io n. th e a n alog cir c ui tr y d o es n o t p o w e r do wn. al l o t h e r re g i ste r s e tt i n g s are re t a i n e d . t o a v oid p o s s i b l e sy n c hr o n iza t io n p r ob lem s , if m c lk is 512 f s o r 768 f s , t h e clo c k ra te sh o u ld b e s e t i n a d c c o n t r o l reg i st er 3 wi t h in t h e f i rs t 3072 m c lk c y c l es a f t e r r e s e t, o r d l r c lk and db clk sh o u ld b e w i t h h e l d un t i l a f t e r t h e in t e r n a l ini t ia l i z a t i on co m p let e s (s e e a b o v e). serial control port the ad1836a has a n s p i com p a t ib le co n t r o l p o r t tha t p e r m i t s p r og ra mmin g t h e i n t e r n al con t r o l r e g i s t ers fo r t h e ad c s an d d a cs a n d f o r r e a d i n g t h e a d c si gn al lev e l f r o m th e in t e rn al p e ak de t e c t o r s. the d a c ou t p u t le v e l s ma y be in de p e n d e n tl y p r og ra mm e d b y m e an s o f a n in ter n al dig i tal a t t e n u a t o r ad j u s t ab le in 10 24 lin e a r st eps. the s p i con t r o l p o r t is a 4-wir e s e r i al co n t r o l p o r t . th e f o r m a t is simila r t o t h e m o t o r o la s p i f o r m a t excep t the in p u t da t a -w o r d is 1 6 b i t s w i d e . t h e max i m u m s e r i a l b i t cl o c k f r e q ue nc y i s 8 m h z and m a y b e c o m p le t e ly as y n chr o no us t o t h e s a m p le r a te o f t h e ad cs and d a c s . f i gure 3 sh ows t h e fo r m a t o f t h e s p i s i g n al. a l l co n t r o l r e g i s t ers a r e wr i t e-onl y . the y cann ot b e r e ad b a ck. the a d c p e a k reg i st ers a r e re ad-onl y . the y a r e res e t t o zer o e a ch tim e t h ey a r e r e a d a n d a r e u p da t e d a t t h e n e xt s a m p le t i m e . d u e t o a n an o m al y in t h e s p i i n t e r f ace , w h en a wr i t e t o a d a c c o n t ro l re g i ste r f o l l ow s af te r a re a d or a w r ite to an a d c r e g i s t er , i t ma y n o t b e exe c u t e d p r o p erl y . an y such wr i t e sh o u ld be p e rf o r m e d tw i c e . clatch cclk cdata cout d15 d9 d0 d14 d8 d0 fi g u r e 3 . fo r m a t o f s p i s i g n a l rev. 0 | page 12 of 24
ad1836a power supply and voltage ref e rence the ad1836a is desig n e d f o r 5 v s u p p lies. s e p a ra t e p o w e r s u pp l y pi ns are prov i d e d f o r t h e an a l o g an d d i g i t a l s e c t i o ns . th es e p i n s sh o u ld be b y p a s s e d wi t h 100 nf cer a mic c h i p c a p a c i tors , a s cl o s e to t h e pi ns a s p o ss ibl e , to m i ni mi z e noi s e p i ck u p . a b u l k a l umin u m e l e c t r oly t ic ca p a ci t o r o f a t le ast 22 f shou l d a l s o b e prov i d e d o n t h e s a me pc b o a r d a s t h e co de c. f o r cr i t ica l a p plic a t i o n s , im p r o v e d p e r f o r ma n c e wi l l b e ob t a i n e d w i t h se pa ra t e su p p li e s f o r th e a n alog a n d d i gi tal secti o n s . i f th i s is n o t p o ssi b le, i t is r e co m m e n d e d t h a t t h e a n a l o g a n d dig i t a l s u p p lies be is ol a t ed b y m e a n s o f a f e r r i t e bead in s e r i es wi th e a ch su p p ly . i t is im p o r t an t t h a t t h e an a l o g su p p ly b e as cl e a n as pos s i b l e . f o r e a s e in in t e r f acin g t o va r i o u s log i c fa milies, th e dig i t a l o u t p ut dr i v ers ar e s u p p lie d f r om t h e o d vd d p i n. f o r cmos logi c, th i s s h o u ld b e co nn ect e d t o th e 5 v d i gi ta l s u p p l y . f o r 3.3 v log i c, i t s h o u ld be conn ec ted t o t h e 3.3 v su p p l y . f o r t t l le v e l s, i t ca n be tie d t o e i ther . al l dig i ta l in p u ts ar e co m p a t i b le wi t h t t l and c m os le vels. the i n t e r n al v o l t a g e r e fer e n c e v ref is b r o u g h t ou t o n pi n 13 (fil tr) a nd sho u ld be b y p a s s e d as c l os e as p o ssi b l e t o t h e c h i p , wi t h a p a ral l e l c o m b ina t ion o f 10 f a n d 100 nf . th e r e f e r e n c e v o l t a g e ma y b e us ed t o b i as exter n al o p a m ps to th e co mm on- m o de v o l t a g e o f t h e i n p u t an d ou t p ut sig n al p i ns. th e c u r r en t dr a w n sh o u ld b e limi te d to less t h a n 50 a. t h i s s o ur ce ca n b e co nnec t e d dir e c t l y t o o p a m p in p u ts b u t sh o u ld be b u f f er ed if i t is r e q u ir e d t o dr i v e r e sist i v e n e t w o r ks. th e f i l t d pi n shou l d b e c o n n e c te d to an e x te r n a l g r ou nde d ca p a c i t o r . this p i n is us e d t o r e d u ce t h e n o is e of t h e in t e r n a l d a c b i as ci r c ui tr y , th e r e b y r e d u ci n g th e d a c o u t p u t n o ise . i n s o me cas e s, t h is ca p a ci t o r ma y b e e l imin a t e d w i t h li t t le ef fe c t on pe rf o r m a n c e . serial data portsdata format the a d c s e r i a l d a t a o u t p ut m o de def a u l ts to t h e p o p u la r i 2 s fo r m a t , w h er e t h e da t a is dela ye d b y 1 b c l k i n t e r v al f r o m t h e edg e o f the lr c l k. b y p r og ra mmin g b i ts 8 an d 9 in ad c c o n t r o l reg i ste r 2, t h e s e r i a l mo de can b e change d to r i g h t j u st if ie d (rj), lef t j u st if ie d d s p (ds p ), lef t j u st if ie d (lj), p a ck e d m o de 128, o r p a c k e d m o de 25 6. i n the rj m o de , i t is n e ces s a r y t o s e t b i t s 6 a n d 7 t o d e fi n e th e w i d t h o f th e d a ta - w o r d . t h e d a c ser i al da ta i n p u t m o de d e fa ul ts t o i 2 s. b y p r og ra mmin g bi ts 5, 6, a nd 7 in d a c c o n t r o l reg i s t er 1, the m o de can be c h a n g e d t o rj , ds p , lj , p a c k e d m o de 128, o r p a c k e d m o de 2 56. th e w o rd wid t h defa u l ts t o 2 4 b i ts b u t ca n b e ch a n ge d b y p r o g r a mmin g bi ts 3 an d 4 in d a c c o n t r o l reg i st er 1. th e p a c k e d m o des accep t six c h a n ne ls o f da t a a t t h e ds d a t a 1 in p u t p i n, w h ich is ro u t e d i n dep e nd en t l y t o e a ch o f th e si x in t e rn al d a c s . a sp e c ia l a uxi l i a r y m o de is p r o v ide d t o a l lo w tw o ext e r n a l s t er e o ad cs and on e ext e r n al st er e o d a c t o b e in ter f ace d wi t h th e ad1836 a to p r o v ide 8 in/8 o u t o p era t ion. i n addi tion, this m o de s u p p o r ts g l ue les s in t e r f ac e t o a sin g le s h ar c ds p s e r i al p o r t , al lo win g a s h ar c ds p t o acces s al l eig h t c h a n n e ls o f a n alog i/o . i n t h is s p ec ial m o de , ma n y p i n s a r e r e def i n e d s e e t a bl e 1 1 for a l i st of re d e f i ne d pi ns . t w o ve r s i o ns of t h i s mo d e a r e a v a i la b l e . i n th e mas t er m o de , th e ad1836a p r o v ides the lr clk an d b c lk sig n als fo r t h e ext e r n al ad cs an d d a c. i n t h e sla v e m o de , ext e r n al ad c1 p r o v ides t h e lrclk and b c lk sig n als (whic h m u s t be di v i de d do wn p r o p erl y f r o m th e ext e r n al mas t er c l o c k), a nd the ad1836a wil l s y n c t o t h es e ext e r n al clo c ks. i n t h e a b s e n c e of t h e ext e r n al a d c clo c ks i n s l a v e m o de , t h e alr c l k and ab clk ou t p u t s of th e ad1836a (td m f r am e sy n c and b i t c l o c k) wil l def a u l t t o be t h e s a me as in mas t er m o de . s e e f i g u re 9 t h rou g h f i g u re 1 1 f o r d e t a i l s of t h e s e mo d e s . f i g u re 1 2 show s t h e i n te r n a l s i g n a l f l ow d i ag r a m of t h e a u x i l i ar y mo d e . the f o l l o w in g f i gur e s s h o w the s e r i al m o de f o r m a t s. rev. 0 | page 13 of 24
ad1836a lrclk bclk sdata lrclk bclk sdata lrclk bclk sdata lrclk bclk sdata left channel right channel left channel right channel msb lsb lsb lsb lsb lsb left justified mode??16 bits to 24 bits per channel i 2 s mode??16 bits to 24 bits per channel right justified mode??select number of bits per channel dsp mode??16 bits to 24 bits per channel notes 1. dsp mode does not identify channel 2. lrclk normally operates at f s except for dsp mode which is 2 u f s 3. bclk frequency is normally 64 u lrclk but may be operated in burst mode msb msb msb lsb left channel msb lsb msb right channel lsb msb msb 1/f s f i gure 4. stereo s e r i a l m o des rev. 0 | page 14 of 24
ad1836a rev. 0 | page 15 of 24 lrclk bclk data slot 1 left 0 slot 2 left 1 slot 3 right 0 slot 4 right 1 msb msb?1 msb ? 2 lrclk bclk data 32 bclks 128 bclks f i gure 5. a d c p a cked mod e 1 2 8 lrclk bclk data slot 1 left 0 slot 2 left 1 slot 5 right 0 slot 6 right 1 32 bclks msb msb ? 1 msb?2 256 bclks slot 3 slot 4 slot 7 slot 8 lrclk bclk data f i gure 6. a d c p a cked mod e 2 5 6 lrclk bclk data slot 1 left 0 slot 2 left 1 msb msb?1 msb?2 20 bclks slot 4 right 0 slot 5 right 1 slot 3 left 2 slot 6 right 2 lrclk bclk data 128 bclks f i gure 7. d a c p a cked mod e 1 2 8 lrclk bclk data slot 1 left 0 slot 2 left 1 msb msb?1 msb? 2 32 bclks slot 4 right 0 slot 5 right 1 slot 3 left 2 slot 6 right 2 lrclk bclk data 256 bclks f i gure 8. d a c p a cked mod e 2 5 6
ad1836a rev. 0 | page 16 of 24 fstdm adc l0 adc l1 aux_adc l0 aux_adc l1 adc r0 internal adc r1 aux_adc r0 aux_adc r1 dac l0 dac l1 d ac l2 aux_dac l0 dac r0 dac r1 dac r2 aux_dac r0 msb tdm 1st ch left right i 2 s ?? msb left bclk tdm asdata1 tdm (out) asdata1 dsdata1 dsdata1 aux lrclk i 2 s (from aux adc no. 1) aux bclk i 2 s (from aux adc no. 1) aauxdata1 (in) (from aux adc no. 1) aauxdata2 (in) (from aux adc no. 2) dauxdata (out) (to aux dac) note aux bclk frequency is 64 u frame rate; tdm bclk frequency is 256 u frame rate. fstdm follows aux lrclk by 3 1/2 1/2 tdm bclk in both master and slave modes. tdm interface aux ? i 2 s interface msb tdm 8th ch 32 32 1st ch msb tdm 8th ch tdm (in) internal internal internal msb tdm internal internal internal internal internal internal i 2 s ?? msb left i 2 s ?? msb left i 2 s ?? msb right i 2 s ?? msb right i 2 s ?? msb right f i g u re 9. a u x m o d e tim i ng (n ote t h at t h e cl ock s a r e n o t to s c ale)
ad1836a rev. 0 | page 17 of 24 30mhz 12.288mhz sharc is always running in slave mode (interrupt-driven) fsync-tdm (rfs) rx clk rx data tfs (nc) txclk tx data asdata1 alrclk abclk dsdata1 lrclk bclk data mclk adc no. 1 slave sharc ad1836a master mclk dsdata3/aauxdata2 dsdata2/aauxdata1 dlrclk/auxlrclk asdata2/dauxdata dbclk/auxbclk (64f s ) lrclk bclk adc no. 2 slave lrclk bclk data mclk dac data mclk f i gure 10. a u x m o de co nnec t ion to s h a r c (mas ter m o d e ) 30mhz 12.288mhz sharc is always running in slave mode (interrupt-driven) fsync-tdm (rfs) rx clk rx data tfs (nc) txclk tx data asdata1 alrclk abclk dsdata1 lrclk bclk data mclk adc no. 1 master sharc ad1836a slave mclk dsdata3/aauxdata2 dsdata2/aauxdata1 dlrclk/auxlrclk asdata2/dauxdata dbclk/auxbclk (64f s ) lrclk bclk lrclk bclk data mclk dac adc no. 2 slave data mclk f i gure 11. a u x m o de co nnec t ion to s h a r c (slave m o de)
ad1836a table 11. pin function chang e s in au x mod e pin name (i 2 s/aux mo de) i 2 s mo de aux mo de asdata1 ( o ) i 2 s data out, int e rnal adc1 tdm data ou t, t o sharc asdata2 ( o)/dauxdata ( o ) i 2 s data out, int e rnal adc2 auxi 2 s data out (to ex ternal dac) dsdata1 ( i ) i 2 s data in, inter n al dac1 tdm data in, from sharc dsdata2 ( i)/aa u xdata ( i ) i 2 s data in, inter n al dac2 auxi 2 s data i n 1 (to external adc) dsdata3 ( i)/aa u xdata2 ( i ) i 2 s data in, inter n al dac3 auxi 2 s data i n 2 (to external adc) alrclk(o) lrclk for internal adc1, ad c2 tdm frame syn c out, to sha r c abclk(o) bclk for internal adc1 , adc2 tdm bckl out, to sharc dlrclk(i)/ au xl rclk(i/ o ) l r clk in/ o ut in ternal dacs au x lr clk in/o ut , driv en b y ext e rnal ir clk fro m adc (in sla ve mo de ). in master mode, driven by internal mclk/512. d b c l k ( i ) / a u x b c l k ( i / o ) b c l k in/ o ut internal dacs aux bclk in/out, driven by external bclk from adc (in slave mode). in master mode, driven by internal mclk/8. auxdata1 asdata2/dauxdata data to ext dac bclk and lrclk for ext dac comes from adc bclk, lrclk. must be in i 2 s mode. adc sync signal derived from auxlrclk used to reset internal adc counter asdata1 auxdata i 2 s formatter mux auxlrclk 2 aux channels 6-ch dac 6 main channels dac sport dsdata1 dsdata2 dsdata3 lrclk bclk sport sync 4 adc s auxbclk auxlrclk auxdata2 i 2 s decode lrclk abclk asdata1 alrclk abclk asdata1 data to sharc indicates mux position for aux-tdm mode master/slave mode, from adc spi port from sharc from ext a/d from ext a/d dsdata1 dsdata2/auxdata1 dsdata3/auxdata2 dlrclk/auxlrclk mclk timing gen lrclk bclk dbclk/auxbclk mux auxbclk mux i 2 s f i gure 12. ex tend e d tdm m o de (in t er nal f l o w d i ag r a m) rev. 0 | page 18 of 24
ad1836a spi control registers n o te t h a t a l l c o n t ro l re g i ste r s d e f a u l t to z e ro a t p o we r - up . table 12. serial spi word for m at register addre ss read/write reserve d data fie l d 1 5 : 1 2 1 1 1 0 9 : 0 4 bits 1 = read 0 = write 0 1 0 b i t s tab l e 13. register ad d r esses a n d fun c tion s register address rd/wr reserved function bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bits 9:0 0 0 0 0 0 0 d a c c o n t r o l 1 0 0 0 1 0 0 d a c c o n t r o l 2 0 0 1 0 0 0 d a c 1 l v o l u m e 0 0 1 1 0 0 d a c 1 r volume 0 1 0 0 0 0 d a c 2 l v o l u m e 0 1 0 1 0 0 d a c 2 r volume 0 1 1 0 0 0 d a c 3 l v o l u m e 0 1 1 1 0 0 d a c 3 r volume 1 0 0 0 0 0 adc1lpeak level (read-only ) 1 0 0 1 0 0 adc1rpeak level (read-only ) 1 0 1 0 0 0 adc2lpeak level (read-only ) 1 0 1 1 0 0 adc2rpeak level (read-only ) 1 1 0 0 0 0 a d c c o n t r o l 1 1 1 0 1 0 0 a d c c o n t r o l 2 1 1 1 0 0 0 a d c c o n t r o l 3 1 1 1 1 0 0 r e s e r v e d table 14. dac control register 1 p a c k ed m o de : ei g h t c h a n n e ls a r e p ac k e d in ds d a t a 1 s e r i al in p u t. p a c k ed m o de 128 : ref e r t o f i g u r e 7. p a c k ed m o de 25 6: ref e r t o fi g u r e 8 . function addres s r d / w r reserve d de-emphasis serial mode data-word width power-down interpolator mode reserved 15, 14, 13, 12 11 10 9, 8 7, 6, 5 4, 3 2 1 0 0000 0 0 00 = none 01 = 44.1 khz 10 = 32.0 khz 11 = 48.0 khz 000 = i 2 s 001 = rj 010 = dsp 011 = l j 100 = packed mode 256 101 = packed mode 128 110 = reserved 111 = reserved 00 = 24 bits 01 = 20 bits 10 = 16 bits 11 = reserved 0 = normal 1 = pwrdwn 0 = 8 (48 khz) 1 = 4 (96 khz) 0 rev. 0 | page 19 of 24
ad1836a table 15. dac control register 2 dac m u te addres s rd/wr reserve d d a c 3 r d a c 3 l d a c 2 r d a c 2 l d a c 1 r d a c 1 l 15, 14, 13, 12 11 10, 9, 8, 7, 6 5 4 3 2 1 0 0001 0 00000 0 = on 1 = mute 0 = on 1 = mute 0 = on 1 = mute 0 = on 1 = mute 0 = on 1 = mute 0 = on 1 = mute table 16. dac volume registers function addres s rd/wr reserve d volume 15, 14, 13, 12 11 10 9:0 0010: dac1l 0011: dac1r 0100: dac2l 0101: dac2r 0110: dac3l 0111: dac3r 0 0 0 to 1023 in 102 4 linear steps table 17. a d c control register 1 function addres s rd/wr reserve d filter power-down sample rate left gain right gain 15, 14, 13, 12 11 10, 9 8 7 6 5, 4, 3 2, 1, 0 1100 0 00 0 = dc 1 = high pass 0 = normal 1 = pwrdwn 0 = 48 khz 1 = 96 khz 000 = 0 db 001 = 3 db 010 = 6 db 011 = 9 db 100 = 12 db 101 = reserved 110 = reserved 111 = reserved 000 = 0 db 001 = 3 db 010 = 6 db 011 = 9 db 100 = 12 db 101 = reserved 110 = reserved 111 = reserved table 18. a d c control register 2 p a c k ed m o de : ei g h t c h a n n e ls a r e p ac k e d in a s d a t a 1 s e r i al o u t p u t . p a c k ed m o de 128 : re f e r t o f i g u r e 5. p a c k ed m o de 25 6: ref e r t o f i gur e 6. p a c k ed m o de a u x: ref e r t o f i g u r e 9 t o f i gu r e 1 1 . n o t e tha t p a c k ed a u x m o de a f f e c t s th e en ti r e c h i p , in c l udin g th e d a c s e r i al m o de. adc mute address rd/w r reserved maste r /slave aux mo de sout m o de word w i dth a d c 2 r a d c 2 l a d c 1 r a d c 1 l 15, 14, 13 , 12 11 10 9 8, 7, 6 5, 4 3 2 1 0 110 1 0 0 0 = s l a v e 1 = mas t er 000 = i 2 s 001 = rj 010 = ds p 011 = lj 100 = packe d mo de 25 6 101 = packe d mo de 12 8 110 = packe d mo de au x 00 = 2 4 bi ts 01 = 2 0 bi ts 10 = 1 6 bi ts 11 = reserve d 0 = on 1 = mute 0 = on 1 = mute 0 = on 1 = mute 0 = on 1 = mute rev. 0 | page 20 of 24
ad1836a table 19. a d c control register 3 w h en c h an g i n g c l o c k mo de , o t h e r s p i b i ts tha t a r e wr i t t e n d u r i n g the s a m e s p i tra n s a c t io n ma y be los t . th er ef o r e , i t is r e co mm e nd e d t h a t t h es e b e s e t s e p a ra t e l y . function addres s rd/wr reserved clock mode left different ial i/p select right differentia l i/p select left mux/pga enable left mux i/p select right mux/pga enable right mux i/p select 15, 14, 13, 12 11 10, 9, 8 7, 6 5 4 3 2 1 0 1110 0 000 00 = 256 f s 01 = 512 f s 10 = 768 f s 0 = differential pga mode 1 = pga/mux mode (singl e- ended input ) 0 = differential pga mode 1 = pga/mux mode (singl e- ended input ) 0 = direct 1 = mux/pga 0 = i/p 0 1 = i/p 1 0 = direct 1 = mux/pga 0 = i/p 0 1 = i/p 1 table 20. a d c peak lev e l dat a registers peak level dat a (10 bits) addres s rd/wr reserve d 6 data bits 4 fixed bits 15, 14, 13, 12 11 10 9:4 3:0 1000 = adc1l 1001 = adc1r 1010 = adc2l 1011 = adc2r 1 0 000000 = 0.0 db fs 000001 = C1.0 dbfs 000010 = C2.0 dbfs 000011 = C3.0 dbfs 111100 = C60 dbfs min 0000 the 4 lsbs are always zer o . rev. 0 | page 21 of 24
ad1836a rev. 0 | page 22 of 24 ad1836a adc2l c1 1nf c2 1nf left input no. 1 left input no. 2 cap1l i nput select 250 ? pga ? + ? + v ref 250 ? mu x cap2l gain select power-dow n note adc2 single-ended mux pga input mode??left channel only shown. control register 3 contents: 6 lsbs: select input no. 1: 11 1010 select input no. 2: 11 1111 v ref f i gure 13. sing le -ended mux / pg a m o de ad1836a adc2l c1 1nf c2 1nf left + ve input left ? ve input cap1l ? + ? + v ref pga gain select 250 ? 250 ? cap2l note adc2 differential pga input mode ?left channel only shown. control register 3 contents: 6 lsbs: 00 1010 power-down f i g u re 14. d i f f e r e nt ia l pg a m o de
ad1836a rev. 0 | page 23 of 24 outline dimensions sea t i n g p l ane v iew a 0.23 0.11 2.45 max 1.03 0.88 0.73 top v ie w (p in s d o w n ) 1 39 40 13 14 27 26 52 pin 1 0.65 bsc 13.45 13.20 12.95 10.20 10.00 9.80 sq 7.80 ref s q 0.40 0.22 view a rotated 90 ccw 7 0 2.20 2.00 1.80 0.13 min coplanarity compliant to jedec standards m-022-ac f i g u re 15. 5 2 -l ead p l as t i c q u ad f l at p a ckag e [m qfp ] (s-52a) di me nsio ns sho w n i n mi ll im e t e r s esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. ordering guide ad18 36a prod ucts temperature p a ckage package descri ption package option ad1836aas C40c to +85c ambient 52-lead mqfp s-52a AD1836AASRL C40c to +85c ambient 52-lead mqfp s-52a on 13" re els ad1836acs C40c to +85c ambient 52-lead mqfp s-52a ad1836acsrl C40c to +85c ambient 52-lead mqfp s-52a on 13" re els eval-ad1836 a e b e v a l u a t i o n boar d
ad1836a rev. 0 | page 24 of 24 notes ? 2003 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c03800C0 C 8/03(0)

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