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preliminary data this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. rev 1 november 2005 1/37 37 L9942 integrated stepper motor driver for bipolar stepper motors with microstepping and programmable current profile features two full bridges for max. 1.3 a load (r dson = 500 m ? ) programmable current waveform with look-up table: 9 entries with 5bit resolution current regulation by integrated pwm controller and internal current sensing programmable stepping mode: full, half, mini and microstepping programmable slew rate for emc and power dissipation optimisation programmable fast-, slow-, mixed-and auto- decay mode full-scale current programmable with 3bit resolution very low current consumption in standby mode i s < 3a, typ. t j 85 c all outputs short circuit protected with openload, overloadcurrent, temperature warning and thermal shutdown the pwm signal of the internal pwm controller is available as digital output. all parameters guaranteed for 7v < vs < 20v applications stepper motor driver for bipolar stepper motors in automotive applications like light levelling, bending light and throttle control. description the device is an integrated stepper motor driver for bipolar stepper motors with microstepping and programmable current profile look-up-table to allow a flexible adaptation of the stepper motor characteristics and intended operating conditions. it is possible to use different current profiles depending on target criteria: audible noise, vibrations, rotation speed or torque. the decay mode used in pwm-current control circuit can be programmed to slow-, fast-, mixed-and auto- decay. in autodecay mode device will use slow decay mode if the current for the next step will increase and the fast decay or mixed decay mode if the current will decrease. order codes powersso-24 part number junction temp range, c package packing L9942 -40 to 150 powersso-24 tube www.st.com
L9942 2/37 contents 1 block diagram and pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 dual power supply: vs and vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 standby-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 over-voltage and under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.5 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6 inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.7 cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.8 pwm current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.9 decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.10 over current detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.11 open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.12 stepping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.13 decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4.1 supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4.2 over- and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.3 reference current output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.4 charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.5 outputs: qxn (x=a;b n=1;2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.6 outputs: qxn (x=a;b n=1;2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.7 pwm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 functional description of the logic with spi . . . . . . . . . . . . . . . . . . . . . . 19 4.1 motor stepping clock input( step) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 pwm output (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
L9942 3/37 4.3 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 chip select not (csn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 serial data in (di) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 serial data out (do) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7 serial clock (clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.8 data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 spi - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 counter and profiles register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4 signal and profile register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 counter and profile (register 4 and register 5) . . . . . . . . . . . . . . . . . . . . . . 23 5.6 control, status and profile register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.7 status register7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.8 auxiliary logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.8.1 fault condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.8.2 spi communication monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.8.3 pwm monitoring for stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 logic with spi - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 inputs: csn, clk, step, en and di . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 di timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3 outputs: do, pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4 output: do timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 csn timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6 step timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1 stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.2 load current control and detection of overcurrent (shortages at outputs) 31 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1 block diagram and pin information L9942 4/37 1 block diagram and pin information figure 1. block diagram figure 2. pin connection (top view) gate-driver & pwm-controller spi + register + logic phase counter+current profile ? pwm current dac diagnostic charge pump u/i- converter vcc vbat reversepolarityprotection csn clk di do en step c oscillator biasing vs gnd note: value of capacitor has to be choosen carefully to limit the vs voltage below absolute maximum ratings in case of an unexpected freewheeling condition (e.g. tsd, por) stepper motor qa1 qa2 qb1 qb2 gate-driver & pwm-controller rref diagnostic cp pwm gndp qb2 qb2 gnd all pins with the same name must be externally connected! all pins pgnd are internally connected to the heat slug. pgnd 1 qa1 2 vs 3 4 di 5 csn 6 do 7 8 step 9 vs 10 qb1 11 pgnd 12 pwm pgnd 24 qa2 23 22 en 21 rref 20 vcc 19 test 18 17 cp 16 vs 15 qb2 14 pgnd 13 gnd power sso24 slug- down vs clk
L9942 1 block diagram and pin information 5/37 table 1. pin description pin symbol function 1, 12, 13, 24 pgnd power ground: all pins pgnd are internally connected to the heat slug. important : all pins of pgnd must be externally connected! 3, 10, 15, 22 vs power supply voltage (external reverse protection required): for emi reason a ceramic capacitor as close as possible to pgnd is recommended. important : all pins of vs must be externally connected ! 2, 23 qa1,qa2 fullbridge-outputs an: the output is built by a highside and a lowside switch, which are internally connected. the output stage of both switches is a power dmos transistor. each driver has an internal reverse diode (bulk-drain-diode: highside driver from output to vs, lowside driver from pgnd to output). this output is over-current protected. 11, 14 qb1,qb2 fullbridge-outputs bn: the output is built by a highside and a lowside switch, which are internally connected. the output stage of both switches is a power dmos transistor. each driver has an internal reverse diode (bulk-drain-diode: highside driver from output to vs, lowside driver from pgnd to output). this output is over-current protected. 4 clk spi clock input: the input requires cmos logic levels. the clk input has a pull-down current. it controls the internal shift register of the spi. 5 di serial data input: the input requires cmos logic levels. the di input has a pull-down current. it receives serial data from the microcontroller. the data is a 16bit control word and the least significant bit (lsb, bit 0) is transferred first. 6 csn chip select not input the input requires cmos logic levels. the csn input has a pull-up current. the serial data transfer between device and micro controller is enabled by pulling the input csn to low level. 7 do spi data output: the diagnosis data is available via the spi and it is a tristate- output. the output is cmos compatible will remain highly resistive, if the chip is not selected by the input csn (csn = high) 8 pwm pwm output this cmos compatible output reflects the current duty cycle of the internal pwm controller of bridge a. it is an high resistance output until vcc has reached minimum voltage ore can switched off via the spi command. 9 step step clock input: the input requires cmos logic levels. the step input has a pull-down current. it is clock of up and down counter of control register 0. rising edge starts new pwm cycle to drive motor in next position. 16 cp charge pump output: a ceramic capacitor (e.g.100 nf) to vs can be connected to this pin to buffer the charge-pump voltage. 17 gnd ground: reference potential besides power ground e.g. for reference resistor rref. from this pin exist a resistive path via substrate to pgnd. 18 test test input the test input has a pull-down current. pin used for production test only. in the application it must be connected to gnd. 19 vcc logic supply voltage: for this input a ceramic capacitor as close as possible to gnd is recommended. 20 rref reference resistor the reference resistor is used to generate a temperature stable reference current used for current control and internal oscillator. at this output a voltage of about 1.28v is present. the resistor should be chosen that a current of about 200ua will flow through the resistor. 21 en enable input: the input requires cmos logic levels. the en input has a pull- down resistor. in standby-mode outputs will be switched off and all registers will be cleared. if en is set to a logic high level then the device will enter the active mode.
2 device description L9942 6/37 2 device description 2.1 dual power supply: vs and vcc the power supply voltage vs supplies the half bridges. an internal charge-pump is used to drive the highside switches. the logic supply voltage vcc (stabilized) is used for the logic part and the spi of the device. due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. in case of power-on (vcc increases from under voltage to v por off = 2.60 v, typical) the circuit is initialized by an internally generated power-on-reset (por). if the voltage vcc decreases under the minimum threshold (v por on = 2.45 v, typical), the outputs are switched to tristate (high impedance) and the internal registers are cleared. 2.2 standby-mode the en input has a pull-down resistor. the device is in standby mode if en input isn't set to a logic high level. all latched data will be cleared and the inputs and outputs are switched to high impedance. in the standby mode the current at vs (vcc) is less than 3 a (1a) for csn = high (do in tristate). if en is set to a logic high level then the device will enter the active mode. in the active mode the chargepump and the supervisor functions are activated. 2.3 diagnostic functions all diagnostic functions (overload/-current, open load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered (t gl = 32s, typical) and the condition has to be valid for a minimum time before the corresponding status bit in the status registers will be set. the filters are used to improve the noise immunity of the device. open load and temperature warning function are intended for information purpose and will not change the state of the bridge drivers. on contrary, the overload/-current and thermal shutdown condition will disable the corresponding driver (overload/-current) or all drivers (thermal shutdown), respectively. the microcontroller has to clear the status bit to reactivate the bridge driver. 2.4 over-voltage and under-voltage detection if the power supply voltage vs rises above the over-voltage threshold v sov off (typical 20 v), the outputs are switched to high impedance state to protect the load. when the voltage vs drops below the undervoltage threshold v suv off (uv-switch-off voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). error condition is lached and the microcontroller needs to clear the status bits to reactivate the drivers. 2.5 temperature warning and thermal shutdown if junction temperature rises above t j tw a temperature warning flag is set which is detectable via the spi. if junction temperature increases above the second threshold t j sd , the thermal shutdown bit will be set and power dmos transistors of all output stages are switched off to
L9942 2 device description 7/37 protect the device. in order to reactivate the output stages the junction temperature must decrease below tj sd -tj sd hys and the thermal shutdown bit has to be cleared by the microcontroller. 2.6 inductive loads each half bridge is built by an internally connected highside and a lowside power dmos transistor. due to the built-in reverse diodes of the output transistors, inductive loads can be driven without external free-wheeling diodes. in order to reduce the power dissipation during free-wheeling condition the pwmcontroller will switch-on the output transistor parallel to the freewheeling diode (synchronous rectification). 2.7 cross-current protection the four half-brides of the device are cross-current protected by an internal delay time depending on the programmed slew rate. if one driver (ls or hs) is turned-off then activation of the other driver of the same half bridge will be automatically delayed by the cross-current protection time . 2.8 pwm current regulation an internal current monitor output of each high-side and low-side transistor sources a current image which has a fixed ratio of the instantaneous load current. this current images are compared with the current limit in pwm control. range of limit can reach from programmed full scale value (register1 dac scale) down belonging lsb value of 5 bit dac (register1 dac phase x). the data of the two 5 bit dacs comes form set up in 9 current profiles (register2 to 6). if signal changes to logic high at pin step then 2 currentprofiles are moved in register1 for dac phase a and b. number of profile depends on phase counter reading and direction bit in register0 ( figure 7 ). the bridges are switched on until the load current sensed at hs switch exceeds the limit . load current comparator signal is used to detect open load or overcurrent condition also. 2.9 decay modes during off-time the device will use one of several decay modes programmable by spi ( figure 4 top). in slow decay mode hs switches are activated after cross current protection time for synchronous rectification to reduce the power dissipation ( figure 4 detail a). in fast decay opposite halfbridge will switched on after cross current protection time, that is same like change in the direction. for mixed decay the duration of fast decay period before slow decay can be set to a fixed time ( figure 4 detail b continuous line ) or is triggered by under-run of the load current limit ( figure 4 detail b dashed line), that can be detected at ls switch. the special mode where the actual phase counter value is taken into account to select the decay mode is called auto decay (e.g. in figure 3 micro stepping dir=1). if the absolute value of the current limit is higher as during step before then pwm control uses slow decay mode always. otherwise one of the fast decay modes is automatic selected for a quick decrease of the load current and so it obtains new lower target value.
2 device description L9942 8/37 2.10 over current detection the overcurrent detection circuit monitors the load current in each activated output stage. in hs stage it is in function after detection of currentlimit during pwm cycle and in ls stage it works permanently. if the load current exceeds the overcurrent detection threshold for at least tisc = 4 s, the over-current flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. error condition is lached and the microcontroller needs to clear the status bits to reactivate the drivers. 2.11 open load detection the open load detection monitors the activity time of the pwm controller and is available for each phase. if the limit of load current is below around 100ma then open load condition is detectable. open load bit for a bridge is set in the register6 if this low current limit can't reached after at least 15 consecutive pwm cycles. table 2. truth table truth table shows possible profiles for active open load detection. maximum threshold iol is shown in left column if x bits are 1 (see also figure 7 ). lowest possible limit is e.g. 3.1 ma for dc2=dc1=dc0=0 and it is set only i0=1. 2.12 stepping modes one full revolution can consist of four full steps, eight half steps, sixteen mini steps or 32 microsteps. mode is set up in register 0 and it defines increment size of phase counter. phase counter value defines address of corresponding currentprofile. stepping modes with typical profile values can see in figure 3 (e.g. also so called 'two phase on' shown in dashed line). dc2 dc1 dc0 i4 i3 i2 i1 i0 max. iol 0000 xxxx48ma 0010 xxxx72ma 01000xxx56ma 11000xxx90ma 100000xx58ma 101000xx87ma 1100000142ma 1110000148ma
L9942 2 device description 9/37 figure 3. stepping modes 080 8 081624 080 8 current driver a current driver b step signal phase counter full-stepping mode: dir=0 address of current profile entry 0808 24 16 8 0 080 8 current driver a current driver b step signal full-stepping mode: dir=1 address of current profile entry 04840 484 0 4 812 162024 28 048 404 84 current driver a current driver b step signal address of current profile entry phase counter half-stepping mode: dir=0 048 404 84 0 2824 2016128 4 048404 84 driver current a driver current b step signal half-stepping mode: dir=1 address of current profile entry 0246864202468642 0 2 4 6 81012141618 202224262830 024686420246 8642 current driver a current driver b step signal phase counter mini-stepping mode: dir=0 0246864202468642 0 3028 26 2422 20 1816 14 1210 8 6 4 2 024686420246 8642 current driver a current driver b step signal mini-stepping mode: dir=1 adress of current profile entry adress of current profile entry 012 345 678 765 432 101 234 567 876 543 21 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 123 456 787 654 321 012 345 67 876 543 21 current driver a current driver b adress of current profile entry phase counter micro stepping mode: dir=0 (e.g auto decay) 0 12 345 678 765 432 101 234567 876 543 21 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 123 456 787 654321 012 345 67 8 76 543 21 slow decay mode mixed decay mode current driver a current driver b micro stepping mode: dir=1 (e.g. auto decay) 0 adress of current profile entry mixed decay mode mixed decay mode mixed decay mode slow decay mode slow decay mode slow decay mode slow decay mode mixed decay mode slow decay mode slow decay mode slow decay mode mixed decay mode mixed decay mode mixed decay mode
2 device description L9942 10/37 2.13 decay modes figure 4. decay modes a slow decay internal pwm_clk on b load current detail a: switch on and slow decay step limit hs detail b: mixed decay t when limit is reached so fast decay duration time is set by dm1 dm2 register0 t ft filter time for the purpose of switch off delay in on mode is set by ft register6 t cc t ft dm2 dm1 dm0 mode 0 0 0 register0 time time slow dm2 dm1 dm0 mode curve x 0 1 register0 x 1 0 x 1 1 md1 t md2 t mc t cross current protection time is set by sr1 sr0 register0 md1 filter time for purpose of delay when decay mode has to change after limit under-run cc t t cc t vs on on vs on on vs on on mdx = mc t cc + 2t = t ft t md t ft vs on on vs on slow decay md2 or t fast decay is caused by current through internal diodes during cross current protection time. vs off on off off off fast decay mixed decay t mdx time cc t slow decay with delay load current load current step limit ls time t ft cc t slow decay after current undershoot mc t load current fast decay cc t cc t > t b t b blank time of load current comparator fast decay t bcc =t fast decay fast decay
L9942 3 electrical specifications 11/37 3 electrical specifications 3.1 absolute maximum ratings table 3. absolute maximum ratings note: leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit ! 3.2 esd protection table 4. esd protection note: 1 hbm according to mil 883c, method 3015.7 or eia/jesd22-a114-a 2 hbm with all unzapped pins grounded 3.3 thermal data table 5. operating junction temperature symbol parameter value unit vs dc supply voltage -0.3...28 v single pulse t max < 400 ms 40 v vcc stabilized supply voltage, logic supply -0.3 to 5.5 v v di ,v do , v clk v csn , v step v en digital input / output voltage -0.3 to vcc + 0.3 v v rref current reference resistor -0.3 to vcc + 0.3 v v cp charge pump output -0.3 to vs + 11 v v qxn (x=a;b n=1;2) output voltage -0.3 to vs + 0.3 v i qxn (x=a;b n=1;2) output current 2.5 a parameter value unit all pins 2 1 kv output pins: qxn (x=a;b n=1;2) 4 2 kv symbol parameter value unit t j operating junction temperature -40 to 150 c
3 electrical specifications L9942 12/37 table 6. temperature warning and thermal shutdown figure 5. thermal data of package symbol parameter min. typ. max. unit t jtw on temperature warning threshold junction temperature t j increasing 150 c t jtw off temperature warning threshold junction temperature 130 c t jsd on thermal shutdown thresholdjunction temperature 170 c t jsd off thermal shutdown threshold junction temperature 150 c t jsd hys thermal shutdown hysteresis 5 k note: 1s 1 signal layer 2s2p 2 signal layers 2 internal planes
L9942 3 electrical specifications 13/37 3.4 electrical characteristics 3.4.1 supply vs = 7 to 16v, vcc = 3.0 to 5.3 v, t j = -40 to 150 c, i ref = -200 a , unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. note: 1 this parameter is guaranteed by design. table 7. supply symbol parameter test condition min. typ. max. unit i s vs dc supply current in active mode vs = 13.5 v, en=vcc outputs floating 7 20 ma vs quiescent supply current vs = 13.5 v, test, en = 0v outputs floating t j = -40 c to 25c 3 10 a t j = 125 c 6 20 i cc vcc dc supply current in active mode vcc = 5.0 v en=vcc, di=clk=step=0v 1 3 ma vcc = 5.0 v test; en = 0v; csn = vcc no clocks outputs floating t j = -40 c to 25c 1 3 a i cc vcc quescent suppy current csn=vcc no clocks outputs floating t j = 125 c 2 6 a vs = 13.5 v, vcc = 5.0 v t j = -40 c to 25c 4 13 a i s + i cc sum quiescent supply current test; en=0v csn=vcc no clocks outputs floating t j = 125 c 8 26 t setpor 1 vcc on set up time en = 5v, csn=clk=0v do changes from high ohmic to logic level low 2 s
3 electrical specifications L9942 14/37 3.4.2 over- and undervoltage detection vs = 7 to 20 v, vcc = 3.0 to 5.3 v, en=vcc, t j = -40 to 150 c, i ref = -200 a, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. table 8. over- and undervoltage detection . figure 6. vs monitoring 3.4.3 reference current output vs = 7 to 20 v, vcc = 3.0 to 5.3 v, en=vcc, t j = -40 to 150 c, i ref = -200 a, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. table 9. reference current output the device works properly without the external resistor at pin ref. in this case it doesn't have to fullfill all specified parameters. symbol parameter test condition min. typ. max. unit v suv on vs uv-threshold voltage vs increasing 6.90 v v suv off vs uv-threshold voltage vs decreasing 4.8 v v suv hyst vs uv-hysteresis v suv on -v suv off 0.3 v v sov off vs ov-threshold voltage vs increasing 25 v v sov on vs ov-threshold voltage vs decreasing 20 v v sov hys t vs ov-hysteresis v sov off -v sov on 0.5 v v por off power-on-reset threshold vcc increasing 2.6 2.9 v v por on power-on-reset threshold vcc decreasing 2.00 2.3 v v por hyst power-on-reset hysteresis v por off -v por on 0.11 v symbol parameter test condition min. typ. max. unit v ref reference voltage range i ref = -200 a 1.05 1.25 1.45 v i refshorted reference current threshold shorted pin ref register6 bit7 rerr = 1 -250 a i refopen reference current threshold open pin ref register6 bit7 rerr = 1 -150 a register 7 uv 1 0 vs vsuv on vsuv off register 7 ov 1 0 vs vsov off vsov on
L9942 3 electrical specifications 15/37 3.4.4 charge pump output vs = 7 to 20 v, vcc = 3.0 to 5.3 v, en=vcc, t j = -40 to 150 c, i ref = -200 a, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. table 10. charge pump output the ripple of voltage at cp can suppressed using a capicity of e.g.100nf. 3.4.5 outputs: qxn (x=a;b n=1;2) vs = 7 to 20 v, vcc = 3.0 to 5.3 v, en=vcc, t j = -40 to 150 c, i ref = -200 a, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin table 11. outputs: qxn (x=a;b n=1;2) symbol parameter test condition min. typ. max. unit vcp charge pump output voltage vs=7v i cp = -100 a, all switches off at qxn 11 20 v vs=13.5v 20 35 v vs=20v 30 40 v symbol parameter test condition min. typ. max. unit r dson hs on-resistance qxn to vs vs = 13.5 v, t j = 25 c, i qxn = -1.0a 500 700 m ? vs = 13.5 v, t j = 125 c, i qxn = -1.0 a 750 1000 m ? vs = 7.0 v, t j = 25 c, i qxn = -1.0 a 550 750 m ? r dson ls on-resistance qxn to pgnd vs = 13.5 v, t j = 25 c, i qxn = + 1.0a 500 700 m ? vs = 13.5 v, t j = 125 c, i qxn = + 1.0 a 750 1000 m ? vs = 7.0 v, t j = 25 c, i qxn = + 1.0 a 550 750 m ? |i qxnoc | output overcurrent limitation to vs or pgnd testmode exclusive of filtertime 4us ( chapter 2.10 ) 1.6 2 a
3 electrical specifications L9942 16/37 3.4.6 outputs: qxn (x=a;b n=1;2) the comparator, which is monitoring current image of hs, is working during on cycle of pwm control. if load current is higher as set value then the signal ilimit is generated and after filter time the bridge is switched off. test mode gets access to signal ilimit and threshold of current can be measured. table 12. outputs: qxn (x=a;b n=1;2) vs = 7 to 20 v, vcc = 3.0 to 5.3 v, en=vcc, t j = -40 to 150 c, i ref = -200 a, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin note: 1 current profile has to pre set with i4 i3 i2 i1 i0 = 11111 and load to register 1 . 2 min= 0.92 i qxnlim ? 0.02 |i qxnfs_hs | , max= 1.08 i qxnlim + 0.02 |i qxnfs_hs | output current limit iqxnlim is product of full scale current |iqxnfs_ | ( bits dc2 dc1 dc0) and value of dac phasea/b ( bits i4 i3 i2 i1 i0) in register1. values of dac phase a and b can read out and depends on set up done before: 1. direction dir , stepping mode st1 st0 and phase counter p4 p3 p2 p1 p0 in register 0 and 2. value of corresponding current profile (for address of current profile entry see also figure 3 ). symbol parameter test condition min. typ. max. unit i qxnfs_hs value of output current to supply vs ( so called full scale value) 1 sourcing from hs switch bits: dc2 dc1 dc0=000 60 95 130 ma bits: dc2 dc1 dc0=001 100 140 180 bits: dc2 dc1 dc0=010 180 230 280 bits: dc2 dc1 dc0=011 300 360 420 bits: dc2 dc1 dc0=100 485 550 615 bits: dc2 dc1 dc0=101 720 810 900 bits: dc2 dc1 dc0=110 1000 1150 1300 bits: dc2 dc1 dc0=111 1200 1350 1500 i qxnlim_hs accuracy of micro steps current limit min 2 max 2 ma
L9942 3 electrical specifications 17/37 figure 7. logic to set load current limit 3.4.7 pwm control vs = 7 to 20 v, vcc = 3.0 to 5.3 v, en=vcc, t j = -40 to 150 c, i ref = -200 a, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. table 13. pwm control (see figure 4 and figure 7 ) symbol parameter test condition min. typ. max. unit f pwm 1 frequency of pwm cycles bit: fre= 1 20.8 khz bit: fre= 0 31.3 khz t md 1 mixed decay switch off delay time bits: dm1 dm0= 0 1 4 us bits: dm1 dm0= 1 0 8 us t ft 1 glitch filter delay time bit: filter= 0 1.5 us bit: filter= 1 2.5 us register 0 up/down step i4 i3 i2 i1 i0 count by 1,2,4,8 a0 a1 a2 a3 mux a0 a1 a2 0 0 0 012301230123 current-profile table stored in register2, ...6 a3=0 adr a[3..0] phase a profile 8 address calculation i4 i3 i2 i1 i0 profile 7 i4 i3 i2 i1 i0 profile 6 i4 i3 i2 i1 i0 profile 5 i4 i3 i2 i1 i0 profile 4 i4 i3 i2 i1 i0 profile 3 i4 i3 i2 i1 i0 profile 2 i4 i3 i2 i1 i0 profile 1 i4 i3 i2 i1 i0 profile 0 5 5 5 5 5 5 5 5 5 a3=1 adr neg(a[3..0]) a3=0 adr neg(a[3..0]) phase b a3=1 adr a[3..0] register 1 9 5 dir p0 p1 p2 p3 p4 phasecounter stepmode sr0 sr1 st1 st0 slew rate dm2 dm1 dm0 mux mux i0 i1 i2 i3 i4 i0 i1 i2 i3 i4 dac phase b dac phase a decay mode 5 bit dac phase a 5 bit dac phase b dc0 dc1 dc2 dac scale dac full scale ref ref i max i limit b limit a i di qb1 qb2 qa1 qa2 qx1lim i qx2lim i qa1lim i 1000 qb2lim i 1000 qb1lim i 1000 qa2lim i 1000
3 electrical specifications L9942 18/37 note: 1 this parameter is guaranteed by design. time base is an internal trimmed oscillator of typical 2mhz and it has an accuracy of 6% . figure 8. switching on minimum time symbol parameter test condition min. typ. max. unit t cc 1 t b 1 cross current protection time blank time of comparator bits: sr1 sr0= 0 0 0.5 us bits: sr1 sr0= 0 1 1 us bits: sr1 sr0= 1 0 2 us bits: sr1 sr0= 1 1 4 us vsr slew rate (dv/dt 30%-70%) @hs switches on resistive load of 10 ? , vs=13.5v bits: sr1 sr0= 0 0 13 v/us bits: sr1 sr0= 0 1 13 v/us bits: sr1 sr0= 1 0 6 v/us bits: sr1 sr0= 1 1 6 v/us table 13. pwm control (see figure 4 and figure 7 ) (continued) internal pwm clock 20 or 30 khz decay on load current at qxn step limit t b blank time of current comparator t cc t ft time cross current protection time cc t t cc t pwm t b t ft filter time of current comparator pin pwm (for bridge a) t int _2mhz e.g. t b = t cc t ft = 1.5 us = 1 us
L9942 4 functional description of the logic with spi 19/37 4 functional description of the logic with spi 4.1 motor stepping clock input( step) rising edge of signal step is latched. it is synchronised by internal clock. at next start of a new pwm cycle the new values of output current limit are used to drive motor in next position. before start new motor step this signal has to be low for at least two internal clock periods to reset latch. 4.2 pwm output (pwm) this output reflects the current duty cycle of the internal pwm controller of bridge a. high level indicates on state to increase current through load and low level is in off state so load current decreases depending on chosen decay mode. 4.3 serial peripheral interface (spi) this device uses a standard 16 bit spi to communicate with a microcontroller. the spi can be driven by a microcontroller with its spi peripheral running in following mode: cpol = 0 and cpha = 0. for this mode, input data is sampled by the low to high transition of the clock clk, and output data is changed from the high to low transition of clk. a fault condition can be detected by setting csn to low. if csn = 0, the do-pin will reflect an internal error flag of the device which is a logical-or of all status bits in the status register (reg7) and in the current profile register 4 (reg6). the microcontroller can poll the status of the device without the need of a full spi-communication cycle. 4.4 chip select not (csn) the input pin is used to select the serial interface of this device. when csn is high, the output pin (do) will be in high impedance state. a low signal will activate the output driver and a serial communication can be started. the state when csn is going low until the rising edge of csn will be called a communication frame. 4.5 serial data in (di) the input pin is used to transfer data serial into the device. the data applied to the di will be sampled at the rising edge of the clk signal and latched into an internal 16 bit shift register. the first 3 bit are interpreted as address of the data register. at the rising edge of the csn signal the contents of the shift register will be transferred to the selected data register. the writing to the register is only enabled if exactly 16 bits are transmitted within one communication frame (i.e. csn low). if more or less clock pulses are counted within one frame the complete frame will be ignored. this safety function is implemented to avoid an activation of the output stages by a wrong communication frame.
4 functional description of the logic with spi L9942 20/37 note: due to this safety functionality a daisy chaining of spi is not possible. instead, a parallel operation of the spi bus by controlling the csn signal of the connected ics is recommended. 4.6 serial data out (do) the data output driver is activated by a logical low level at the csn input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). the first rising edge of the clk input after a high to low transition of the csn pin will transfer the content of the selected status register into the data out shift register. each subsequent falling edge of the clk will shift the next bit out. 4.7 serial clock (clk) the clk input is used to synchronize the input and output serial bit streams. the data input (di) is sampled at the rising edge of the clk and the data output (do) will change with the falling edge of the clk signal. 4.8 data register the device has eight data registers. the first three bits (bit0 ... bit2) at the di-input are used to select one of the input registers. all bits are first shifted into an input shift register. after the rising edge of csn the contents of the input shift register will be written to the selected input data register only if a frame of exact 16 data bits are detected. the selected register will be transferred to do during the current communication frame. figure 9. spi and registers d di clk_adr d1 a1 d0 a2 d3 d4 d5 d6 d7 d8 d9 d10 d11 do dir control register 0 ai0 ai1 ai2 ai3 ai4 bi0 bi1 bi2 bi3 bi4 dac phase b dac phase a counter and profiles register 2 p0 p1 p2 p3 p4 phase a phase b status register 7 d2 d12 phase counter control register 1 i0 i1 i2 i3 i4 i0 i1 i2 i3 i4 current profile 0 current profile 1 t2 test openload lsa1 hsa1 lsa2 hsa2 lsb1 lsb2 hsb1 hsb2 overcurrent uv ov csn clk int_2mhz spi- controll por slew rate step mode sr0 sr1 st1 st0 dac_scale dc1 dc2 temperature vs monitor sel_error spi2reg d a1 a0 a2 tsd tw rref error clr status clr status read-only dc0 read only pwm freq filter i0 i1 i2 i3 i4 current profile 8 read-only st i0 i1 i2 i3 i4 i0 i1 i2 i3 i4 current profile 2 current profile 3 npwm t3 t4 t5 test i0 i1 i2 i3 i4 i0 i1 i2 i3 i4 current profile 4 current profile 5 i0 i1 i2 i3 i4 i0 i1 i2 i3 i4 current profile 6 current profile 7 decay mode dm0 dm1 dm2 sst a0 pwm counter pwm test pwm counter pwm counter dt5 dt6 dt7 dt2 dt3 dt4 dt0 dt1 singnal and profiles register 3 counter and profiles register 4 counter and profiles register 5 control, status and profile register 6
L9942 5 spi - control and status registers 21/37 5 spi - control and status registers 5.1 control register 0 the meaning of the different bits is as follows: bit phase counter decay mode slew rate step mode dir 12 11 10 9 8 7 6 5 4 3 2 1 0 access r w r w r w r w r w r w r w r w r w r w r w r w r w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 name p4 p3 p2 p1 p0 dm2 dm1 dm0 sr1 sr0 st1 st0 dir dir this bit controls direction of motor movement. dir=1 clockwise dir=0 counter clockwise. st1 st0 this bits controls step mode of motor movement ( figure 3 ). 00 micro-stepping 01 mini-stepping 10 half-stepping 11 full-stepping sr1 sr0 this bit controls slew rate of bridge switches. see also parameter ta b l e 1 3 dm2 dm1 dm0 this bits controls decay mode of output current ( figure 3 ). 000 slow decay 001 mixed decay, fast decay until t md > 4us 010 mixed decay, fast decay until t md > 8us 011 mixed decay, fast decay until current undershoot t mc =t ft +t cc 100 auto decay, fast decay without delay time auto decay uses mixed decay automatically to reduce current for next step if required ( see figure 3 down right). 101 auto decay, fast decay until t md > 4us 110 auto decay, fast decay until t md > 8us 111 auto decay, fast decay until current undershoot t mc p4 p3 p2 p1 p0 this bits control position of motor, e.g. 00000 step angle is 0 , 01111 step angle is 180..
5 spi - control and status registers L9942 22/37 5.2 control register 1 the meaning of the different bits is as follows: 5.3 counter and profiles register 2 the meaning of the different bits is as follows: 5.4 signal and profile register 3 bit dac scale dac phase b dac phase a 12 11 10 9 8 7 6 5 4 3 2 1 0 access r w r w r w r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 name dc2 dc1 dc0 bi4 bi3 bi2 bi1 bi0 ai4 ai3 ai2 ai1 ai0 ai4 ai3 ai2 ai1 ai0 these bits control dac of bridge a. value depends on address and the value of corresponding current profile. bi4 bi3 bi2 bi1 bi0 these bits control dac of bridge b . dc2 dc1 dc0 these bits set full scale range of limit, e.g. 000 for 100 ma or 111for e.g. 1500ma see also parameter ta b le 1 2 . bit current profile 1 not used current profile 0 12 11 10 9 8 7 6 5 4 3 2 1 0 access r w r w r w r w r w r w r w r w r w r w r w r w r w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 name i4 i3 i2 i1 i0 t2 t1 t0 i4 i3 i2 i1 i0 i4 i3 i2 i1 i0 these bits are loaded in register1 dac phase a or b if needed. see also parameter ta bl e 1 2 t2 t1 t0 these bits are used in test mode only. bit current profile 3 pwm counter pwm current profile 2 12 11 10 9 8 7 6 5 4 3 2 1 0 access r r r r r r r r r r r r r w w w w w w w w w w w w w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 name i4 i3 i2 i1 i0 d1 (t5) d0 (t4) npw m(t3) i4 i3 i2 i1 i0
L9942 5 spi - control and status registers 23/37 the meaning of the different bits is as follows: 5.5 counter and profile (register 4 and register 5) the meaning of the different bits is as follows: 5.6 control, status a nd profile register 6 the meaning of the different bits is as follows: i4 i3 i2 i1 i0 these bits are loaded in register1 dac phase a or b if needed. see also parameter ta b le 1 2 dt1 dt0 these bits are for threshold value in counter of active time during signal pwm. npwm this bit switches internal pwm signal of bridge a to pin pwm if it is set to 0, otherwise pin is in high resistance status. (t5 t4 t3) these bits are used in test mode only. bit current profile 5 (7) pwm counter current profile 4 (6) 12 11 10 9 8 7 6 5 4 3 2 1 0 access r w r w r w r w r w r w r w r w r w r w r w r w r w reset000000 0 000000 name i4 i3 i2 i1 i0 d4(7) d3(6) d2(5) i4 i3 i2 i1 i0 i4 i3 i2 i1 i0 these bits are loadedneeded. in register1 dac phase a or b if needed. see also parameter table 12 d4 d3 d2 (register4 ) these bits are for threshold value in counter of active time during signal pwm. lsb and next value are set in register3 by d0 and d1. d7 d6 d5 (register5) clr st ( pwm ) filter freq st ref err openload current profile 8 bit 12 11 10 9 8 7 6 5 4 3 2 1 0 access r w r w r w r w r r r r r w r w r w r w r w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 name clr6 sst ft fre st rerr ob oa i4 i3 i2 i1 i0 i4 i3 i2 i1 i0 these bits are loaded in register1 dac phase a or b if needed see also parameter ta bl e 1 2 ob oa these bits indicate openload at bridges rerr this bit indicates if reference current is ok (150ua 5 spi - control and status registers L9942 24/37 5.7 status register7 the meaning of the different bits is as follows: 5.8 auxiliary logic blocks 5.8.1 fault condition logical level at pin d0 represents fault condition. it is valid from first high to low edge of signal clk up to transfer of data bit d12. fault bit is an logical or of: control and status register 6 bit 5 and 6 for open load, bit7 reference current failure (rerr) and control and status register 7 bit 0 to bit 7 for overcurrent, bit 8 and 9 failure at vs (uv,ov) and bit 10 and bit 11 during high temperature (tw,tsd) ft this bit sets filter time in glitch filter. ft=0 t f =1.5us, ft=1 t f =2.5us sst this bit specifies output pwm to reflect same logical level like bit st. clr6 this bit resets all bits to 0 in register 6. bit clr temperature vs monitor overcurrent 12 11 10 9 8 7 6 5 4 3 2 1 0 access r w r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 name clr7 tsd tw ov uv hsb2 hsb1 lsb2 lsb1 hsa2 hsa1 lsa2 lsa1 bit7 ... bit0 these bits indicate overcurrent in each lowside or highside power transistor. 1 overcurrent failure i > 2a ov uv these bits indicates failure at vs ( see also parameter table 8 ) 01 voltage at pin vs is too low. 10 voltage at pin vs is too high. tsd tw these bits indicates temperature failure ( see also parameter ta bl e 6 ) 01 only for information set at temperature warning threshold. 10 in case of thermal shutdown all bridges are switched off. it has to reset by bit clr7. clr7 this bit resets all bits to 0 in register7.
L9942 5 spi - control and status registers 25/37 5.8.2 spi communication monitoring at the rising edge of the csn signal the contents of the shift register will be transferred to the selected data register. a counter monitors proper spi communication. it counts rising edges at pin clk. the writing to the register is only enabled if exactly 16 bits are transmitted within one communication frame (i.e. csn low). if more or less clock pulses are counted within one frame the complete frame will be ignored. this safety function is implemented to avoid an activation of the output stages by a wrong communication frame. spi communication can be checked by loading a command twice and then answer at pin do must be same. note: due to this safety functionality a daisy chaining of spi is not possible. instead, a parallel operation of the spi bus by controlling the csn signal of the connected ics is recommended. 5.8.3 pwm monitoring for stall detection control registers 4, 5, and 3 contain bits d0-d7, use for setting a stall detection threshold. the value in this set of bits determine the minimum time for current rise over one quadrant of motor driving. d7-d0 is compared with the sum of the rise times over one quadrant. when the sum is less than the value stored in d7-d0 the st bit (register6 bit 8) is set to a logic ?1?. the pwm pin reflects the pwm control signal of the load current in bridge a. this is so after power on when the sst bit (register 6, bit11) is reset to a logic ?0?. if this bit is set to a logical ?1? then status of the st bit 8 is mirrored to pin pwm. this provides stall detection without the need of reading register 6 through the spi bus.
6 logic with spi - electrical characteristics L9942 26/37 6 logic with spi - electrical characteristics vs = 7 to 20 v, vcc = 3.0 to 5.3 v, en=vcc, t j = -40 to 150 c, i ref = -200 a, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6.1 inputs: csn, clk, step, en and di table 14. inputs: csn, clk, step, en and di (1) parameter guaranteed by design. 6.2 di timing table 15. di timing (see figure 11 and figure 13 ) (2) (2) di timing parameters tested in production by a passed/failed test: t j =-40c/+25c: spi communication @5mhz; t j =+125c: spi communication @4.25mhz symbol parameter test condition min. typ. max. unit v in l input low level vcc = 5 v 1.5 2.0 v v in h input high level vcc = 5 v 3.0 3.5 v v in hyst input hysteresis vcc = 5 v 0.5 v i csn in pull up current at input csn v csn = vcc-1.5 v, -50 -25 -10 a i clk in pull down current at input clk v clk = 1.5 v 10 25 50 a i di in pull down current at input di v di = 1.5 v 10 25 50 a i step in pull down current at input step v step = 1.5 v 10 25 50 a r en in resistance at input en to gnd v en in = vcc 110 510 k ? c in (1) input capacitance at input csn, clk, di and pwm 0 v < vcc < 5.3 v 10 15 pf symbol parameter test condition min. typ. max. unit t clk clock period vcc = 5 v 250 ns t clkh clock high time vcc = 5 v 100 ns t clkl clock low time vcc = 5 v 100 ns t set csn csn set up time, csn low before rising edge of clk vcc = 5 v 100 ns t set clk clk set up time, clk high before rising edge of csn vcc = 5 v 100 ns t set di di set up time vcc = 5 v 50 ns t hold di di hold time vcc = 5 v 50 ns t r in rise time of input signal di, clk, csn vcc = 5 v 25 ns t f in fall time of input signal di, clk, csn vcc = 5 v 25 ns
L9942 6 logic with spi - electrical characteristics 27/37 6.3 outputs: do, pwm table 16. outputs: do, pwm 6.4 output: do timing table 17. output: do timing (see figure 12 and figure 13 ) 6.5 csn timing table 18. csn timing symbol parameter test condition min. typ. max. unit v dooutl output low level vcc = 5 v, i d = 2 ma 0.2 0.4 v v pwmoutl v doouth output high level vcc = 5 v, i d = -2 ma vcc - 0.4 vcc - 0.2 v v pwmouth i dooutlk tristate leakage current v csn = vcc, 0 v < v do < vcc -10 10 a i pwmoutlk tristate leakage current register3bit5=1 (npwm) 0 v < v pwm < vcc -10 10 a c out (1) tristate input capacitance v csn = vcc, 0 v < vcc < 5.3 v 10 15 pf symbol parameter test condition min. typ. max. unit t r do do rise time c l = 100 pf, i load = -1 ma 50 100 ns t f do do fall time c l = 100 pf, i load = 1 ma 50 100 ns t en do tri l do enable time from tristate to low level c l = 100 pf, i load = 1 ma pull- up load to vcc 50 250 ns t dis do l tri do disable time from low level to tristate c l = 100 pf, i load = 4 ma pull- up load to vcc 50 250 ns t en do tri h do enable time from tristate to high level c l = 100 pf, i load = -1 ma pull- down load to gnd 50 250 ns t dis do h tri do disable time from high level to tristate c l = 100 pf, i load = -4 ma pull-down load to gnd 50 250 ns t d do do delay time v do < 0.3 vcc, v do > 0.7 vcc, c l = 100 pf 50 250 ns symbol parameter test condition min. typ. max. unit t csn_hi,min (1) csn high time, active mode transfer of spi-command to input register 2 s
6 logic with spi - electrical characteristics L9942 28/37 6.6 step timing table 19. step timing (1) parameter guaranteed by design. figure 10. transfer timing diagram figure 11. input timing symbol parameter test condition min. typ. max. unit t stepmin (1) step low or high time 2 s a2 a1 time time time time time csn high to low: do enabled actual data di: data will be accepted on the rising edge of clk signal new data csn clk di do control and status register do: data will change on the falling edge of clk signal status information fault bit csn low to high: actual data is transfered to registers old data 123 456 7891011 0121314151 0 actual data a1 a0 d12d11 d10 d9 d8 d7 d6 d5 d4 a2 d3 d2 d1 d0 d0 d12d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t csn_hi,min fault bit 0.8 vcc 0.8 vcc 0.8 vcc 0.2 vcc 0.2 vcc 0.2 vcc va l id va l id csn clk di t set csn t clkh t set clk t cl kl t hold di t set di t clk
L9942 6 logic with spi - electrical characteristics 29/37 figure 12. spi - do valid data delay time and valid time figure 13. do enable and disable time 0.8 vcc 0.8 vcc 0.8 vcc 0.2 vcc 0.2 vcc 0.2 vcc clk do (low to hi g h) do (hi g h to low) 0.5 vcc t r i n t rdo t f do t ddo t fin csn t f in r in t do do e n d o tri l t t dis d o l tri 50% 0.8 v c c 0.2 v c c 50% 50% e n d o tri h t t dis d o h tri c = 100 pf l c = 100 pf l pull-up load to v c c pull-dow n load to g n d
6 logic with spi - electrical characteristics L9942 30/37 figure 14. timing of status bit 0 (fault condition) csn clk di do csn hi g h to l ow an d clk stays l ow : status i n f orm at i on o f d ata bi t 0 (f au l t c o n di t i on ) i s trans f ere d to do d i: d a ta is n o t a c c e p te d d o : status inform ation of data bit 0 (fault condition) w ill stay as long as c s n is low tim e tim e tim e tim e 0 -
L9942 7 appendix 31/37 7 appendix 7.1 stall detection the L9942 contains logic blocks designed to detect a motor stall caused by excessive mechanical load. during a motor stall condition the load current rises much faster than during normal operation. the L9942 measures this time and compares it to a programmed value. this is done by summing the pwm on times for one full quadrant. for a full wave stepping this is just one value (step 0). for microstepping this includes 8 separate values added together, one for each step. this measurement is only done on phase a during the quadrants where the current is increasing naturally (quadrants 1 and 3 of figure 15 ); e.g. stall detection is active during phase counter values 1 to 8 and 17 to 24 for dir=0. during the quadrants where the current is decreasing fast decay recirculation interferes with accurate measurement of this time. if the sum of the pwm on time is less than a programmed threshold stored in d0-d7, stall is detected and indicated as a logic ?1? in the stall (st) bit found in register 6 bit 8 ( figure 15 bottom). if bit 11 of register 6 is set to logical ?1? then the st bit is mirrored to the pwm pin providing detection externally. the register values dt7-dt0 store the threshold value in 16us intervals. these bits can be found interstitially in register 3 (d0, d1), register4 (d2, d3, d4) and register5 (d5, d6, d7). care should be taken when deciding the threshold timing. motor current slew rates are dependant on the driving voltage, the actual speed of the motor, the back emf of the motor as well as the motor and the inductance. be sure to set your threshold well away from what can be seen in normal operation at any temperature. 7.2 load current control and detection of overcurrent (shortages at outputs) the L9942 controls load current in the two full bridges by using a pulls with modulation (pwm) regulator. the mirrored output current of active hs switch is compared with a programmed reference current (e.g. in figure a2 hsa1 and hsb2). bridge is switched off if current has exceeded the programmed limit value. a second comparator of the related ls switch uses the mirrored load current to detect an overcurrent to ground during on state of bridges (e.g. in figure 16 lsa2 and lsb1). the event of shortage from output to supply voltage vs is detectable, but short current between outputs is limited through pwm controller and so an overcurrent failure will not occur. load currents decrease more or less fast during off state of bridges depending on selected decay mode. slow decay mode is realised by activating the hs switches of the bridge and current comparator has as new reference the overcurrent limit. a shortage to ground can be detected, but not between the outputs. is it recommended to use the different fast decay modes too, especially in period if the load current has to reduce from step to step. the duration of fast decay can set by fixed time ore that it depends on the comparator signal utilising the second current mirror at ls switch. there can be monitored the undershoot of bridge current during off state.
7 appendix L9942 32/37 fast decay can be seen as switching the bridge in opposite direction, if it is compared to on state before. the load current control at hs switch is not used, but the comparator is still active. the reference value is changed to overcurrent limit and a shortage to ground or now between the outputs too will result in a signal. the internal filter time of at least 4 us will inhibit the signal in many applications. then you can use the mode ?auto decay without any delay time? (on section 5.1 on page 21 mode 100). on page 34 you can find in the lower part of figure 3 the phase counter values, when fast decay as only part of mixed decay is used and the shortages can be detected during a longer time. after this it is signalised in register 7 as overcurrent in hs switch (e.g. in figure 17 hsa1). figure 15. stall detection 0123456787654321012345678765432 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 012345678765432101234567 87654321 current driver a current driver b step signal adress of current profile entry phase counter micro stepping mode: dir=0 0123456787654321012345678765432 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 012345678765432101234567 87654321 current driver a current driver b micro stepping mode: dir=1 0 adress of current profile entry time pwm activ detection load current rising during high speed pwm activ counter stall threshold stall threshold activ sampling and threshold activ sampling and threshold pwm activ counter pwm activ detection pwm activ detection counter value is above threshold value. bit6 bit7 d7 d6 d5 d4 d3 d2 d1 d0 register 4 bit5 bit6 bit7 reg3 register 5 bit5 bit6 bit7 stall time threshold 16us * no stall signal 0123456787654321012345678765432 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 012345678765432101234567 87654321 current driver a current driver b step signal adress of current profile entry phase counter micro stepping mode: dir=0 0123456787654321012345678765432 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 012345678765432101234567 87654321 current driver a current driver b micro stepping mode: dir=1 0 adress of current profile entry time pwm activ detection pwm activ counter stall threshold stall threshold activ sampling and threshold activ sampling and threshold pwm activ counter pwm activ detection pwm activ detection stall signal stall signal load current rising during low speed or stall counter value is below threshold value.
L9942 7 appendix 33/37 figure 16. reference generation for pwm control (switch on) register 0 up/down step count by 1,2,4,8 a0 a1 a2 a3 mux a0 a1 a2 0 0 0 01 23 01 23 01 23 current-profile table stored in register2, ...6 a3=0 adr a[3..0] phase a profile 8 address calculation 11110 profile 7 profile 6 profile 5 profile 4 profile 3 01100 profile 2 00110 profile 1 00000 profile 0 5 5 5 5 5 5 5 5 5 a3=1 adr neg(a[3..0]) a3=0 adr neg(a[3..0]) phase b a3=1 adr a[3..0] register 1 9 5 dir 0 1 0 phasecounter stepmode sr0 sr1 0 0 slew rate dm2 dm1 dm0 mux mux 0 1 1 1 1 0 1 1 0 0 dac phase b dac phase a decay mode 5 bit dac phase a 5 bit dac phase b 0 0 0 dac scale dac full scale ref ref i max i limit b i limit a i di hs1 on ls2 on ls1 on hs2on 0 1 23456787654321012345678765432 1 0 1 2345678910111213141516171819202122232425262728293031 012345678765432101234567 8 7 654321 current driver a current driver b step signal adress of current profile entry phase a phase counter adress of current profile entry phase b 0 0 0 95 ma 100ma * 6/31 = 18.4ma 100ma * 30/31 = 91.9ma 200 ua 10110 11010 11101 10001 11111 a i qa1lim i 1000 1 1 counter value changes after an signal at step to next one depending on selected stepping mode described in figure 3 (e.g. during micro stepping to value 2) . pwm control with hs current monitoring overcurrent detection at ls switch qa1 qa2 + - - + hsa1 limit - 2ma + - 2ma - + - - + lsa2 - 2ma + - 2ma oc - b i qa2lim i 1000 qb1 qb2 + - - + lsb1 - 2ma + - 2ma oc - + - - + hsb2 limit - 2ma + - 2ma - hs current monitoring (load control) ls current monitoring (overcurrentl) hs current monitoring (load control) ls current monitoring (overcurrent)
7 appendix L9942 34/37 figure 17. reference generation for pwm contro (decay)l register 0 up/down step count by 1,2,4,8 a0 a1 a2 a3 mux a0 a1 a2 0 0 0 01 23 01 23 01 23 current-profile table stored in register2, ...6 a3=0 adr a[3..0] phase a profile 8 address calculation 11110 profile 7 profile 6 profile 5 profile 4 profile 3 01100 profile 2 00110 profile 1 00000 profile 0 5 5 5 5 5 5 5 5 5 a3=1 adr neg(a[3..0]) a3=0 adr neg(a[3..0]) phase b a3=1 adr a[3..0] register 1 9 5 dir 0 1 0 phasecounter stepmode sr0 sr1 0 0 slew rate dm2 dm1 dm0 mux mux 0 1 1 1 1 0 1 1 0 0 dac phase b dac phase a decay mode 5 bit dac phase a 5 bit dac phase b 0 0 0 dac scale dac full scale ref ref i max i limit b i limit a i di hs1 on hs2 on hs1 on ls2on 0 1 23456787654321012345678765432 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 012345678765432101234567 8 7 654321 current driver a current driver b step signal adress of current profile entry phase a phase counter adress of current profile entry phase b 0 0 0 95 ma 100ma * 6/31 = 18.4ma 95ma * 30/31 = 91.9ma 200 ua 10110 11010 11101 10001 11111 auto decay mixed decay slow decay fast and slow decay a i 1 1 counter value changes after an signal at step to next one depending on selected stepping mode described in figure 1.2 (e.g. during micro stepping to value 2) . slow decay fast decay qa1 qa2 + - - + - 2ma + - 2ma - + - - + - 2ma + - 2ma - b i qb1 i 1000 qb1 qb2 + - - + hsb1 oc - 2ma + - 2ma - + - - + - 2ma + - limit 2ma lsb2 - hs current monitoring (overcurrent) ls current monitoring (load control) hs current monitoring (overcurrent) hs current monitoring (overcurrent) hsa1 oc hsb1 oc
L9942 8 package information 35/37 8 package information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 18. powersso-24 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.15 2.47 0.085 0.097 a2 2.15 2.40 0.085 0.094 a1 0 0.075 0.003 b 0.33 0.51 0.013 0.02 c 0.23 0.32 0.009 0.012 d 10.10 10.50 0.398 0.413 e 7.4 7.6 0.291 0.299 e 0.8 0.031 e3 8.8 0.346 g 0.1 0.004 g1 0.06 0.002 h 10.1 10.5 0.398 0.413 k5? 5? h 0.4 0.016 l 0.55 0.85 0.021 0.033 n10?10? x 4.1 4.7 0.161 0.185 y 6.5 7.1 0.256 0.279 powersso-24 (exposed pad)
9 revision history L9942 36/37 9 revision history date revision changes 7-nov-2005 1 initial release.
L9942 37/37 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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