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sy88149ndl 1.25gbps burst-mode limiting amplifier with ultra-fast signal assert timing micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com february 2012 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 general description the sy88149ndl is a high-sensitivity, burst-mode capable limiting post amplifier designed for optical line terminal (olt) receiver applications. the sy88149ndl satisfies the strict timing restrictions of the gpon standards by providing ultra- fast loss-of-signal (los) or signal-detect (sd) output. auto reset and manual reset options are provided to control los/sd output timing. for increased flexibility, this devic e also includes an option to select between los or sd output. the device can be connected to burst-mode capable transimpedance amplifiers (tias) using ac or dc coupling. the sy88149ndl generates a high-gain los or sd lvttl output. a programmable los/sd level set pin (los/sd lvl ) sets the sensitivity of the input amplitude detection. when los/sd sel pin is left open or tied to vcc, jam is active high, sd is selected and asserts high if the input amplitude rises above the threshold sets by los/sd lvl and de-asserts low otherwise. when los/sd sel pin is set low or tied to gnd, jam is active low, los is selected and asserts low if the input amplitude rises above the threshold sets by los/sd lvl and de-asserts high otherwise. the los/sd output can be fed back to the jam input to maintain output stability under an invalid signal conditions. typically, 4?5 db sd hysteresis is provided to prevent chattering. the sy88149ndl also features a selectable proprietary noise discriminator that aids by filtering out input signals that do not qualify as a 1.25gbps gpon preamble signal in the initial startup phase. this feature minimizes false sd asserts that can be trigge red by random noise. the sy88149ndl operates from a single +3.3v power supply, over temperatures ranging from ?40 o c to +85 o c. with its wide bandwidth and high gain, signals up to 1.25gbps and as small as 5mvpp can be amplified to drive devices with lvpecl inputs. all support documentation can be found on micrel?s web site at: www.micrel.com . features ? <5ns sd assert (los deassert) time ? option to auto reset or manual reset los/sd output ? selectable los/sd output option ? high-sensitivity los/sd signal detect ? low-noise lvpecl data outputs ? squelching function to maintain output stability ? programmable los/sd level set (los/sd lvl ) ? 5mvpp input sensitivity ? 1.25gbps operation ? single 3.3v power supply ? available in a 16-pin (3mm 3mm) qfn ? package applications ? ge-pon/gpon olt ? gigabit ethernet ? fibre channel ? oc-3/12/24 sonet/sdh ? high-gain line driver and line receiver ? low-gain tia interface markets ? ftth pon ? datacom/telecom ? optical transceiver
micrel, inc. sy88149ndl february 2012 2 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 ordering information part number package type operating range package marking SY88149NDLMG lead-free qfn-16 industrial 149n with pb-free bar-line indicator SY88149NDLMG tr (1) lead-free qfn-16 industrial 149n with pb-free bar-line indicator notes: 1. tape and reel. pin configuration 16-pin qfn ? (qfn-16) truth table for sd/los select and noise discriminator function los/sdsel pin los/sd selection noise discriminator input to jam outputs 0 ? to vcc sd enab led high enabled 0 ? to vcc sd enabled low disabled 16k ? to vcc sd disabled high enabled 16k ? to vcc sd disabled low disabled 16k ? to gnd los disabled high disabled 16k ? to gnd los disabled low enabled 0 ? to gnd los enabled high disabled 0 ? to gnd los enabled low enabled
micrel, inc. sy88149ndl february 2012 3 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 pin description pin number pin name pin function 1, 4 din, /din differential data input s. if ac-coupled, terminate each pin to v ref with 50 ? . 2 vref reference voltage output. typically v cc ? 1.3v. 3, 11, 8 gnd device ground. exposed pad must be soldered (o r equivalent) to the same potential as the ground pins. 10 /auto reset lvttl input. this pin is internally connected to a 25k ? pull-up resistor and defaults to high. when this pin is low or tied to ground, the /a uto reset function is enabled and sd deasserts or los asserts within 120ns (typical) after the la st high-to-low transition of the burst input. when this pin is left floating or tied high, the auto reset function is disabled and the sd deassert or los assert must be forced by usi ng the manual reset function. 5, 16 vcc positive power supply. bypass with 0.1uf | | 0.01uf low esr capacitor s. 0.01uf capacitors should be as close as possible to vcc pins. 6 reset lvttl input. apply a high-level signal ( > 2v) to this pin to reset t he sd deassert time or los assert within 5ns. reset defaults to low if left floating. if the /auto reset function is not used, this reset function needs to be used to qui ckly deassert the sd or assert los. this pin is internally connected to a 25k ? pull-down resistor and defaults to low. 7 sd/los lvttl output. signal detect (sd) asserts high when the data input amplitude rises above the threshold sets by sd lvl . conversely, loss-of-signal (los) deasserts low when the data input amplitude rises above the threshold set by los/sd lvl . 12, 9 dout, /dout lvpecl outputs. when jam disables the devi ce, output dout is forced to logic low and output /dout is forced to logic high. 13 los/sd sel allows the user to select between whether los or sd is outputted on the los/sd pin. also controls the polarity of the jam input. when sd is selected, jam is active high and los/sd (pin 7) operates as signal detect. conversely , when los is selected, jam is active low and los/sd operates as loss-of-signal. this pin is internally connected to a 25k ? pull-up resistor and defaults to high (sd output selected). 14 los/sdlvl voltage input. sets the los/sd level. a resistor from this pin to v cc sets the threshold for the data input amplitude at which los/sd will be asserted. 15 jam lvttl input. this jam input acts as a squelch function and switches its polarity depending on los/sd sel status. when los is selected, this pi n is active low. when sd is selected, this pin is active high. to create a squelch functi on, connect jam to los/sd. when jam disables the device, output q is forced to logic low and out put /q is forced to logic high. note that this input is internally connected to a 25k ? pull-up resistor.
micrel, inc. sy88149ndl february 2012 4 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc ) ....................................... 0v to +4.0v input voltage (din , /din) ....................................... 0 to v cc output current (i out ) continuous ........................................................ 50ma surge .............................................................. 100ma en voltage ............................................................. 0 to v cc v ref current .......................................... -800 a to +500 a sd lvl voltage ....................................................v ref to v cc lead temperature (sol dering, 20s) .......................... 260c storage temperature (t s ) ....................... ?65c to +150c operating ratings (2) supply voltage (v cc )................................. +3.0v to +3.6v ambient temperature (t a ) ....................... ?40c to +85c junction temperature (t j ) ..................... ?40c to +125c junction thermal resistance (3) qfn ? ( ja ) still-air ........................................... 60c/w qfn ? ( jb ) junction-to-board ......................... 38c/w dc electrical characteristics v cc = 3.0 to 3.6v; t a = ?40c to +85c, typical values at v cc = 3.3v, t a = 25c. symbol parameter condition min. typ. max. units i cc power supply current no output load 77 105 ma los/sd lvl los/sd lvl voltage v ref v cc v v oh lvpecl output high voltage 50 ? to v cc ? 2v v cc ? 1.085 v cc ? 0.955 v cc ? 0.880 v v ol lvpecl output low voltage 50 ? to v cc ? 2v v cc ? 1.830 v cc ? 1.705 v cc ? 1.555 v i offset input offset voltage 1 mv v ihcmr(diff) common-mode range (differential) note 4 gnd + 1.4 vcc v ihcmr(se) common-mode range (single ended ) note 4 gnd + 1.2 vcc v v ref reference voltage v cc ? 1.48 v cc ? 1.32 v cc ? 1.16 v i din input sink current (din & /din) no input load 1.5 7 14 ua lvttl dc electrical characteristics v cc = 3.0 to 3.6v; t a = ?40c to +85c, typical values at v cc = 3.3v, t a = 25c. symbol parameter condition min. typ. max. units v ih lvttl input high voltage 2.0 v v il lvttl input low voltage 0.8 v i ih_jam jam input high current v in = v cc v in = 2.7v 20 20 a i il_jam jam input low current v in = 0.5v ? 0.3 ma i ih_ar /autoreset input high current v in = v cc v in = 2.7v 100 20 a i il_ar /autoreset input low current v in = 0.5v ? 0.3 ma i ih_reset reset input high current v in = v cc v in = 2.7v 300 250 a i il_reset reset input low current v in = 0.5v 0 ma v oh sd/los output high level i oh = ? 100ua 2.1 2.7 v v ol sd/los output low level i ol = 100ua 0.35 0.5 v
micrel, inc. sy88149ndl february 2012 5 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics v cc = 3.0v to 3.6v; r load = 50 ? to v cc ? 2v; t a = ?40c to +85c. symbol parameter condition min. typ. max. units t r , t f output rise/fall time (20% to 80%) note 5 260 ps t jam jam enable/disable time 2 ns t autoreset sd deassert or los a ssert with auto reset enabled. 100 120 150 ns t reset reset disable time note 6 5 ns t on sd assert time/los deassert time 5 ns t jitter deterministic random note 7 note 8 15 5 ps pp ps rms v id differential input voltage swing figure 1 5 1800 mv pp v od differential output voltage swing v id 18mv pp 1500 mv pp sd al /los dl low sd assert/los de- assert level r los/sdlvl = 10k ? , notes (9, 10) 4 mv pp sd dl/ /los al low sd deassert /los assert level r los/sdlvl = 10k ? , notes (10, 12) 3 mv pp hys l low sd/los hysteresis r los/sdlvl = 10k ? , notes (11, 12) 5 db sd am /los dm medium sd assert/los deassert level r los/sdlvl = 5k ? , notes (10, 12) 9.5 12.5 16 mv pp sd dm /los am medium sd deassert /los assert level r los/sdlvl = 5k ? , notes (10,12) 5 7 8.5 mv pp hys m medium sd/los hysteresis r los/sdlvl = 5k ? , notes (11, 12) 3.0 4.5 6.5 db sd ah /los dh high sd assert/los de- assert level r los/sdlvl = 50 ? , notes (10, 12) 27 35 45 mv pp sd dh /los ah high sd deassert/ los assert level r los/sdlvl = 50 ? , notes (10, 12) 15 21 28 mv pp hys h high sd/los hysteresis r los/sdlvl = 50 ? , notes (11, 12) 2.0 3 6 db b -3db 3db bandwidth 750 mhz a v(diff) differential voltage gain 48 db s 21 single-ended small-signal gain 42 db notes: 1. permanent device damage may occur if absolute maximum ra tings are exceeded. this is a stress rating only and functional op eration is not implied at conditions other than those detailed in the operational sections of this data shee t. exposure to absolute maximum rating con ditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. thermal performance assumes the use of a 4-layer pcb. exposed pad must be soldered to the device?s most negative potential on the pcb. 4. vihcmr is defined as common mode range of the vih level on din and /din. it is the most positive level of the differential input signal when driven differentially or is the reference leve l on din\ when being driven single ended. 5. amplifier in limiting mode. input is a 200mhz square wave. 6. the time between applying reset and outputs being disabled. 7. deterministic jitter measured using 1.25gbps k28.7 pattern, v id = 10mv pp . 8. random jitter measured using 1.25gbps k28.7 pattern, v id = 10mv pp . 9. sd is the opposite polarity of los. therefore, an sd assert parameter is equivalent to a los deassert parameter and vice ver sa. 10. see ?typical operating characteristics? fo r a graph showing how to choose a particular r los/sdlvl for a particular assert and its associated deassert amplitude. 11. this specification defines electrical hysteresis as 20log(sd assert/sd dea ssert). the ratio between optical hysteresis and electrical hysteresis is found to vary between 1.5 and 2 depending upon the level of received optical power and rosa characteristics. based upon that ra tio, the optical hysteresis corresponding to the el ectrical hysteresis range 3db ? 6db, shown in the ac char acteristics table, will be 1.5db-4db optical hysteresis. 12. all sd assert (los de-assert) level, sd de-assert (los assert) level and hysteresis s pecifications listed above are spec ified using a 1010 pon preamble data pattern at the specified data rate of 1.288 gbps.
micrel, inc. sy88149ndl february 2012 6 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics v cc = 3.3v, t a = 25c, r l = 50 ? to v cc ? 2v, unless otherwise stated. los assert/de-assert levels 1 10 100 0.01 0.1 1 10 los/sdlvl resistor (kohm) signal amplitude (mv) los/sd hysteresis 2 3 4 5 6 7 8 0.01 0.1 1 10 los/sdlvl resistor (kohm) hysteresis (db)
micrel, inc. sy88149ndl february 2012 7 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 sy88149ndl input preamble burst with signal detect (sd) response, with noise discriminator disengaged sy88149ndl input preamble burst with signal detect (sd) response, with noise discriminator engaged functional block diagram
micrel, inc. sy88149ndl february 2012 8 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 detailed description the sy88149ndl is a high-sensitivity limiting post amplifier which operates on a +3.3v power supply over the industrial temperature range . signals with data rates up to 1.25gbps and as small as 5mvpp can be amplified. depending on the los/sd sel option, the sy88149ndl can generate an sd or los output, and allow feedback to the jam input for output stability. los/sd lvl sets the sensitivity of the input amplitude detection. to satisfy the stringent timing requirements of the gpon specifications, the signal detect circuit offers 5ns sd assert (los deassert) time and the option to deassert sd (assert los) using the /auto reset or manual reset function. when /auto reset is enabled, sd deasserts/los asserts automatically within 120ns after the last high-to- low transition of the input burst. when the /autoreset function is disabled, the sd deassert/los assert time can be reset by using the provided reset pin. input buffer figure 2 shows a simplified schematic of the input stage. the high sensitivity of the input amplifier allows signals as small as 5mvpp to be detected and amplified. the input buffer can allow input signals as large as 1800mv pp . input signals are linearly amplifi ed with a typically 48db differential voltage gain un til the outputs reach 1500mv pp (typical). applications requiring the sy88149ndl to operate with high-gain shoul d have the upstream tia placed as close as possible to the sy88149ndl?s input pins. this ensures the best performance of the device. output buffer the sy88149ndl?s lvpecl output buffer is designed to drive 50 ? lines. the output buffer requires appropriate termination for proper operation. an external 50 ? resistor to v cc ? 2v for each output pin provides this. figure 3 shows a simplified schematic of the output stage loss of signal/signal detect the sy88149ndl generates a chatter-free signal-detect (sd) or loss of signal (los) lvttl output, as shown in figure 4. a highly-sensitive signa l detect circuit is used to determine that the input amplitude is too small to be considered a valid input. los asserts high if the input amplitude falls below the threshold sets by los/sdlvl and deasserts low otherwise. sd asserts high if the input amplitude rises above threshold set by los/sdlvl and deasserts low otherwise. los/sd can be fed back to the jam input to maintain output stability under the absence of an invalid signal condition typically, a 3db to 4 db hysteresis is provided to mi nimize or prevent chattering. los/sd level set a programmable los/sd level pin (los/sd lvl ) sets the threshold of the input amplitude detection. connecting an external resistor between v cc and los/sd lvl sets the voltage at los/sd lvl . this voltage ranges from v cc to v ref . the external resistor creates a voltage divider between v cc and v ref , as shown in figure 5. set the los/sd lvl voltage closer to v ref or more sensitive los/sd detection or closer to v cc for higher inputs. note that the sy88149ndl is designed for use in the burst mode pon application, where every burst is preceded with several bytes of a 1010 pon preamble pattern. therefore, the sd assert (los de-assert) is designed to trigger on the first few bits of this preamble pattern and therefore the sd/los thresholds outlined in the ac electrical characteristics are specified using this preamble pattern. once the sd is asserted (los de- asserted), the sd is de-ass erted (los asserted) only by the application of a manual reset or an auto reset if the auto reset is activated, the auto reset asserts a reset approximately 120 ns after the last negative going transition of the data as explained earlier. noise discriminator the noise discriminator feature is intended for the high- gain burst-mode tias where noise can trigger a false los deassert or sd assert while no input data is present. the noise discriminator will filter input data through a series of speciali zed circuitry that will only trigger los/sd on the rising edge of a valid pon 1.244 gbps preamble bit stream (10101). the sy88149ndl noise discriminator is designed to accept a 1.244 gbps +/-300 mbps preamble burst. any other bit pattern will be rejected. if this part is used at any other data rate, the noise discriminator should be disengaged. the noise discriminator, implemented in the edge detector circuit, can be selected or bypassed by selecting the proper resistor value using the settings at los/sdsel pin. refer to the ?truth table for sd/los select and noise discriminator function? found on page 2 for more detailed information.
micrel, inc. sy88149ndl february 2012 9 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 timing diagrams a) no manual reset & /autoreset tied high (noise discriminator off) b) no manual reset & /autoreset tied high (noise discriminator on) c) no manual reset & /autoreset tied low (noise discriminator off) d) no manual reset & /autoreset tied low (noise discriminator on) e) manual reset & /autor eset tied high or low (noise discriminator off) f) manual reset & /autoreset tied high or low (noise discriminator on)
micrel, inc. sy88149ndl february 2012 10 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 g) manual reset pulse & /autoreset tied low (noise discriminator off) h) manual reset pulse & /autoreset tied low (noise discriminator on) figure 1. vis (single ended) and vid (differential) definition
micrel, inc. sy88149ndl february 2012 11 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 figure 2. simplified input structure fi gure 3. simplified output structure figure 4. simplified los/sd output structure figure 5. simplified los/sd lvl setting circuit
micrel, inc. sy88149ndl february 2012 12 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 package information 16-pin qfn ? (qfn-16) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com micrel makes no representations or warranties with respect to t he accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for it s use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether expre ss, implied, arising by estoppel or other wise, to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, mi crel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including l iability or warranties relating to fitness for a particular purpose, merchantability, or infringement of an y patent, copyright or other intellectual p roperty right. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2012 micrel, incorporated.
micrel, inc. sy88149ndl february 2012 13 m9999-020712-a hbwhelp@micrel.com or (408) 955-1690 hbw datasheet revision history part number: sy88149ndl initial release date: rev. date revisions reason engineer a 4/29/10 made from sy88149hl ds new version of part. contains fixed jam tpd & reset hysteresis d. cheng 5/11/10 changed package marking to ?149a? from ?149h? mistake left over from 149hl d. cheng 8/31/10 revised ac-table specs ? los assert/deassert ? hysteresis ? removed reset hyst. ? changed 3db value design tweak to address chattering issue d. cheng 01/7/11 added noise discriminator description new feature d. cheng 01/8/11 multiple error fixes after peer review d. cheng 2/11/11 added dieter?s comments only partially completed. waiting for bench char d. cheng 6/9/2011 signoff signoff purposes d. cheng 7/1/2011 implement sign-off changes recomme nded changes from reviewers d. cheng 7/28/11 change in epn from sy88149hal to sy88149ndl misc. changes in organization, figures and epn change d. cheng 8/11/11 add los deassert time waveforms and other art finalize data sheet. g.brown 9/01/11 add comments in noise discriminator description add comments to nd description and do minor cleanup gbrown 9/31/11 update icc update icc typical to 77 ma/105 ma max gbrown 01/27/12 update to make compatible with sy88349ndl upgrade waveforms and add notes and updates to dc/ac tables gbrown

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