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_______________general description the max517/max518/max519 are 8-bit voltage output digital-to-analog converters (dacs) with a simple 2-wire serial interface that allows communication between multiple devices. they operate from a single 5v supply and their internal precision buffers allow the dac out- puts to swing rail-to-rail. the max517 is a single dac and the max518/max519 are dual dacs. the max518 uses the supply voltage as the reference for both dacs. the max517 has a ref- erence input for its single dac and each of the max519? two dacs has its own reference input. the max517/max518/max519 feature a serial interface and internal software protocol, allowing communication at data rates up to 400kbps. the interface, combined with the double-buffered input configuration, allows the dac registers of the dual devices to be updated indi- vidually or simultaneously. in addition, the devices can be put into a low-power shutdown mode that reduces supply current to 4?. power-on reset ensures the dac outputs are at 0v when power is initially applied. the max517/max518 are available in space-saving 8- pin dip and so packages. the max519 comes in 16- pin dip and so packages. ________________________applications minimum component analog systems digital offset/gain adjustment industrial process control automatic test equipment programmable attenuators ____________________________features single +5v supply simple 2-wire serial interface i 2 c compatible output buffer amplifiers swing rail-to-rail space-saving 8-pin dip/so packages (max517/max518) reference input range includes both supply rails (max517/max519) power-on reset clears all latches 4a power-down mode ______________ordering information max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs ________________________________________________________________ maxim integrated products 1 1 2 3 4 8 7 6 5 out1 (ref0) v dd ad0 ad1 sda scl gnd out0 max517 max518 dip/so top view _________________pin configurations input latch 0 output latch 0 start/stop detector dac0 input latch 1 8-bit shift register out0 ref ref out1 max518 8 1 decode address comparator dac1 output latch 1 v dd 7 scl sda ad0 ad1 3 4 65 gnd 2 ________________functional diagram 19-0393; rev 1; 9/02 part max517 acpa max517bcpa max517acsa 0? to +70? 0? to +70? 0? to +70? temp range pin-package 8 plastic dip 8 plastic dip 8 so tue (lsb) 1 1.5 1 max517bcsa max517bc/d 0? to +70? 0? to +70? 8 so dice* 1.5 1.5 ordering information continued at end of data sheet. *dice are specified at t a = +25?, dc parameters only. **contact factory for availability and processing to mil-std-883. ( ) are for max517 pin configurations continued at end of data sheet. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 5v ?0%, v ref_ = 4v (max517, max519), r l = 10k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v out_ ..........................................................-0.3v to (v dd + 0.3v) ref_ (max517, max519)...........................-0.3v to (v dd + 0.3v) ad_.............................................................-0.3v to (v dd + 0.3v) scl, sda to gnd.....................................................-0.3v to +6v maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 8-pin plastic dip (derate 9.09mw/? above +70?) ...727mw 8-pin so (derate 5.88mw/? above +70?)................471mw 8-pin cerdip (derate 8.00mw/? above +70?)........640mw 16-pin plastic dip (derate 10.53mw/? above +70?)..842mw 16-pin narrow so (derate 8.70mw/? above +70?) ...696mw 16-pin cerdip (derate 10.00mw/? above +70?) ......800mw operating temperature ranges max51_c_ _ .......................................................0? to +70? max51_e_ _.....................................................-40? to +85? max51_mjb ..................................................-55? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? ? max51 _bm ? max51 _e max51 _c full-scale-error temperature coefficient full-scale-error supply rejection ? mv ?0 ?/? max517, max519 code = ff hex v dd = +5v ?0% code = ff hex ?0 max51 _e mv max51 _c ? max51 _bm ? max51 _e max51 _c 20 max51 _bm 20 max51 _e max51 _c max51 _a parameter symbol min typ max units resolution 8 bits tue ? differential nonlinearity (note 1) dnl ? lsb zero-code error zce 18 mv zero-code-error supply rejection ? zero-code-error temperature coefficient ?0 ?/? full-scale error ?8 conditions guaranteed monotonic code = 00 hex code = 00 hex code = 00 hex code = ff hex, max518 unloaded mv max51 _b ?.5 total unadjusted error (note 1) lsb ?0 max51 _bm static accuracy
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 5v ?0%, v ref_ = 4v (max517, max519), r l = 10k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are t a = +25?.) 0.6 i sink = 6ma i sink = 3ma 0.3v dd input high voltage v ih 0.7v dd v input leakage current i in ?0 ? output low voltage v ol 0.4 v three-state leakage current i l ?0 ? three-state output capacitance c out 10 0v v in v dd v in = 0v to v dd (note 6) parameter symbol min typ max units output leakage current ?0 ? conditions out_ = 0v to v dd , power-down mode pf lsb 1.5 v il input hysteresis v hyst 0.05v dd v input capacitance c in 10 pf (note 6) input high voltage v ih 2.4 v input low voltage v il 0.8 v input leakage current i in ?0 ? v in = 0v to v dd voltage output slew rate 2.0 positive and negative v/? max51 _c output settling time ? digital feedthrough 5 code = 00 hex, all digital inputs from 0v to v dd nv-s 1.4 max51 _e 1.0 max51 _m input voltage range 0v dd v input resistance r in 16 24 k ? code = 55 hex (note 2) input current ?0 ? power-down mode input capacitance 30 pf code = ff hex (note 3) channel-to-channel isolation (max519) -60 (note 4) max51 _m, ref_ = v dd (max517, max519), code = ff hex, 0? to 500? 2.0 ac feedthrough -70 db (note 5) max51 _c/e, ref_ = v dd (max517, max519), code = ff hex, 0? to 500? full-scale output voltage 0v dd v output load regulation 0.25 out_ = 4v, 0ma to 2.5ma 6 to 1/2 lsb, 10k ? and 100pf load (note 8) dac outputs digital inputs scl, sda digital inputs ad0, ad1, ad2, ad3 digital output sda (note 7) dynamic performance reference inputs (max517, max519) db input low voltage v
ma max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs 4 _______________________________________________________________________________________ note 1: for the max518 (full-scale = v dd ) the last three codes are excluded from the tue and dnl specifications, due to the limited output swing when loaded with 10k ? to gnd. note 2: input resistance is code dependent. the lowest input resistance occurs at code = 55 hex. note 3: input capacitance is code dependent. the highest input capacitance occurs at code ff hex. note 4: v ref_ = 4v p-p , 10khz. channel-to-channel isolation is measured by setting the code of one dac to ff hex and setting the code of all other dacs to 00 hex. note 5: v ref_ = 4vp-p, 10khz, dac code = 00 hex. note 6: guaranteed by design. note 7: i 2 c compatible mode. r pullup = 1.7k ? . note 8: output settling time is measured by taking the code from 00 hex to ff hex, and from ff hex to 00 hex. note 9: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) in order to bridge the undefined region of scl? falling edge. note 10: cb = total capacitance of one bus line in pf. t r and t f measured between 0.3v dd and 0.7v dd . note 11: input filters on the sda and scl inputs suppress noise spikes less than 50ns. hold time, (repeated) start condition t hd, sta 0.6 ? low period of the scl clock t low 1.3 ? high period of the scl clock t high 0.6 parameter symbol min typ max units serial clock frequency f scl 0400 khz bus free time between a stop and a start condition t buf 1.3 ? conditions ? setup time for a repeated start condition t su, sta 0.6 ? data hold time t hd, dat 0 0.9 ? data setup time t su, dat 100 (note 9) ns fall time of sda transmitting t f 20 + 0.1cb 250 ns setup time for stop condition t su, sto 0.6 ? capacitive load for each bus line cb 400 i sink 6ma (notes 7, 10) pf rise time of both sda and scl signals, receiving t r 20 + 0.1cb 300 ns fall time of both sda and scl signals, receiving t f 20 + 0.1cb 300 (note 10) (note 10) ns pulse width of spike suppressed t sp 050 (notes 6, 11) ns timing characteristics (v dd = 5v ?0%, t a = t min to t max , unless otherwise noted. typical values are t a = +25?.) electrical characteristics (continued) (v dd = 5v ?0%, v ref_ = 4v (max517, max519), r l = 10k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are t a = +25?.) parameter symbol min typ max units conditions digital-analog glitch impulse 12 code 128 to 127 nv-s signal to noise + distortion ratio (max517, max519) sinad 87 v ref_ = 4vp-p at 1khz, v dd = 5v, code = ff hex db multiplying bandwidth (max517, max519) 1 mhz wideband amplifier noise 60 ? rms supply voltage v dd 4.5 5.5 v 1.5 3.0 max517e/m max517c 2.5 5 1.5 3.5 v ref_ = 4vp-p, 3db bandwidth supply current normal mode, output(s) unloaded, all digital inputs at 0v or v dd 2.5 6 max518c, max519c max518e/m, max519e/m i dd power-down mode 420 ? power requirements
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs _______________________________________________________________________________________ 5 10 0 0 0.5 1.5 2.5 3.0 3.5 4.0 full-scale error vs. source current (v ref = v dd ) 2 8 max517-01 output source current (ma) full-scale error (lsb) 1.0 2.0 6 4 v dd = v ref = 5v dac code = ff hex load to agnd 10 0 0 0.5 2.0 zero-code error vs. sink current 2 8 max517-02 output sink current (ma) zero-code error (lsb) 1.0 1.5 6 4 v dd = v ref = 5v dac code = 00 hex load to v dd 3.0 0 -55 -15 5 -35 65 125 max517/max519 supply current vs. temperature 0.5 2.0 2.5 max517-03 temperature (?) supply current (ma) 45 25 85 105 1.5 1.0 v dd = 5.5v ref_ inputs = 0.6v all digital inputs to v dd max519, dac code = ff hex max517, max519 dac code = 00 hex max517, dac code = ff hex 3.0 3.5 0 -55 -35 -15 565 45 125 105 max518 supply current vs. temperature 0.5 2.0 2.5 max517-04 temperature ( c) supply current (ma) 25 85 1.5 1.0 v dd = 5.5v ad0, ad1 = v dd dac code = ff hex dac code = 1b hex dac code = 00 hex 6 0 -55 -15 -35 45 65 125 shutdown supply current vs. temperature 1 4 5 max517-07 temperature ( c) shutdown supply current ( a) 25 5 85 105 3 2 v dd = 5.5v all digital inputs to v dd max518 supply current vs. dac code max517-05 dac code (decimal) supply current (ma) v dd = 5.5v both dacs set 0 0 0.5 1.0 1.5 2.0 2.5 3.0 32 64 96 128 160 192 224 256 2.5 0 01 0.5 3 2.5 5 4.5 max517/max519 supply current vs. reference voltage 0.5 1.5 2.0 max517-08 reference voltage (v) supply current (ma) 2 1.5 4 3.5 1.0 v dd = 5v dac code(s) ff hex max519 max517 0 1k 100k 10k 1m 10m max517/max519 reference voltage input frequency response -16 max517-09 frequency (hz) relative output (db) -12 -8 -4 v dd = 5v v ref = sine wave centered at 2.5v 4v p-p sine 2v p-p sine 1v p-p sine 0.5v p-p sine __________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.) out0 loaded with 10k ? ii 100pf ref0 = 4v (max517/max519) dac code = 00 hex to ff hex 1 s/div positive full-scale step response out0 1v/div
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs 6 _______________________________________________________________________________________ a = ref0, 1v/div (4v p-p ) b = out0, 50 v/div, unloaded filter passband = 10khz to 1mhz dac code = 00 hex max517/max519 reference feedthrough at 100khz b a ______________________________t ypical operating characteristics (continued) (t a = +25?, unless otherwise noted.) a = scl, 400khz, 5v/div b = out0, 5mv/div dac code = 7f hex ref0 = 5v (max517/max519) clock feedthrough b a a = ref0, 1v/div (4v p-p ) b = out0, 50 v/div, unloaded filter passband = 100hz to 10khz dac code = 00 hex max517/max519 reference feedthrough at 1khz b a a = ref0, 1v/div (4v p-p ) b = out0, 50 v/div, unloaded filter passband = 1khz to 100khz dac code = 00 hex max517/max519 reference feedthrough at 10khz b a out0 loaded with 10k ? ii 100pf ref0 = 4v (max517/max519) dac code = ff hex to 00 hex 1 s/div negative full-scale step response out0 1v/div ref0 = 5v (max517/max519) dac code = 80 hex to 7f hex 500ns/div worst-case 1lsb step change out0 20mv/div ac coupled
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs _______________________________________________________________________________________ 7 figure 1. max517/max519 functional diagram _______________detailed description serial interface the max517/max518/max519 use a simple 2-wire serial interface requiring only two i/o lines (2-wire bus) of a standard microprocessor (?) port. figure 2 shows the timing diagram for signals on the 2-wire bus. figure 3 shows a typical application. the 2-wire bus can have several devices (in addition to the max517/ max518/max519) attached. the two bus lines (sda and scl) must be high when the bus is not in use. when in use, the port bits are toggled to generate the appropriate signals for sda and scl. external pull-up resistors are not required on these lines. the max517/max518/ max519 can be used in applications where pull-up resis- tors are required (such as in i 2 c systems) to maintain compatibility with existing circuitry. the max517/max518/max519 are receive-only devices and must be controlled by a bus master device. they operate at scl rates up to 400khz. a master device sends information to the devices by transmitting their address over the bus and then transmitting the desired information. each transmission consists of a start condition, the max517/max518/max519? programm- able slave-address, one or more command-byte/out- put-byte pairs (or a command byte alone, if it is the last byte in the transmission), and finally, a stop condition (figure 4). ______________________________________________________________pin description pin max517 max518 max519 name function 1 1 1 out0 dac0 voltage output 2 2 4 gnd ground 5 ad3 address input 3; sets ic? slave address 3 3 6 scl serial clock input 4 4 8 sda serial data input 9 ad2 address input 2; sets ic? slave address 5 5 10 ad1 address input 1; sets ic? slave address 6 6 11 ad0 address input 0; sets ic? slave address 7 7 12 vdd power supply, +5v; used as reference for max518 13 ref1 reference voltage input for dac1 8 15 ref0 reference voltage input for dac0 8 16 out1 dac1 voltage output 2, 3, 7, 14 n.c. no connect?ot internally connected. input latch 0 output latch 0 start/stop detector dac0 input latch 1 8-bit shift register out0 ref0 (ref1) (out1) max517/max519 decode address comparator dac1 output latch 1 v dd scl sda ad0 (ad2) ad1 (ad3) gnd max519 only ( ) are for max519
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs 8 _______________________________________________________________________________________ the address byte and pairs of command and output bytes are transmitted between the start and stop con- ditions. the sda state is allowed to change only while scl is low, with the exception of start and stop condi- tions. sda? state is sampled, and therefore must remain stable while scl is high. data is transmitted in 8-bit bytes. nine clock cycles are required to transfer the data bits to the max517/max518/max519. set sda low dur- ing the 9th clock cycle as the max517/max518/max519 pull sda low during this time. r c (see figure 3) limits the current that flows during this time if sda stays high for short periods of time. the start and stop conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a transmis- sion with a start condition by transitioning sda from high to low while scl is high (figure 5). when the mas- ter has finished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. the slave address the max517/max518/max519 each have a 7-bit long slave address (figure 6). the first three bits (msbs) of the slave address have been factory programmed and are always 010. in addition, the max517 and max518 have the next two bits factory programmed to 1s. the logic state of the address inputs (ad0 and ad1 on the max517/max518; ad0, ad1, ad2, and ad3 on the max519) determine the lsb bits of the 7-bit slave address. these input pins may be connected to vdd or dgnd, or they may be actively driven by ttl or cmos logic levels. the max517/max518 have four possible slave addresses and therefore a maximum of four of max518 sda scl c sda scl +5v ad1 ad0 dual dac max519 ad0 sda ref1 ref0 r c 1k ? scl +4v +1v ad2 ad1 dual dac sda scl ad1 ad0 single dac max517 ad3 out0 offset adjustment out1 gain adjustment out0 brightness adjustment out1 contrast adjustment ref0 +2.5v out0 threshold adjustment figure 3. max517/max518/max519 application circuit scl sda t low t high t f t r t hd , sta t hd , dat t hd , sta t su , dat t su , sta t buf t su , sto start condition stop condition repeated start condition start condition figure 2. two-wire serial interface timing diagram
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs _______________________________________________________________________________________ 9 these devices may share the bus. the max519 has 16 possible slave addresses. the eighth bit (lsb) in the slave address byte should be low when writing to the max517/max518/max519. the max517/max518/max519 monitor the bus continu- ously, waiting for a start condition followed by their slave address. when a device recognizes its slave address, it is ready to accept data. the command byte and output byte a command byte follows the slave address. figure 7 shows the format for the command byte. a command byte is usually followed by an output byte unless it is the last byte in the transmission. if it is the last byte, all bits except pd (power-down) and rst (reset) are ignored. if an output byte follows the command byte, a0 of the command byte indicates the digital address of the dac whose input data latch receives the digital output data. set this bit to 0 when writing to the max517. the data is transferred to the dac? output latch during the stop condition following the transmis- sion. this allows both dacs of the max518/max519 to be updated simultaneously (figure 8). setting the pd bit high powers down the max517/ max518/max519 following a stop condition (figure 9a). if a command byte with pd set high is followed by an output byte, the addressed dac? input latch will be updated and the data will be transferred to the dac? output latch following the stop condition (figure 9b). scl sda 0 0 1 or ad3 1 or ad2 10 ad1 ad0 lsb ack slave address figure 6. address byte slave address bits ad0, ad1, ad2, and ad3 correspond to the logic state of the address input pins. lsb msb sda scl r2 r1 r0 rst pd x x a0/0 ack figure 7. command byte r2, r1, r0: reserved bits. set to 0. rst: reset bit, set to 1 to reset all dac registers. pd: power-down bit. set to 1 to place the device in the 4? shutdown mode. set to 0 to return to the normal operational state. a0: address bit. determines which dac's input latch receives the 8 bits of data in the next byte. set to 0 for max517. ack: acknowledge bit. the max517/max518/max519 pulls sda low during the 9th clock pulse. x: don? care. start condition stop condition output byte command byte slave address byte scl sda msb msb msb lsb lsb lsb ack ack ack figure 4. a complete serial transmission scl sda start condition stop condition figure 5. all communications begin with a start condition and end with a stop condition, both generated by a bus master.
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs 10 ______________________________________________________________________________________ ( ) sda 0 start condition address byte ack 10 1 or ad3 1 or ad2ad1 ad0 0 0 00 0000000 0 1 11 11 11 1 stop condition command byte (addressing dac0) ack output byte (full scale) ack dac output changes here: dac0 goes to full scale. dac0 input latch set to full scale ( ) figure 8a. setting one dac output (max517/max518/max519) ( ) sda sda 0 start condition address byte ack ack 10 1 or ad3 1 or ad2 ad1 ad0 0 0 00 0000000 1 1 1111110 0 00 0000 00 1 1 11 11 11 1 stop condition output byte (full scale) command byte (addressing dac0) ack output byte (full scale) ack command byte (addressing dac1) ack dac outputs change here: dac0 and dac1 go to full scale. dac0 input latch set to full scale ( ) ( ) dac1 input latch set to full scale figure 8b. setting both dac outputs (max518/max519) sda 0 start condition address byte ack 10 1 or ad3 1 or ad2 ad1 ad0 0 0 0 00001 (pd) (pd) stop condition command byte ack device enters power-down state ( ) sda 0 start condition address byte ack 10 1 or ad3 1 or ad2 ad1ad0 0 0 0 0 00001 0 1 111 1 11 1 stop condition command byte (addressing dac0) ack output byte (full scale) ack (a) (b) device enters power-down state. dac0 output latch set to full scale. note: x = don't care dac0 input latch set to full scale. x x x x x ( ) ( ) figure 9. entering the power-down state
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs ______________________________________________________________________________________ 11 furthermore if the transmission? last command byte has pd high, the output latches are updated, but volt- age outputs will not reflect the newly entered data because the dac enters power-down mode when the stop condition is detected. when in power-down, the dac outputs float. in this mode, the supply current is a maximum of 20?. a command byte with the pd bit low returns the max517/max518/max519 to normal opera- tion following a stop condition, with the voltage out- puts reflecting the output-latch contents (figures 10a and 10b). because each subsequent command byte overwrites the previous pd bit, only the last command byte of a transmission affects the power-down state. setting the rst bit high clears the dac input latches. the dac outputs remain unchanged until a stop con- dition is detected (figure 11a). if a reset is issued, the following output byte is ignored. subsequent pairs of command/output bytes overwrite the input latches (figure 11b). all changes made during a transmission affect the max517/max518/max519? outputs only when the transmission ends and a stop has been recognized. the r0, r1, and r2 bits are reserved and must be set to zero. i 2 c compatibility the max517/max518/max519 are fully compatible with existing i 2 c systems. scl and sda are high- impedance inputs; sda has an open drain that pulls the data line low during the 9th clock pulse. figure 12 shows a typical i 2 c application. ( ) ( ) ( ) sda 0 start condition address byte ack 10 1 or ad3 1 or ad2 ad1ad000 00010 0 (rst) (rst) stop condition command byte ack all outputs set to 0. ( ) all input latches set to 0. all input latches set to 0. sda 0 start condition address byte ack 10 1 or ad3 1 or ad2 ad1ad00000010 0 0 stop condition command byte ack "dummy" output byte ack (a) (b) dac outputs set to 0 unless changed by additional command byte/output byte pairs. note: x = don't care additional command byte/ output byte pairs x x x x x x x x x x x x x x figure 11. resetting dac outputs ( ) sda 0 start condition address byte ack 10 1 or ad3 1 or ad2 ad1 ad0 0 0 0 00000 (pd) (pd) stop condition command byte ack device returns to normal operation ( ) dac0 input latch set to 0. sda 0 start condition address byte ack 10 1 or ad3 1 or ad2 ad1 ad0 0 0 0 0000 0 0 0 0 0 00 00 00 stop condition command byte (addressing dac0) ack output byte (set to 0) ack (a) (b) device returns to normal operation. dac0 set to 0. note: x = don't care x x x x x ( ) figure 10. returning to normal operation from power-down
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs 12 ______________________________________________________________________________________ additional start conditions it is possible to interrupt a transmission to a device with a new start (repeated start) condition (perhaps addressing another device), which leaves the input latches with data that has not been transferred to the output latches (figure 13). only the currently addressed device will recognize a stop condition and transfer data to its output latches. if the device is left with data in its input latches, the data can be transferred to the out- put latches the next time the device is addressed, as long as it receives at least one command byte and a stop condition. early stop conditions the addressed device recognizes a stop condition at any point in a transmission. if the stop occurs during a command byte, all previous uninterrupted command and output byte pairs are accepted, the interrupted command byte is ignored, and the transmission ends (figure 14a). if the stop occurs during an output byte, all previous uninterrupted command and output byte pairs are accepted, the final command byte s pd and rst bits are accepted, the interrupted output byte is ignored, and the transmission ends (figure 14b). analog section dac operation the max518 and max519 contain two matched volt- age-output dacs. the max517 contains a single dac. the dacs are inverted r-2r ladder networks that con- vert 8-bit digital words into equivalent analog output voltages in proportion to the applied reference volt- ages. the max518 has both dac? reference inputs connected to v dd . figure 15 shows a simplified dia- gram of one dac. max517/max519 reference inputs the max517 and max519 can be used for multiplying applications. the reference accepts a 0v to v dd volt- ( ) ( ) ( ) sda 0 start condition address byte (device 0) ack 10110000 0 0 00000 000 010110100 1 repeated start condition stop condition command byte addressing dac0 command byte (addressing dac0) ack output byte (full scale) ack address byte (device 1) ack device 0's dac0 input latch set to full scale. device 1's dac0 input latch set to full scale. sda ack ack output byte (full scale) only device 1's dac0 output latch set to full scale. device 0's output latch unchanged. 1111 111 0000 00 00 0 01 1111 111 figure 13. repeated start conditions max518 sda scl c sda scl e 2 prom xicor x24c04 sda scl ad1 ad0 dual dac sda scl ad1 ad0 single dac +5v max517 out0 out1 out0 figure 12. max517/max518/max519 used in a typical i 2 c application circuit
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs ______________________________________________________________________________________ 13 age, both dc and ac signals. the voltage at each ref input sets the full-scale output voltage for its respective dac. the reference voltage must be positive. the dac? input impedance is code dependent, with the lowest value occurring when the input code is 55 hex or 0101 0101, and the maximum value occurring when the input code is 00 hex. since the ref input resistance (rin) is code dependent, it must be driven by a circuit with low output impedance (no more than rin 2000) to maintain output linearity. the ref input capacitance is also code dependent, with the maximum value occurring at code ff hex (typically 30pf). the output voltage for any dac can be represented by a digitally programmable voltage source as: v out = (n x v ref ) / 256, where n is the numerical value of the dac? binary input code. output buffer amplifiers the dac voltage outputs are internally buffered preci- sion unity-gain followers that slew up to 1v/?. the out- puts can swing from 0v to v dd . with a 0v to 4v (or 4v to 0v) output transition, the amplifier outputs typically settle to 1/2lsb in 6? when loaded with 10k ? in paral- lel with 100pf. the buffer amplifiers are stable with any combination of resistive loads 2k ? and capacitive loads 300pf. the max517/max518/max519 are designed for unipo- lar-output, single-quadrant multiplication where the out- put voltages and the reference inputs are positive with respect to agnd. table 1 shows the unipolar code. table 1. unipolar code table 2r r rr 2r 2r 2r 2r 2r d0 d5 d6 d7 ref_* gnd shown for all 1s on dac out_ *ref = v dd for the max518 figure 15. dac simplified circuit diagram ( ) sda 0 start condition address byte ack 10 1 or ad3 1 or ad2 ad1 ad0 0 0 0 0 0 011 (rst) (pd) (pd) early stop condition interrupted command byte max517/max518/max519's state remains unchanged. ( ) sda 0 start condition address byte ack 10 1 or ad3 1 or ad2 ad1ad000000 000011100 rst 1 command byte (power down) ack interrupted output byte (a) (b) max517/max518/max519 power down; input latch unchanged if rst = 0, dac output(s) reset if rst = 1. early stop condition x x figure 14. early stop conditions dac contents analog output 11111111 255 + v ref ( ) 256 10000001 129 + v ref ( ) 256 10000000 128 v ref + v ref ( ) = 256 2 01111111 127 + v ref ( ) 256 00000001 1 + v ref ( ) 256 00000000 0v
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs 14 ______________________________________________________________________________________ __________applications information power-supply bypassing and ground management bypass v dd with a 0.1? capacitor, located as close to v dd and gnd as possible. careful pc board layout minimizes crosstalk among dac outputs, reference inputs, and digital inputs. figure 16 shows the suggest- ed pc board layout to minimize crosstalk. when using the max518 (or the max517/max519 with v dd as the reference), you may want to add a noise fil- ter to the v dd supply (figure 17) or to the reference input(s) (figure 18), especially in noisy environments. the reference input? bandwidth exceeds 1mhz for ac signals, so disturbances on the reference input can easily affect the dac output(s). the maximum input current for a single reference input is v ref /16k ? = i ref (max). in figure 17, choose r f so that changes in the reference input current will have lit- tle effect on the reference voltage. for example, with r f = 6 ? , the maximum output error due to r f is given by: 6 ? x i ref (max) = 1.9mv or 0.1lsb in figure 18, there is a voltage drop across r f that adds to the tue. this voltage drop is due to the sum of the reference input current (v ref /16k ? maximum), sup- ply current (6ma maximum), and the amplifier output current (v ref /r load ). choose r f to limit this voltage drop to an acceptable value. for example, with a 10k ? load, you can limit the error due to r f to 0.5lsb (9.8mv) by selecting r f so that: r f = v r f / i r f 9.8mv / (5v / 16k ? + 6ma + 5v / 10k ? ) r f 1.4 ? out1 ref0 n.c. ref1 out0 n.c. n.c. gnd system gnd figure 16. pc board layout for minimizing max519 crosstalk (bottom view) figure 17. reference filter when using v dd as a reference max518 r f c f 0.1 f v dd +5v max517 max519 ref_ r f c f 0.1 f v dd +5v figure 18. v dd filter when using v dd as a reference
max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs ______________________________________________________________________________________ 15 __ordering information (continued) *dice are specified at t a = +25?, dc parameters only. **contact factory for availability and processing to mil-std-883. max517bmja -55? to +125? 8 cerdip** 1.5 max517bepa -40? to +85? 8 plastic dip 1.5 max517aepa -40? to +85? 8 plastic dip 1 max518 acpa 0? to +70? 8 plastic dip 1 1.5 16 cerdip** -55? to +125? 1.5 16 narrow so -40? to +85? max519bese 1 16 narrow so -40? to +85? max519aese 1.5 16 plastic dip -40? to +85? max519bepe 1 16 plastic dip -40? to +85? max519aepe 1.5 dice* 0? to +70? max519bc/d 1.5 16 narrow so 0? to +70? max519bcse 1 16 narrow so 0? to +70? max519acse 1.5 16 plastic dip 0? to +70? max519bcpe 1 16 plastic dip 0? to +70? max519 acpe 1.5 8 cerdip** -55? to +125? max518bmja 1.5 8 so -40? to +85? max518besa 1 8 so -40? to +85? max518aesa part temp range pin-package tue (lsb) max518bcpa max518acsa 0? to +70? 0? to +70? 8 plastic dip 8 so 1.5 1 max518bcsa max518bc/d max518aepa -40? to +85? 0? to +70? 0? to +70? 8 so dice* 8 plastic dip 1.5 1.5 1 max518bepa -40? to +85? 8 plastic dip 1.5 max519bmje 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 out1 ref0 n.c. ref1 gnd n.c. n.c. out0 max519 v dd ad0 ad1 ad2 sda n.c. scl ad3 dip/so _____ pin configurations (continued) max517besa -40? to +85? 8 so 1.5 max517aesa -40? to +85? 8 so 1 top view transistor count: 1797 substrate connected to v dd ____________________chip t opography ref0 (max517/ max519) ref1 (max519) v dd ad0 out0 out1 (max518/max519) sda ad2 (max519) ad1 0.135" (3.429mm) 0.078" (1.981mm) ad3 (max519) scl gnd
pdipn.eps soicn .eps package outline, .150" soic 1 1 21-0041 b rev. document control no. approval proprietary information title: top view front view max 0.010 0.069 0.019 0.157 0.010 inches 0.150 0.007 e c dim 0.014 0.004 b a1 min 0.053 a 0.19 3.80 4.00 0.25 millimeters 0.10 0.35 1.35 min 0.49 0.25 max 1.75 0.050 0.016 l 0.40 1.27 0.394 0.386 d d min dim d inches max 9.80 10.00 millimeters min max 16 ac 0.337 0.344 ab 8.75 8.55 14 0.189 0.197 aa 5.00 4.80 8 n ms012 n side view h 0.244 0.228 5.80 6.20 e 0.050 bsc 1.27 bsc c h e e b a1 a d 0-8 l 1 variations: maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. max517/max518/max519 2-wire serial 8-bit dacs with rail-to-rail outputs package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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