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dsp56000 24-bit digital signal processor famil y manual motorola, inc. semiconductor products sector dsp division 6501 william cannon drive, west austin, texas 78735-8598 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
? motorola inc., 1995 motorola technical data semiconductor this document, containing changes, additional features, further explanations, and clarifications, is a supplement to the original document: change the following: page 11-4, section 11.2.1 - delete ?. next tm under mach? page a-83, third line - replace ?;len;le24 with ? n 24 page a-104, under the ?peration:?heading - replace d -1 t d ?with d+1 t d ? page a-104, second sentence after ?escription:?heading - replace one is added from the lsb of d. ?with one is added to the lsb of d; i.e. bit 0 of a0 or b0. page a-130, first symbolic description under the ?peration:?heading - replace if s[n]=0 ?with if s[n]=1 ? page a-218, timing description - replace timing: 2+mvp oscillator clock cycles ?with timing: 6 + ea + ap oscillator clock cycles ? page a-219, timing description - replace timing: 2+mvp oscillator clock cycles ?with timing: 6 + ea + ap oscillator clock cycles ? page a-225, timing description - replace timing: 4+mvp oscillator clock cycles ?with timing: 2+mvp oscillator clock cycles ? page a-261, timing description - replace timing: 4 oscillator clock cycles ?with timing: 2+mvp oscillator clock cycles ? page a-261, memory description - replace ?emory: 1 program words ?with ?emory: 1+ mv program words ? page b-11, an inch below the middle of the page - replace the cir ?instruction with clr ? page b-16, 7 th instruction from bottom - replace lsl a,n0 ?with lsl b a,n0 ? dsp56kfamum/ad family manual dsp56k family 24-bit digital signal processors addendum to 24-bit digital signal processor family manual dsp56k family order this document by dsp56kfamum/ad f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola table of contents iii table of contents paragraph page number title number section 1 dsp56k family introduction 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3 1.2 origin of digital signal processing . . . . . . . . . . . . . . . . . . . . . . . .1-3 1.3 summary of dsp56k family features . . . . . . . . . . . . . . . . . . . . . . . .1-9 1.4 manual organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11 section 2 dsp56k central architecture overview 2.1 dsp56k central architecture overview . . . . . . . . . . . . . . . . . . . .2-3 2.2 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 2.3 address buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 2.4 data alu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 2.5 address generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 2.6 program control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 2.7 memory expansion port (port a) . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 2.8 on-chip emulator (once) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 2.9 phase-locked loop (pll) based clocking . . . . . . . . . . . . . . . . . . .2-6 section 3 data arithmetic logic unit 3.1 data arithmetic logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 3.2 overview and data alu architecture . . . . . . . . . . . . . . . . . . . . . .3-3 3.3 data representation and rounding . . . . . . . . . . . . . . . . . . . . . . .3-10 3.4 double precision multiply mode . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
iv table of contents motorola table of contents (continued) paragraph page number title number 3.5 data alu programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19 3.6 data alu summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19 section 4 address generation unit 4.1 address generation unit and addressing modes . . . . . . . . . . .4-3 4.2 agu architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 4.3 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6 4.4 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8 section 5 program control unit 5.1 program control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 5.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 5.3 program control unit (pcu) architecture . . . . . . . . . . . . . . . . .5-5 5.4 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8 section 6 instruction set introduction 6.1 instruction set introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 6.2 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 6.3 instruction formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 6.4 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20 section 7 processing states 7.1 processing states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.2 normal processing state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.3 exception processing state (interrupt processing) . . . . . .7-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola table of contents v table of contents (continued) paragraph page number title number 7.4 reset processing state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-33 7.5 wait processing state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-36 7.6 stop processing state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-37 section 8 port a 8.1 port a overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3 8.2 port a interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3 section 9 pll clock oscillator 9.1 pll clock oscillator introduction . . . . . . . . . . . . . . . . . . . . . . . .9-3 9.2 pll components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 9.3 pll pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9 9.4 pll operation considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-11 section 10 on-chip emulation (once) 10.1 on-chip emulation introduction . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10.2 on-chip emulation (once) pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10.3 once controller and serial interface . . . . . . . . . . . . . . . . . . . .10-6 10.4 once memory breakpoint logic . . . . . . . . . . . . . . . . . . . . . . . . . . .10-11 10.5 once trace logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-13 10.6 methods of entering the debug mode . . . . . . . . . . . . . . . . . . . .10-14 10.7 pipeline information and global data bus register . . . . . .10-16 10.8 program address bus history buffer . . . . . . . . . . . . . . . . . . .10-18 10.9 serial protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-19 10.10 dsp56k target site debug system requirements . . . . . . . . .10-19 10.11 using the once . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-20 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
vi table of contents motorola table of contents (continued) paragraph page number title number section 11 additional support 11.1 user support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3 11.2 motorola dsp product support . . . . . . . . . . . . . . . . . . . . . . . . . .11-4 11.3 dsp56kadsx application development system . . . . . . . . . . . . .11-6 11.4 dr. bub electronic bulletin board . . . . . . . . . . . . . . . . . . . . . . . . .11-7 11.5 motorola dsp news . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16 11.6 motorola field application engineers . . . . . . . . . . . . . . . . . . .11-16 11.7 design hotlinee 1-800-521-6274 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16 11.8 dsp help line e (512) 891-3230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16 11.9 marketing informatione (512) 891-2030 . . . . . . . . . . . . . . . . . . . . .11-16 11.10 third-party support information e (512) 891-3098 . . . . . . . . . .11-16 11.11 university support e (512) 891-3098 . . . . . . . . . . . . . . . . . . . . . . . .11-16 11.12 training courses e (602) 897-3665 or (800) 521-6274 . . . . . . . . . . .11-17 11.13 reference books and manuals . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17 appendix a instruction set details a.1 appendix a introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.2 instruction guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.3 notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 a.4 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-10 a.5 condition code computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-15 a.6 parallel move descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-20 a.7 instruction descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-21 a.8 instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-294 a.9 instruction sequence restrictions . . . . . . . . . . . . . . . . . . . . . a-305 a.10 instruction encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-311 appendix b benchmark programs b.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.2 benchmark programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
revision 2.1 dsp56004 design specification vii motorola list of figures vii list of figures figure page number title number 1-1 analog signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1-2 digital signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1-3 dsp hardware origins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 2-1 dsp56k block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 3-1 dsp56k block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-2 data alu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-3 mac unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-4 data alu accumulator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3-5 saturation arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-6 integer-to-fractional data conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3-7 bit weighting and alignment of operands . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3-8 integer/fractional number comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3-9 integer/fractional multiplication comparison . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-10 convergent rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3-11 full double precision multiply algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3-12 single x double multiply algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3-13 single x double multiply-accumulate algorithm . . . . . . . . . . . . . . . . . . . . . . 3-18 3-14 dsp56k programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 4-1 dsp56k block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-2 agu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-3 agu programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-4 address register indirect ? no update . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4-5 address register indirect ? postincrement . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4-6 address register indirect ? postdecrement . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4-7 address register indirect ? postincrement by offset nn . . . . . . . . . . . . . . 4-13 4-8 address register indirect ? postdecrement by offset nn . . . . . . . . . . . . . . 4-14 4-9 address register indirect ? indexed by offset nn . . . . . . . . . . . . . . . . . . . 4-15 4-10 address register indirect ? predecrement . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4-11 circular buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4-12 linear addressing with a modulo modifier . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 4-13 modulo modifier example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
viii list of figures motorola list of figures (continued) figure page number title number 4-14 bit-reverse address calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 4-15 address modifier summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 5-1 program address generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5-2 dsp56k block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5-3 three-stage pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5-4 program control unit programming model . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5-5 status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5-6 omr format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5-7 stack pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5-8 sp register values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5-9 dsp56k central processing module programming model . . . . . . . . . . . . . . 5-18 6-1 dsp56k central processing module programming model . . . . . . . . . . . . . . 6-4 6-2 general format of an instruction operation word . . . . . . . . . . . . . . . . . . . . 6-5 6-3 operand sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6-4 reading and writing the alu extension registers . . . . . . . . . . . . . . . . . . . . 6-7 6-5 reading and writing the address alu registers . . . . . . . . . . . . . . . . . . . . . 6-7 6-6 reading and writing control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6-7 special addressing e immediate data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6-8 special addressing e absolute addressing . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6-9 special addressing e immediate short data . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6-10 special addressing e short jump address . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6-11 special addressing e absolute short address . . . . . . . . . . . . . . . . . . . . . . . 6-19 6-12 special addressing e i/o short address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6-13 hardware do loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 6-14 nested do loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 6-15 classifications of parallel data moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6-16 parallel move examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 7-1 fast and long interrupt examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7-2 interrupt priority register (addr x:$ffff) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7-3 interrupting an swi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 7-4 illegal instruction interrupt serviced by a fast interrupt . . . . . . . . . . . . . . . . 7-19 7-5 illegal instruction interrupt serviced by a long interrupt . . . . . . . . . . . . . . . . 7-20 7-6 repeated illegal instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 7-7 trace exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 7-8 fast interrupt service routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 7-9 two consecutive fast interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 7-10 long interrupt service routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30 7-11 jsr first instruction of a fast interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31 7-12 jsr second instruction of a fast interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola list of figures ix list of figures (continued) figure page number title number 7-13 interrupting an rep instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 7-14 interrupting sequential rep instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35 7-15 wait instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 7-16 simultaneous wait instruction and interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 7-17 stop instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 7-18 stop instruction sequence followed by irqa . . . . . . . . . . . . . . . . . . . . . . 7-39 7-19 stop instruction sequence recovering with reset . . . . . . . . . . . . . . . . . 7-42 8-1 port a signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 9-1 pll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9-2 dsp56k block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9-3 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 10-1 once block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10-2 dsp56k block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10-3 once controller and serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10-4 once command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10-5 once status and control register (oscr) . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10-6 once memory breakpoint logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 10-7 once trace logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10-8 once pipeline information and gdb registers . . . . . . . . . . . . . . . . . . . . . . 10-16 10-9 once pab fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 b-1 20-tap fir filter example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-5 b-2 radix 2, in-place, decimation-in-time fft. . . . . . . . . . . . . . . . . . . . . . . . . . b-7 b-3 8-pole 4-multiply cascaded canonic iir filter . . . . . . . . . . . . . . . . . . . . . . . b-9 b-4 lms fir adaptive filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-11 b-5 real input fft based on glenn bergland algorithm. . . . . . . . . . . . . . . . . . . b-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
list of tables table page number title number x list of tables motorola 1-1 benchmark summary in instruction cycles . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 3-1 limited data values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 4-1 address register indirect summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4-2 address modifier summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4-3 bit-reverse addressing sequence example . . . . . . . . . . . . . . . . . . . . . . . . 4-23 6-1 addressing modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 7-1 instruction pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7-2 status register interrupt mask bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7-3 interrupt priority level bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7-4 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7-5 central processor interrupt priorities within an ipl . . . . . . . . . . . . . . . . . . 7-15 7-6 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 9-1 multiplication factor bits mf0-mf11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9-2 division factor bits df0-df3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9-3 pstp and pen relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9-4 clock output disable bits cod0-cod1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 10-1 chip status information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10-2 once register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10-3 memory breakpoint control table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 a-1 instruction description notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-5 a-2 dsp56k addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-11 a-3 dsp56k addressing mode encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-12 a-4 addressing mode modifier summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-14 a-5 condition code computations for instructions (no parallel move) . . . . . . . a-19 a-6 instruction timing summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-301 a-7 parallel data move timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-302 a-8 movec timing summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-302 a-9 movep timing summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-302 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola list of tables xi list of tables (continued) table page number title number a-10 bit manipulation timing summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-303 a-11 jump instruction timing summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-303 a-12 rti/rts timing summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-304 a-13 addressing mode timing summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-304 a-14 memory access timing summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-305 a-15 single-bit register encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-312 a-16 single-bit special register encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-312 a-17 double-bit register encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-312 a-18 triple-bit register encodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-313 a-19 (a)four-bit register encodings for 12 registers in data alu . . . . . . . . . . . a-313 a-19 (b)four-bit register encodings for 16 condition codes . . . . . . . . . . . . . . . . a-313 a-20 five-bit register encodings for 28 registers in data alu and address alu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-314 a-21 six-bit register encodings for 43 registers on-chip . . . . . . . . . . . . . . . . . a-314 a-22 write control encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-314 a-23 memory space bit encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-314 a-24 program controller register encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-315 a-25 condition code and address encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . a-315 a-26 effective addressing mode encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-316 a-27 operation code k0-2 decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-331 a-28 operation code qqq decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-332 a-29 nonmultiply instruction encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-333 a-30 special case #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-334 a-31 special case #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-334 b-1 27-mhz benchmark results for the dsp56001r27 . . . . . . . . . . . . . . . . . . b-4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xii list of tables motorola list of tables (continued) table page number title number f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola dsp56k family introduction 1 - 1 section 1 dsp56k family introduction f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents 1 - 2 dsp56k family introduction motorola section 1.1 introduction ........................................................................ 3 section 1.2 origin of digital signal processing .......................... 3 section 1.2 summary of dsp56k family features .......................... 9 section 1.3 manual organization ........................................................ 11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction motorola dsp56k family introduction 1 - 3 1.1 introduction the dsp56k family is motorola?s series of 24-bit general purpose digital signal proces- sors (dsps * ). the family architecture features a central processing module that is common to the various family members, such as the dsp56002 and the dsp56004. note: the dsp56000 and the dsp56001 are not based on the central processing module architecture and should not be used with this manual. they will continue to be described in the dsp56000/dsp56001 user?s manual (DSP56000UM/ad rev. 2). this manual describes the dsp56k family?s central processor and instruction set. it is intended to be used with a family member?s user?s manual, such as the dsp56002 user?s manual . the user?s manual presents the device?s specifics, including pin descriptions, operating modes, and peripherals. packaging and timing information can be found in the device?s technical data sheet. this chapter introduces general dsp theory and discusses the features and benefits of the motorola dsp56k family of 24-bit processors. it also presents a brief description of each of the sections of the manual. 1.2 origin of digital signal processing dsp is the arithmetic processing of real-time signals sampled at regular intervals and dig- itized. examples of dsp processing include the following: filtering of signals convolution, which is the mixing of two signals correlation, which is a comparison of two signals rectification, amplification, and/or transformation of a signal all of these functions have traditionally been performed using analog circuits. only recent- ly has semiconductor technology provided the processing power necessary to digitally perform these and other functions using dsps. figure 1-1 shows a description of analog signal processing. the circuit in the illustration filters a signal from a sensor using an operational amplifier, and controls an actuator with the result. since the ideal filter is impossible to design, the engineer must design the filter for acceptable response, considering variations in temperature, component aging, power supply variation, and component accuracy. the resulting circuit typically has low noise im- munity, requires adjustments, and is difficult to modify. *this manual uses the acronym dsp for digital signal processing or digital signal processor, de- pending on the context. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
origin of digital signal processing 1- 4 dsp56k family introduction motorola the equivalent circuit using a dsp is shown in figure 1-2. this application requires an analog-to-digital (a/d) converter and digital-to-analog (d/a) converter in addition to the dsp. even with these additional parts, the component count can be lower using a dsp due to the high integration available with current components. processing in this circuit begins by band-limiting the input with an anti-alias filter, eliminat- ing out-of-band signals that can be aliased back into the pass band due to the sampling process. the signal is then sampled, digitized with an a/d converter, and sent to the dsp. the filter implemented by the dsp is strictly a matter of software. the dsp can directly implement any filter that can also be implemented using analog techniques. also, adap- tive filters can be easily implemented using dsp, whereas these filters are extremely difficult to implement using analog techniques. the dsp output is processed by a d/a converter and is low-pass filtered to remove the effects of digitizing. in summary, the advantages of using the dsp include the following: yt () xt () --------- r f r i ------ 1 1 jwr f c f + ----------------------------- - = - + y(t) output to actuator t x(t) input from sensor x(t) r i r f c f analog filter frequency characteristics ideal filter f f c frequency gain y(t) figure 1-1 analog signal processing f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
origin of digital signal processing motorola dsp56k family introduction 1 - 5 fewer components self-test can be built in stable, deterministic performance no filter adjustments wide range of applications filters with much closer tolerances high noise immunity and adaptive filters easily implemented power-supply rejection a dsp operation ideal filter f f c frequency gain fir filter finite impulse response ck () nk () k 0 = n ? a/d d/a x(n) y(n) y(t) x(t) analog filter f f c frequency gain digital filter f f c frequency gain sampler and analog-to-digital converter low-pass antialiasing filter digital-to-analog converter reconstruction low-pass filter a a figure 1-2 digital signal processing analog in analog out f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
origin of digital signal processing 1- 6 dsp56k family introduction motorola the dsp56k family is not designed for a particular application but is designed to execute commonly used dsp benchmarks in a minimum time for a single-multiplier architecture. for example, a cascaded, 2nd-order, four-coefficient infinite impulse response (iir) bi- quad section has four multiplies for each section. for that algorithm, the theoretical minimum number of operations for a single-multiplier architecture is four per section. ta- ble 1-1 shows a list of benchmarks with the number of instruction cycles a dsp56k chip uses compared to the number of multiplies the algorithm requires. these benchmarks and others are used independently or in combination to implement functions whose characteristics are controlled by the coefficients of the benchmarks being executed. useful functions using these and other benchmarks include the following: benchmark number of cycles number of algorithm multiplies real multiply 3 1 n real multiplies 2n n real update 4 1 n real updates 2n n n term real convolution (fir) n n n term real * complex convolution 2n n complex multiply 6 4 n complex multiplies 4n n complex update 7 4 n complex updates 4n 4n n term complex convolution (fir) 4n 4n n th - order power series 2n 2n 2 nd - order real biquad filter 7 4 n cascaded 2 nd - order biquads 4n 4n n radix two fft butter?ies 6n 4n table 1-1 benchmark summary in instruction cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
origin of digital signal processing motorola dsp56k family introduction 1 - 7 digital filtering finite impulse response (fir) infinite impulse response (iir) matched filters (correlators) hilbert transforms windowing adaptive filters/equalizers signal processing compression (e.g., linear predictive coding of speech signals) expansion averaging energy calculations homomorphic processing mu-law/a-law to/from linear data conversion data processing encryption/scrambling encoding (e.g., trellis coding) decoding (e.g., viterbi decoding) useful applications are based on combining these and other functions. dsp applications affect almost every area in electronics because any application for analog electronic cir- cuitry can be duplicated using dsp. the advantages in doing so are becoming more compelling as dsps become faster and more cost effective.some typical applications for dsps are presented in the following list: numeric processing scaler, vector, and matrix arithmetic transcendental function computation (e.g., sin(x), exp(x)) other nonlinear functions pseudo-random-number generation modulation amplitude frequency phase spectral analysis fast fourier transform (fft) discrete fourier transform (dft) sine/cosine transforms moving average (ma) modeling autoregressive (ar) modeling arma modeling telecommunication tone generation dual-tone multifrequency (dtmf) subscriber line interface full-duplex speakerphone teleconferencing voice mail adaptive differential pulse code modulation (adpcm) transcoder medium-rate vocoders noise cancelation repeaters integrated services digital network (isdn) transceivers secure telephones data communication high-speed modems multiple bit-rate modems high-speed facsimile radio communication secure communications point-to-point communications broadcast communications cellular mobile telephone computer array processors work stations personal computers graphics accelerators f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
origin of digital signal processing 1- 8 dsp56k family introduction motorola image processing pattern recognition optical character recognition image restoration image compression image enhancement robot vision graphics 3-d rendering computer-aided engineering (cae) desktop publishing animation instrumentation spectral analysis waveform generation transient analysis data acquisition speech processing speech synthesizer speech recognizer voice mail vocoder speaker authentication speaker verification audio signal processing digital am/fm radio digital hi-fi preamplifier noise cancelation music synthesis music processing acoustic equalizer as shown in figure 1-3, the keys to dsp are as follows: the multiply/accumulate (mac) operation fetching operands for the mac program control to provide versatile operation input/output to move data in and out of the dsp mac is the basic operation used in dsp. the dsp56k family of processors has a dual harvard architecture optimized for mac operations. figure 1-3 shows how the dsp56k high-speed control laser-printer servo hard-disk servo robotics motor controller position and rate controller vibration analysis electric motors jet engines turbines medical electronics cat scanners sonographs x-ray analysis electrocardiogram electroencephalogram nuclear magnetic resonance analysis digital video digital television high-resolution monitors radar and sonar processing navigation oceanography automatic vehicle location search and tracking seismic processing oil exploration geological exploration f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
summary of dsp56k family features motorola dsp56k family introduction 1 - 9 architecture matches the shape of the mac operation. the two operands, c() and x(), are directed to a multiply operation, and the result is summed. this process is built into the chip by using two separate memories (x and y) to feed a single-cycle mac. the entire process must occur under program control to direct the correct operands to the multiplier and save the accumulator as needed. since the two memories and the mac are indepen- dent, the dsp can perform two moves, a multiply and an accumulate, in a single operation. as a result, many of the benchmarks shown in table 1-1 can be executed at or near the theoretical maximum speed for a single-multiplier architecture. 1.3 summary of dsp56k family features the high throughput of the dsp56k family of processors makes them well suited for com- munication, high-speed control, numeric processing and computer and audio applications. the main features that contribute to this high throughput include: speed ? speeds high enough to easily address applications traditionally served by low-end floating point dsps. fir filter ck () nk () k 0 = n ? a/d d/a x(n) y(n) y(t) x(t) x ? x ? mac x memory y memory program figure 1-3 dsp hardware origins f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
summary of dsp56k family features 1- 10 dsp56k family introduction motorola precision ? the data paths are 24 bits wide, providing 144 db of dynamic range; intermediate results held in the 56-bit accumulators can range over 336 db. parallelism ? each on-chip execution unit (agu, program control unit, data alu), memory, and peripheral operates independently and in parallel with the other units through a sophisticated bus system. the data alu, agu, and program control unit operate in parallel so that an instruction prefetch, a 24-bit x 24-bit multiplication, a 56- bit addition, two data moves, and two address-pointer updates using one of three types of arithmetic (linear, modulo, or reverse-carry) can be executed in a single instruction cycle. this parallelism allows a four-coefficient iir filter section to be executed in only four cycles, the theoretical minimum for single-multiplier architecture. at the same time, the two serial controllers can send and receive full-duplex data, and the host port can send/receive simplex data. flexibility ? while many other dsps need external communications circuitry to interface with peripheral circuits (such as a/d converters, d/a converters, or host processors), the dsp56k family provides on-chip serial and parallel interfaces which can support various configurations of memory and peripheral modules sophisticated debugging ? motorola?s on-chip emulation technology (once) allows simple, inexpensive, and speed independent access to the internal registers for debugging. once tells application programmers exactly what the status is within the registers, memory locations, buses, and even the last five instructions that were executed. phase-locked loop (pll) based clocking ? pll allows the chip to use almost any available external system clock for full-speed operation while also supplying an output clock synchronized to a synthesized internal core clock. it improves the synchronous timing of the processors? external memory port, eliminating the timing skew common on other processors. invisible pipeline ? the three-stage instruction pipeline is essentially invisible to the programmer, allowing straightforward program development in either assembly language or a high-level language such as a full kernighan and ritchie c. instruction set ? the instruction mnemonics are mcu-like, making the transition from programming microprocessors to programming the chip as easy as possible. the orthogonal syntax controls the parallel execution units. the hardware do loop instruction and the repeat (rep) instruction make writing straight-line code obsolete. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
manual organization motorola dsp56k family introduction 1 - 11 dsp56001 compatibility ? all members of the dsp56k family are downward compatible with the dsp56001, and also have added flexibility, speed, and functionality. low power ? as a cmos part, the dsp56000/dsp56001 is inherently very low power and the stop and wait instructions further reduce power requirements. 1.4 manual organization this manual describes the central processing module of the dsp56k family in detail and provides practical information to help the user: understand the operation of the dsp56k family design parallel communication links design serial communication links code dsp algorithms code communication routines code data manipulation algorithms locate additional support the following list describes the contents of each section and each appendix: section 2 e dsp56k central architecture overview the dsp56k central architecture consists of the data arithmetic logic unit (alu), ad- dress generation unit (agu), program control unit, on-chip emulation (once) circuitry, the phase locked loop (pll) based clock oscillator, and an external memory port (port a). this section describes each subsystem and the buses interconnecting the major components in the dsp56k central processing module. section 3 e data arithmetic logic unit this section describes in detail the data alu and its programming model. section 4 e address generation unit this section specifically describes the agu, its programming model, address indirect modes, and address modifiers. section 5 e program control unit this section describes in detail the program control unit and its programming model. section 6 e instruction set introduction this section presents a brief description of the syntax, instruction formats, oper- and/memory references, data organization, addressing modes, and instruction set. a detailed description of each instruction is given in appendix a - instruction set details. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
manual organization 1- 12 dsp56k family introduction motorola section 7 e processing states this section describes the five processing states (normal, exception, reset, wait, and stop). section 8 e port a this section describes the external memory port, its control register, and control signals. section 9 e pll clock oscillator this section describes the pll and its functions section 10 e on-chip emulator (once) this section describes the once circuitry and its functions. section 11 e additional support this section presents a brief description of current support products and services and information on where to obtain them. appendix a e instruction set details a detailed description of each dsp56k family instruction, its use, and its affect on the processor are presented. appendix b e benchmarks dsp5k family benchmark results are listed in this appendix. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola dsp56k central architecture overview 2 - 1 section 2 dsp56k central architecture overview f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents 2 - 2 dsp56k central architecture overview motorola section 2.1 dsp56k central architecture overview ..................3 section 2.2 data buses .............................................................................3 section 2.3 address buses .....................................................................4 section 2.4 data alu ..................................................................................5 section 2.5 address generation unit ................................................5 section 2.6 program control unit .....................................................5 section 2.7 memory expansion port (port a) ..................................6 section 2.8 on-chip emulator (once) ..................................................6 section 2.9 phase-locked loop (pll) based clocking ..................6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dsp56k central architecture overview motorola dsp56k central architecture overview 2 - 3 2.1 dsp56k central architecture overview the dsp56k family of processors is built on a standard central processing module. in the expansion area around the central processing module, the chip can support various con- figurations of memory and peripheral modules which may change from family member to family member. this section introduces the architecture and the major components of the central processing module. the central components are: data buses address buses data arithmetic logic unit (data alu) address generation unit (agu) program control unit (pcu) memory expansion (port a) on-chip emulator (oncea) circuitry phase-locked loop (pll) based clock circuitry figure 2-1 shows a block diagram of a typical dsp56k family processor, including the central processing module and a nonspecific expansion area for memory and peripherals. the following paragraphs give brief descriptions of each of the central components. each of the components is explained in detail in subsequent chapters. 2.2 data buses the dsp56k central processing module is organized around the registers of three inde- pendent execution units: the pcu, the agu, and the data alu. data movement between the execution units occurs over four bidirectional 24-bit buses: the x data bus (xdb), the y data bus (ydb), the program data bus (pdb), and the global data bus (gdb). (certain instructions treat the x and y data buses as one 48-bit data bus by concatenating them.) data transfers between the data alu and the x data memory or y data memory occur over xdb and ydb, respectively. xdb and ydb are kept local on the chip to maximize speed and minimize power dissipation. all other data transfers, such as i/o transfers with peripherals, occur over the gdb. instruction word prefetches occur in parallel over the pdb. the bus structure supports general register-to-register, register-to-memory, and memory- to-register data movement. it can transfer up to two 24-bit words and one 56-bit word in the same instruction cycle. transfers between buses occur in the internal bus switch. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
address buses 2- 4 dsp56k central architecture overview motorola 2.3 address buses addresses are specified for internal x data memory and y data memory on two unidirec- tional 16-bit buses ? x address bus (xab) and y address bus (yab). program memory addresses are specified on the bidirectional program address bus (pab). external mem- clock generator peripheral pins internal data bus switch program ram/rom expansion program interrupt controller program decode controller program address generator ya b xab pa b ydb xdb pdb gdb modc/nmi modb/irqb reset data alu 24x24 + 56 ? 56-bit mac two 56-bit accumulators external address bus switch bus control external data b u s switch address data 16 bits 24 bits port a moda/irqa pll x memory ram/rom expansion y memory ram/rom expansion address generation unit oncea peripheral modules expansion area control 24-bit 56k module figure 2-1 dsp56k block diagram program control unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
data alu motorola dsp56k central architecture overview 2 - 5 ory spaces are addressed over a single 16-bit unidirectional address bus driven by a three-input multiplexer that can select the xab, the yab, or the pab. only one external memory access can be made in an instruction cycle. there is no speed penalty if only one external memory space is accessed in an instruction cycle. however, if two or three ex- ternal memory spaces are accessed in a single instruction, there will be a one or two instruction cycle execution delay, respectively. a bus arbitrator controls external access. 2.3.1 internal bus switch transfers between buses occur in the internal bus switch. the internal bus switch, which is similar to a switch matrix, can connect any two internal buses without adding any pipe- line delays. this flexibility simplifies programming. 2.3.2 bit manipulation unit the bit manipulation unit is physically located in the internal bus switch block because the internal data bus switch can access each memory space. the bit manipulation unit per- forms bit manipulation operations on memory locations, address registers, control registers, and data registers over the xdb, ydb, and gdb. 2.4 data alu the data alu performs all of the arithmetic and logical operations on data operands. it consists of four 24-bit input registers, two 48-bit accumulator registers, two 8-bit accumu- lator extension registers, an accumulator shifter, two data bus shifter/limiter circuits, and a parallel, single-cycle, nonpipelined multiply-accumulator (mac) unit. 2.5 address generation unit the agu performs all of the address storage and address calculations necessary to indi- rectly address data operands in memory. it operates in parallel with other chip resources to minimize address generation overhead. the agu has two identical address arithmetic units that can generate two 16-bit addresses every instruction cycle. each of the arith- metic units can perform three types of arithmetic: linear, modulo, and reverse-carry. 2.6 program control unit the program control unit performs instruction prefetch, instruction decoding, hardware do loop control, and interrupt (or exception) processing. it consists of three components: the program address generator, the program decode controller, and the program interrupt controller. it contains a 15-level by 32-bit system stack memory and the following six di- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
memory expansion port (port a) 2- 6 dsp56k central architecture overview motorola rectly addressable registers: the program counter (pc), loop address (la), loop counter (lc), status register (sr), operating mode register (omr), and stack pointer (sp). the 16-bit pc can address 65,536 locations in program memory space. there are four mode and interrupt control pins that provide input to the program interrupt controller. the mode select a/external interrupt request a(moda/irqa ) and mode se- lect b/external interrupt request b (modb/irqb ) pins select the chip operating mode and receive interrupt requests from external sources. the mode select c/non-maskable interrupt (modc/nmi ) pin provides further operating mode options and non-maskable interrupt input. the reset pin resets the chip. when it is asserted, it initializes the chip and places it in the reset state. when it is deasserted, the chip assumes the operating mode indicated by the moda, modb, and modc pins. 2.7 memory expansion port (port a) port a synchronously interfaces with a wide variety of memory and peripheral devices over a common 24-bit data bus. these devices include high-speed static rams, slower memory devices, and other dsps and mpus in master/slave configurations. this variety is possible because the expansion bus timing is programmable and can be tailored to match the speed requirements of the different memory spaces. not all dsp56k family members feature a memory expansion port. see the individual device?s user?s manual to determine if a particular chip includes this feature. 2.8 on-chip emulator (once) dsp56k on-chip emulation (once) circuitry allows the user to interact with the dsp56k and its peripherals non-intrusively to examine registers, memory, or on-chip peripherals. it provides simple, inexpensive, and speed independent access to the internal registers for sophisticated debugging and economical system development. dedicated once pins allow the user to insert the dsp into its target system and retain debug control without sacrificing other user accessible on-chip resources. the design eliminates the costly cabling and the access to processor pins required by traditional em- ulator systems. 2.9 phase-locked loop (pll) based clocking the pll allows the dsp to use almost any available external system clock for full-speed operation, while also supplying an output clock synchronized to a synthesized internal clock. the pll performs frequency multiplication, skew elimination, and low-power division. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola data arithmetic logic unit 3 - 1 section 3 data arithmetic logic unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents 3 - 2 data arithmetic logic unit motorola section 3.1 data arithmetic logic unit ............................................. 3 section 3.2 overview and data alu architecture ....................... 3 3.2.1 data alu input registers (x1, x0, y1, y0) ........................................ 5 3.2.2 mac and logic unit ............................................................................ 6 3.2.3 data alu a and b accumulators ........................................................ 7 3.2.4 accumulator shifter ............................................................................ 9 3.2.5 data shifter/limiter ............................................................................. 9 3.2.5.1 limiting (saturation arithmetic) .................................................. 9 3.2.5.2 scaling ........................................................................................ 10 section 3.3 data representation and rounding .......................... 10 section 3.4 double precision multiply mode ................................. 16 section 3.5 data alu programming model ....................................... 19 section 3.6 data alu summary .............................................................. 19 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
data arithmetic logic unit motorola data arithmetic logic unit 3 - 3 3.1 data arithmetic logic unit this section describes the operation of the data alu registers and hardware. it dis- cusses data representation, rounding, and saturation arithmetic used within the data alu, and concludes with a discussion of the programming model. 3.2 overview and data alu architecture as described in section 2, the dsp56k family central processing module is composed of three execution units that operate in parallel. they are the data alu, address genera- tion unit (agu), and the program control unit (pcu) (see figure 3-1). these three units are register oriented rather than bus oriented and interface over the system buses with memory and memory-mapped i/o devices. the data alu (see figure 3-2) is the first of these execution units to be presented. it bal- ances speed with the capability to process signals that have a wide dynamic range and performs all arithmetic and logical operations on data operands. the data alu registers may be read or written over the xdb and the ydb as 24- or 48- bit operands. the source operands for the data alu, which may be 24, 48, or 56 bits, always originate from data alu registers. the results of all data alu operations are stored in an accumulator. the 24-bit data words provide 144 db of dynamic range. this range is sufficient for most real-world applications since the majority of data converters are 16 bits or less e and cer- tainly not greater than 24 bits. the 56-bit accumulator inside the data alu provides 336 db of internal dynamic range so that no loss of precision will occur due to intermediate processing. special circuitry handles data overflows and roundoff errors. the data alu can perform any of the following operations in a single instruction cycle: multiplication, multiply-accumulate with positive or negative accumulation, convergent rounding, multiply-accumulate with positive or negative accumulation and convergent rounding, addition, subtraction, a divide iteration, a normalization iteration, shifting, and logical operations. the components of the data alu are: four 24-bit input registers a parallel, single-cycle, nonpipelined multiply-accumulator/logic unit (mac) two 48-bit accumulator registers two 8-bit accumulator extension registers an accumulator shifter two data bus shifter/limiter circuits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview and data alu architecture 3 - 4 data arithmetic logic unit motorola the following paragraphs describe each of these components and provide a description of data representation, rounding, and saturation arithmetic. clock generator peripheral pins internal data bus switch program ram/rom expansion program interrupt controller program decode controller program address generator ya b xab pa b ydb xdb pdb gdb modc/nmi modb/irqb reset data alu 24x24 + 56 ? 56-bit mac two 56-bit accumulators external address bus switch bus control external data b u s switch address data 16 bits 24 bits port a moda/irqa pll x memory ram/rom expansion y memory ram/rom expansion address generation unit oncea peripheral modules expansion area control 24 bit 56k module figure 3-1 dsp56k block diagram program control unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview and data alu architecture motorola data arithmetic logic unit 3 - 5 3.2.1 data alu input registers (x1, x0, y1, y0) x1, x0, y1, and y0 are four 24-bit, general-purpose data registers. they can be treated as four independent, 24-bit registers or as two 48-bit registers called x and y, developed by concatenating x1:x0 and y1:y0, respectively. x1 is the most significant word in x and y1 is the most significant word in y. the registers serve as input buffer registers between the xdb or ydb and the mac unit. they act as data alu source operands and allow new operands to be loaded for the next instruction while the current instruction uses the 56 24 24 56 56 56 56 x data bus y data bus 24 24 x0 x1 y0 y1 24 24 multiplier accumulator, rounding, and logic unit shifter a (56) b (56) shifter/limiter figure 3-2 data alu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview and data alu architecture 3 - 6 data arithmetic logic unit motorola register contents. the registers may also be read back out to the appropriate data bus to implement memory-delay operations and save/restore operations for interrupt service routines. 3.2.2 mac and logic unit the mac and logic unit shown in figure 3-3 conduct the main arithmetic processing and perform all calculations on data operands in the dsp. for arithmetic instructions, the unit accepts up to three input operands and outputs one 56-bit result in the following form: extension:most significant product:least significant product (ext:msp:lsp). the operation of the mac unit occurs independently and in par- allel with xdb and ydb activity, and its registers facilitate buffering for data alu inputs and outputs. latches on the mac unit input permit writing an input register which is the source for a data alu operation in the same instruction. the arithmetic unit contains a multiplier and two accumulators. the input to the multiplier can only come from the x or y registers (x1, x0, y1, y0). the multiplier executes 24-bit x 24-bit, parallel, twos-complement fractional multiplies. the 48-bit product is right justi- fied and added to the 56-bit contents of either the a or b accumulator. the 56-bit sum is stored back in the same accumulator (see figure 3-3). an 8-bit adder, which acts as an extension accumulator for the mac array, accommodates overflow of up to 256 and al- lows the two 56-bit accumulators to be added to and subtracted from each other. the extension adder output is the ext portion of the mac unit output. this multiply/accumu- late operation is not pipelined, but is a single-cycle operation. if the instruction specifies a multiply without accumulation (mpy), the mac clears the accumulator and then adds the contents to the product. in summary, the results of all arithmetic instructions are valid (sign-extended and zero- filled) 56-bit operands in the form of ext:msp:lsp (a2:a1:a0 or b2:b1:b0). when a 56- bit result is to be stored as a 24-bit operand, the lsp can be simply truncated, or it can be rounded (using convergent rounding) into the msp. convergent rounding (round-to-nearest) is performed when the instruction (for example, the signed multiply-accumulate and round (macr) instruction) specifies adding the mul- tiplier?s product to the contents of the accumulator. the scaling mode bits in the status register specify which bit in the accumulator shall be rounded. the logic unit performs the logical operations and, or, eor, and not on data alu reg- isters. it is 24 bits wide and operates on data in the msp portion of the accumulator. the lsp and ext portions of the accumulator are not affected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview and data alu architecture motorola data arithmetic logic unit 3 - 7 3.2.3 data alu a and b accumulators the data alu features two general-purpose, 56-bit accumulators, a and b. each con- sists of three concatenated registers (a2:a1:a0 and b2:b1:b0, respectively). the 8-bit sign extension (ext) is stored in a2 or b2 and is used when more than 48-bit accuracy is needed; the 24-bit most significant product (msp) is stored in a1 or b1; the 24-bit least figure 3-3 mac unit 24 bits 48 bits 56 bits x0,x1, y0, or y1 x0,x1, y0, or y1 x0,x1, y0, or y1 24-bitx24-bit fractional multiplier 56 - bit arithmetic and logic unit r 24 s h i f t e r convergent - rounding forcing function scaling mode bits condition code generator accumulator a accumulator b + e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview and data alu architecture 3 - 8 data arithmetic logic unit motorola significant product (lsp) is stored in a0 or b0 as shown in figure 3-4. overflow occurs when a source operand requires more bits for accurate representation than are available in the destination. the 8-bit extension registers offer protection against overflow. in the dsp56k chip family, the extreme values that a word operand can assume are - 1 and + 0.9999998. if the sum of two numbers is less than - 1 or greater than + 0.9999998, the result (which cannot be represented in a 24 bit word oper- and) has underflowed or overflowed. the 8-bit extension registers can accurately repre- sent the result of 255 overflows or 255 underflows. whenever the accumulator extension registers are in use, the v bit in the status register is set. automatic sign extension occurs when the 56-bit accumulator is written with a smaller operand of 48 or 24 bits. a 24-bit operand is written to the msp (a1 or b1) portion of the accumulator, the lsp (a0 or b0) portion is zero filled, and the ext (a2 or b2) portion is sign extended from msp. a 48-bit operand is written into the msp:lsp portion (a1:a0 or b1:b0) of the accumulator, and the ext portion is sign extended from msp. no sign extension occurs if an individual 24-bit register is written (a1, a0, b1, or b0).when either a or b is read, it may be optionally scaled one bit left or one bit right for block floating- point arithmetic. sign extension can also occur when writing a or b from the xdb and/or ydb or with the results of certain data alu operations (such as the transfer conditionally (tcc) or transfer data alu register (tfr) instructions). overflow protection occurs when the contents of a or b are transferred over the xdb and ydb by substituting a limiting constant for the data. limiting does not affect the content of a or b e only the value transferred over the xdb or ydb is limited. this overflow pro- tection occurs after the contents of the accumulator has been shifted according to the scaling mode. shifting and limiting occur only when the entire 56-bit a or b accumulator is specified as the source for a parallel data move over the xdb or ydb. when individual registers a0, a1, a2, b0, b1, or b2 are specified as the source for a parallel data move, 55 0 55 0 * a2 a1 a0 7023 0 23 0 * b2 b1 b0 7023 0 23 0 data alu accumulator registers *read as sign extension bits, written as don?t care. accumulator a accumulator b ext msp lsp ext msp lsp figure 3-4 data alu accumulator registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview and data alu architecture motorola data arithmetic logic unit 3 - 9 shifting and limiting are not performed. 3.2.4 accumulator shifter the accumulator shifter (see figure 3-3) is an asynchronous parallel shifter with a 56-bit input and a 56-bit output that is implemented immediately before the mac accumulator input. the source accumulator shifting operations are as follows: no shift (unmodified) 1-bit left shift (arithmetic or logical) asl, lsl, rol 1-bit right shift (arithmetic or logical) asr, lsr, ror force to zero 3.2.5 data shifter/limiter the data shifter/limiter circuits (see figure 3-3) provide special post-processing on data read from the data alu a and b accumulators out to the xdb or ydb. there are two in- dependent shifter/limiter circuits (one for xdb and one for the ydb); each consists of a shifter followed by a limiting circuit. 3.2.5.1 limiting (saturation arithmetic) the a and b accumulators serve as buffer registers between the mac unit and the xdb and/or ydb. they act both as data alu source and destination operands.test logic exists in each accumulator register to support the operation of the data shifter/limiter circuits. this test logic detects overflows out of the data shifter so that the limiter can substitute one of several constants to minimize errors due to the overflow. this process is called sat- uration arithmetic the data alu a and b accumulators have eight extension bits. limiting occurs when the extension bits are in use and either a or b is the source being read over xdb or ydb. if the contents of the selected source accumulator can be represented without overflow in the destination operand size (i.e., accumulator extension register not in use), the data lim- iter is disabled, and the operand is not modified. if contents of the selected source accumulator cannot be represented without overflow in the destination operand size, the data limiter will substitute a limited data value with maximum magnitude (saturated) and with the same sign as the source accumulator contents: $7fffff for 24-bit or $7fffff ffffff for 48-bit positive numbers, $800000 for 24-bit or $800000 000000 for 48-bit neg- ative numbers. this process is called saturation arithmetic. the value in the accumulator register is not shifted and can be reused within the data alu. when limiting does occur, a flag is set and latched in the status register.two limiters allow two-word operands to be limited independently in the same instruction cycle. the two data limiters can also be com- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
data representation and rounding 3 - 10 data arithmetic logic unit motorola bined to form one 48-bit data limiter for long-word operands. for example, if the source operand were 01.100 (+ 1.5 decimal) and the destination reg- ister were only four bits, the destination register would contain 1.100 (- 1.5 decimal) after the transfer, assuming signed fractional arithmetic. this is clearly in error as overflow has occurred. to minimize the error due to overflow, it is preferable to write the maximum (limited) value the destination can assume. in the example, the limited value would be 0.111 (+ 0.875 decimal), which is clearly closer to + 1.5 than - 1.5 and therefore intro- duces less error. figure 3-5 shows the effects of saturation arithmetic on a move from register a1 to regis- ter x0. the instruction move a1,x0 causes a move without limiting, and the instruction move a,x0 causes a move of the same 24 bits with limiting. the error without limiting is 2.0; whereas, it is 0.0000001 with limiting. table 3-1 shows a more complete set of limiting situations. 3.2.5.2 scaling the data shifters can shift data one bit to the left or one bit to the right, or pass the data unshifted. each data shifter has a 24-bit output with overflow indication and is controlled by the scaling mode bits in the status register. these shifters permit dynamic scaling of fixed-point data without modifying the program code. for example, this permits block floating-point algorithms such as fast fourier transforms to be implemented in a regular fashion. 3.3 data representation and rounding the dsp56k uses a fractional data representation for all data alu operations. figure 3- figure 3-5 saturation arithmetic 55 0 7 0 23 0 23 0 0. . . 0 1 0 0 . . . . . . . . . . . 0 0 0 0 . . . . . . . . . . . . 0 0 55 0 7 0 23 0 23 0 0 . . . 0 1 0 0 . . . . . . . . . . . 0 0 0 0 . . . . . . . . . . . . 0 0 without limiting* with limiting* a = +1.0 1 0 0 . . . . . . . . . . . 0 0 0 1 1 . . . . . . . . . . . 1 1 23 0 23 0 move a1 , x0 move a , x0 x0 = -1.0 x0 = +0.9999999 |error| = 2.0 a = +1.0 |error| = .0000001 * limiting automatically occurs when the 56 - bit operands a or b (not a2, a1, a0, b2, b1, or b0) are read. the contents of a or b are not changed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
data representation and rounding motorola data arithmetic logic unit 3 - 11 7 shows the bit weighting of words, long words, and accumulator operands for this repre- sentation. the decimal points are all aligned and are left justified. data must be converted to a fractional number by scaling before being used by the dsp or the user will have to be very careful in how the dsp manipulates the data. moving $3f to a 24-bit data alu register does not result in the contents being $00003f as might be expected. assuming numbers are fractional, the dsp left justifies rather than right justi- fies. as a result, storing $3f in a 24-bit register results in the contents being $3f0000. the simplest example of scaling is to convert all integer numbers to fractional numbers by shifting the decimal 24 places to the left (see figure 3-6). thus, the data has not changed; only the position of the decimal has moved. for words and long words, the most negative number that can be represented is -1 whose internal representation is $800000 and $800000000000, respectively. the most positive word is $7fffff or 1 - 2 -23 and the most positive long word is $7fffffffffff destination memory reference source operand accumulator sign limited value (hexadecimal) type of access xdb ydb x x:a x:b + - 7fffff 800000 ? ? one 24 bit y y:a y:b + - ? ? 7fffff 800000 one 24 bit x and y x:a y:a x:a y:b x:b y:a x:b y:b l:ab l:ba + - + - + - 7fffff 800000 7fffff 800000 7fffff 800000 7fffff 800000 7fffff 800000 7fffff 800000 two 24 bit l (x:y) l:a l:b + - 7fffff 800000 ffffff 000000 one 48 bit table 3-1 limited data values s3f . s . 3f s = sign bit 3f = hexadecimal data to be converted figure 3-6 integer-to-fractional data conversion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
data representation and rounding 3 - 12 data arithmetic logic unit motorola or 1 - 2 -47 . these limitations apply to all data stored in memory and to data stored in the data alu input buffer registers. the extension registers associated with the accumula- tors allow word growth so that the most positive number that can be used is approxi- mately 256 and the most negative number is approximately -256. when the accumulator extension registers are in use, the data contained in the accumulators cannot be stored exactly in memory or other registers. in these cases, the data must be limited to the most positive or most negative number consistent with the size of the destination and the sign of the accumulator (the most significant bit (msb) of the extension register). to maintain alignment of the binary point when a word operand is written to accumulator a or b, the operand is written to the most significant accumulator register (a1 or b1), and its msb is automatically sign extended through the accumulator extension register. the least significant accumulator register is automatically cleared. when a long-word oper- and is written to an accumulator, the least significant word of the operand is written to the least significant accumulator register a0 or b0 and the most significant word is written to 2 e47 2 e24 2 0 e2 8 2 e47 2 e24 e2 0 2 e23 e2 0 * a2, b2 a1, b1 a0, b0 sign extension operand zero data alu word operand x1, x0 y1, y0 a1, a0 b1, b0 long - word operand x1:x0 = x y1:y0 = y a1:a0 = a10 b1:b0 = b10 accumulator a or b figure 3-7 bit weighting and alignment of operands f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
data representation and rounding motorola data arithmetic logic unit 3 - 13 a1 or b1(see figure 3-8). a comparison between integer and fractional number representation is shown in figure 3-8 . the number representation for integers is between 2 (n-1) ; whereas, the fractional representation is limited to numbers between 1. to convert from an integer to a frac- tional number, the integer must be multiplied by a scaling factor so the result will always be between 1. the representation of integer and fractional numbers is the same if the numbers are added or subtracted but is different if the numbers are multiplied or divided. an example of two numbers multiplied together is given in figure 3-9. the key difference is that the extra bit in the integer multiplication is used as a duplicate sign bit and as the least significant bit (lsb) in the fractional multiplication. the advantages of fractional data representation are as follows: the msp (left half) has the same format as the input data. the lsp (right half) can be rounded into the msp without shifting or updating the exponent. a significant bit is not lost through sign extension. conversion to floating-point representation is easier because the industry-standard floating-point formats use fractional mantissas. coefficients for most digital filters are derived as fractions by the high-level language programs used in digital-filter design packages, which implies that the results can be used without the extensive data conversions that other formats require. should integer arithmetic be required in an application, shifting a one or zero, depending on the sign, into the msb converts a fraction to an integer. the data alu mac performs rounding of the accumulator register to single precision if requested in the instruction (the a1 or b1 register is rounded according to the contents of the a0 or b0 register). the rounding method is called round-to-nearest (even) number, or convergent rounding. the usual rounding method rounds up any value above one-half s s n bits n bits e2 (ne1) to [ +2 (ne1) e1 ] e1 to [ +1e2 e(ne1) ] twos complement integer twos complement fractional fractional = integer except for x and ? figure 3-8 integer/fractional number comparison f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
data representation and rounding 3 - 14 data arithmetic logic unit motorola and rounds down any value below one-half. the question arises as to which way one- half should be rounded. if it is always rounded one way, the results will eventually be biased in that direction. convergent rounding solves the problem by rounding down if the number is odd (lsb=0) and rounding up if the number is even (lsb=1). figure 3-10 shows the four cases for rounding a number in the a1 (or b1) register. if scaling is set in the status register, the resulting number will be rounded as it is put on the data bus. how- ever, the contents of the register are not scaled. s s . . . signed multiplier s s msp lsp 2n ? 1 product sign extension 2n bits s s . . . signed multiplier 0 s msp lsp 2n ? 1 product zero fill 2n bits integer fractional signed multiplication n x n - 2n e 1 bits figure 3-9 integer/fractional multiplication comparison f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
data representation and rounding motorola data arithmetic logic unit 3 - 15 a2 a1 a0 xx . . xx xxx . . . xxx0100 011xxx . . . . xxx 55 48 47 24 23 0 case i: if a0 < $800000 (1/2), then round down (add nothing) before rounding after rounding after rounding after rounding before rounding before rounding 0 a2 a1 a0* xx . . xx xxx . . . xxx0100 000 . . . . . . . . 000 55 48 47 24 23 0 case ii: if a0 > $800000 (1/2), then round up (add 1 to a1) a2 a1 a0 xx . . xx xxx . . . xxx0100 1110xx . . . . xxx 55 48 47 24 23 0 1 a2 a1 a0* xx . . xx xxx . . . xxx0101 000 . . . . . . . . 000 55 48 47 24 23 0 case iii: if a0 = $800000 (1/2), and the lsb of a1 = 0,then round down (add nothing) a2 a1 a0 xx . . xx xxx . . . xxx0100 10000 . . . . . . 000 55 48 47 24 23 0 0 a2 a1 a0* xx . . xx xxx . . . xxx0100 000 . . . . . . . . 000 55 48 47 24 23 0 case iv: if a0 = $800000 (1/2), and the lsb = 1, then round up (add 1 to a1) before rounding a2 a1 a0 xx . . xx xxx . . . xxx0101 10000 . . . . . . 000 55 48 47 24 23 0 1 after rounding a2 a1 a0* xx . . xx xxx . . . xxx0110 000 . . . . . . . . 000 55 48 47 24 23 0 figure 3-10 convergent rounding *a0 is always clear; performed during rnd, mpyr, macr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
double precision multiply mode 3 - 16 data arithmetic logic unit motorola 3.4 double precision multiply mode the data alu double precision multiply operation multiplies two 48-bit operands with a 96-bit result. the processor enters the dedicated double precision multiply mode when the user sets bit 14 (dm) of the status register (bit 6 of the mr register). the mode is disabled by clearing the dm bit. for information on the dm bit, see section 5.4.2.13 - double precision multiply mode (bit 14). caution: while in the double precision multiply mode, only the double precision multiply algorithms shown in figure 3-11, figure 3-12, and figure 3-13 may be executed by the data alu; any other data alu operation will give indeterminate results. figure 3-11 shows the full double precision multiply algorithm. to allow for pipeline delay, the andi instruction should not be immediately followed by a data alu instruc- tion. for example, the ori instruction sets the dm mode bit, but, due to the instruction execution pipeline, the data alu enters the double precision multiply mode only after y: x: r5 msp2 lsp2 msp1 lsp1 r1 dp2 dp0 dp3 dp1 r0 r0 dp3_dp2_dp1_dp0 = msp1_lsp1 x msp2_lsp2 ori #$40,mr ;enter mode move x:(r1)+,x0 y:(r5)+,y0 ;load operands mpy y0,x0,a x:(r1)+,x1 y:(r5)+,y1 ;lsp*lsp t a mac x1,y0,a a0,y:(r0) ;shifted(a)+ ; msp*lsp t a mac x0,y1,a ;a+lsp*msp t a mac y1,x1,a a0,x:(r0)+ ;shifted(a)+ ; msp*msp t a move a,l:(r0)+ andi #$bf,mr ;exit mode non-data alu operation ;pipeline delay figure 3-11 full double precision multiply algorithm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
double precision multiply mode motorola data arithmetic logic unit 3 - 17 one instruction cycle. the andi instruction clears the dm mode bit, but, due to the instruction execution pipeline, the data alu leaves the mode after one instruction cycle. the double precision multiply algorithm uses the y0 register at all stages. if the use of the data alu is required in an interrupt service routine, y0 should be saved together with other data alu registers to be used, and should be restored before leaving the interrupt routine. if just single precision times double precision multiply is desired, two of the multiply oper- ations may be deleted and replaced by suitable initialization and clearing of the accumu- lator and y0. figure 3-12 shows the single precision times double precision algorithm. figure 3-13 shows a single precision times double precision multiply-accumulate algo- rithm. first, the least significant parts of the double precision values are multiplied by the single precision values and accumulated in the double precision multiply mode. then the dm bit is cleared and the least significant part of the result is saved to memory. the most significant parts of the double precision values are then multiplied by the single pre- y: x: r5 sp msp1 lsp1 r1 dp2 dp3 dp1 r0 r0 dp3_dp2_dp1 = msp1_lsp1 x sp clr a #0,y0 ;clear a and y0 ori #$40,mr ;enter dp mode move x:(r1)+,x0 y:(r5)+,y1 ;load lsp1 and sp mac x0,y1,a x:(r1)+,x1 ;lsp1*sp t a, ;load msp1 mac y1,x1,a a0,x:(r0)+ ;shifted(a)+ ; sp*msp1 t a, ;save dp1 move a,l:(r0)+ ;save dp3_dp2 andi #$bf,mr ;exit dp mode non-data alu operation ;pipeline delay figure 3-12 single double multiply algorithm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
double precision multiply mode 3 - 18 data arithmetic logic unit motorola cision values and accumulated using regular mac instructions. note that the maximum number of single times double mac operations in this algorithm are limited to 255 since overflow may occur (the a2 register is just eight bits long). if a longer sequence is required, it should be split into sub-sequences each with no more than 255 mac opera- tions. y: x: r5 spi mspi lspi r1 dp2 dp3 dp1 r0 r0 dp3_dp2_dp1 = ? mspi_lspi x spi move #n-1,m5 clr a #0,y0 ;clear a and y0 ori #$40,mr ;enter dp mode move x:(r1)+,x0 y:(r5)+,y1 ;load lspi and spi rep #n ;0 data alu programming model motorola data arithmetic logic unit 3 - 19 3.5 data alu programming model the data alu features 24-bit input/output data registers that can be concatenated to ac- commodate 48-bit data and two 56-bit accumulators, which are segmented into three 24- bit pieces that can be transferred over the buses. figure 3-14 illustrates how the registers in the programming model are grouped. 3.6 data alu summary the data alu performs arithmetic operations involving multiply and accumulate opera- tions. it executes all instructions in one machine cycle and is not pipelined. the two 24-bit numbers being multiplied can come from the x registers (x0 or x1) or y registers (y0 or y1). after multiplication, they are added (or subtracted) with one of the 56-bit accumula- tors and can be convergently rounded to 24 bits. the convergent-rounding forcing function detects the $800000 condition in the lsp and makes the correction as neces- sary. the final result is then stored in one of the accumulators as a valid 56-bit number. the condition code bits are set based on the rounded output of the logic unit. 47 0 55 0 55 0 data alu x0 23 0 23 0 47 0 y1 y0 23 0 23 0 data alu * a2 a1 a0 23 8 7 0 23 0 23 0 * b2 b1 b0 23 8 7 0 23 0 23 0 x1 input registers accumulator registers *read as sign extension bits, written as don?t care. x y a b figure 3-14 dsp56k programming model f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
data alu summary 3 - 20 data arithmetic logic unit motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola address generation unit 4 - 1 section 4 address generation unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents 4 - 2 address generation unit motorola section 4.1 address generation unit and addressing modes ....3 section 4.2 agu architecture ..................................................................3 4.2.1 address register files (rn) ................................................................3 4.2.2 offset register files (nn) ....................................................................4 4.2.3 modifier register files (mn) ................................................................5 4.2.4 address alu .......................................................................................5 4.2.5 address output multiplexers ...............................................................6 section 4.3 programming model .............................................................6 4.3.1 address register files (r0 - r3 and r4 - r7) ....................................7 4.3.2 offset register files (n0 - n3 and n4 - n7) .......................................7 4.3.3 modifier register files (m0 - m3 and m4 - m7) ...................................8 section 4.4 addressing ...............................................................................8 4.4.1 address register indirect modes ........................................................9 4.4.1.1 no update ................................................................................... 9 4.4.1.2 postincrement by 1 ..................................................................... 9 4.4.1.3 postdecrement by 1 ................................................................... 9 4.4.1.4 postincrement by offset nn ....................................................... 10 4.4.1.5 postdecrement by offset nn ...................................................... 11 4.4.1.6 indexed by offset nn .................................................................. 12 4.4.1.7 predecrement by 1 ..................................................................... 13 4.4.2 address modifier arithmetic types .....................................................14 4.4.2.1 linear modifier (mn=$ffff) ....................................................... 16 4.4.2.2 modulo modifier .......................................................................... 18 4.4.2.3 reverse-carry modifier (mn=$0000) .......................................... 22 4.4.2.4 address-modifier-type encoding summary ............................... 25 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
address generation unit and addressing modes motorola address generation unit 4 - 3 4.1 address generation unit and addressing modes this section contains three major subsections. the first subsection describes the hard- ware architecture of the address generation unit (agu), the second subsection describes the programming model, and the third subsection describes the addressing modes, explaining how the rn, nn, and mn registers work together to form a memory address. 4.2 agu architecture the agu is shown in the dsp56k block diagram in figure 4-1. it uses integer arithmetic to perform the effective address calculations necessary to address data operands in memory, and contains the registers used to generate the addresses. it implements lin- ear, modulo, and reverse-carry arithmetic, and operates in parallel with other chip resources to minimize address-generation overhead. the agu is divided into two identical halves, each of which has an address arithmetic logic unit (alu) and four sets of three registers (see figure 4-2). they are the address registers (r0 - r3 and r4 - r7), offset registers (n0 - n3 and n4 - n7), and the modifier registers (m0 - m3 and m4 - m7). the eight rn, nn, and mn registers are treated as reg- ister triplets ? e.g., only n2 and m2 can be used to update r2. the eight triplets are r0:n0:m0, r1:n1:m1, r2:n2:m2, r3:n3:m3, r4:n4:m4, r5:n5:m5, r6:n6:m6, and r7:n7:m7. the two arithmetic units can generate two 16-bit addresses every instruction cycle ? one for any two of the xab, yab, or pab. the agu can directly address 65,536 locations on the xab, 65,536 locations on the yab, and 65,536 locations on the pab. the two inde- pendent address alus work with the two data memories to feed the data alu two operands in a single cycle. each operand may be addressed by an rn, nn, and mn triplet. 4.2.1 address register files (rn) each of the two address register files (see figure 4-2) consists of four 16-bit registers. the two files contain address registers r0 - r3 and r4 - r7, which usually contain addresses used as pointers to memory. each register may be read or written by the global data bus (gdb). when read by the gdb, 16-bit registers are written into the two least significant bytes of the gbd, and the most significant byte is set to zero. when written from the gbd, only the two least significant bytes are written, and the most significant byte is truncated. each address register can be used as input to its associated address alu for a register update calculation. each register can also be written by the output of its respective ad- dress alu. one rn register from the low address alu and one rn register from the high address alu can be accessed in a single instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
agu architecture 4 - 4 address generation unit motorola 4.2.2 offset register files (nn) each of two offset register files shown in figure 4-2 consists of four 16-bit registers. the two files contain offset registers n0 - n3 and n4 - n7, which contain either data or offset values used to update address pointers. each offset register can be read or written by the clock generator peripheral pins internal data bus switch program ram/rom expansion program interrupt controller program decode controller program address generator ya b xab pa b ydb xdb pdb gdb modc/nmi modb/irqb reset data alu 24x24 + 56 ? 56-bit mac two 56-bit accumulators external address bus switch bus control external data b u s switch address data 16 bits 24 bits port a moda/irqa pll x memory ram/rom expansion y memory ram/rom expansion address generation unit oncea peripheral modules expansion area control 24-bit 56k module figure 4-1 dsp56k block diagram program control unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
agu architecture motorola address generation unit 4 - 5 gdb. when read by the gdb, the contents of a register are placed in the two least signif- icant bytes, and the most significant byte on the gdb is zero extended. when a register is written, only the least significant 16 bits of the gdb are used; the upper portion is truncated. 4.2.3 modifier register files (mn) each of the two modifier register files shown in figure 4-2 consists of four 16-bit registers. the two files contain modifier registers m0 - m3 and m4 - m7, which specify the type of arithmetic used during address register update calculations or contain data. each modifier register can be read or written by the gdb. when read by the gdb, the contents of a reg- ister are placed in the two least significant bytes, and the most significant byte on the gdb is zero extended. when a register is written, only the least significant 16 bits of the gdb are used; the upper portion is truncated. each modifier register is preset to $ffff during a processor reset. 4.2.4 address alu the two address alus are identical (see figure 4-2) in that each contains a 16-bit full adder (called an offset adder), which can add 1) plus one, 2) minus one, 3) the contents of the respective offset register n, or 4) the twos complement of n to the contents of the global data bus n0 n1 n2 n3 m3 m2 m1 m0 address alu address alu r0 r1 r2 r3 r7 r6 r5 r4 m4 m5 m6 m7 n7 n6 n5 n4 triple multiplexer low address alu high address alu xab ya b pa b 16 bits 24 bits figure 4-2 agu block diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model 4 - 6 address generation unit motorola selected address register. a second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value, m or minus m, where m-1 is stored in the respective modifier register. a third full adder (called a reverse-carry adder) can add 1) plus one, 2) minus one, 3) the offset n (stored in the respective offset register), or 4) minus n to the selected address register with the carry propagating in the reverse direction ? i.e., from the most significant bit (msb) to the least significant bit (lsb). the offset adder and the reverse-carry adder are in parallel and share common inputs. the only difference between them is that the carry propagates in opposite directions. test logic determines which of the three summed results of the full adders is output. each address alu can update one address register, rn, from its respective address reg- ister file during one instruction cycle and can perform linear, reverse-carry, and modulo arithmetic. the contents of the selected modifier register specify the type of arithmetic to be used in an address register update calculation. the modifier value is decoded in the address alu. the output of the offset adder gives the result of linear arithmetic (e.g., rn 1; rn n) and is selected as the modulo arithmetic unit output for linear arithmetic addressing mod- ifiers. the reverse-carry adder performs the required operation for reverse-carry arithmetic and its result is selected as the address alu output for reverse-carry address- ing modifiers. reverse-carry arithmetic is useful for 2 k -point fast fourier transform (fft) addressing. for modulo arithmetic, the modulo arithmetic unit will perform the function (rn n) modulo m, where n can be one, minus one, or the contents of the offset register nn. if the modulo operation requires wraparound for modulo arithmetic, the summed out- put of the modulo adder gives the correct updated address register value; if wraparound is not necessary, the output of the offset adder gives the correct result. 4.2.5 address output multiplexers the address output multiplexers (see figure 4-2) select the source for the xab, yab, and pab. these multiplexers allow the xab, yab, or pab outputs to originate from r0 - r3 or r4 - r7. 4.3 programming model the programmer?s view of the agu is eight sets of three registers (see figure 4-3). these registers can act as temporary data registers and indirect memory pointers. automatic up- dating is available when using address register indirect addressing. the mn registers can be programmed for linear addressing, modulo addressing, and bit-reverse addressing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model motorola address generation unit 4 - 7 4.3.1 address register files (r0 - r3 and r4 - r7) the eight 16-bit address registers, r0 - r7, can contain addresses or general-purpose data. the 16-bit address in a selected address register is used in the calculation of the effective address of an operand. when supporting parallel x and y data memory moves, the address registers must be thought of as two separate files, r0 - r3 and r4 - r7. the contents of an rn may point directly to data or may be offset. in addition, rn can be pre- updated or post-updated according to the addressing mode selected. if an rn is updated, modifier registers, mn, are always used to specify the type of update arithmetic. offset registers, nn, are used for the update-by-offset addressing modes. the address register modification is performed by one of the two modulo arithmetic units. most addressing modes modify the selected address register in a read-modify-write fashion; the address register is read, its contents are modified by the associated modulo arithmetic unit, and the register is written with the appropriate output of the modulo arithmetic unit. the form of address register modification performed by the modulo arithmetic unit is controlled by the contents of the offset and modifier registers discussed in the following paragraphs. ad- dress registers are not affected by a processor reset. 4.3.2 offset register files (n0 - n3 and n4 - n7) the eight 16-bit offset registers, n0 - n7, can contain offset values used to increment/dec- rement address registers in address register update calculations or can be used for 16-bit general-purpose storage. for example, the contents of an offset register can be used to step through a table at some rate (e.g., five locations per step for waveform generation), or the contents can specify the offset into a table or the base of the table for indexed ad- dressing. each address register, rn, has its own offset register, nn, associated with it. * r7 r6 r5 r4 r3 r2 r1 r0 * * * * * * * 23 16 15 0 n7 n6 n5 n4 n3 n2 n1 n0 23 16 15 0 offset registers m7 m6 m5 m4 m3 m2 m1 m0 23 16 15 0 modifier registers upper file lower file address registers * * * * * * * * * * * * * * * * * written as don?t care; read as zero figure 4-3 agu programming model f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing 4 - 8 address generation unit motorola offset registers are not affected by a processor reset. 4.3.3 modifier register files (m0 - m3 and m4 - m7) the eight 16-bit modifier registers, m0 - m7, define the type of address arithmetic to be performed for addressing mode calculations, or they can be used for general-purpose storage. the address alu supports linear, modulo, and reverse-carry arithmetic types for all address register indirect addressing modes. for modulo arithmetic, the contents of mn also specify the modulus. each address register, rn, has its own modifier register, mn, associated with it. each modifier register is set to $ffff on processor reset, which spec- ifies linear arithmetic as the default type for address register update calculations. 4.4 addressing the dsp56k provides three different addressing modes: register direct, address register indirect, and special. since the register direct and special addressing modes do not nec- essarily use the agu registers, they are described in section 6 - instruction set introduction. the address register indirect addressing modes use the registers in address register indirect uses mn moditer operand reference assembler syntax scdapxyl xy no update no xxxx x (rn) postincrement by 1 yes xxxx x (rn)+ postdecrement by 1 yes xxxx x (rn)e postincrement by offset nn yes xxxx x (rn)+nn note: s = system stack reference c = program control unit register reference d = data alu register reference a = address alu register reference p = program memory reference x = x memory reference y = y memory reference l = l memory reference xy = xy memory reference table 4-1 address register indirect summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing motorola address generation unit 4 - 9 the agu and are described in the following paragraphs. 4.4.1 address register indirect modes when an address register is used to point to a memory location, the addressing mode is called address register indirect (see table 4-1). the term indirect is used because the register contents are not the operand itself, but rather the address of the operand. these addressing modes specify that an operand is in memory and specify the effective address of that operand. a portion of the data bus movement field in the instruction specifies the memory space to be referenced. the contents of specific agu registers that determine the effective address are modified by arithmetic operations performed in the agu. the type of address arithmetic used is specified by the address modifier register, mn. the offset reg- ister, nn, is only used when the update specifies an offset. not all possible combinations are available, such as + (rn). the 24-bit instruction word size is not large enough to allow a completely orthogonal instruction set for all instruc- tions used by the dsp. an example and description of each mode is given in the following paragraphs. sec- tion 6 - instruction set introduction and appendix a - instruction set details give a complete description of the instruction syntax used in these examples. in particular, xy: memory references refer to instructions in which an operand in x mem- ory and an operand in y memory are referenced in the same instruction. 4.4.1.1 no update the address of the operand is in the address register, rn (see table 4-1). the contents of the rn register are unchanged by executing the instruction. figure 4-4 shows a move instruction using address register indirect addressing with no update. this mode can be used for making xy: memory references. this mode does not use nn or mn registers. 4.4.1.2 postincrement by 1 the address of the operand is in the address register, rn (see table 4-1 and figure 4-5). after the operand address is used, it is incremented by 1 and stored in the same address register. this mode can be used for making xy: memory references and for modifying the contents of rn without an associated data move. 4.4.1.3 postdecrement by 1 the address of the operand is in the address register, rn (see table 4-1 and figure 4-6). after the operand address is used, it is decremented by 1 and stored in the same address register. this mode can be used for making xy: memory references and for f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing 4 - 10 address generation unit motorola modifying the contents of rn without an associated data move. 4.4.1.4 postincrement by offset nn the address of the operand is in the address register, rn (see table 4-1 and figure 4-7). after the operand address is used, it is incremented by the contents of the nn register and stored in the same address register. the contents of the nn register are unchanged. this mode can be used for making xy: memory references and for modifying the contents of x memory 23 0 0123456789abcd 15 0 15 0 15 0 example: move a1,x: (r0) before execution after execution a2 a1 a0 55 48 47 24 23 0 7 0 23 0 23 0 x memory 23 0 xxxxxx $1000 $1000 a2 a1 a0 0 123 4567 89abcd 55 48 47 24 23 0 7 0 23 0 23 0 $1000 xxxx $ffff r0 n0 m0 15 0 15 0 15 0 $1000 xxxx $ffff r0 n0 m0 assembler syntax: (rn) memory spaces: p:, x:, y:, xy:, l: additional instruction execution time (clocks): 0 additional effective address words: 0 $234 5 6 7 figure 4-4 address register indirect ? no update f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing motorola address generation unit 4 - 11 rn without an associated data move. 4.4.1.5 postdecrement by offset nn the address of the operand is in the address register, rn (see table 4-1 and figure 4-8). after the operand address is used, it is decremented by the contents of the nn register and stored in the same address register. the contents of the nn register are unchanged. this mode cannot be used for making xy: memory references, but it can be used to mod- af654321fedcba 15 0 15 0 15 0 example: move b0,y: (r1)+ before execution after execution b2 b1 b0 55 48 47 24 23 0 7 0 23 0 23 0 y memory 23 0 xxxxxx $2500 y memory 23 0 $2500 $2500 xxxx $ffff r1 n1 m1 15 0 15 0 15 0 $2501 xxxx $ffff r1 n1 m1 assembler syntax: (rn)+ memory spaces: p:, x:, y:, xy:, l: additional instruction execution time (clocks): 0 additional effective address words: 0 $fedcba af654321fedcba b2 b1 b0 55 48 47 24 23 0 7 0 23 0 23 0 xxxxxx $2501 xxxxx xx $2501 figure 4-5 address register indirect ? postincrement f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing 4 - 12 address generation unit motorola ify the contents of rn without an associated data move. 4.4.1.6 indexed by offset nn the address of the operand is the sum of the contents of the address register, rn, and the contents of the address offset register, nn (see table 4-1 and figure 4-9). the con- tents of the rn and nn registers are unchanged. this addressing mode, which requires 12 3 1 2 3 45 6 4 56 15 0 15 0 15 0 example: move y0,y: (r3)- before execution after execution y1 y0 47 24 23 0 23 0 23 0 y memory 23 0 xxxxxx $4734 y memory 23 0 $4734 $4735 xxxx $ffff r3 n3 m3 15 0 15 0 15 0 $4734 xxxx $ffff r3 n3 m3 assembler syntax: (rn)e memory spaces: p:, x:, y:, xy:, l: additional instruction execution time (clocks): 0 additional effective address words: 0 xxxxxx $4735 $4735 12 3 1 23 4 5 6 4 56 y1 y0 47 24 23 0 23 0 23 0 456456 xxxxxx figure 4-6 address register indirect ? postdecrement f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing motorola address generation unit 4 - 13 an extra instruction cycle, cannot be used for making xy: memory references. 4.4.1.7 predecrement by 1 the address of the operand is the contents of the address register, rn, decremented by 1 before the operand address is used (see table 4-1 and figure 4-10). the contents of rn are decremented and stored in the same address register. this addressing mode re- quires an extra instruction cycle. this mode cannot be used for making xy: memory references, nor can it be used for modifying the contents of rn without an associated data a5 b4 c 6 00 000 1 15 0 15 0 15 0 example: move x1,x: (r2)+n2 before execution after execution x1 x0 47 24 23 0 23 0 23 0 x memory 23 0 xxxxxx $3200 x memory 23 0 $3200 $3200 $ffff r2 n2 m2 15 0 15 0 15 0 $3204 $ffff r2 n2 m2 assembler syntax: (rn)+nn memory spaces: p:, x:, y:, xy:, l: additional instruction execution time (clocks): 0 additional effective address words: 0 xxxxxx $3204 $3204 xxxxxx a5b4c6 000001 x1 x0 47 24 23 0 23 0 23 0 $0004 $0004 $a5 b 4 c6 figure 4-7 address register indirect ? postincrement by offset nn f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing 4 - 14 address generation unit motorola move. 4.4.2 address modifier arithmetic types the address alu supports linear, modulo, and reverse-carry arithmetic for all address register indirect modes. these arithmetic types easily allow the creation of data structures in memory for fifos (queues), delay lines, circular buffers, stacks, and bit-reversed fft buffers. 0 f74105 a 3fa6 b0 15 0 15 0 15 0 example: move x:(r4)en4,a0 before execution after execution a2 a1 a0 55 48 47 24 23 0 7 0 23 0 23 0 x memory 23 0 xxxxxx $7703 $7706 $ffff r4 n4 m4 assembler syntax: (rn)enn memory spaces: p:, x:, y:, l: additional instruction execution time (clocks): 0 additional effective address words: 0 $7706 0f74105a505050 a2 a1 a0 55 48 47 24 23 0 7 0 23 0 23 0 $50 5 05 0 $0003 15 0 15 0 15 0 x memory 23 0 xxxxxx $7703 $7703 $ffff r4 n4 m4 $7706 $505050 $0003 figure 4-8 address register indirect ? postdecrement by offset nn f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing motorola address generation unit 4 - 15 the contents of the address modifier register, mn, defines the type of arithmetic to be per- formed for addressing mode calculations. for modulo arithmetic, the contents of mn also specifies the modulus, or the size of the memory buffer whose addresses will be refer- enced. see table 4-2 for a summary of the address modifiers implemented on the + 62100 9ba4c22 15 0 15 0 15 0 example: move y1,x: (r6+n6) before execution after execution y1 y0 47 24 23 0 23 0 23 0 x memory 23 0 xxxxxx $6000 x memory 23 0 $6000 $6000 $ffff r6 n6 m6 15 0 15 0 15 0 $6000 $ffff r6 n6 m6 assembler syntax: (rn+nn) memory spaces: p:, x:, y:, l: additional instruction execution time (clocks): 2 additional effective address words: 0 xxxxxx $6004 $6004 xxxxxx 62 10 0 9 b a 4 c2 2 y1 y0 47 24 23 0 23 0 23 0 $0004 $0004 $621009 figure 4-9 address register indirect ? indexed by offset nn f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing 4 - 16 address generation unit motorola dsp56k. the mmmm column indicates the hex value which should be stored in the mn register. 4.4.2.1 linear modifier (mn=$ffff) when the value in the modifier register is $ffff, address modification is performed using normal 16-bit linear arithmetic (see table 4-2). a 16-bit offset, nn, and + 1 or e1 can be used in the address calculations. the range of values can be considered as signed (nn from e32,768 to + 32,767) or unsigned (nn from 0 to + 65,535) since there is no arithmetic 15 0 15 0 15 0 example: move x: e(r5),b1 before execution after execution b2 b1 b0 55 48 47 24 23 0 7 0 23 0 23 0 x memory 23 0 $3006 $3007 $ffff r5 n5 m5 assembler syntax: ern memory spaces: p:, x:, y:, l: additional instruction execution time (clocks): 2 additional effective address words: 0 $3007 3 b 123 4 5 6a554c 0 b2 b1 b0 55 48 47 24 23 0 7 0 23 0 23 0 xxxx 15 0 15 0 15 0 x memory 23 0 $3006 $3006 $ffff r5 n5 m5 $3007 $abcdef xxxx $123456 $abcdef $123456 3bb62d04a 554c0 figure 4-10 address register indirect ? predecrement f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing motorola address generation unit 4 - 17 difference between these two data representations. addresses are normally considered unsigned, and data is normally considered signed. 4.4.2.2 modulo modifier when the value in the modifier register falls into one of two ranges (mn=$0001 to $7fff or mn= $8001 to $bfff with the reserved gaps noted in the table), address modification is performed using modulo arithmetic (see table 4-2). modulo arithmetic normally causes the address register value to remain within an address range of size m, whose lower boundary is determined by rn. the upper boundary is de- termined by the modulus, or m. the modulus value, in turn, is determined by mn, the value in the modifier register (see figure 4-11). there are certain cases where modulo arithmetic addressing conditions may cause the address register to jump linearly to the same relative address in a different buffer. other cases firmly restrict the address register to the same buffer, causing the address register to wrap around within the buffer. the range in which the value contained in the modifier register falls determines how the processor will handle modulo addressing. 4.4.2.2.1 mn=$0001 to $7fff in this range, the modulus (m) equals the value in the modifier register (mn) plus 1. the memory buffer?s lower boundary (base address) value, determined by rn, must have ze- ros in the k lsbs, where 2 k 3 m, and therefore must be a multiple of 2 k . the upper boundary is the lower boundary plus the modulo size minus one (base address plus me 1). since m 2 k , once m is chosen, a sequential series of memory blocks (each of length 2 k ) is created where these circular buffers can be located. if m<2 k , there will be a space between sequential circular buffers of (2 k )em. for example, to create a circular buffer of 21 stages, m is 21, and the lower address boundary must have its five lsbs equal to zero (2 k 3 21, thus k 3 5). the mn register is loaded with the value 20. the lower boundary may be chosen as 0, 32, 64, 96, 128, 160, etc. the upper boundary of the buffer is then the lower boundary plus 21. there will be an unused space of 11 memory locations between the upper address and next usable lower address. the address pointer is not required to start at the lower address boundary or to end on the upper address boundary; it can initially point anywhere within the defined mod- ulo address range. neither the lower nor the upper boundary of the modulo region is stored; only the size of the modulo region is stored in mn. the boundaries are determined by the contents of rn. assuming the (rn)+ indirect addressing mode, if the address reg- ister pointer increments past the upper boundary of the buffer (base address plus me1), it will wrap around through the base address (lower boundary). alternatively, assuming the (rn)- indirect addressing mode, if the address decrements past the lower boundary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing 4 - 18 address generation unit motorola mmmm addressing mode arithmetic 0000 reverse carry (bit reverse) 0001 modulo 2 0002 modulo 3 :: 7ffe modulo 32767 7fff modulo 32768 8000 reserved 8001 multiple wrap-around modulo 2 8002 reserved 8003 multiple wrap-around modulo 4 : reserved 8007 multiple wrap-around modulo 8 : reserved 800f multiple wrap-around modulo 2 4 : reserved 801f multiple wrap-around modulo 2 5 : reserved 803f multiple wrap-around modulo 2 6 : reserved 807f multiple wrap-around modulo 2 7 : reserved 80ff multiple wrap-around modulo 2 8 : reserved 81ff multiple wrap-around modulo 2 9 : reserved 83ff multiple wrap-around modulo 2 10 : reserved 87ff multiple wrap-around modulo 2 11 : reserved 8fff multiple wrap-around modulo 2 12 : reserved 9fff multiple wrap-around modulo 2 13 : reserved bfff multiple wrap-around modulo 2 14 : reserved ffff linear (modulo 2 15 ) table 4-2 address modifier summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing motorola address generation unit 4 - 19 (base address), it will wrap around through the base address plus me1 (upper boundary). if an offset (nn) is used in the address calculations, the 16-bit absolute value, |nn|, must be less than or equal to m for proper modulo addressing in this range. if nn>m, the result is data dependent and unpredictable, except for the special case where nn=p x 2 k , a mul- tiple of the block size where p is a positive integer. for this special case, when using the (rn)+ nn addressing mode, the pointer, rn, will jump linearly to the same relative address in a new buffer, which is p blocks forward in memory (see figure 4-12). similarly, for (rn)enn, the pointer will jump p blocks backward in memory. this technique is useful in sequentially processing multiple tables or n-dimensional arrays. the range of values for nn is e32,768 to + 32,767. the modulo arithmetic unit will automatically wrap around the address pointer by the required amount. this type of address modification is useful for creating circular buffers for fifos (queues), delay lines, and sample buffers up to 32,768 words long as well as for decimation, interpolation, and waveform generation. the special case of (rn) nn mod m with nn=p x 2 k is useful for performing the same algorithm on multiple blocks of data in memory ? e.g., parallel infinite impulse response (iir) filtering. an example of address register indirect modulo addressing is shown in figure 4-13. start- ing at location 64, a circular buffer of 21 stages is created. the addresses generated are offset by 15 locations. the lower boundary = l x (2 k ) where 2 k 3 21; therefore, k=5 and the lower address boundary must be a multiple of 32. the lower boundary may be chosen circular buffer address pointer m = modulus upper boundary lower boundary figure 4-11 circular buffer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing 4 - 20 address generation unit motorola as 0, 32, 64, 96, 128, 160, etc. for this example, l is arbitrarily chosen to be 2, making the lower boundary 64. the upper boundary of the buffer is then 84 (the lower boundary plus 20 (me1)). the mn register is loaded with the value 20 (me1). the offset register is arbitrarily chosen to be 15 (nn m). the address pointer is not required to start at the lower address boundary and can begin anywhere within the defined modulo address range ? i.e., within the lower boundary + (2 k ) address region. the address pointer, rn, is arbitrarily chosen to be 75 in this example. when r2 is post-incremented by the offset by the move instruction, instead of pointing to 90 (as it would in the linear mode) it wraps around to 69. if the address register pointer increments past the upper boundary of the buffer (base ad- dress plus me1), it will wrap around to the base address. if the address decrements past the lower boundary (base address), it will wrap around to the base address plus me1. if rn is outside the valid modulo buffer range and an operation occurs that causes rn to be updated, the contents of rn will be updated according to modulo arithmetic rules. for example, a move b0,x:(r0)+ n0 instruction (where r0=6, m0=5, and n0=0) would ap- parently leave r0 unchanged since n0=0. however, since r0 is above the upper boundary, the agu calculates r0+ n0em0e1 for the new contents of r0 and sets r0=0. (rn) nn mod m where nn = 2 k (i.e., p = 1) m m 2 k 2 k figure 4-12 linear addressing with a modulo modifier f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing motorola address generation unit 4 - 21 the move instruction in figure 4-13 takes the contents of the x0 register and moves it to a location in the x memory pointed to by (r2), and then (r2) is updated modulo 21. the new value of r2 is not 90 (75+ 15), which would be the case if linear arithmetic had been used, but rather is 69 since modulo arithmetic was used. 4.4.2.2.2 mn=$8001 to $bfff in this range, the modulo (m) equals (mn+1)-$8000, where mn is the value in the modi- fier register (see table 4-2). this range firmly restricts the address register to the same buffer, causing the address register to wrap around within the buffer. this multiple wrap- around addressing feature reduces argument overhead and is useful for decimation, interpolation, and waveform generation. the address modification is performed modulo m, where m may be any power of 2 in the range from 2 1 to 2 14 . modulo m arithmetic causes the address register value to remain within an address range of size m defined by a lower and upper address boundary. the value m-1 is stored in the modifier register mn least significant 14 bits while the two most significant bits are set to ?10?. the lower boundary (base address) value must have zeroes in the k lsbs, where 2 k = m, and therefore must be a multiple of 2 k . the upper boundary is the lower boundary plus the modulo size minus one (base address plus m-1). 0..010 00000 xd bus (84) r2 (69) (75) (90) let: m2 n2 r2 example: move x0,x:(r2)+n 00.....0010100 00.....0001111 00.....1001011 modulus=21 offset=15 pointer=75 n2 + (64) 21 x0 k=5 figure 4-13 modulo modifier example f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing 4 - 22 address generation unit motorola for example, to create a circular buffer of 32 stages, m is chosen as 32 and the lower ad- dress boundary must have its 5 least significant bits equal to zero (2 k = 32, thus k = 5). the mn register is loaded with the value $801f. the lower boundary may be chosen as 0, 32, 64, 96, 128, 160, etc. the upper boundary of the buffer is then the lower boundary plus 31. the address pointer is not required to start at the lower address boundary and may begin anywhere within the defined modulo address range (between the lower and upper bound- aries). if the address register pointer increments past the upper boundary of the buffer (base address plus m-1) it will wrap around to the base address. if the address decre- ments past the lower boundary (base address) it will wrap around to the base address plus m-1. if an offset nn is used in the address calculations, it is not required to be less than or equal to m for proper modulo addressing since multiple wrap around is supported for (rn)+nn, (rn)-nn and (rn+nn) address updates (multiple wrap-around cannot occur with (rn)+, (rn)- and -(rn) addressing modes). the multiple wrap-around address modifier is useful for decimation, interpolation and waveform generation since the multiple wrap-around capability may be used for argument reduction. 4.4.2.3 reverse-carry modifier (mn=$0000) reverse carry is selected by setting the modifier register to zero (see table 4-2). the ad- dress modification is performed in hardware by propagating the carry in the reverse direction ? i.e., from the msb to the lsb. reverse carry is equivalent to bit reversing the contents of rn (i.e., redefining the msb as the lsb, the next msb as bit 1, etc.) and the offset value, nn, adding normally, and then bit reversing the result. if the + nn addressing mode is used with this address modifier and nn contains the value 2 (ke1) (a power of two), this addressing modifier is equivalent to bit reversing the k lsbs of rn, incrementing rn by 1, and bit reversing the k lsbs of rn again. this address modification is useful for ad- dressing the twiddle factors in 2k-point fft addressing and to unscramble 2 k -point fft data. the range of values for nn is 0 to + 32k (i.e., nn=2 15 ), which allows bit-reverse ad- dressing for ffts up to 65,536 points. to make bit-reverse addressing work correctly for a 2 k point fft, the following proce- dures must be used: 1. set mn=0; this selects reverse-carry arithmetic. 2. set nn=2 (ke1) . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing motorola address generation unit 4 - 23 3. set rn between the lower boundary and upper boundary in the buffer mem- ory. the lower boundary is l x (2 k ), where l is an arbitrary whole number. this boundary gives a 16-bit binary number xx . . . xx00 . . . 00, where xx . . . xx=l and 00 . . . 00 equals k zeros. the upper boundary is l x (2 k )+ ((2 k )e1). this boundary gives a 16-bit binary number xx . . . xx11 . . . 11, where xx . . . xx=l and 11 . . . 11 equals k ones. 4. use the (rn)+ nn addressing mode. as an example, consider a 1024-point fft with real data stored in the x memory and imaginary data stored in the y memory. since 1,024=2 10 , k=10. the modifier register (mn) is zero to select bit-reverse addressing. offset register (nn) contains the value 512 (2 (ke 1) ), and the pointer register (rn) contains 3,072 (l x (2 k )=3 x (2 10 )), which is the lower boundary of the memory buffer that holds the results of the fft. the upper boundary is 4,095 (lower boundary + (2 k )e1=3,072+ 1,023). postincrementing by + n generates the address sequence (0, 512, 256, 768, 128, 640,...), which is added to the lower boundary. this sequence (0, 512, etc.) is the scrambled fft data order for sequential frequency points from 0 to 2 p . table 4-3 shows the successive contents of rn when using (rn)+ nn updates. the reverse-carry modifier only works when the base address of the fft data buffer is a multiple of 2 k , such as 1,024, 2,048, 3,072, etc. the use of addressing modes other than postincrement by + nn is possible but may not provide a useful result. rn contents offset from lower boundary 3072 0 3584 512 3328 256 3840 768 3200 128 3712 640 table 4-3 bit-reverse addressing sequence example f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing 4 - 24 address generation unit motorola the term bit reverse with respect to reverse-carry arithmetic is descriptive. the lower boundary that must be used for the bit-reverse address scheme to work is l x (2 k ). in the previous example shown in table 4-3, l=3 and k=10. the first address used is the lower boundary (3072); the calculation of the next address is shown in figure 4-14. the k lsbs of the current contents of rn (3,072) are swapped: bits 0 and 9 are swapped. bits 1 and 8 are swapped. bits 2 and 7 are swapped. bits 3 and 6 are swapped. bits 4 and 5 are swapped. the result is incremented (3,073), and then the k lsbs are swapped again: bits 0 and 9 are swapped. bits 1 and 8 are swapped. bits 2 and 7 are swapped. bits 3 and 6 are swapped. bits 4 and 5 are swapped. the result is rn equals 3,584. l k bits each update, (rn)+nn, is equivalent to: 1. bit reversing: rn=000011 0000000000=3072 0000000000 2. increment rn by 1: rn=000011 0000000000 +1 000011 0000000001 3. bit reversing again: rn=000011 0000000001 1000000000 000011 1000000000=3584 figure 4-14 bit-reverse address calculation example f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing motorola address generation unit 4 - 25 4.4.2.4 address-modifier-type encoding summary there are three address modifier types: linear addressing reverse-carry addressing modulo addressing bit-reverse addressing is useful for 2 k -point fft addressing. modulo addressing is useful for creating circular buffers for fifos (queues), delay lines, and sample buffers up to 32,768 words long. the linear addressing is useful for general-purpose addressing. there is a reserved set of modifier values (from 32,768 to 65,534) that should not be used. figure 4-15 gives examples of the three addressing modifiers using 8-bit registers for sim- plification (all agu registers are 16 bit). the addressing mode used in the example, postincrement by offset nn, adds the contents of the offset register to the contents of the address register after the address register is accessed. the results of the three examples are as follows: the linear address modifier addresses every fifth location since the offset register contains $5. using the bit-reverse address modifier causes the postincrement by offset nn addressing mode to use the address register, bit reverse the four lsbs, increment by 1, and bit reverse the four lsbs again. the modulo address modifier has a lower boundary at a predetermined location, and the modulo number plus the lower boundary establishes the upper boundary. this boundary creates a circular buffer so that, if the address register is pointing within the boundaries, addressing past a boundary causes a circular wraparound to the other boundary. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing 4 - 26 address generation unit motorola linear address modifier m0 = 255 = 11111111 for linear addressing with r0 original registers: n0 = 5, r0 = 75 = 0100 1011 postincrement by offset n0: r0 = 80 = 0101 0000 postincrement by offset n0: r0 = 85 = 0101 0101 postincrement by offset n0: r0 = 90 = 0101 1010 modulo address modifier m0 = 19 = 0001 0011 for modulo 20 addressing with r0 original registers: n0 = 5, r0 = 75 = 0100 1011 postincrement by offset n0: r0 = 80 = 0101 0000 postincrement by offset n0: r0 = 65 = 0100 0001 postincrement by offset n0: r0 = 70 = 0100 0110 reverse-carry address modifier m0 = 0= 0000 0000 for reverse-carry addressing with r0 original registers: n0 = 8, r0 = 64 = 0100 0000 postincrement by offset n0: r0 = 72 = 0100 1000 postincrement by offset n0: r0 = 68 = 0100 0100 postincrement by offset n0: r0 = 76 = 0100 1100 75 80 85 90 r0 65 70 75 80 r0 64 83 upper boundary lower boundary 64 68 72 76 r0 figure 4-15 address modifier summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola program control unit 5 - 1 section 5 program control unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents 5 - 2 program control unit motorola section 5.1 program control unit .................................................... 3 section 5.2 overview ................................................................................ 3 section 5.3 program control unit (pcu) architecture ............ 5 5.3.1 program decode controller ................................................................ 5 5.3.2 program address generator (pag) ................................................... 5 5.3.3 program interrupt controller ............................................................... 6 5.3.4 instruction pipeline format ................................................................. 6 section 5.4 programming model ......................................................... 8 5.4.1 program counter ................................................................................ 8 5.4.2 status register ................................................................................... 9 5.4.2.1 carry (bit 0) .................................................................................10 5.4.2.2 overflow (bit 1) ...........................................................................10 5.4.2.3 zero (bit 2) ..................................................................................10 5.4.2.4 negative (bit 3) ...........................................................................10 5.4.2.5 unnormalized (bit 4) ...................................................................10 5.4.2.6 extension (bit 5) ..........................................................................11 5.4.2.7 limit (bit 6) ..................................................................................11 5.4.2.8 scaling bit (bit 7) .........................................................................11 5.4.2.9 interrupt masks (bits 8 and 9) .....................................................12 5.4.2.10 scaling mode (bits 10 and 11) ..................................................12 5.4.2.11 reserved status (bit 12) ...........................................................13 5.4.2.12 trace mode (bit 13) ..................................................................13 5.4.2.13 double precision multiply mode (bit 14) ...................................13 5.4.2.14 loop flag (bit 15) ......................................................................13 5.4.3 operating mode register ................................................................... 14 5.4.4 system stack ...................................................................................... 14 5.4.5 stack pointer register ........................................................................ 15 5.4.5.1 stack pointer (bits 0e3) ..............................................................16 5.4.5.2 stack error flag (bit 4) ................................................................16 5.4.5.3 underflow flag (bit 5) .................................................................16 5.4.5.4 reserved stack pointer registration (bits 6e23) ........................17 5.4.6 loop address register ....................................................................... 17 5.4.7 loop counter register ....................................................................... 17 5.4.8 programming model summary ........................................................... 17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
program control unit motorola program control unit 5 - 3 5.1 program control unit this section describes the hardware of the program control unit (pcu) and concludes with a description of the programming model. the instruction pipeline description is also included since understanding the pipeline is particularly important in understanding the dsp56k family of processors. 5.2 overview the program control unit is one of the three execution units in the central processing module (see figure 5-2). it performs program address generation (instruction prefetch), instruction decoding, hardware do loop control, and exception (interrupt) processing. the programmer sees the program control unit as six registers and a hardware system stack (ss) as shown in figure 5-1. in addition to the standard program flow-control resources, such as a program counter (pc), complete status register (sr), and ss, the program control unit features registers (loop address (la) and loop counter (lc)) dedi- cated to supporting the hardware do loop instruction. the ss is a 15-level by 32-bit separate internal memory which stores the pc and sr for subroutine calls, long interrupts, and program looping. the ss also stores the lc and la registers. each location in the ss is addressable as a 16-bit register, system stack high (ssh) and system stack low (ssl). the stack pointer (sp) points to the ss locations. 32 x 15 stack omr pc la lc sp sr clock interrupts control pa b pdb 16 24 24 24 global data bus figure 5-1 program address generator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview 5 - 4 program control unit motorola all of the pcu registers are read/write to facilitate system debugging. although none of the registers are 24 bits, they are read or written over 24-bit buses. when they are read, the least significant bits (lsbs) are significant, and the most significant bits (msbs) are zeroed as appropriate. when they are written, only the appropriate lsbs are significant, and the msbs are written as don?t care. clock generator peripheral pins internal data bus switch program ram/rom expansion program interrupt controller program decode controller program address generator ya b xab pa b ydb xdb pdb gdb modc/nmi modb/irqb reset data alu 24x24 + 56 ? 56-bit mac two 56-bit accumulators external address bus switch bus control external data b u s switch address data 16 bits 24 bits port a moda/irqa pll x memory ram/rom expansion y memory ram/rom expansion address generation unit oncea peripheral modules expansion area control 24-bit 56k mod- figure 5-2 dsp56k block diagram program control unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
program control unit (pcu) architecture motorola program control unit 5 - 5 the program control unit implements a three-stage (prefetch, decode, execute) pipeline and controls the five processing states of the dsp: normal, exception, reset, wait, and stop. 5.3 program control unit (pcu) architecture the pcu consists of three hardware blocks: the program decode controller (pdc), the program address generator (pag), and the program interrupt controller (pic). 5.3.1 program decode controller the pdc contains the program logic array decoders, the register address bus generator, the loop state machine, the repeat state machine, the condition code generator, the inter- rupt state machine, the instruction latch, and the backup instruction latch. the pdc decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control. the backup instruction latch stores a duplicate of the prefetched instruction to optimize execution of the repeat (rep) and jump (jmp) instructions. 5.3.2 program address generator (pag) the pag contains the pc, the sp, the ss, the operating mode register (omr), the sr, the lc register, and the la register (see figure 5-1). the pag provides hardware dedicated to support loops, which are frequent constructs in dsp algorithms. a do instruction loads the lc register with the number of times the loop should be executed, loads the la register with the address of the last instruction word in the loop (fetched during one loop pass), and asserts the loop flag in the sr. the do in- struction also supports nested loops by stacking the contents of the la, lc, and sr prior to the execution of the instruction. under control of the pag, the address of the first in- struction in the loop is also stacked so the loop can be repeated with no overhead. while the loop flag in the sr is asserted, the loop state machine (in the pdc) will compare the pc contents to the contents of the la to determine if the last instruction word in the loop was fetched. if the last word was fetched, the lc contents are tested for one. if lc is not equal to one, then it is decremented, and the ss is read to update the pc with the address of the first instruction in the loop, effectively executing an automatic branch. if the lc is equal to one, then the lc, la, and the loop flag in the sr are restored with the stack con- tents, while instruction fetches continue at the incremented pc value (la + 1). more information about the la and lc appears in section 5.3.4 instruction pipeline format. the repeat (rep) instruction loads the lc with the number of times the next instruction is to be repeated. the instruction to be repeated is only fetched once, so throughput is in- creased by reducing external bus contention. however, rep instructions are not f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
program control unit (pcu) architecture 5 - 6 program control unit motorola interruptible since they are fetched only once. a single-instruction do loop can be used in place of a rep instruction if interrupts must be allowed. 5.3.3 program interrupt controller the pic receives all interrupt requests, arbitrates among them, and generates the inter- rupt vector address. interrupts have a flexible priority structure with levels that can range from zero to three. levels 0 (lowest level), 1, and 2 are maskable. level 3 is the highest interrupt priority level (ipl) and is not maskable. two interrupt mask bits in the sr reflect the current ipl and indicate the level needed for an interrupt source to interrupt the processor. interrupts cause the dsp to enter the exception processing state which is discussed fully in sec- tion 7 e processing states. the four external interrupt sources include three external interrupt request inputs (irqa , irqb , and nmi ) and the reset pin. irqa and irqb can be either level sensitive or neg- ative edge triggered. the nonmaskable interrupt (nmi ) is edge sensitive and is a level 3 interrupt. moda/irqa , modb/irqb , and modc/nmi pins are sampled when reset is deasserted. the sampled values are stored in the operating mode register (omr) bits ma, mb, and mc, respectively (see section 5.4.3 for information on the omr). only the fourth external interrupt, reset , and illegal instruction have higher priority than nmi . the pic also arbitrates between the different i/o peripherals. the currently selected pe- ripheral supplies the correct vector address to the pic. 5.3.4 instruction pipeline format the program control unit uses a three-level pipelined architecture in which concurrent in- struction fetch, decode, and execution occur. this pipelined operation remains essentially hidden from the user and makes programming straightforward. the pipeline is illustrated in figure 5-3, which shows the operations of each of the execution units and all initial con- ditions necessary to follow the execution of the instruction sequence shown in the figure. the pipeline is described in more detail in section 7.2.1 instruction pipeline. the first instruction, i1, should be interpreted as follows: multiply the contents of x0 by the contents of y0, add the product to the contents already in accumulator a, round the result to the nearest even, store the result back in accumulator a, move the contents in x data memory (pointed to by r0) into x0 and postincrement r0, and move the contents in y data memory (pointed to by r4) into y1 and postincrement r4. the second instruction, i2, should be interpreted as follows: clear accumulator a, move the contents in x0 into the location in x data memory pointed to by r0 and postincrement r0. before the clear oper- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
program control unit (pcu) architecture motorola program control unit 5 - 7 instruction fetch logic instruction fetch logic instruction fetch logic instruction fetch instruction decode instruction execution i1 i2 i1 i3 i2 i1 i4 i3 i2 i5 i4 i3 parallel operations initial conditions address update (agu) r0=$0005 r4=$0008 r0=5+1 r4=8+1 r0=6+1 r4=9e1 r0=7+1 r4=8+1 instruction execution (data alu) a: a2=$00 a1=$000066 a0=$000000 x0=$400000 y1=$000077 a: a2=$00 a1=$0000a2 a0=$000000 x0=$000005 y1=$000008 a: a2=$00 a1=$000000 a0=$000000 x0=$000005 y1=$000008 a: a2=$00 a1=$000000 a0=$000050 x0=$000007 y1=$000008 x memory at address $0005 $0006 $0007 data $000005 $000006 $000007 $000005 $000006 $000007 $000005 $000005 $000007 $000005 $000005 $000007 y memory at address $0008 $0009 data $000008 $000009 $000008 $000009 $000008 $0000a2 $000008 $0000a2 figure 5-3 three-stage pipeline instruction decode logic instruction decode logic instruction decode logic instruction execution logic instruction execution logic instruction execution logic instruction/data fetch instruction decode instruction execution parallel processing of instructions serial execution of instructions instruction cycle 1 instruction cycle 2 instruction cycle 3 instruction cycle 5 instruction cycle instruction cycle 1 instruction cycle 2 instruction cycle 3 instruction cycle 4 instruction cycle 5 exampl e p r ogram segmen t instruction 1 macr x0,y1,a x:(r0)+,x0 y:(r4)+,y1 instruction 2 clr a x0,x:(r0)+ a,y:(r4)- instruction 3 mac x0,y1,a x:(r0)+,x0 y:(r4)+,y1 seq uence of opera tions instruction fetch logic instruction fetch logic instruction decode logic 5 4 4 3 3 3 2 2 2 1 1 1 execution of example pr ogram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model 5 - 8 program control unit motorola ation, move the contents in accumulator a into the location in y data memory pointed to by r4 and postdecrement r4. the third instruction, i3, is the same as i1, except the rounding operation is not performed. 5.4 programming model the program control unit features la and lc registers which support the do loop instruc- tion and the standard program flow-control resources, such as a pc, complete sr, and ss. with the exception of the pc, all registers are read/write to facilitate system debug- ging. figure 5-4 shows the program control unit programming model with the six registers and ss. the following paragraphs give a detailed description of each register. 5.4.1 program counter this 16-bit register contains the address of the next location to be fetched from program memory space. the pc can point to instructions, data operands, or addresses of oper- ands. references to this register are always inherent and are implied by most instructions. figure 5-4 program control unit programming model 23 6 5 0 23 16 15 0 program control unit 23 16 15 0 23 16 15 0 * 23 16 15 8 7 0 * 23 8 7 6 5 4 3 2 1 0 * program counter (pc) 31 ssh 16 15 ssl 0 1 15 system stack status register (sr) operating mode register (omr) mr ccr ma de mb sd * loop address register (la) loop counter (lc) stack pointer (sp) * * * * read as zero, should be written with zero for future compatibility yd mc * f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model motorola program control unit 5 - 9 this special-purpose address register is stacked when program looping is initialized, when a jsr is performed, or when interrupts occur (except for no-overhead fast interrupts). 5.4.2 status register the 16-bit sr consists of a mode register (mr) in the high-order eight bits and a condition code register (ccr) in the low-order eight bits, as shown in figure 5-5. the sr is stacked when program looping is initialized, when a jsr is performed, or when interrupts occur, (except for no-overhead fast interrupts). the mr is a special purpose control register which defines the current system state of the processor. the mr bits are affected by processor reset, exception processing, the do, end current do loop (enddo), return from interrupt (rti), and swi instructions and by instructions that directly reference the mr register, such as or immediate to control reg- ister (ori) and and immediate to control register (andi). during processor reset, the interrupt mask bits of the mr will be set. the scaling mode bits, loop flag, and trace bit will be cleared. all bits are cleared after hardware reset except bits 8 and 9 which are set to ones. 15 14 13 12 11 10 9 8 76 543210 mr ccr * lf dm t s1 s0 i1 i0 s l e u n z v c figure 5-5 status register format carry overflow zero negative unnormalized extension limit scaling interrupt mask scaling mode reserved trace mode double precision multiply mode loop flag bits 12 and 16 to 23 are reserved, read as zero and should be written with zero for future compatibility f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model 5 - 10 program control unit motorola the ccr is a special purpose control register that defines the current user state of the processor. the ccr bits are affected by data arithmetic logic unit (alu) operations, par- allel move operations, and by instructions that directly reference the ccr (ori and andi). the ccr bits are not affected by parallel move operations unless data limiting oc- curs when reading the a or b accumulators. during processor reset, all ccr bits are cleared. 5.4.2.1 carry (bit 0) the carry (c) bit is set if a carry is generated out of the msb of the result in an addition. this bit is also set if a borrow is generated in a subtraction. the carry or borrow is gener- ated from bit 55 of the result. the carry bit is also affected by bit manipulation, rotate, and shift instructions. otherwise, this bit is cleared. 5.4.2.2 overflow (bit 1) the overflow (v) bit is set if an arithmetic overflow occurs in the 56-bit result. this bit indi- cates that the result cannot be represented in the accumulator register; thus, the register has overflowed. otherwise, this bit is cleared. 5.4.2.3 zero (bit 2) the zero (z) bit is set if the result equals zero; otherwise, this bit is cleared. 5.4.2.4 negative (bit 3) the negative (n) bit is set if the msb (bit 55) of the result is set; otherwise, this bit is cleared. 5.4.2.5 unnormalized (bit 4) the unnormalized (u) bit is set if the two msbs of the most significant product (msp) portion of the result are identical. otherwise, this bit is cleared. the msp portion of the a or b accumulators, which is defined by the scaling mode and the u bit, is computed as follows: s1 s0 scaling mode u bit computation 0 0 no scaling u = (bit 47 ? bit 46) 0 1 scale down u = (bit 48 ? b it 47) 1 0 scale up u = (bit 46 ? bit 45) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model motorola program control unit 5 - 11 5.4.2.6 extension (bit 5) the extension (e) bit is cleared if all the bits of the integer portion of the 56-bit result are all ones or all zeros; otherwise, this bit is set. the integer portion, defined by the scaling mode and the e bit, is computed as follows: if the e bit is cleared, then the low-order fraction portion contains all the significant bits; the high-order integer portion is just sign extension. in this case, the accumulator exten- sion register can be ignored. if the e bit is set, it indicates that the accumulator extension register is in use. 5.4.2.7 limit (bit 6) the limit (l) bit is set if the overflow bit is set. the l bit is also set if the data shifter/limiter circuits perform a limiting operation; otherwise, it is not affected. the l bit is cleared only by a processor reset or by an instruction that specifically clears it, which allows the l bit to be used as a latching overflow bit (i.e., a sticky bit). l is affected by data movement operations that read the a or b accumulator registers. 5.4.2.8 scaling bit (bit 7) the scaling bit (s) is used to detect data growth, which is required in block floating point fft operation. typically, the bit is tested after each pass of a radix 2 fft and, if it is set, the scaling mode should be activated in the next pass. the block floating point fft al- gorithm is described in the motorola application note apr4/d, implementation of fast fourier transforms on motorola?s dsp56000/dsp56001 and dsp96002 digital signal processors. this bit is computed according to the following logical equations when the result of accumulator a or b is moved to xdb or ydb. it is a sticky bit, cleared only by an instruction that specifically clears it. s1 s0 scaling mode integer portion 0 0 no scaling bits 55,54........48,47 0 1 scale down bits 55,54........49,48 1 0 scale up bits 55,54........47,46 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model 5 - 12 program control unit motorola 5.4.2.9 interrupt masks (bits 8 and 9) the interrupt mask bits, i1 and i0, reflect the current ipl of the processor and indicate the ipl needed for an interrupt source to interrupt the processor. the current ipl of the processor can be changed under software control. the interrupt mask bits are set during hardware reset but not during software reset. 5.4.2.10 scaling mode (bits 10 and 11) the scaling mode bits, s1 and s0, specify the scaling to be performed in the data alu shifter/limiter, and also specify the rounding position in the data alu multiply-accumula- if s1=0 and s0=0 (no scaling) then s = (a46 xor a45) or (b46 xor b45) if s1=0 and s0=1 (scale down) then s = (a47 xor a46) or (b47 xor b46) if s1=1 and s0=0 (scale up) then s = (a45 xor a44) or (b45 xor b44) if s1=1 and s0=1 (reserved) then the s flag is undefined. where ai and bi means bit i in accumulator a or b. i1 i0 exceptions permitted exceptions masked 0 0 ipl 0,1,2,3 none 0 1 ipl 1,2,3 ipl 0 1 0 ipl 2,3 ipl 0,1 1 1 ipl 3 ipl 0,1,2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model motorola program control unit 5 - 13 tor (mac). the scaling modes are shown in the following table: the scaling mode affects data read from the a or b accumulator registers out to the xdb and ydb. different scaling modes can occur with the same program code to allow dynam- ic scaling. dynamic scaling facilitates block floating-point arithmetic. the scaling mode also affects the mac rounding position to maintain proper rounding when different por- tions of the accumulator registers are read out to the xdb and ydb. the scaling mode bits, which are cleared at the start of a long interrupt service routine, are also cleared dur- ing a processor reset. 5.4.2.11 reserved status (bit 12) this bits is reserved for future expansion and will read as zero during dsp read opera- tions. 5.4.2.12 trace mode (bit 13) the trace mode (t) bit specifies the tracing function of the dsp56000/56001 only . (with other members of the dsp56k family, use the once trace mode described in section 10.5.) for the dsp56000/56001, if the t bit is set at the beginning of any instruction exe- cution, a trace exception will be generated after the instruction execution is completed. if the t bit is cleared, tracing is disabled and instruction execution proceeds normally. if a long interrupt is executed during a trace exception, the sr with the trace bit set will be stacked, and the trace bit in the sr is cleared (see section 7 e processing states for a complete description of a long interrupt operation). the t bit is also cleared during processor reset. 5.4.2.13 double precision multiply mode (bit 14) the processor is in double precision multiply mode when this bit is set. (see section 3.4 for detailed information on the double precision multiply mode.) when the dm bit is set, the operations performed by the mpy and mac instructions change so that a double precision 48-bit by 48-bit double precision multiplication can be performed in six instruc- s1 s0 rounding bit scaling mode 0 0 23 no scaling 0 1 24 scale down (1-bit arithmetic right shift) 1 0 22 scale up (1-bit arithmetic left shift) 1 1 ? reserved for future expansion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model 5 - 14 program control unit motorola tions. the dsp56k software simulator accurately shows how the mpy, mac, and other data alu instructions operate while the processor is in the double precision multiply mode. 5.4.2.14 loop flag (bit 15) the loop flag (lf) bit is set when a program loop is in progress. it detects the end of a program loop. the lf is the only sr bit that is restored when a program loop is termi- nated. stacking and restoring the lf when initiating and exiting a program loop, respec- tively, allow the nesting of program loops. at the start of a long interrupt service routine, the sr (including the lf) is pushed on the ss and the sr lf is cleared. when returning from the long interrupt with an rti instruction, the ss is pulled and the lf is restored. during a processor reset, the lf is cleared. 5.4.3 operating mode register the omr is a 24-bit register (only six bits are defined) that sets the current operating mode of the processor. each chip in the dsp56k family of processors has its own set of operating modes which determine the memory maps for program and data memories, and the startup procedure that occurs when the chip leaves the reset state. the omr bits are only affected by processor reset and by the andi, ori, and movec instructions, which directly reference the omr. the omr format with all of its defined bits is shown in figure 5-6. for product-specific omr bit definitions, see the individual chip?s user manual for details on its respective op- erating modes. 5.4.4 system stack the ss is a separate 15x32-bit internal memory divided into two banks, the ssh and the * sd mc yd de mb ma 23 8 76543210 * operating mode a, b data rom enable internal y memory disable operating mode c reserved stop delay reserved reserved * figure 5-6 omr format f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model motorola program control unit 5 - 15 ssl, each 16 bits wide. the ssh stores the pc contents, and the ssl stores the sr con- tents for subroutine calls, long interrupts, and program looping. the ss will also store the la and lc registers. the ss is in stack memory space; its address is always inherent and implied by the current instruction. the contents of the pc and sr are pushed on the top location of the ss when a subrou- tine call or long interrupt occurs. when a return from subroutine (rts) occurs, the contents of the top location in the ss are pulled and put in the pc; the sr is not affected. when an rti occurs, the contents of the top location in the ss are pulled to both the pc and sr. the ss is also used to implement no-overhead nested hardware do loops. when the do instruction is executed, the la:lc are pushed on the ss, then the pc:sr are pushed on the ss. since each ss location can be addressed as separate 16-bit registers (ssh and ssl), software stacks can be created for unlimited nesting. the ss can accommodate up to 15 long interrupts, seven do loops, 15 jsrs, or combi- nations thereof. when the ss limit is exceeded, a nonmaskable stack error interrupt occurs, and the pc is pushed to ss location zero, which is not implemented in hardware. the pc will be lost, and there will be no sp from the stack interrupt routine to the program that was executing when the error occurred. 5.4.5 stack pointer register the 6-bit sp register indicates the location of the top of the ss and the status of the ss (underflow, empty, full, and overflow). the sp register is referenced implicitly by some in- structions (do, rep, jsr, rti, etc.) or directly by the movec instruction. the sp register format is shown in figure 5-7. the sp register works as a 6-bit counter that ad- dresses (selects) a 15-location stack with its four lsbs. the possible sp values are shown in figure 5-8 and described in the following paragraphs. 5.4.5.1 stack pointer (bits 0e3) the sp points to the last location used on the ss. immediately after hardware reset, figure 5-7 stack pointer register format 54 3210 stack pointer stack error flag underflow flag uf se p3 p2 p1 p0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model 5 - 16 program control unit motorola these bits are cleared (sp=0), indicating that the ss is empty. data is pushed onto the ss by incrementing the sp, then writing data to the location to which the sp points. an item is pulled off the stack by copying it from that location and then by decrementing the sp. 5.4.5.2 stack error flag (bit 4) the stack error flag indicates that a stack error has occurred, and the transition of the stack error flag from zero to one causes a priority level-3 stack error exception. when the stack is completely full, the sp reads 001111, and any operation that pushes data onto the stack will cause a stack error exception to occur. the sr will read 010000 (or 010001 if an implied double push occurs). any implied pull operation with sp equal to zero will cause a stack error exception, and the sp will read 111111 (or 111110 if an implied double pull occurs). the stack error flag is a sticky bit which, once set, remains set until cleared by the user. there is a sequence of instructions that can cause a stack overflow and, without the sticky bit, would not be detected because the stack pointer is decremented before the stack error interrupt is taken. the sticky bit keeps the stack error bit set until the user clears it by writ- ing a zero to sp bit 4. it also latches the overflow/underflow bit so that it cannot be changed by stack pointer increments or decrements as long as the stack error is set. the overflow/underflow bit remains latched until the first move to sp is executed. note: when sp is zero (stack empty), instructions that read the stack without sp post- decrement and instructions that write to the stack without sp preincrement do not cause a stack error exception (i.e., 1) do ssl,xxxx 2) rep ssl 3) movec or move peripheral figure 5-8 sp register values uf se p3 p2 p1 p0 1 1 1 1 1 0 stack underflow condition after double pull 1 1 1 1 1 1 stack underflow condition 0 0 0 0 0 0 stack empty (reset); pull causes underflow 0 0 0 0 0 1 stack location 1 0 0 1 1 1 0 stack location 14 0 0 1 1 1 1 stack location 15; push causes overflow 0 1 0 0 0 0 stack overflow condition 0 1 0 0 0 1 stack overflow condition after double push f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model motorola program control unit 5 - 17 data (movep) when ssl is specified as a source or destination). 5.4.5.3 underflow flag (bit 5) the underflow flag is set when a stack underflow occurs. the underflow flag is a sticky bit when the stack error flag is set. that is, when the stack error flag is set, the underflow flag will not change state. the combination of underflow=1 and stack error=0 is an illegal combination and will not occur unless it is forced by the user. if this condition is forced by the user, the hardware will correct itself based on the result of the next stack operation. 5.4.5.4 reserved stack pointer registration (bits 6e23) sp register bits 6 through 23 are reserved for future expansion and will read as zero dur- ing read operations. 5.4.6 loop address register the la is a read/write register which is stacked into the ssh by a do instruction and is unstacked by end-of-loop processing or by an enddo instruction. the contents of the la register indicate the location of the last instruction word in a program loop. when that last instruction is fetched, the processor checks the contents of the lc register (see the fol- lowing section). if the contents are not one, the processor decrements the lc and takes the next instruction from the top of the ss. if the lc is one, the pc is incremented, the loop flag is restored (pulled from the ss), the ss is purged, the la and lc registers are pulled from the ss and restored, and instruction execution continues normally. 5.4.7 loop counter register the lc register is a special 16-bit counter which specifies the number of times a hardware program loop shall be repeated. this register is stacked into the ssl by a do instruction and unstacked by end-of-loop processing or by execution of an enddo instruction. when the end of a hardware program loop is reached, the contents of the lc register are tested for one. if the lc is one, the program loop is terminated, and the lc register is loaded with the previous lc contents stored on the ss. if lc is not one, it is decremented and the program loop is repeated. the lc can be read under program control, which allows the number of times a loop will be executed to be monitored/changed dynamically. the lc is also used in the rep instruction 5.4.8 programming model summary the complete programming model for the dsp56k central processing module is shown in figure 5-9. programming models for the peripherals are shown in the appropriate user manuals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
programming model 5 - 18 program control unit motorola 23 16 15 0 55 b 0 55 a 0 47 y 0 23 16 15 0 * * * * * * * r7 r6 r5 r4 r3 r1 r2 r0 23 16 15 0 * * * * * * * * n7 n6 n5 n4 n3 n1 n2 n0 23 16 15 0 * * * * * * * * m7 m6 m5 m4 m3 m1 m2 m0 upper file lower file modifier registers offset registers pointer registers address generation unit program control unit 23 16 15 0 23 16 15 0 * 23 16 15 8 7 0 * program counter (pc) 31 ssh 16 15 ssl 0 1 15 system stack status register (sr) mr ccr loop address register (la) loop counter (lc) 47 x 0 x1 x0 23 0 23 0 y1 y0 input registers accumulator registers 23 0 b1 b0 23 8 7 0 # 23 0 b2 23 0 a1 a0 23 8 7 0 # 23 0 a2 data arithmetic logic unit * 23 0 23 0 * * * read as zero, should be written with zero for future compatibility # read as sign extension bits, written as don?t care figure 5-9 dsp56k central processing module programming model 23 6 5 0 * 23 8 7 6 5 4 3 2 1 0 operating mode register (omr) ma de mb sd * stack pointer (sp) * yd mc * f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola instruction set introduction 6 - 1 section 6 instruction set introduction fetch f1 f2 f3 f3e f4 f5 f6 . . . decode d1 d2 d3 d3e d4 d5 . . . execute e1 e2 e3 e3e e4 . . . instruction cycle: 1 2 3 4 5 6 7 . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents 6 - 2 instruction set introduction motorola section 6.1 instruction set introduction ...................................... 3 section 6.2 syntax ..................................................................................... 3 section 6.3 instruction formats ........................................................ 3 6.3.1 operand sizes .................................................................................... 5 6.3.2 data organization in registers ........................................................... 6 6.3.2.1 data alu registers ...................................................................... 6 6.3.2.2 agu registers .............................................................................. 7 6.3.2.3 program control registers ........................................................... 8 6.3.3 data organization in memory ............................................................. 9 6.3.4 operand references .......................................................................... 11 6.3.4.1 program references ..................................................................... 11 6.3.4.2 stack references ......................................................................... 11 6.3.4.3 register references ..................................................................... 11 6.3.4.4 memory references ..................................................................... 11 6.3.4.4.1 x memory references ............................................................ 11 6.3.4.4.2 y memory references ............................................................ 12 6.3.4.4.3 l memory references ............................................................. 12 6.3.4.4.4 yx memory references .......................................................... 12 6.3.5 addressing modes .............................................................................. 12 6.3.5.1 register direct modes .................................................................. 13 6.3.5.1.1 data or control register direct ............................................... 13 6.3.5.1.2 address register direct .......................................................... 13 6.3.5.2 address register indirect modes .................................................. 13 6.3.5.3 special addressing modes ........................................................... 14 6.3.5.3.1 immediate data ....................................................................... 14 6.3.5.3.2 absolute address .................................................................... 14 6.3.5.3.3 immediate short ...................................................................... 14 6.3.5.3.4 short jump address ............................................................... 14 6.3.5.3.5 absolute short ........................................................................ 14 6.3.5.3.6 i/o short .................................................................................. 16 6.3.5.3.7 implicit reference ................................................................... 16 6.3.5.4 addressing modes summary ........................................................ 20 section 6.4 instruction groups .......................................................... 20 6.4.1 arithmetic instructions ........................................................................ 22 6.4.2 logical instructions ............................................................................. 23 6.4.3 bit manipulation instructions ............................................................... 24 6.4.4 loop instructions ................................................................................ 24 6.4.5 move instructions ................................................................................ 26 6.4.6 program control instructions .............................................................. 27 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set introduction motorola instruction set introduction 6 - 3 6.1 instruction set introduction the programming model shown in figure 6-1 suggests that the dsp56k central pro- cessing module architecture can be viewed as three functional units which operate in parallel: data arithmetic logic unit (data alu), address generation unit (agu), and pro- gram control unit (pcu). the instruction set keeps each of these units busy throughout each instruction cycle, achieving maximal speed and maintaining minimal program size. this section introduces the dsp56k instruction set and instruction format. the complete range of instruction capabilities combined with the flexible addressing modes used in this processor provide a very powerful assembly language for implementing digital signal pro- cessing (dsp) algorithms. the instruction set has been designed to allow efficient coding for dsp high-level language compilers such as the c compiler. execution time is mini- mized by the hardware looping capabilities, use of an instruction pipeline, and parallel moves. 6.2 syntax the instruction syntax is organized into four columns: opcode, operands, and two parallel- move fields. the assembly-language source code for a typical one-word instruction is shown in the following illustration. because of the multiple bus structure and the parallel- ism of the dsp, up to three data transfers can be specified in the instruction word e one on the x data bus (xdb), one on the y data bus (ydb), and one within the data alu. these transfers are explicitly specified. a fourth data transfer is implied and occurs in the program control unit (instruction word prefetch, program looping control, etc.). each data transfer involves a source and a destination. opcode operands xdb ydb mac x0,y0,a x:(r0)+,x0 y:(r4)+,y0 the opcode column indicates the data alu, agu, or program control unit operation to be performed and must always be included in the source code. the operands column spec- ifies the operands to be used by the opcode. the xdb and ydb columns specify optional data transfers over the xdb and/or ydb and the associated addressing modes. the address space qualifiers (x:, y:, and l:) indicate which address space is being referenced. parallel moves are allowed in 30 of the 62 instructions. additional information is presented in appendix a - instruction set details. 6.3 instruction formats the dsp56k instructions consist of one or two 24-bit words e an operation word and an optional effective address extension word. the general format of the operation word is f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats 6 - 4 instruction set introduction motorola 23 16 15 0 55 b 0 55 a 0 47 y 0 23 16 15 0 * * * * * * * r7 r6 r5 r4 r3 r1 r2 r0 23 16 15 0 * * * * * * * * n7 n6 n5 n4 n3 n1 n2 n0 23 16 15 0 * * * * * * * * m7 m6 m5 m4 m3 m1 m2 m0 upper file lower file modifier registers offset registers pointer registers address generation unit program control unit 23 16 15 0 23 16 15 0 * 23 16 15 8 7 0 * program counter (pc) 31 ssh 16 15 ssl 0 1 15 system stack status register (sr) mr ccr loop address register (la) loop counter (lc) 47 x 0 x1 x0 23 0 23 0 y1 y0 input registers accumulator registers 23 0 b1 b0 23 8 7 0 # 23 0 b2 23 0 a1 a0 23 8 7 0 # 23 0 a2 data arithmetic logic unit * 23 0 23 0 * * * read as zero, should be written with zero for future compatibility # read as sign extension bits, written as don?t care figure 6-1 dsp56k central processing module programming model 23 6 5 0 * 23 8 7 6 5 4 3 2 1 0 operating mode register (omr) ma de mb sd * stack pointer (sp) * yd mc * f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats motorola instruction set introduction 6 - 5 shown in figure 6-2. most instructions specify data movement on the xdb, ydb, and data alu operations in the same operation word. the dsp56k performs each of these oper- ations in parallel. the data bus movement field provides the operand reference type. it selects the type of memory or register reference to be made, the direction of transfer, and the effective address(es) for data movement on the xdb and ydb. this field may require additional information to fully specify the operand for certain addressing modes. an effective address extension word following the operation word provides an immediate data address or an absolute address if required (see section 6.3.5.3 for the description of special addressing modes). examples of operations that may include the extension word include the move operations x:, x:r, y:, r:y, and l:. additional information is presented in appendix a - instruction set details. the opcode field of the operation word specifies the data alu operation or the program control unit operation to be performed, and any additional operands required by the instruction. only those data alu and program control unit operations that can accompany data bus movement will be specified in the opcode field of the instruction. other data alu, program control unit, and all address alu operations will be specified in an instruction word with a different format. these formats include operation words which contain short immediate data or short absolute addresses (see section 6.3.5.3 for the description of special addressing modes). 6.3.1 operand sizes operand sizes are defined as follows: a byte is 8 bits long, a short word is16 bits long, a word is 24 bits long, a long word is 48 bits long, and an accumulator is 56 bits long (see figure 6-3). the operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. implicit instructions support some subset of the five sizes shown in figure 6-3. figure 6-2 general format of an instruction operation word 23 8 7 0 xxxxxxx x data bus movement opcode optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats 6 - 6 instruction set introduction motorola 6.3.2 data organization in registers the ten data alu registers support 8- or 24-bit data operands. instructions also support 48- or 56-bit data operands by concatenating groups of specific data alu registers. the eight address registers in the agu support 16-bit address or data operands. the eight agu offset registers support 16-bit offsets or may support 16-bit address or data oper- ands. the eight agu modifier registers support 16-bit modifiers or may support 16-bit address or data operands. the program counter (pc) supports 16-bit address operands. the status register (sr) and operating mode register (omr) support 8- or 16-bit data operands. both the loop counter (lc) and loop address (la) registers support 16-bit address operands. 6.3.2.1 data alu registers the eight main data alu registers are 24 bits wide. word operands occupy one register; long-word operands occupy two concatenated registers. the least significant bit (lsb) is the right-most bit (bit 0) and the most significant bit (msb) is the left-most bit (bit 23 for word operands and bit 47 for long-word operands). the two accumulator extension regis- ters are eight bits wide. when an accumulator extension register acts as a source operand, it occupies the low- order portion (bits 0e7) of the word and the high-order portion (bits 8e23) is sign extended (see figure 6-4). when used as a destination operand, this register receives the low-order portion of the word, and the high-order portion is not used. accumulator operands occupy an entire group of three registers (i.e., a2:a1:a0 or b2:b1:b0). the lsb is the right-most bit (bit 0), and the msb is the left-most bit (bit 55). figure 6-3 operand sizes 55 0 47 0 23 0 70 15 0 accumulator long word word short word byte f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats motorola instruction set introduction 6 - 7 6.3.2.2 agu registers the 24 agu registers are 16 bits wide. they may be accessed as word operands for address, address modifier, and data storage. when used as a source operand, these reg- isters occupy the low-order portion of the 24-bit word; the high-order portion is read as zeros (see figure 6-5). when used as a destination operand, these registers receive the low-order portion of the word; the high-order portion is not used. the notation rn desig- nates one of the eight address registers, r0er7; the notation nn designates one of the eight address offset registers, n0en7; and the notation mn designates one of the eight figure 6-4 reading and writing the alu extension registers 23 8 7 0 23 8 7 0 23 8 7 0 bus not used lsb of word a2 bus register a2, b2 used as a destination register a2, b2 used as a source sign extension of a2 contents of a2 not used register a2, b2 figure 6-5 reading and writing the address alu registers 23 0 bus not used 23 16 15 0 bus address alu address alu registers as a destination as a source address alu registers 15 0 zero fill registers lsb of word f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats 6 - 8 instruction set introduction motorola address modifier registers, m0em7. 6.3.2.3 program control registers the 8-bit operating mode register (omr) may be accessed as a word operand. however, not all eight bits are defined, and those that are defined will vary depending on the dsp56k family member. in general, undefined bits are written as don?t care and read as zero. the 16-bit sr has the system mode register (mr) occupying the high-order eight bits and (b) 8 bit (a) 16 bit figure 6-6 reading and writing control registers 23 8 7 0 23 8 7 0 bus not used lsb a2 bus mr, ccr, omr, and sp as a destination as a source mr, ccr, omr, and sp mr, ccr, omr, and sp zero fill 23 16 15 0 23 0 bus not used lsb of word bus lc, la, sr, ssh, and ssl as a destination as a source lc, la, sr, ssh, and ssl 15 0 zero fill lc, la, sr, ssh, and ssl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats motorola instruction set introduction 6 - 9 the user condition code register (ccr) occupying the low-order eight bits. the sr may be accessed as a word operand. the mr and ccr may be accessed individually as word operands (see figure 6-6(b)). the lc, la, system stack high (ssh), and system stack low (ssl) registers are 16 bits wide and may be accessed as word operands (see figure 6-6(a)). when used as a source operand, these registers occupy the low-order portion of the 24-bit word; the high-order portion is zero. when used as a destination operand, they receive the low-order portion of the 24-bit word; the high-order portion is not used. the system stack pointer (sp) is a 6-bit register that may be accessed as a word operand . the pc, a special 16-bit-wide program control register, is always referenced implicitly as a short-word operand. 6.3.3 data organization in memory the 24-bit program memory can store both 24-bit instruction words and instruction exten- sion words. the 32-bit system stack (ss) can store the concatenated pc and sr registers (pc:sr) for subroutine calls, interrupts, and program looping. the ss also supports the concatenated la and lc registers (la:lc) for program looping. the 24-bit-wide x and y memories can store word, short-word, and byte operands. short-word and byte operands, which usually occupy the low-order portion of the x or y memory word, are either zero extended or sign extended on the xdb or ydb. the symbols used to abbreviate the various operands and operations in each instruction and their respective meanings are shown in the following list: data alu xn input registers x1, x0 (24 bits) yn input registers y1, y0 (24 bits) an accumulator registers a2 (8 bits), a1, a0 (24 bits) bn accumulator registers b2 (8 bits), b1, b0 (24 bits) x input register x (x1:x0, 48 bits) y input register y (y1:y0, 48 bits) a accumulator a (a2:a1:a0, 56 bits) * b accumulator b (b2:b1:b0, 56 bits) * ab accumulators a and b (a1:b1, 48 bits) * *data move operations: when specited as a source operand, shifting and limiting are performed. when specited as a destination operand, sign extension and zero tlling are performed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats 6 - 10 instruction set introduction motorola ba accumulators b and a (b1:a1, 48 bits) * a10 accumulator a (a1:a0, 48 bits) b10 accumulator b (b1:b0, 48 bits) address alu rn address registers r0er7 (16 bits) nn address offset registers n0en7 (16 bits) mn address modifier registers m0em7 (16 bits) program control unit pc program counter (16 bits) mr mode register (8 bits) ccr condition code register (8 bits) sr status register (mr:ccr, 16 bits) omr operating mode register (8 bits) la hardware loop address register (16 bits) lc hardware loop counter (16 bits) sp system stack pointer (6 bits) ss system stack ram (15x32 bits) ssh upper 16 bits of the contents of the current top of stack ssl lower 16 bits of the contents of the current top of stack addresses ea effective address xxxx absolute address (16 bits) xxx short jump address (12 bits) aa absolute short address (6 bits zero extended) pp i/o short address (6 bits ones extended) < . . . > contents of the specified address x: x memory reference y: y memory reference l: long memory reference e x concatenated with y p: program memory reference miscellaneous #xx immediate short data (8 bits) #xxx immediate short data (12 bits) #xxxxxx immediate data (24 bits) #n immediate short data (5 bits) s,sn source operand register d,dn destination operand register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats motorola instruction set introduction 6 - 11 d[n] bit n of d affected r rounding constant i1,i0 interrupt priority level in sr lf loop flag in sr 6.3.4 operand references the dsp separates operand references into four classes: program, stack, register, and memory references. the type of operand reference(s) required for an instruction is spec- ified by both the opcode field and the data bus movement field of the instruction. however, not all operand reference types can be used with all instructions. the operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. implicit instructions support some subset of the five operand sizes. 6.3.4.1 program references program (p) references, which are references to 24-bit-wide program memory space, are usually instruction reads. instructions or data operands may be read from or written to pro- gram memory space using the move program memory (movem) and move peripheral data (movep) instructions. depending on the address and the chip operating mode, pro- gram references may be internal or external memory references. 6.3.4.2 stack references stack (s) references, which are references to the system stack (ss), a separate 32-bit- wide internal memory space, are used implicitly to store the pc and sr for subroutine calls, interrupts, and returns. in addition to the pc and sr, the la and lc registers are stored on the stack when a program loop is initiated. s references are always implied by the instruction. data is written to the stack memory to save the processor state and is read from the stack memory to restore the processor state. in contrast to s references, refer- ences to ssl and ssh are always explicit. 6.3.4.3 register references register (r) references are references to the data alu, agu, and program control unit registers. data can be read from one register and written into another register. 6.3.4.4 memory references memory references, which are references to the 24-bit-wide x or y memory spaces, can be internal or external memory references, depending on the effective address of the operand in the data bus movement field of the instruction. data can be read or written from any address in either memory space. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats 6 - 12 instruction set introduction motorola 6.3.4.4.1 x memory references the operand, which is in x memory space, is a word reference. data can be transferred from memory to a register or from a register to memory. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats motorola instruction set introduction 6 - 13 6.3.4.4.2 y memory references the operand, a word reference, is in y memory space. data can be transferred from mem- ory to a register or from a register to memory. 6.3.4.4.3 l memory references long (l) memory space references both x and y memory spaces with one operand address. the data operand is a long-word reference developed by concatenating the x and y memory spaces (x:y). the high-order word of the operand is in the x memory; the low-order word of the operand is in the y memory. data can be read from memory to con- catenated registers x1:x0, a1:a0, etc. or from concatenated registers to memory. 6.3.4.4.4 yx memory references xy memory space references both x and y memory spaces with two operand addresses. two independent addresses are used to access two word operands e one word operand is in x memory space, and one word operand is in y memory space. two effective addresses in the instruction are used to derive two independent operand addresses e one operand address may reference either x or y memory space and the other operand address must reference the other memory space. one of these two effective addresses specified in the instruction must reference one of the address registers, r0er3, and the other effective address must reference one of the address registers, r4er7. addressing modes are restricted to no-update and post-update by +1, e1, and +n addressing modes. each effective address provides independent read/write control for its memory space. data may be read from memory to a register or from a register to memory. 6.3.5 addressing modes the dsp instruction set contains a full set of operand addressing modes. to minimize execution time and loop overhead, all address calculations are performed concurrently in the address alu. addressing modes specify whether the operand(s) is in a register or in memory, and pro- vide the specific address of the operand(s). an effective address in an instruction will specify an addressing mode, and, for some addressing modes, the effective address will further specify an address register. in addition, address register indirect modes require additional address modifier information that is not encoded in the instruction. the address modifier information is specified in the selected address modifier register(s). all indirect memory references require one address modifier, and the xy memory reference requires two address modifiers. the definition of certain instructions implies the use of specific reg- isters and addressing modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats 6 - 14 instruction set introduction motorola some address register indirect modes require an offset and a modifier register for use in address calculations. these registers are implied by the address register specified in an effective address in the instruction word. each offset register (nn) and each modifier reg- ister (mn) is assigned to an address register (rn) having the same register number (n). thus, the assigned register triplets are r0;n0;m0, r1;n1;m1, r2;n2;m2, r3;n3;m3, r4;n4;m4, r5;n5;m5, r6;n6;m6, and r7;n7;m7. rn is used as the address register; nn is used to specify an optional offset; and mn is used to specify the type of arithmetic used to update the rn. the addressing modes are grouped into three categories: register direct, address register indirect, and special. these addressing modes are described in the following paragraphs. refer to table 6-1 for a summary of the addressing modes and allowed operand references. 6.3.5.1 register direct modes these effective addressing modes specify that the operand source or destination is one of the data, control, or address registers in the programming model. 6.3.5.1.1 data or control register direct the operand is in one, two, or three data alu register(s) as specified in a portion of the data bus movement field in the instruction. classified as a register reference, this address- ing mode is also used to specify a control register operand for special instructions such as or immediate to control registers (ori) and and immediate to control registers (andi). 6.3.5.1.2 address register direct classified as a register reference, the operand is in one of the 24 address registers (rn, nn, or mn) specified by an effective address in the instruction. note: due to instruction pipelining, if an address register (mn, nn, or rn) is changed with a move instruction, the new contents will not be available for use as a pointer until the second following instruction. 6.3.5.2 address register indirect modes the address register indirect mode description is presented in section 4 - address generation unit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats motorola instruction set introduction 6 - 15 6.3.5.3 special addressing modes the special addressing modes do not use specific registers to specify an effective address. these modes specify the operand or the operand address in a field of the instruction, or they implicitly reference an operand. figure examples are given for each of the special addressing modes discussed in the following paragraphs. 6.3.5.3.1 immediate data classified as a program reference, this addressing mode requires one word of instruction extension containing the immediate data. figure 6-7 shows three examples. example a moves immediate data to register a0 without affecting a1 or a2. examples b and c zero fill register a0 and sign extend register a2 . 6.3.5.3.2 absolute address this addressing mode requires one word of instruction extension containing the absolute address. figure 6-8 shows that move y:$5432,b0 copies the contents of address $5432 into b0 without changing memory location $5432, register b1, or register b2. this addressing mode is classified as both a memory reference and program reference. the 16-bit absolute address is stored in the 16 lsbs of the extension word; the eight msbs are zero filled. 6.3.5.3.3 immediate short the 8- or 12-bit operand, which is in the instruction operation word, is classified as a pro- gram reference. the immediate data is interpreted as an unsigned integer (low-order portion) or signed fraction (high-order portion), depending on the destination register. fig- ure 6-9 shows the use of immediate short addressing in four examples. 6.3.5.3.4 short jump address the operand occupies 12 bits in the instruction operation word, which allows addresses $0000e$0fff to be accessed (see figure 6-10). the address is zero extended to 16 bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats 6 - 16 instruction set introduction motorola when used to address program memory. this addressing mode is classified as a program reference. figure 6-7 special addressing e immediate data f f 8 0 12 3 4 000000 0 0 1 2 34 5 6 000000 x x xxxxxx 123456 a2 a1 a0 x x x x xx x x xxxxxx 55 48 47 24 23 0 7 0 23 0 23 0 example a: immediate into 24-bit register (move #$123456,a0) before execution after execution example b:positive immediate into 56-bit register (move #$123456,a) after execution example c: negative immediate into 56-bit register (move #$801234,a) after execution assembler syntax: #xxxxxx memory spaces: p: additional instruction execution time (clocks): 2 additional effective address words: 1 a2 a1 a0 x x x x xx x x xxxxxx 55 48 47 24 23 0 7 0 23 0 23 0 before execution a2 a1 a0 x x x x xx x x xxxxxx 55 48 47 24 23 0 7 0 23 0 23 0 before execution a2 a1 a0 55 48 47 24 23 0 7 0 23 0 23 0 a2 a1 a0 55 48 47 24 23 0 7 0 23 0 23 0 a2 a1 a0 55 48 47 24 23 0 7 0 23 0 23 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats motorola instruction set introduction 6 - 17 6.3.5.3.5 absolute short the address of the operand occupies six bits in the instruction operation word, allowing addresses $0000e$003f to be accessed (see figure 6-11). classified as both a memory reference and program reference, the address is zero extended to 16 bits when used to address an operand or program memory. 6.3.5.3.6 i/o short classified as a memory reference, the i/o short addressing mode is similar to absolute short addressing. the address of the operand occupies six bits in the instruction operation word. i/o short is used with the bit manipulation and movep instructions. the i/o short address is ones extended to 16 bits to address the i/o portion of x and y memory (addresses $ffc0e$ffff e see figure 6-12). 6.3.5.3.7 implicit reference some instructions make implicit reference to pc, ss, la, lc, or sr. for example, the jump instruction (jmp) implicitly references the pc; whereas, the repeat next instruction (rep) implicitly references lc. the registers implied and their uses are defined by the individual instruction descriptions (see appendix a - instruction set details). 6.3.5.4 addressing modes summary figure 6-8 special addressing e absolute addressing b2 b1 b0 before execution b2 b1 b0 after execution example: move y:$5432,b0 23 y memory 0 $5432 abcdef assembler syntax: xxxx or aa memory spaces: p: additional instruction execution time (clocks): 2 additional effective address words: 1 x x x x xx x x xxxxxx 55 48 47 24 23 0 7 0 23 0 23 0 x x xxxxxx abcdef 55 48 47 24 23 0 7 0 23 0 23 0 23 y memory 0 $5432 abcdef f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction formats 6 - 18 instruction set introduction motorola x x 0 0 0 0 f f xxxxxx 0 0 1 f 00 0 0 000000 a2 a1 a0 x x x x xx x x xxxxxx 55 48 47 24 23 0 7 0 23 0 23 0 example a: immediate short into a0, a1, a2, b0, b1, b2, rn, nn (move #$ff,a1) before execution after execution example b:positive immediate short into x0, x1, y0, y1, a, b (move #$1f, y1) after execution after execution y1 y0 47 24 23 0 23 0 23 0 before execution a2 a1 a0 x x x x xx x x xxxxxx 55 48 47 24 23 0 7 0 23 0 23 0 before execution a2 a1 a0 55 48 47 24 23 0 7 0 23 0 23 0 a2 a1 a0 55 48 47 24 23 0 7 0 23 0 23 0 xxx xxxxx xxxx y1 y0 47 24 23 0 23 0 23 0 1f0 000xxxxxx example c: positive immediate short into x, y, a, b (move #$1f, a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction groups motorola instruction set introduction 6 - 19 6.4 instruction groups the instruction set is divided into the following groups: arithmetic logical bit manipulation loop move program control each instruction group is described in the following paragraphs; detailed information on each instruction is given in appendix a - instruction set details. 6.4.1 arithmetic instructions the arithmetic instructions, which perform all of the arithmetic operations within the data figure 6-10 special addressing e short jump address after execution $0fff jmp $0123 $0123 $0000 p memory pc next instruction before execution example: jmp $123 $0fff assembler syntax: xxx memory spaces: p: additional instruction execution time (clocks): 0 additional effective address words: 0 p memory pc jmp $0123 $0123 $0000 short jump range 4,096 words f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction groups 6 - 20 instruction set introduction motorola figure 6-11 special addressing e absolute short address p memory 23 0 after execution before execution example a: move p: $3200,x0 assembler syntax: aa memory spaces: p:, x:, y:, l: additional instruction execution time (clocks): 0 additional effective address words: 0 xxxxxx $0000 absolute short addressin- grange a2 a1 a0 x x 3 4 f5 e 6 xxxxxx 55 48 47 24 23 0 7 0 23 0 23 0 x1 x0 47 24 23 0 23 0 23 0 000 001xxxxxx $3204 $3200 $ a 5 b 4 c 6 x1 x0 47 24 23 0 23 0 23 0 000 001a5 b4c6 p memory 23 0 xxxxxx $3204 $3200 $ a 5 b 4 c 6 example b: move a1, x: $3 before execution a2 a1 a0 x x 3 4 f5 e 6 xxxxxx 55 48 47 24 23 0 7 0 23 0 23 0 after execution x memory 23 0 xxxxxx $0003 $003f $0040 $0000 x memory 23 0 34 f 5 e6 $0003 $003f $0040 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction groups motorola instruction set introduction 6 - 21 alu, execute in one instruction cycle. these instructions may affect all of the ccr bits. arithmetic instructions are register based (register direct addressing modes used for oper- ands) so that the data alu operation indicated by the instruction does not use the xdb, the ydb, or the global data bus (gdb). optional data transfers may be specified with most arithmetic instructions, which allows for parallel data movement over the xdb and ydb or over the gdb during a data alu operation. this parallel movement allows new data to be prefetched for use in subsequent instructions and allows results calculated in previous instructions to be stored. the following list contains the arithmetic instructions: figure 6-12 special addressing e i/o short address example: movep a1, x:<<$fffe assembler syntax: pp operands referenced: x:, y memories additional instruction execution time (clocks): 0 additional effective address words: 0 $ffc0 i/o short absolute address space a2 a1 a0 x x 1 2 3 4 5 6 xxxxxx 55 48 47 24 23 0 7 0 23 0 23 0 before execution a2 a1 a0 x x 1 2 3 4 5 6 xxxxxx 55 48 47 24 23 0 7 0 23 0 23 0 after execution x memory 23 0 00ffff* $fffe $ffff $ffc0 x memory 23 0 003456 $fffe $ffff *contents of bus control register (x:$fffe) after reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction groups 6 - 22 instruction set introduction motorola addressing mode moditer mmmm operand reference pscd a x y l xy register direct data or control register address register address modifier register address offset register no no no no xx x x x address register indirect no update postincrement by 1 postdecrement by 1 postincrement by offset nn postdecrement by offset nn indexed by offset nn predecrement by 1 no ye s ye s ye s ye s ye s ye s x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x table 6-1 addressing modes summary where: mmmm = address moditer p = program reference s = stack reference c = program control unit register reference d = data alu register reference a = agu register reference x = x memory reference y = y memory reference l = l memory reference xy = xy memory reference f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction groups motorola instruction set introduction 6 - 23 abs absolute value adc add long with carry add addition addl shift left and add addr shift right and add asl arithmetic shift left asr arithmetic shift right clr clear an operand cmp compare cmpm compare magnitude dec* decrement by one div * divide iteration inc* increment by one mac signed multiply-accumulate ** macr signed multiply-accumulate and round** mpy signed multiply** mpyr signed multiply and round** neg negate accumulator norm * normalize rnd round sbc subtract long with carry sub subtract subl shift left and subtract subr shift right and subtract tcc * transfer conditionally tfr transfer data alu register tst test an operand 6.4.2 logical instructions the logical instructions execute in one instruction cycle and perform all of the logical oper- ations within the data alu (except andi and ori). they may affect all of the ccr bits and, like the arithmetic instructions, are register based. logical instructions are the only instructions that allow apparent duplicate destinations, such as: and x0,a x:(r0):a0 a logical instruction uses only the msp portion of the a and b registers (a1 and b1). *these instructions do not allow parallel data moves. **certain applications of these instructions do not allow parallel data moves. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction groups 6 - 24 instruction set introduction motorola therefore, the instruction actually ignores what appears to be a duplicate destination and logically ands the value in the x0 register with the bits in the a1 portion (bits 47-24) of the a accumulator. the parallel move shown above can simultaneously write to either of the other two portions of the a or the b accumulator without conflict. avoid confusion by explicitly stating a1 or b1 in the original instruction. optional data transfers may be specified with most logical instructions, allowing parallel data movement over the xdb and ydb or over the gdb during a data alu operation. this parallel movement allows new data to be prefetched for use in subsequent instruc- tions and allows results calculated in previous instructions to be stored. the following list includes the logical instructions: and logical and andi * and immediate to control register eor logical exclusive or lsl logical shift left lsr logical shift right not logical complement or logical inclusive or ori * or immediate to control register rol rotate left ror rotate right *these instructions do not allow parallel data moves. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction groups motorola instruction set introduction 6 - 25 6.4.3 bit manipulation instructions the bit manipulation instructions test the state of any single bit in a memory location or a register and then optionally set, clear, or invert the bit. the carry bit of the ccr will contain the result of the bit test. the following list defines the bit manipulation instructions: bclr bit test and clear bset bit test and set bchg bit test and change btst bit test on memory and registers 6.4.4 loop instructions the hardware do loop executes with no overhead cycles after the do instruction itself has been executede i.e., it runs as fast as straight-line code. replacing straight-line code with do loops can significantly reduce program memory. the loop instructions control hardware looping by 1) initiating a program loop and establishing looping parameters or by 2) restoring the registers by pulling the ss when terminating a loop. initialization includes saving registers used by a program loop (la and lc) on the ss so that program loops can be nested. the address of the first instruction in a program loop is also saved to allow no-overhead looping. the loop instructions are as follows: do start hardware loop enddo exit from hardware loop both static and dynamic loop counts are supported in the following forms: do #xxx,expr ; (static) do s,expr ; (dynamic) expr is an assembler expression or absolute address, and s is a directly addressable reg- ister such as x0. the operation of a do loop is shown in figure 6-13. when a program loop is initiated with the execution of a do instruction, the following events occur: 1. the stack is pushed. a. the sp is incremented. b. the current 16-bit la and 16-bit lc registers are pushed onto the ss to allow nested loops. c. the lc register is initiated with the loop count value specified in the do instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction groups 6 - 26 instruction set introduction motorola 2. the stack is pushed again. a. the sp is incremented. b. the address of the first instruction in the program loop (pc) and the current sr contents are pushed onto the ss. c. the la register is initialized with the value specified in the do instruction decremented by one. 3. the lf bit in the sr is set. the lf bit is set when a program loop is in progress and enables the end-of-loop detection. the program loop continues execution until the program address fetched equals the la register contents (last address of program loop). the contents of the lc are then tested for one. if the lc is not one, it is decremented, and the top location in the stack ram is read (but not pulled) into the pc to return to the start of the loop. if the lc is one, the pro- gram loop is terminated by the following sequence: 1. reading the previous lf bit from the top location in the ss into the sr 2. purging the ss (pulling the top location and discarding the contents), pulling the la and lc registers off the ss, and restoring the respective registers 3. incrementing the pc the lf bit (pulled from the ss when a loop is terminated) indicates if the terminated loop was a nested loop. figure 6-14 shows two do loops, one nested inside the other. if the stack is managed to prevent a stack overflow, do loops can be stacked indefinitely. the enddo instruction is not used for normal termination of a do loop; it is only used to terminate a do loop before the lc has been decremented to one. figure 6-13 hardware do loop 1)sp+1 - sp; la - ssh; lc - ssl; #xxx - lc 2)sp+1 - sp; pc - ssh; sr - ssl; expre1 - la 3)1 - lf start of loop end of loop 1)ssl(lf) - sr 2)spe1 - sp; ssh - la; ssl - lc; spe1 - sp 3)pc + 1 - pc note: #xxx=loop count number expr=expression f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction groups motorola instruction set introduction 6 - 27 6.4.5 move instructions the move instructions perform data movement over the xdb and ydb or over the gdb. move instructions only affect the ccr bits s and l the s bit is affected if data growth is detected when the a or b registers are moved onto the bus. the l bit is affected if limiting is performed when reading a data alu accumulator register. an address alu instruction (lua) is also included in the following move instructions. the move instruction is the par- allel move with a data alu no-operation (nop). lua load updated address move move data register movec move control register movem move program memory movep move peripheral data note: due to instruction pipelining, if an agu register (mn, nn, or rn) is directly changed with a move-type instruction, the new contents may not be available for use until the sec- ond following instruction. see the restrictions discussed in section 7 - processing states on page 7-10. there are nine classifications of parallel data moves between registers and memory. fig- ure 6-15 shows seven parallel moves. the source of the data to be moved and the destination are separated by a comma. examples of the other two classifications, xy and long (l) moves, are shown in figure 6- 16. example a illustrates the following steps: 1) register x0 is added to register a and the result is placed in register a; 2) register x0 is moved to the x memory register location pointed to by r3, and r3 is incremented; and 3) the contents of the y memory location pointed to by r7 is moved to the b register, and r7 is decremented. example b depicts the following sequence: 1) register x0 is added to register a and the result is placed in register a; and 2) registers a and b are moved, respectively, to the loca- figure 6-14 nested do loops do #n1,end1 : do #n2,end2 : : move a,x:(r0)+ end2 add a,b x:(r1)+,x0 end1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction groups 6 - 28 instruction set introduction motorola contents of the 56-bit registers a and b were rounded to 24 bits before moving to the 24- bit memory registers. the dsp offers parallel processing of the data alu, agu, and program control unit. for the instruction word above, the dsp will perform the designated operation (data alu), the data transfers specified with address register updates (agu), and will decode the next instruction and fetch an instruction from program memory (program control unit) all in one instruction cycle. when an instruction is more than one word in length, an additional instruction execution cycle is required. most instructions involving the data alu are reg- ister based (all operands are in data alu registers), thereby allowing the programmer to keep each parallel processing unit busy. an instruction that is memory oriented (such as a bit manipulation instruction) or that causes a control-flow change (such as a jmp) pre- vents the use of parallel processing resources during its execution. 6.4.6 program control instructions the program control instructions include jumps, conditional jumps, and other instructions affecting the pc and ss. program control instructions may affect the ccr bits as speci- fied in the instruction. optional data transfers over the xdb and ydb may be specified in some of the program control instructions. the following list contains the program control instructions: debug enter debug mode debugcc enter debug mode conditionally iil illegal instruction jcc jump conditionally jmp jump figure 6-15 classifications of parallel data moves immediate short data add x0,a #$05,y1 address register update add x0,a (r0)+n0 register to register add x0,a a1,y0 x memory add x0,a x0,x:(r3)+ x memory plus register add x0,a x:(r4)e,x1 a,y0 y memory add x0,a y:(r6)+n6,x0 y memory plus register add x0,a a,x0 b,y:(r0) note: parallel move syntax?source(src), destination(dst) opcode/operands parallel move examples f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction groups motorola instruction set introduction 6 - 29 jclr jump if bit clear jset jump if bit set jscc jump to subroutine conditionally jsr jump to subroutine jsclr jump to subroutine if bit clear jsset jump to subroutine if bit set nop no operation rep repeat next instruction reset reset on-chip peripheral devices rti return from interrupt rts return from subroutine stop stop processing (low-power standby) swi software interrupt wait wait for interrupt (low-power standby) xy memory move +1 r3 x memory x0 add x0,a x0,x:(r3)+ y:(r7)-,b r7 y memory -1 b1 b0 b2 sign extended b0 cleared example a a2 a1 a0 b2 add x0,a ab,l:(r2)+n2 y memory b1 b0 long memory move x memory r2 +n2 a,b are shifted and limited example b figure 6-16 parallel move examples f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction groups 6 - 30 instruction set introduction motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola processing states 7 - 1 section 7 processing states stop wait exception normal reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents 7 - 2 processing states motorola section 7.1 processing states ............................................................ 3 section 7.2 normal processing state .............................................. 3 7.2.1 instruction pipeline ............................................................................. 3 7.2.2 summary of pipeline-related restrictions ......................................... 8 section 7.3 exception processing state ......................................... 10 7.3.1 interrupt types .................................................................................... 12 7.3.2 interrupt priority structure ................................................................... 12 7.3.2.1 interrupt priority levels ................................................................. 14 7.3.2.2 exception priorities within an ipl ................................................. 15 7.3.3 interrupt sources ................................................................................ 16 7.3.3.1 hardware interrupt sources .......................................................... 16 7.3.3.2 software interrupt sources ........................................................... 17 7.3.3.3 other interrupt sources ................................................................ 22 7.3.4 interrupt arbitration ............................................................................. 24 7.3.5 interrupt instruction fetch ................................................................... 24 7.3.6 instructions preceding the interrupt instruction fetch ........................ 25 7.3.7 interrupt instruction execution ............................................................ 26 section 7.4 reset processing state .................................................. 33 section 7.5 wait processing state ..................................................... 36 section 7.6 stop processing state .................................................... 37 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
processing states motorola processing states 7 - 3 7.1 processing states the dsp56k processor is always in one of five processing states: normal, exception, reset, wait, or stop. this section describes each of the processing states. 7.2 normal processing state the normal processing state is associated with instruction execution. details about nor- mal processing of the individual instructions can be found in appendix a - instruc- tion set details. instructions are executed using a three-stage pipeline, which is described in the following paragraphs. 7.2.1 instruction pipeline dsp56k instruction execution occurs in a three-stage pipeline, which allows most instructions to execute at a rate of one instruction per instruction cycle. however, certain instructions require additional time to execute: instructions longer than one word, instruc- tions using an addressing mode that requires more than one cycle, and instructions that cause a control-flow change. in the latter case, a cycle is needed to clear the pipeline. pipelining allows instruction executions to overlap so that the fetch-decode-execute operations of a given instruction occur concurrently with the fetch-decode-execute oper- ations of other instructions. specifically, while the processor is executing one instruction, it is decoding the next instruction, and fetching the next instruction from program mem- ory. the processor fetches only one word per cycle, so if an instruction is two words in length, it fetches the additional word before it fetches the next instruction. table 7-1 demonstrates pipelining. f1, d1, and e1 refer to the fetch, decode, and exe- cute operations, respectively, of the first instruction. the third instruction, which contains an instruction extension word, takes two instruction cycles to execute. the extension word will be either an absolute address or immediate data. although it takes three instruction cycles for the pipeline to fill and the first instruction to execute, an instruction usually executes on each instruction cycle thereafter. operation instruction cycle 1234 5 6 7 fetch f1 f2 f3 f3e f4 f5 f6 decode d1 d2 d3 d3e d4 d5 execute e1 e2 e3 e3e e4 table 7-1 instruction pipelining f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
normal processing state 7 - 4 processing states motorola each instruction requires a minimum of three instruction cycles (12 clock phases) to be fetched, decoded, and executed. this means that there is a delay of three instruction cycles on powerup to fill the pipe. a new instruction may begin immediately following the previous instruction. two-word instructions require a minimum of four instruction cycles to execute (three cycles for the first instruction word to move through the pipe and exe- cute and one more cycle for the second word to execute). a new instruction may start after two instruction cycles. the pipeline is normally transparent to the user. however, there are certain instruction- sequence dependent situations where the pipeline will affect the program execution. such situations are best described by case studies. most of these restricted sequences occur because 1) all addresses are formed during instruction decode, or 2) they are the result of contention for an internal resource such as the status register (sr). if the execu- tion of an instruction depends on the relative location of the instruction in a sequence of instructions, there is a pipeline effect. to test for a suspected pipeline effect, compare between the execution of the suspect instruction 1) when it directly follows the previous instruction and 2) when four nops are inserted between the two. if there is a difference, it is caused by a pipeline effect. the dsp56k assembler flags instruction sequences with potential pipeline effects so that the user can determine if the operation will execute as expected. case 1: the following two examples show similar code sequences. 1. no pipeline effect: ori #xx,ccr ;changes ccr at the end of execution time slot jcc xxxx ;reads condition codes in sr in its execution time slot the jcc will test the bits modified by the ori without any pipeline effect in the code seg- ment above. 2. instruction that started execution during decode: ori #04,omr ;sets de bit at execution time slot move x:$100,a ;reads external ram instead of internal rom a pipeline effect occurs in example 2 because the address of the move is formed at its decode time before the ori changes the de bit (which changes the memory map) in the ori?s execution time slot. the following code produces the expected results of reading the internal rom: ori #04,omr ;sets de bit at execution time slot nop ;delays the move so it will read the updated memory map move x:$100,a ;reads internal rom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
normal processing state motorola processing states 7 - 5 case 2: one of the more common sequences where pipeline effects are apparent is as follows: ;move a number into register rn (n=0e7). move #xx,rn move x:(rn),a ;use the new contents of rn to address memory. in this case, before the first move instruction has written rn during its execution cycle, the second move has accessed the old rn, using the old contents of rn. this is because the address for indirect moves is formed during the decode cycle. this overlap- ping instruction execution in the pipeline causes the pipeline effect. one instruction cycle should be allowed after an address register has been written by a move instruction before the new contents are available for use as an address register by another move instruction. the proper instruction sequence is as follows: ;move a number into register rn. move x0,rn nop ;execute any instruction or instruction ;sequence not using rn. move x:(rn),a use the new contents of rn. case 3: a situation related to case 2 can be seen in the boot rom code shown in ap- pendix a of the dsp56001 technical data sheet . at the end of the bootstrap operation, the operation mode register (omr) is changed to mode #2, and then the program that was loaded is executed. this process is accomplished in the last three instructions: _bootend movec #2,omr ;set the operating mode to 2 ;(and trigger an exit from ;bootstrap mode). andi #$0,ccr ;clear sr as if reset and ;introduce delay needed for ;op. mode change. jmp <$0 ;start fetching from pram, p:$0000 the jmp instruction generates its jump address during its decode cycle. if the jmp instruction followed the movec, the movec instruction would not have changed the omr before the jmp instruction formed the fetch address. as a result, the jump would fetch the instruction at p:$0000 of the bootstrap rom (move #$ffe9,r2). the omr would then change due to the movec instruction, and the next instruction would be the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
normal processing state 7 - 6 processing states motorola second instruction of the downloaded code at p:$0001 of the internal ram. however, the andi instruction allows the omr to be changed before the jmp instruction uses it, and the jmp fetches p:$0000 of the internal ram. case 4: an interrupt has two additional control cycles that are executed in the interrupt controller concurrently with the fetch, decode, and execute cycles (see section 7.3 and figure 7-4). during these two control cycles, the interrupt is arbitrated by comparing the interrupt mask level with the interrupt priority level (ipl) of the interrupt and allowing or disallowing the interrupt. therefore, if the interrupt mask is changed after an interrupt is arbitrated and accepted as pending but before the interrupt is executed, the interrupt will be executed, regardless of what the mask was changed to. the following examples show that the old interrupt mask is in effect for up to four additional instruction cycles after the interrupt mask is changed. all instructions shown in the examples here are one-word in- structions; however, one two-word instruction can replace two one-word instructions except where noted. 1. program flow with no interrupts after interrupts are disabled: ori #03,mr ;disable interrupts inst 1 inst 2 inst 3 inst 4 2. the four possible variations in program flow that may occur after interrupts are disabled: ori #03,mr ori #03,mr ori #03,mr ori #03,mr ii (see note 2) inst 1 inst 1 inst 1 ii+1 ii inst 2 inst 2 inst 1 ii+1 ll inst 3 (see note 1) inst 2 inst 2 ii+1 ll inst 3 inst 3 inst 3 ii+1 inst 4 inst 4 inst 4 inst 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
normal processing state motorola processing states 7 - 7 note 1: inst 3 may be executed at that point only if the preceding instruction (inst 2) was a single-word instruction. note 2: ii=interrupt instruction from maskable interrupt. the following program flow will not occur because the new interrupt mask level becomes effective after a pipeline latency of four instruction cycles: ori #03,mr ;disable interrupts. inst 1 inst 2 inst 3 inst 4 ii ;interrupts disabled. ii+1 ;interrupts disabled. 1. program flow without interrupts after interrupts are re-enabled: andi #00,mr ;enable interrupts inst 1 inst 2 inst 3 inst 4 2. program flow with interrupts after interrupts are re-enabled: andi #00,mr ;enable interrupts inst 1 ;uninterruptable inst 2 ;uninterruptable inst 3 ;ii fetched inst 4 ;ii+1 fetched ii ii+1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
normal processing state 7 - 8 processing states motorola the do instruction is another instruction that begins execution during the decode cycle of the pipeline. as a result, there are a number of restrictions concerning access conten- tion with the program controller registers accessed by the do instruction. the enddo instruction has similar restrictions. appendix a - instruction set details con- tains additional information on the do and enddo instruction restrictions. case 5: a resource contention problem can occur when one instruction is using a register during its decode while the instruction executing is accessing the same resource. one ex- ample of this is as follows: movec x:$100,ssh do #$10,end the problem occurs because the movec instruction loads the contents of x:$100 into the system stack high (ssh) during its execution cycle. the do instruction that follows pushes the stack (la ? ssh, lc ? ssl) during its decode cycle. therefore, the two instructions try writing to the ssh simultaneously and conflict. 7.2.2 summary of pipeline-related restrictions the following paragraphs give a summary of the instruction sequences that cause pipe- line effects. additional information about the individual instructions can be found in appendix a - instruction set details. do instruction restrictions: the do instruction must not be immediately preceded by any of the following instruc- tions: bchg/bclr/bset la, lc, ssh, ssl, or sp movec/movem to la, lc, ssh, ssl, or sp movec/movem from ssh the do instruction cannot specify ssh as a source register, as in the following example: do ssh,xxxx restrictions near the end of do loops: proper do loop operation is guaranteed if no instruction starting at address la-2, la-1, or la specifies the program controller registers sr, sp, ssl, la, lc, or (implicitly) pc as a destination register, or specifies ssh as a source or a destination register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
normal processing state motorola processing states 7 - 9 the restricted instructions at la-2, la-1, and la are as follows: do bchg/bclr/bset la, lc, sr, sp, ssh, or ssl btst ssh jclr/jset/jsclr/jsset ssh movec/movem/movep from ssh movec/movem/movep to la, lc, sr, sp, ssh, or ssl andi/ori mr the restricted instructions at la include the following: any two-word instruction jcc, jmp, jscc, jsr, rep, reset, rti, rts, stop, wait another restriction is shown below: jsr/jscc/jsclr/jsset to la, if loop flag is set enddo instruction restrictions: the enddo instruction must not be immediately preceded by any of the following instructions: bchg/bclr/bset la, lc, sr, ssh, ssl, or sp movec/movem to la, lc, sr, ssh, ssl, or sp movec/movem from ssh andi/ori mr rti and rts instruction restrictions: the rti instruction must not be immediately preceded by any of the following instruc- tions: bchg/bclr/bset sr, ssh, ssl, or sp movec/movem to sr, ssh, ssl, or sp movec/movem from ssh andi mr, andi ccr ori mr, ori ccr the rts instruction must not be immediately preceded by any of the following instruc- tions: bchg/bclr/bset ssh, ssl, or sp movec/movem to ssh, ssl, or sp movec/movem from ssh f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) 7 - 10 processing states motorola sp and ssh/ssl register manipulation restrictions: in addition to all the above restrictions concerning sp, ssh, and ssl, the following instruction sequences are illegal: 1. bchg/bclr/bset sp 2. movec/movem/movep from ssh or ssl and 1. movec/movem to sp 2. movec/movem/movep from ssh or ssl and 1. movec/movem to sp 2. jclr/jset/jsclr/jsset ssh or ssl and 1. bchg/bclr/bset sp 2. jclr/jset/jsclr/jsset ssh or ssl also, the instruction movec ssh,ssh is illegal. rn, nn, and mn register restrictions: due to pipelining, if an address register rn is the destination of a move-type instruction except movep (move, movec, movem, lua, tcc), the new contents will not be available for use as an address pointer until the second following instruction cycle. likewise, if an offset register nn or a modifier register mn is the destination of a move- type instruction except movep, the new contents will not be available for use in address calculations until the second following instruction cycle. however, if the processor is in the no update addressing mode (where mn and nn are ignored) and register mn or nn is the destination of a move instruction, the next instruc- tion may use the corresponding rn register as an address pointer. also, if the processor is in the postincrement by 1, postdecrement by 1, or predecrement by 1 addressing mode (where nn is ignored), a move to nn may be immediately followed by an instruc- tion that uses rn as an address pointer. fast interrupt routines: swi, stop, and wait may not be used in a fast interrupt routine. (fast interrupts are described in section 7.3.1.) 7.3 exception processing state (interrupt processing) the exception processing state is associated with interrupts that can be generated by conditions inside the dsp or from external sources. in digital signal processing, one of f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) motorola processing states 7 - 11 the main uses of interrupts is to transfer data between dsp memory or registers and a peripheral device. when such an interrupt occurs, a limited context switch with minimal overhead is ideal. a fast interrupt accomplishes a limited context switch. the processor relies on a long interrupt when it must accomplish a more complex task to service the interrupt. fast interrupts and long interrupts are described in more detail in section 7.3.1. there are many sources for interrupts on the dsp56k family of chips, and some of these sources can generate more than one interrupt. the dsp56k family of processors fea- tures a prioritized interrupt vector scheme with 32 vectors to provide fast interrupt ser- vice. the interrupt priority structure is discussed in section 7.3.2. the following list outlines how the dsp56k processes interrupts: 1. a hardware interrupt is synchronized with the dsp clock, and the interrupt pending flag for that particular hardware interrupt is set. an interrupt source can have only one interrupt pending at any given time. 2. all pending interrupts (external and internal) are arbitrated to select which interrupt will be processed. the arbiter automatically ignores any interrupts with an ipl lower than the interrupt mask level in the sr and selects the remaining interrupt with the highest ipl. 3. the interrupt controller then freezes the program counter (pc) and fetches two instructions at the two interrupt vector addresses associated with the selected interrupt. 4. the interrupt controller jams the two instructions into the instruction stream and releases the pc, which is used for the next instruction fetch. the next interrupt arbitration then begins. if neither instruction is a change of program-flow instruction (i.e., a jsr), the state of the machine is not saved on the stack, and a fast interrupt is executed. a long interrupt occurs if one of the interrupt instructions fetched is a jsr instruction. the pc is immedi- ately released, the sr and the pc are saved in the stack, and the jump instruction con- trols where the next instruction shall be fetched. while either an unconditional jump or a conditional jump can be used to form a long interrupt, they do not store the pc on the stack. therefore, there is no return path. activities 2 and 3 listed above require two additional control cycles, which effectively make the interrupt pipeline five levels deep. 7.3.1 interrupt types the dsp56k relies on two types of interrupt routines: fast and long. the fast interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) 7 - 12 processing states motorola fetches only two words and then automatically resumes execution of the main program; whereas, the long interrupt must be told to return to the main program by executing an rti instruction. the fast routine consists of two automatically inserted interrupt instruc- tion words. these words can contain any unrestricted, single two-word instruction or any two one-word instructions (see section a.9 in appendix a - instruction set details for a list of restrictions). fast interrupt routines are never interruptible. caution status is not preserved during a fast interrupt routine; therefore, instructions that modify status should not be used at the interrupt starting address and interrupt starting address +1. if one of the instructions in the fast routine is a jsr, then a long interrupt routine is formed. the following actions occur during execution of the jsr instruction when it occurs in the interrupt starting address or in the interrupt starting address +1: 1. the pc (containing the return address) and the sr are stacked. 2. the loop flag is reset. 3. the scaling mode bits are reset. 4. the ipl is raised to disallow further interrupts at the same or lower levels (except that hardware reset , nmi, stack error, trace, and swi can always interrupt). 5. the trace bit in the sr is cleared (in the dsp56000/56001 only). the long interrupt routine should be terminated by an rti. long interrupt routines are interruptible by higher priority interrupts. figure 7-1 shows examples of fast and long interrupts. 7.3.2 interrupt priority structure interrupts are organized in a flexible priority structure. each interrupt has an associated interrupt priority level (ipl) that can range from zero to three. levels 0 (lowest level), 1, and 2 are maskable. level 3 is the highest ipl and is not maskable. the only ipl 3 inter- rupts are reset , illegal instruction interrupt (iii), nonmaskable interrupt (nmi ), stack error, trace, and software interrupt (swi). the interrupt mask bits (i1, i0) in the sr reflect the current priority level and indicate the ipl needed for an interrupt source to interrupt the processor (see table 7-2). interrupts are inhibited for all priority levels below the cur- rent processor priority level. however, level 3 interrupts are not maskable and therefore can always interrupt the processor. dsp56k family central processor interrupt sources f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) motorola processing states 7 - 13 and their ipls are listed in table 7-6. for information on on-chip peripheral interrupt pri- (a) dsp56k fast interrupt (b) dsp56k long interrupt explicit return from interrupt recognized main program main program $0100 ? $0101 $0104 $0105 $0106 macr rep mac ? $0102 $0103 move mac interrupt recognized implicit return from interrupt ssi receive data fast interrupt service routine $000c $000d movep xxxxxx interrupt recognized jsr instruction forms long interrupt service $0100 ? $0101 $000e $000f $0104 $0105 $0106 macr jsr $0300 rep mac ? $0102 $0103 move mac ssi receive data with exception status long interrupt service routine $0300 $0301 ? do $0303 $0304 move rti figure 7-1 fast and long interrupt examples f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) 7 - 14 processing states motorola ority levels, see the individual dsp56k family member?s user?s manual. 7.3.2.1 interrupt priority levels the ipl for each on-chip peripheral device (hi, ssi, sci) and for each external interrupt source (irqa , irqb ) can be programmed to one of the three maskable priority levels (ipl 0, 1, or 2) under software control. ipls are set by writing to the interrupt priority reg- ister shown in figure 7-2. this read/write register is located in program memory at address $ffff. it specifies the ipl for each of the interrupting devices including irqa, irqb and each peripheral device. (for specific peripheral information, see the specific dsp56k family member?s user?s manual.) in addition, it specifies the trigger mode of the external interrupt sources and is used to enable or disable the individual external inter- rupts. the interrupt priority register is cleared on reset or by the reset instruction. table 7-3 defines the ipl bits. table 7-4 defines the external interrupt trigger mode bits. 7.3.2.2 exception priorities within an ipl if more than one interrupt is pending when an instruction is executed, the processor will service the interrupt with the highest priority level first. when multiple interrupt requests i1 i0 exceptions permitted exceptions masked 0 0 ipl 0, 1, 2, 3 none 0 1 ipl 1, 2, 3 ipl 0 1 0 ipl 2, 3 ipl 0, 1 1 1 ipl 3 ipl 0, 1, 2 table 7-2 status register interrupt mask bits ial1 ial0 ial2 ibl0 ibl1 ibl2 * * * * ** ** 0 23 10987654321 irqa mode irqb mode reserved for expansion reserved for peripheral ipl levels bits 6 to 9 are reserved, read as zero and should be written with zero for future compatibility. figure 7-2 interrupt priority register (addr x:$ffff) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) motorola processing states 7 - 15 with the same ipl are pending, a second fixed-priority structure within that ipl deter- mines which interrupt the processor will service. the fixed priority of interrupts within an ipl and the interrupt enable bits for all interrupts are shown in table 7-5. 7.3.3 interrupt sources interrupts can originate from any of the vector addresses listed in table 7-6, which shows the corresponding interrupt starting address for each interrupt source. these addresses are located in the first 64 locations of program memory. xxl1 xxl0 enabled ipl 0 0 no ? table 7-3 interrupt priority level bits table 7-4 external interrupt priority exception enabled by bit no. x data memory address level 3 (nonmaskable) highest hardware reset ??? iii ? ? ? nmi ? ? ? stack error ? ? ? trace ? ? ? lowest swi ? ? ? levels 0, 1, 2 (maskable) higher irqa (external interrupt) irqa mode bits 0 and 1 $ffff lower irqb (external interrupt) irqb mode bits 3 and 4 $ffff table 7-5 central processor interrupt priorities within an ipl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) 7 - 16 processing states motorola when an interrupt occurs, the instruction at the interrupt starting address is fetched first. because the program flow is directed to a different starting address for each interrupt, the interrupt structure of the dsp56k can be described as vectored. a vectored inter- rupt structure has low execution overhead. if it is known beforehand that certain inter- rupts will not be used, those interrupt vector locations can be used for program or data storage. 7.3.3.1 hardware interrupt sources there are two types of hardware interrupts in the dsp56k: internal and external. the internal interrupt sources include all of the on-chip peripheral devices. for further infor- mation on a device?s internal interrupt sources, see the device?s individual user?s man- ual. the external hardware interrupt sources are the r eset , nmi , irqa , and irqb pins on the program interrupt controller in the program control unit. the level sensitive reset interrupt is the highest priority interrupt with an ipl of 3. irqa and irqb can be programmed to one of three priority levels: 0, 1, or 2 - all of which are maskable. i rqa and irqb have independent enable control and can be programmed to be level sensitive or edge sensitive. since level-sensitive interrupts will not be cleared automatically when they are serviced, they must be cleared by other means to prevent multiple interrupts. edge-sensitive interrupts are latched as pending on the high-to-low transition of the interrupt input and are automatically cleared when the interrupt is ser- viced. interrupt starting address ipl interrupt source $0000 3 hardware reset $0002 3 stack error $0004 3 trace $0006 3 swi $0008 0 - 2 irqa $000a 0 - 2 irqb : : vectors available for peripherals $001e 3 nmi : : vectors available for peripherals $003e 3 illegal instruction table 7-6 interrupt sources f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) motorola processing states 7 - 17 when either the irqa or irq b pin is disabled in the interrupt priority register, the inter- rupt request coming in on the pin will be ignored, regardless of whether the input was defined as level sensitive or edge sensitive. if the interrupt input is defined as edge sen- sitive, its edge-detection latch will remain in the reset state for as long as the interrupt pin is disabled. if the interrupt is defined as level-sensitive, its edge-detection latch will stay in the reset state. if the level-sensitive interrupt is disabled while it is pending it will be cancelled. however, if the interrupt has been fetched, it normally will not be cancelled. the processor begins interrupt service by fetching the instruction word in the first vector location. the interrupt is considered finished when the processor fetches the instruction word in the second vector location. in an edge-triggered interrupt, the internal latch is automatically cleared when the sec- ond vector location is fetched. the fetch of the first vector location does not guarantee that the second location will be fetched. figure 7-3 illustrates the one case where the second vector location is not fetched. the swi instruction in the figure discards the fetch of the first interrupt vector to ensure that the swi vectors will be fetched. instruction n4 is decoded as an swi while ii1 is being fetched. execution of the swi requires that ii1 be discarded and the two swi vectors (ii3 and ii4) be fetched instead. interrupt control cycle 1 ii * interrupt control cycle 2 ii * fetch n3 n4 n5 ii1 ii3 ii4 sw1 sw2 sw3 sw4 decode n2 n3 swi ? ? ? jsr ? sw1 sw2 sw3 execute n1 n2 n3 swi nop nop nop jsr ? sw1 sw2 instruction being decoded 1 i = interrupt request i* = interrupt request generated by swi ii1 = first vector of interrupt i ii3 = first swi vector (one-word jsr) ii4 = second swi vector n = normal instruction word n4 = swi sw = instructions pertaining to the swi long interrupt routine figure 7-3 interrupting an swi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) 7 - 18 processing states motorola caution on all level-sensitive interrupts, the interrupt must be externally released be- fore interrupts are internally re-enabled. otherwise, the processor will be in- terrupted repeatedly until the release of the level-sensitive interrupt occurs. the edge sensitive nmi is a priority 3 interrupt and cannot be masked. only reset and illegal instruction have higher priority than nmi. 7.3.3.2 software interrupt sources there are two software interrupt sources ? software interrupt (swi) and illegal instruc- tion interrupt (iii). swi is a nonmaskable interrupt (ipl 3), which is serviced immediately following the swi instruction execution, usually using a long interrupt service routine. the difference between an swi and a jsr instruction is that the swi sets the interrupt mask to prevent interrupts below ipl 3 from being serviced. the swi?s ability to mask out lower level interrupts makes it very useful for setting breakpoints in monitor programs. the jsr instruction does not affect the interrupt mask. the iii is also a nonmaskable interrupt (ipl 3). it is serviced immediately following the execution or the attempted execution of an illegal instruction (any undefined operation code). iiis are fatal errors. only a long interrupt routine should be used for the iii routine. rti or rts should not be used at the end of the interrupt routine because, during the iii service, the jsr located in the iii vector will normally stack the address of the illegal instruction (see figure 7-4). returning from the interrupt routine would cause the proces- sor to attempt to execute the illegal interrupt again and cause an infinite loop which can only be broken by cycling power. this long interrupt (see figure 7-4) can be used as a diagnostic tool to allow the programmer to examine the stack (move ssh, dest) and locate the illegal instruction, or the application program can be restarted with the hope that the failure was a soft error. the illegal instruction is useful for triggering the illegal interrupt service routine to see if the iii routine can recover from illegal instructions. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) motorola processing states 7 - 19 i1 i2 main program fetches ii (nop) n6 no fetch no fetch infinite loop fast interrupt service routine fetches figure 7-4 illegal instruction interrupt serviced by a fast interrupt interrupt control cycle 1 i interrupt control cycle 2 i fetch n1 n2 n3 n4 n5 n6 ? ? ii1 ii2 n5 decode n1 n2 n3 n4 ii ? ? ? ii1 ii2 ii execute n1 n2 n3 n4 nop ? ? ? i i 1 i i 2 nop instruction cycle count 1 2 3 4 5 6 7 8 9 10111213 14 i = interrupt ii = interrupt instruction word ii = illegal instruction n = normal instruction word illegal instruction interrupt recognized as pending illegal instruction interrupt recognized as pending (a) instruction fetches from memory (b) program controller pipeline f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) 7 - 20 processing states motorola i1 i2 main program fetches ii (nop) n6 no fetch no fetch long interrupt service routine fetches figure 7-5 illegal instruction interrupt serviced by a long interrupt interrupt control cycle 1 i interrupt control cycle 2 i fetch n1 n2 n3 n4 n5 n6 ? ? ii1 ii2 ii3 ii4 ii5 decode n1 n2 n3 n4 ii ? ? ? ii1 ii2 ii3 ii4 execute n1 n2 n3 n4 nop ? ? ? ii1 ii2 ii3 instruction cycle count 1 2 3 4 5 6 7 8 9 10111213 14 i = interrupt ii = interrupt instruction word ii = illegal instruction n = normal instruction word illegal instruction interrupt recognized as pending illegal instruction interrupt recognized as pending (a) instruction fetches from memory (b) program controller pipeline i3 i4 i5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) motorola processing states 7 - 21 there are two cases in which the stacked address will not point to the illegal instruction: 1. if the illegal instruction is one of the two instructions at an interrupt vector loca- tion and is fetched during a regular interrupt service, the processor will stack the address of the next sequential instruction in the normal instruction flow (the regular return address of the interrupt routine that had the illegal opcode in its vector). 2. if the illegal instruction follows an rep instruction (see figure 7-6), the proces- sor will effectively execute the illegal instruction as a repeated nop and the interrupt vector will then be inserted in the pipeline. the next instruction will be fetched but will not be decoded or executed. the processor will stack the address of the next sequential instruction, which is two instructions after the illegal instruction. in do loops, if the illegal instruction is in the loop address (la) location and the instruc- tion preceding it (i.e., at la-1) is being interrupted, the loop counter (lc) will be decre- mented as if the loop had reached the la instruction. when the interrupt service ends and the instruction flow returns to the loop, the illegal instruction will be refetched (since it is the next sequential instruction in the flow). the loop state machine will again decre- ment lc because the la instruction is being executed. at this point, the illegal instruction will trigger the iii. the result is that the loop state machine decrements lc twice in one loop due to the presence of the illegal opcode at the la location. interrupt control cycle 1 i interrupt control cycle 2 i fetch n1 n2 n3 n4 n5 n6 n7 ? ? ? ii1 ii2 n8 decode n1 n2 n3 n4 rep ii ? ? ? ? ii1 ii2 n8 execute n1 n2 n3 n4 rep rep nop ? ? ? ii1 ii2 n8 instruction cycle count 1 2 3 4 5 6 7 8 9 10 111213141516 i = interrupt ii = interrupt instruction word ii = illegal instruction n = normal instruction word illegal instruction interrupt recognized as pending figure 7-6 repeated illegal instruction f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) 7 - 22 processing states motorola 7.3.3.3 other interrupt sources other interrupt sources include the stack error interrupt and trace interrupt (dsp56000/ 56001) which are ipl3 interrupts. an overflow or underflow of the system stack (ss) causes a stack error interrupt which is vectored to p:$0002 (see section 5 - program control unit for additional infor- mation on the stack error flag). since the stack error is nonrecoverable, a long interrupt should be used to service it. the service routine should not end in an rti because exe- cuting an rti instruction pops the stack, which has been corrupted. the dsp56000/56001 includes a facility for instruction-by-instruction tracing as a pro- gram development aid. this trace mode generates a trace exception after each instruc- tion executed (see figure 7-7), which can be used by a debugger program to monitor the execution of a program. (with members of the dsp56k family other than dsp56000/ 56001, use the once trace mode described in 10.5.) the trace bit in the sr defines the trace mode. in the trace mode, the processor will gen- erate a trace exception after it executes each instruction. when the processor is servic- ing the trace exception, it expects to encounter a jsr in the trace vector locations, thereby forming a long interrupt routine. the jsr stacks the sr and clears the trace bit to prevent tracing while executing the trace exception service routine. this service rou- tine should end with an rti instruction, which restores the sr (with the trace bit set) from the ss, and causes the next instruction to be traced. the pipeline must be flushed to allow each sequential instruction to be traced. the tracing facility appends three instruc- tion cycles to the end of each instruction traced (see the three nop instructions shown in figure 7-7) to flush the pipeline and allow the next trace interrupt to follow the next sequential interrupt. during tracing, the processor considers the rep instruction and the instruction being repeated as a single two-word instruction. that is, only after executing the rep instruc- tion and all of the repeats of the next instruction will the trace exception be generated. fast interrupts can not be traced because they are uninterruptable. long interrupts will not be traced unless the processor enters the trace mode in the subroutine because the sr is pushed on the stack and the trace bit is cleared. tracing is resumed upon returning from a long interrupt because the trace bit is restored when the sr is restored. interrupts are not likely to occur during tracing because only an interrupt with a higher ipl can interrupt during a trace operation. while executing the program being traced, the trace interrupt will always be pending and will win the interrupt arbitration. during the trace interrupt, the interrupt mask is set to reject interrupts below ipl3. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) motorola processing states 7 - 23 nop main program fetches n1 trace bit set in sr trace instruction n1 n2 nop nop jsr not used rti debugger program next trace operation three nop instructions inserted by trace mode fast interrupt caused by trace interrupt set trace bit in ssl (a) instruction fetches from memory interrupt control cycle 1 i i interrupt control cycle 2 i i fetch n1 nop nop nop jsr ? trace program rti ? n2 nop nop nop decode n1 nop nop nop jsr nop trace program rti nop n2 nop nop nop execute n1 nop nop nop jsr nop trace program rti nop n2 nop nop nop instruction cycle count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 i = interrupt ii = interrupt instruction word ii = illegal instruction n = normal instruction word interrupt synchronized and recognized as pending interrupt synchronized and recognized as pending figure 7-7 trace exception (b) program controller pipeline f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) 7 - 24 processing states motorola 7.3.4 interrupt arbitration interrupt arbitration and control, which occurs concurrently with the fetch-decode-exe- cute cycle, takes two instruction cycles. external interrupts are internally synchronized with the processor clock before their interrupt-pending flags are set. each external and internal interrupt has its own flag. after each instruction is executed, the dsp arbitrates all interrupts. during arbitration, each interrupt?s ipl is compared with the interrupt mask in the sr, and the interrupt is either allowed or disallowed. the remaining interrupts are prioritized according to the ipls shown in table 7-5, and the highest priority interrupt is chosen. the interrupt vector is then calculated so that the program interrupt controller can fetch the first interrupt instruction. interrupts from a given source are not buffered. the processor won?t arbitrate a new interrupt from the same source until after it fetches the second interrupt vector of the cur- rent interrupt. the internal interrupt acknowledge signal clears the edge-triggered interrupt flags and the internal latches of the nmi, swi, and trace interrupts. the stack error bit in the stack pointer register is sticky and requires a move or a bit clear operation directly on the stack pointer register. some peripheral interrupts may also be cleared by the internal interrupt acknowledge signal, as defined in their specifications. peripheral interrupt requests that need a read/write action to some register do not receive the internal inter- rupt acknowledge signal, and they will remain pending until their registers are read/writ- ten. further, level-triggered interrupts will not be cleared. the acknowledge signal will be generated after the interrupt vectors have been generated, not before. 7.3.5 interrupt instruction fetch the interrupt controller generates an interrupt instruction fetch address, which points to the first instruction word of a two-word interrupt routine. this address is used for the next instruction fetch, instead of the contents of the pc, and the interrupt instruction fetch address +1 is used for the subsequent instruction fetch. while the interrupt instructions are being fetched, the pc cannot be updated. after the two interrupt words have been fetched, the pc is used for any subsequent instruction fetches. after both interrupt vectors have been fetched, they are guaranteed to be executed. this is true even if the instruction that is currently being executed is a change-of-flow instruc- tion (i.e., jmp, jsr, etc.) that would normally ignore the instructions in the pipe. after the interrupt instruction fetch, the pc will point to the instruction that would have been fetched if the interrupt instructions had not been inserted. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) motorola processing states 7 - 25 7.3.6 instructions preceding the interrupt instruction fetch the following one-word instructions are aborted when they are fetched in the cycle pre- ceding the fetch of the first interrupt instruction word ? rep, stop, wait, reset, rti, rts, jcc, jmp, jscc, and jsr. two-word instructions are aborted when the first interrupt instruction word fetched will replace the fetch of the second word of the two-word instruction. aborted instructions are refetched when program control returns from the interrupt routine. the pc is adjusted appropriately before the end of the decode cycle of the aborted instruction. if the first interrupt word fetch occurs in the cycle following the fetch of a one-word instruction not previously listed or the second word of a two-word instruction, that instruc- tion will complete normally before the start of the interrupt routine. the following cases have been identified where service of an interrupt might encounter an extra delay: 1. if a long interrupt routine is used to service an swi, then the processor priority level is set to 3. thus, all interrupts except other level-3 interrupts are disabled until the swi service routine terminates with an rti (unless the swi service routine software lowers the processor priority level). 2. while servicing an interrupt, the next interrupt service will be delayed accord- ing to the following rule: after the first interrupt instruction word reaches the instruction decoder, at least three more instructions will be decoded before decoding the next first interrupt instruction word. if any one pair of instructions being counted is the rep instruction followed by an instruction to be repeated, then the combination is counted as two instructions independent of the num- ber of repeats done. sequential rep combinations will cause pending inter- rupts to be rejected and can not be interrupted until the sequence of rep combinations ends. 3. the following instructions are not interruptible: swi, stop, wait, and reset. 4. the rep instruction and the instruction being repeated are not interruptible. 5. if the trace bit in the sr (dsp56000/56001 only) is set, the only interrupts that will be processed are the hardware reset, iii,nmi, stack error, and trace. peripheral and external interrupt requests will be ignored. the interrupt gener- ated by the swi instruction will be ignored. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) 7 - 26 processing states motorola 7.3.7 interrupt instruction execution interrupt instruction execution is considered fast if neither of the instructions of the interrupt service routine causes a change of flow. a jsr within a fast interrupt routine forms a long interrupt, which is terminated with an rti instruction to restore the pc and sr from the stack and return to normal program execution. reset is a special exception, which will normally contain only a jmp instruction at the exception start address. at the programmer?s option, almost any instruction can be used in the fast interrupt routine. the restricted instructions include swi, stop, and wait. figure 7-8 and figure 7-10 show the fast and the long interrupt service routines. the fast interrupt executes only two instructions and then automatically resumes execution of the main program; whereas, the long interrupt must be told to return to the main program by executing an rti instruc- tion. figure 7-8 illustrates the effect of a fast interrupt routine in the stream of instruction fetches. figure 7-9 shows the sequence of instruction decodes between two fast interrupts. four decodes occur between the two interrupt decodes (two after the first interrupt and two preceding the second interrupt). the requirement for these four decodes establishes the maximum rate at which the dsp56k will respond to interrupts ? namely, one interrupt every six instructions (six instruction cycles if all six instructions are one instruction cycle each). since some instructions take more than one instruction cycle, the minimum num- ber of instructions between two interrupts may be more than six instruction cycles. the execution of a fast interrupt routine always conforms to the following rules: 1. a jsr to the starting address of the interrupt service routine is not located at one of the two interrupt vector addresses. 2. the processor status is not saved. 3. the fast interrupt routine may (but should not) modify the status of the normal instruction stream. 4. the fast interrupt routine may contain any single two-word instruction or any two one-word instructions except swi, stop, and wait. 5. the pc, which contains the address of the next instruction to be executed in normal processing remains unchanged during a fast interrupt routine. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) motorola processing states 7 - 27 ii1 ii2 main program memory n1 interrupt synchronized and recognized as pending additional interrupts disabled during fast interrupt interrupts re-enabled ii = interrupt instruction n = normal instruction n2 n3 n4 interrupt control cycle 1 i interrupt control cycle 2 i fetch n1 n2 ii1 ii2 n3 n4 decode n1 n2 ii1 ii2 n3 n4 execute n1 n2 ii1 ii2 n3 n4 instruction cycle count 12345 678 i = interrupt ii = interrupt instruction word n = normal instruction word interrupt synchronized and recognized as pending interrupts re-enabled (a) instruction fetches from memory (b) program controller pipeline figure 7-8 fast interrupt service routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) 7 - 28 processing states motorola ii1 ii2 main program memory n1 interrupt synchronized and recognized as pending additional interrupts disabled during fast interrupt interrupts re-enabled ii = interrupt instruction n = normal instruction n2 n3 n4 n5 n6 n7 n8 n9 additional interrupts disabled during fast interrupt interrupts re-enabled four instruction decodes ii1 ii2 (a) instruction fetches from memory interrupt control cycle 1 ii interrupt control cycle 2 ii fetch n1 n2 ii1 ii2 n3 n4 n5 n6 ii1 ii2 decode n1 n2 ii1 ii2 n3 n4 n5 n6 ii1 ii2 execute n1 n2 ii1 ii2 n3 n4 n5 n6 ii1 ii2 instruction cycle count 1234 5 6 7 89101112 i = interrupt ii = interrupt instruction word n = normal instruction word interrupt synchronized and recognized as pending interrupts re-enabled 6 i cyc (b) program controller pipeline figure 7-9 two consecutive fast interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) motorola processing states 7 - 29 6. the fast interrupt returns without an rti. 7. normal instruction fetching resumes using the pc following the completion of the fast interrupt routine. 8. a fast interrupt is not interruptible. 9. a jsr instruction within the fast interrupt routine forms a long interrupt routine. 10. the primary application is to move data between memory and i/o devices. the execution of a long interrupt routine always conforms to the following rules: 1. a jsr to the starting address of the interrupt service routine is located at one of the two interrupt vector addresses. 2. during execution of the jsr instruction, the pc and sr are stacked. the inter- rupt mask bits of the sr are updated to mask interrupts of the same or lower priority. the loop flag, trace bit, double precision multiply mode bit, and scaling mode bits are reset. 3. the first instruction word of the next interrupt service (of higher ipl) will reach the decoder only after the decoding of at least four instructions following the decoding of the first instruction of the previous interrupt. 4. the interrupt service routine can be interrupted ? i.e., nested interrupts are supported. 5. the long interrupt routine, which can be any length, should be terminated by an rti, which restores the pc and sr from the stack. figure 7-10 illustrates the effect of a long interrupt routine on the instruction pipeline. a short jsr (a jsr with 12-bit absolute address) is used to form the long interrupt routine. for this example, word 6 of the long interrupt routine is an rti. the point at which inter- rupts are re-enabled and subsequent interrupts are allowed is shown to illustrate the non-interruptible nature of the early instructions in the long interrupt service routine. either one of the two instructions of the fast interrupt can be the jsr instruction that forms the long interrupt. figure 7-11 and figure 7-12 show the two possible cases. if the first fast interrupt vector instruction is the jsr, the second instruction is never used. a rep instruction and the instruction that follows it are treated as a single two-word instruction, regardless of how many times it repeats the second instruction of the pair. instruction fetches are suspended and will be reactivated only after the lc is decre- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) 7 - 30 processing states motorola figure 7-10 long interrupt service routine explicit return from interrupt (should be rti) ii1 ii2 main program fetches n1 interrupt synchronized and recognized as pending jsr can be in either location to form a long interrupt n2 n3 n4 ii3 ii4 interrupt routine ii7 rti long interrupt service routine fetches (starts with a fast interrupt) program counter resumes operation interrupts re-enabled (a) instruction fetches from memory (b) program controller pipeline interrupt control cycle 1 i interrupt control cycle 2 i fetch n1 n2 ii1 ii2 ii3 ii4 ii5 ii6 ii7 rti ? n3 n4 decode n1 n2 ii1 ii2 ii3 ii4 ii5 ii6 ii7 rti nop n3 n4 execute n1 n2 ii1 ii2 ii3 ii4 ii5 ii6 ii7 rti nop n3 n4 instruction cycle count 123456 7 8 9 101112131415 i = interrupt ii = interrupt instruction word n = normal instruction word interrupt synchronized and recognized as pending interrupts re-enabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) motorola processing states 7 - 31 jsr not used main program n1 n2 ii2 ii3 ii4 iin rti fast interrupt vector long interrupt subroutine (a) instruction fetches from memory interrupt control cycle 1 i interrupt control cycle 2 i fetch n1 jsr ? ii2 ii3 ii4 iin rti ? n2 decode n1 jsr nop ii2 ii3 ii4 iin rti nop n2 execute n1 jsr nop ii2 ii3 ii4 iin rti nop n2 instruction cycle count 1 2 3 4 5 6 7 8 9 10 11 12 13 interrupt synchronized and recognized as pending interrupts re-enabled (b) program controller pipeline figure 7-11 jsr first instruction of a fast interrupt i = interrupt ii = interrupt instruction word n = normal instruction word f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
exception processing state (interrupt processing) 7 - 32 processing states motorola ii1 main program n1 n2 iin rti fast interrupt vector long interrupt subroutine jsr ii3 ii4 ii5 ii6 (a) instruction fetches from memory interrupt control cycle 1 i interrupt control cycle 2 i fetch n1 ii1 jsr ? ii3 ii4 ii5 iin rti ? n2 decode n1 ii1 jsr nop ii3 ii4 ii5 ii6 iin rti nop n2 execute n1 ii1 jsr nop ii3 ii4 ii5 ii6 iin rti nop n2 instruction cycle count 123 4 5 6 7 8 9 101112131415 i = interrupt ii = interrupt instruction word n = normal instruction word interrupt synchronized and recognized as pending interrupts re-enabled (b) program controller pipeline figure 7-12 jsr second instruction of a fast interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reset processing state motorola processing states 7 - 33 mented to one (see figure 7-13). during the execution of n2 in figure 7-13, no interrupts will be serviced. when lc finally decrements to one, the fetches are reinitiated, and pending interrupts can be serviced. sequential rep packages will cause pending interrupts to be rejected until the sequence of rep packages ends. rep packages are not interruptible because the instruction being repeated is not refetched. while that instruction is repeating, no instructions are fetched or decoded, and an interrupt can not be inserted. for example, in figure 7-14, if n1, n3, and n5 are all rep instructions, no interrupts will be serviced until the last rep instruction (n5 and its repeated instruction, n6) completes execution. 7.4 reset processing state the processor enters the reset processing state when a hardware reset occurs and the external reset pin is asserted. the reset state: 1. resets internal peripheral devices; 2. sets the modifier registers to $ffff; 3. clears the interrupt priority register; 4. sets the bcr to $ffff, thereby inserting 15 wait states in all external memory accesses; 5. clears the stack pointer; 6. clears the scaling mode, trace mode, loop flag, double precision multiply mode, and condition code bits of the sr, and sets the interrupt mask bits of the sr; 7. clears the data rom enable bit, the stop delay bit, and the internal y memory disable bit, and 8. the dsp remains in the reset state until the reset pin is deasserted. when the processor deasserts the reset state: 9. it loads the chip operating mode bits of the omr from the external mode select pins (moda, modb, modc), and 10. begins program execution at program memory address defined by the state of bits moda, modb, and modc in the omr. the first instruction must be fetched and then decoded before executing. therefore, the first instruction execution is two instruction cycles after the first instruction fetch. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reset processing state 7 - 34 processing states motorola n2 i1 main program fetches n1 rep m n2 interrupt synchro- nized and recognized as pending additional interrupts disabled during fast interrupt fast interrupt service routine fetches (from between p:$0000 and p:$003f) i2 n2 n3 n4 n5 n6 interrupts re-enabled n2 n2 instruction n2 replaced per the rep instruction i = interrupt instruction n = normal instruction figure 7-13 interrupting an rep instruction (a) instruction fetches from memory interrupt control cycle 1 ii interrupt control cycle 2 i% i fetch rep n2 n3 n4 ii1 ii2 n5 n6 decode rep nop n2 n2 n2 n2 n3 n4 ii1 ii2 n5 execute rep nop n2 n2 n2 n2 n3 n4 ii1 ii2 instruction cycle count 1 2 3 4 5 6 7 8 9 10 11 12 i = interrupt ii = interrupt instruction word n = normal instruction word i% = interrupt rejected interrupt synchronized and recognized as pending interrupts re-enabled (b) program controller pipeline repeat m times f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reset processing state motorola processing states 7 - 35 repeat m times n6 n4 n4 n4 n2 n1 rep m ii1 main program fetches n2 ii2 n3 n4 n5 n6 interrupt rejected n7 n8 n9 interrupt pending interrupt rejected interrupt rejected rep m rep m interrupt pending interrupt pending interrupt pending n6 n2 n2 n6 repeat m times (a) instruction fetches from memory interrupt control cycle 1 i i interrupt control cycle 2 i% i fetch rep n2 rep n4 rep n6 n7 n8 ii1 ii2 n9 decode rep nop n2 n2 n2 rep nop n4 n4 n4 rep nop n6 n6 n6 n7 n8 ii1 ii2 n9 execute rep nop n2 n2 n2 rep nop n4 n4 n4 rep nop n6 n6 n6 n7 n8 ii1 ii2 n9 instruction cycle count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 i = interrupt ii = interrupt instruction word n = normal instruction word i% = interrupt rejected interrupt synchronized and recognized as pending interrupts re-enabled (b) program controller pipeline figure 7-14 interrupting sequential rep instructions repeat m times f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
wait processing state 7 - 36 processing states motorola 7.5 wait processing state the wait instruction brings the processor into the wait processing state which is one of two low power-consumption states. asserting the once?s debug request pin releases the dsp from the wait state. in the wait state, the internal clock is disabled from all inter- nal circuitry except the internal peripherals. all internal processing is halted until an unmasked interrupt occurs, the debug request pin of the once is asserted, or the dsp is reset. figure 7-15 shows a wait instruction being fetched, decoded, and executed. it is fetched as n3 in this example and, during decode, is recognized as a wait instruction. the following instruction (n4) is aborted, and the internal clock is disabled from all inter- nal circuitry except the internal peripherals. the processor stays in this state until an interrupt or reset is recognized. the response time is variable due to the timing of the interrupt with respect to the internal clock. figure 7-15 shows the result of a fast interrupt bringing the processor out of the wait state. the two appropriate interrupt vectors are fetched and put in the instruction pipe. the next instruction fetched is n4, which had been aborted earlier. instruction execution proceeds normally from this point. figure 7-16 shows an example of the wait instruction being executed at the same time that an interrupt is pending. instruction n4 is aborted as before. the wait instruction causes a five-instruction-cycle delay from the time it is decoded, after which the interrupt is processed normally. the internal clocks are not turned off, and the net effect is that of executing eight nop instructions between the execution of n2 and ii1. interrupt control cycle 1 i interrupt control cycle 2 i fetch n3 n4 ? ii1 ii2 n4 n5 decode n2 wait ? ii1 ii2 n4 execute n1 n2 wait ii1 ii2 instruction cycle count 1 2 3 4 5 6 7 8 9 10 i = interrupt ii = interrupt instruction word n = normal instruction word interrupt synchronized and recognized as pending only internal peripherals receive clock figure 7-15 wait instruction timing f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
stop processing state motorola processing states 7 - 37 7.6 stop processing state the stop instruction brings the processor into the stop processing state, which is the lowest power consumption state. in the stop state, the clock oscillator is gated off; whereas, in the wait state, the clock oscillator remains active. the chip clears all periph- eral interrupts and external interrupts (irqa , irqb , and nmi ) when it enters the stop state. trace or stack errors that were pending, remain pending. the priority levels of the peripherals remain as they were before the stop instruction was executed. the on-chip peripherals are held in their respective individual reset states while in the stop state. interrupt control cycle 1 i interrupt control cycle 2 i fetch n3 n4 ? ? ? ? ? ? ii1 ii2 n4 decode n2 wait ? ? ? ? ? ? ? ii1 ii2 execute n1 n2 wait ? ? ? ? ? ? ? ii1 instruction cycle count 1 2 3 4 5 6 7 8 9 10 11 i = interrupt ii = interrupt instruction word n = normal instruction word interrupt synchronized and recognized as pending equivalent to eight nops figure 7-16 simultaneous wait instruction and interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
stop processing state 7 - 38 processing states motorola the stop processing state halts all activity in the processor until one of the following actions occurs: 1. a low level is applied to the irqa pin. 2. a low level is applied to the reset pin. 3. a low level is applied to the dr pin either of these actions will activate the oscillator, and, after a clock stabilization delay, clocks to the processor and peripherals will be re-enabled. the clock stabilization delay period is determined by the stop delay (sd) bit in the omr. the stop sequence is composed of eight instruction cycles called stop cycles. they are differentiated from normal instruction cycles because the fourth cycle is stretched for an indeterminate period of time while the four-phase clock is turned off. the stop instruction is fetched in stop cycle 1 of figure 7-17, decoded in stop cycle 2 (which is where it is first recognized as a stop command), and executed in stop cycle 3. the next instruction (n4) is fetched during stop cycle 2 but is not decoded in stop cycle 3 because, by that time, the stop instruction prevents the decode. the processor stops the clock and enters the stop mode. the processor will stay in the stop mode until it is restarted. fetch n3 n4 ? ? n4 decode n2 stop ? ? execute n1 n2 stop ? stop cycle count 1 2 3 4 5 6 7 8 (9) irqa = interrupt request a signal n = normal instruction word stop = interrupt instruction word resume stop cycle count 4, interrupts enabled 131,072 t or 16 t cycle count started irqa clock stopped figure 7-17 stop instruction sequence f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
stop processing state motorola processing states 7 - 39 figure 7-18 shows the system being restarted by asserting the irqa signal. if the exit from stop state was caused by a low level on the irqa pin, then the processor will ser- vice the highest priority pending interrupt. if no interrupt is pending, then the processor resumes at the instruction following the stop instruction that brought the processor into the stop state. an irqa deasserted before the end of the stop cycle count will not be recognized as pending. if irqa is asserted when the stop cycle count completes, then an irqa inter- rupt will be recognized as pending and will be arbitrated with any other interrupts. specifically, when irqa is asserted, the internal clock generator is started and begins a delay determined by the sd bit of the omr. when the chip uses the internal clock oscil- lator, the sd bit should be set to zero, to allow a longer delay time of 128k t cycles (131,072 t cycles) so that the clock oscillator may stabilize. when the chip uses a stable external clock, the sd bit may be set to one to allow a shorter (16 t cycle) delay time and a faster start up of the chip. for example, assume that sd=0 so that the 128k t counter is used. during the 128k t count, the processor ignores interrupts until the last few counts and, at that time, begins to synchronize them. at the end of the 128k t cycle delay period, the chip restarts instruction processing, completes stop cycle 4 (interrupt arbitration occurs at this time), and executes stop cycles 5, 6, 7, and 8 (it takes 17t from the end of the 128k t delay to fetch n3 n4 ? ? ii1 decode n2 stop ? ? execute n1 n2 stop ? stop cycle count 1 2 3 4 5 6 7 8 (9) irqa = interrupt request a signal n = normal instruction word stop = interrupt instruction word resume stop cycle count 4, interrupts enabled irqa clock stopped 131,072 t or 16 t cycle count started figure 7-18 stop instruction sequence followed by irqa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
stop processing state 7 - 40 processing states motorola the first instruction fetch). if the irqa signal is released (pulled high) after a minimum of 4t but less than 128k t cycles, no irqa interrupt will occur, and the instruction fetched after stop cycle 8 will be the next sequential instruction (n4 in figure 7-18). an irqa interrupt will be serviced as shown in figure 7-18 if 1) the irqa signal had previously been initialized as level sensitive, 2) irqa is held low from the end of the 128k t cycle delay counter to the end of stop cycle count 8, and 3) no interrupt with a higher interrupt level is pending. if irqa is not asserted during the last part of the stop instruction sequence (6, 7, and 8) and if no interrupts are pending, the processor will refetch the next sequential instruction (n4). since the irqa signal is asserted (see figure 7-18), the processor will recognize the interrupt and fetch and execute the instructions at p:$0008 and p:$0009 (the irqa interrupt vector locations). to ensure servicing irqa immediately after leaving the stop state, the following steps must be taken before the execution of the stop instruction: 1. define irqa as level sensitive e an edge-triggered interrupt will not be ser- viced. 2. define irqa priority as higher than the other sources and higher than the pro- gram priority. 3. ensure that no stack error or trace interrupts are pending. 4. execute the stop instruction and enter the stop state. 5. recover from the stop state by asserting the irqa pin and holding it asserted for the whole clock recovery time. if it is low, the irqa vector will be fetched. also, the user must ensure that nmi will not be asserted during these last three cycles; otherwise, nmi will be serviced before irqa because nmi prior- ity is higher. 6. the exact elapsed time for clock recovery is unpredictable. the external device that asserts irqa must wait for some positive feedback, such as spe- cific memory access or a change in some predetermined i/o pin, before deas- serting irqa . the stop sequence totals 131,104 t cycles (if sd=0) or 48 t cycles (if sd=1) in addi- tion to the period with no clocks from the stop fetch to the irqa vector fetch (or next instruction). however, there is an additional delay if the internal oscillator is used. an indeterminate period of time is needed for the oscillator to begin oscillating and then sta- bilize its amplitude. the processor will still count 131,072 t cycles (or 16 t cycles), but f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
stop processing state motorola processing states 7 - 41 the period of the first oscillator cycles will be irregular; thus, an additional period of 19,000 t cycles should be allowed for oscillator irregularity (the specification recom- mends a total minimum period of 150,000 t cycles for oscillator stabilization). if an exter- nal oscillator is used that is already stabilized, no additional time is needed. the pll may be disabled or not when the chip enters the stop state. if it is disabled and will not be re-enabled when the chip leaves the stop state, the number of t cycles will be much greater because the pll must regain lock. if the stop instruction is executed when the irqa signal is asserted, the clock genera- tor will not be stopped, but the four-phase clock will be disabled for the duration of the 128k t cycle (or 16 t cycle) delay count. in this case, the stop looks like a 131,072 t + 35 t cycle (or 51 t cycle) nop, since the stop instruction itself is eight instruction cycles long (32 t) and synchronization of irqa is 3t, which equals 35t. a trace or stack error interrupt pending before entering the stop state is not cleared and will remain pending. during the clock stabilization delay, all peripheral and external inter- rupts are cleared and ignored (includes all sci, ssi, hi, irqa , irqb , and nmi interrupts, but not trace or stack error). if the sci, ssi, or hi have interrupts enabled in 1) their respective control registers and 2) in the interrupt priority register, then interrupts like sci transmitter empty will be immediately pending after the clock recovery delay and will be serviced before continuing with the next instruction. if peripheral interrupts must be dis- abled, the user should disable them with either the control registers or the interrupt prior- ity register before the stop instruction is executed. if reset is used to restart the processor (see figure 7-19), the 128k t cycle delay counter would not be used, all pending interrupts would be discarded, and the processor would immediately enter the reset processing state as described in section 7.4. for example, the stabilization time recommended in thedsp56001 technical data sheet for the clock (reset should be asserted for this time) is only 50 t for a stabilized external clock but is the same 150,000 t for the internal oscillator. these stabilization times are recommended and are not imposed by internal timers or time delays. the dsp fetches instructions immediately after exiting reset. if the user wishes to use the 128k t (or 16 t) delay counter, it can be started by asserting irqa for a short time (about two clock cycles). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
stop processing state 7 - 42 processing states motorola interrupt control cycle 1 interrupt control cycle 2 fetch n3 n4 ? ? nop na nb nc nd ne decode n2 stop ? ? nop nop na nb nc nd execute n1 n2 stop ? nop nop nop na nb nc stop cycle count 1234 ireset = interrupt n = normal instruction word na, nb, nc = instructions in reset routine stop = interrupt instruction word reset clock stopped processor leaves reset state processor enters reset state figure 7-19 stop instruction sequence recovering with reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
stop processing state motorola processing states 7 - 43 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
stop processing state 7 - 44 processing states motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola port a 8 - 1 section 8 port a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents 8 - 2 port a motorola section 8.1 port a overview ..................................................................3 section 8.2 port a interface .................................................................3 8.2.1 read/write control signals .................................................................5 8.2.1.1 program memory select (ps) ..................................................... 5 8.2.1.2 data memory select (ds) ........................................................... 5 8.2.1.3 x/y select (x/y) .......................................................................... 5 8.2.2 port a address and data bus signals ................................................5 8.2.2.1 address (a0ea15) ...................................................................... 6 8.2.2.2 data (d0ed23) ............................................................................ 6 8.2.3 port a bus control signals ..................................................................6 8.2.3.1 read enable (rd) ...................................................................... 6 8.2.3.2 write enable (wr) ...................................................................... 6 8.2.3.3 port a access control signals .................................................... 6 8.2.4 interrupt and mode control .................................................................6 8.2.5 port a wait states ...............................................................................6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
port a overview motorola port a 8 - 3 8.1 port a overview port a provides a versatile interface to external memory, allowing economical connection with fast memories, slow memories/devices, and multiple bus master systems. this sec- tion introduces the signals associated with this memory expansion port that are common among the members of the dsp56k family of processors which feature port a. certain characteristics, such as signaling, timing, and bus arbitration, vary between members of the processor family and are detailed in each device?s own user?s manual. port a has two power-reduction features. it can access internal memory spaces, toggling only the external memory signals that need to change, and eliminate unneeded switch- ing current. also, if conditions allow the processor to operate at a lower memory speed, wait states can be added to the external memory access to significantly reduce power while the processor accesses those memories. 8.2 port a interface the dsp56k processor can access one or more of its memory sources (x data memory, y data memory, and program memory) while it executes an instruction. the memory sources may be either internal or external to the dsp. three address buses (xab, yab, and pab) and four data buses (xdb, ydb, pdb, and gdb) are available for internal memory accesses during one instruction cycle. port a?s one address bus and one data bus are available for external memory accesses. if all memory sources are internal to the dsp, one or more of the three memory sources may be accessed in one instruction cycle (i.e., program memory access or program memory access plus an x, y, xy, or l memory reference). however, when one or more of the memories are external to the chip, memory references may require additional instruction cycles because only one external memory access can occur per instruction cycle. if an instruction cycle requires more than one external access, the processor will make the accesses in the following priority: x memory, y memory, and program memory. it takes one instruction cycle for each external memory access e i.e., one access can be executed in one instruction cycle, two accesses take two instruction cycles, etc. since the external bus is only 24 bits wide, one xy or long external access will take two instruction cycles. the port a external data bus shown in figure 8-1 is 24 bits wide. the 16-bit address bus can sustain a rate of one memory access per instruction cycle (using no-wait-state mem- ory which is discussed in section 8.2.5.) figure 8-1 shows the port a signals divided into their three functional groups: address bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
port a interface 8 - 4 port a motorola signals (a0-a15), data bus signals (d0-d15), and bus control. the bus control signals can external address bus switch external address bus a0 - a15 x address (xa) y address (ya) program address (pa) 16 - bit internal address buses 16 external data b u s switch external data b u s d0 - d23 x data (xd) y data (yd) program data (pd) 24 - bit internal data buses 24 global data (gd) external bus control logic bus control signals rd - read enable wr - write enable ps - program memory select ds - data memory select x/y - x memory/y memory select bus access control pins figure 8-1 port a signals f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
port a interface motorola port a 8 - 5 be subdivided into three additional groups: read/write control (rd and wr ), address space selection (including program memory select (ps ), data memory select (ds ), and x/ y select) and bus access control. the read/write controls are self-descriptive. they can be used as decoded read and write controls, or, the write signal can be used as the read/write control and the read signal can be used as an output enable (or data enable) control for the memory. decoding in this fashion simplifies the connection to high-speed random-access memories (rams). the address space selection signals can be considered as additional address signals, which extend the addressable memory from 64k words to 192k words note: depending on system design, unused inputs should have pullup resistors for two reasons: 1) floating inputs draw excessive power, and 2) a floating input can cause erro- neous operation. for example, during reset, all signals are three-stated. output pins ps and ds may require pullup resistors because, without them, the signals may become ac- tive and may cause two or more memory chips to try to simultaneously drive the external data bus, which can damage the memory chips. a pullup resistor in the 50k-ohm range should be sufficient. 8.2.1 read/write control signals the following paragraphs describe the port a read/write control signals. these pins are three-stated during reset and may require pullup resistors to prevent erroneous operation of a memory device or other external components. 8.2.1.1 program memory select (ps ) this three-state output is asserted only when external program memory is referenced. 8.2.1.2 data memory select (ds ) this three-state output is asserted only when external data memory is referenced. 8.2.1.3 x/y select (x/y ) this three-state output selects which external data memory space (x or y) is referenced by ds . 8.2.2 port a address and data bus signals the following paragraphs describe the port a address and data bus signals. these pins are three-stated during reset and may require pullup resistors to prevent erroneous operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
port a interface 8 - 6 port a motorola 8.2.2.1 address (a0ea15) these three-state output pins specify the address for external program and data memory accesses. to minimize power dissipation, a0ea15 do not change state when external memory spaces are not being accessed. 8.2.2.2 data (d0ed23) these pins provide the bidirectional data bus for external program and data memory ac- cesses. d0ed23 are in the high-impedance state when the bus grant signal is asserted. 8.2.3 port a bus control signals the following paragraphs describe the port a bus control signals. the bus control signals provide the means to connect additional bus masters (which may be additional dsps, mi- croprocessors, direct memory access (dma) controllers, etc.) to the port a bus. they are three-stated during reset and may require pullup resistors to prevent erroneous operation. 8.2.3.1 read enable (rd ) this three-state output is asserted to read external memory on the data bus (d0ed23). 8.2.3.2 write enable (wr ) this three-state output is asserted to write external memory on the data bus (d0ed23). 8.2.3.3 port a access control signals port a features a group of configurable pins that perform bus arbitration and bus access control. the pins, such as bus needed (bn ), bus request. (br ), bus grant (bg ), bus wait (wt ), and bus strobe (bs ), and their designations differ between members of the dsp56k family and are explained in the respective devices? user manuals. 8.2.4 interrupt and mode control port a features a pin set that selects the chip?s operating mode and receives interrupt re- quests from external sources. the pins and their designations vary between members of the dsp56k family and are explained in the respective devices? user manuals. 8.2.5 port a wait states the dsp56k processor features two methods to allow the user to accommodate slow memory by changing the port a bus timing. the first method uses the16-bit bus control register (bcr), which resides in x data memory space. the bcr allows a fixed number of wait states to be inserted in a given memory access to all locations in any one of the four memory spaces: x, y, p, and i/o. the second method uses the bus strobe/wait (bs / f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
port a interface motorola port a 8 - 7 wt ) facility, which allows an external device to insert an arbitrary number of wait states when accessing either a single location or multiple locations of external memory or i/o space. wait states are executed until the external device releases the dsp to finish the external memory cycle. an internal wait-state generator can be programmed using the bcr to insert up to15 wait states if it is known ahead of time that access to slower mem- ory or i/o devices is required. a bus wait signal allows an external device to control the number of wait states (not limited to 15) inserted in a bus access operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
port a interface 8 - 8 port a motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola pll clock oscillator 9 - 1 section 9 pll clock oscillator xx d f vco f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents 9 - 2 pll clock oscillator motorola section 9.1 pll clock oscillator introduction ........................... 3 section 9.2 pll components .................................................................. 3 9.2.1 phase detector and charge pump loop filter ................................... 4 9.2.2 voltage controlled oscillator (vco) ................................................... 5 9.2.3 frequency multiplier ........................................................................... 5 9.2.4 low power divider (lpd) ................................................................... 5 9.2.5 pll control register (pctl) .............................................................. 5 9.2.5.1 pctl multiplication factor bits (mf0-mf11) - bits 0-11 ............ 5 9.2.5.2 pctl division factor bits (df0-df3) - bits 12-15 ..................... 6 9.2.5.3 pctl xtal disable bit (xtld) - bit 16 ..................................... 7 9.2.5.4 pctl stop processing state bit (pstp) - bit 17 ..................... 7 9.2.5.5 pctl pll enable bit (pen) - bit 18 .......................................... 8 9.2.5.6 pctl clock output disable bits (cod0-cod1) - bits 19-20 .... 8 9.2.5.7 pctl chip clock source bit (csrc) - bit 21 ............................ 9 9.2.5.8 pctl ckout clock source bit (ckos) - bit 22 ....................... 9 9.2.5.9 pctl reserved bit - bit 23 ........................................................ 9 section 9.3 pll pins ................................................................................... 9 section 9.4 pll operation considerations ..................................... 11 9.4.1 operating frequency .......................................................................... 11 9.4.2 hardware reset .................................................................................. 11 9.4.3 operation with pll disabled .............................................................. 12 9.4.4 changing the mf0-mf11 bits ............................................................. 12 9.4.5 change of df0-df3 bits .................................................................... 13 9.4.6 loss of lock ........................................................................................ 13 9.4.7 stop processing state ...................................................................... 13 9.4.8 ckout considerations ...................................................................... 14 9.4.9 synchronization among extal, ckout, and the internal clock ...... 14 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pll clock oscillator introduction motorola pll clock oscillator 9 - 3 9.1 pll clock oscillator introduction the dsp56k family of processors (with the exception of the dsp56000 and dsp56001) features a pll (phase-locked loop) clock oscillator in its central processing module, shown in figure 9-2. the pll allows the processor to operate at a high internal clock fre- quency using a low frequency clock input, a feature which offers two immediate benefits. lower frequency clock inputs reduce the overall electromagnetic interference generated by a system, and the ability to oscillate at different frequencies reduces costs by eliminat- ing the need to add additional oscillators to a system. the pll performs frequency multiplication to allow the processor to use almost any available external system clock for full speed operation, while also supplying an output clock synchronized to a synthesized internal core clock. it also improves the synchro- nous timing of the processor?s external memory port, significantly reducing the timing skew between extal and the internal chip phases. the pll is unusual in that it pro- vides a low power divider on its output, which can reduce or restore the chip operating frequency without losing the pll lock a dsp56k processor uses a four-phase clock for instruction execution which runs at the instruction execution rate. it can accept an external clock through the extal input, or it can run on an internal oscillator, bypassing the pll function, when the user connects an external crystal between xtal and extal. (the pll need not be disabled when the processor accepts an external clock.) 9.2 pll components the pll block diagram is shown below in figure 9-1. the components of the pll are de- scribed in the following sections. divider out extal vco out mf0-mf11 df0-df3 phase detector (pd) charge pump loop filter voltage controlled oscillator (vco) low power divider 2 0 to 2 15 multiplication factor 1 to 4096 figure 9-1 pll block diagram frequency multiplier f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pll components 9 - 4 pll clock oscillator motorola 9.2.1 phase detector and charge pump loop filter the phase detector (pd) detects any phase difference between the external clock (extal) and an internal clock phase from the frequency multiplier. at the point where there is negligible phase difference and the frequency of the two inputs is identical, the pll is in the locked state. clock generator peripheral pins internal data bus switch program ram/rom expansion program interrupt controller program decode controller program address generator ya b xab pa b ydb xdb pdb gdb modc/nmi modb/irqb reset data alu 24x24 + 56 ? 56-bit mac two 56-bit accumulators external address bus switch bus control external data b u s switch address data 16 bits 24 bits port a moda/irqa pll x memory ram/rom expansion y memory ram/rom expansion address generation unit oncea peripheral modules expansion area control 24-bit 56k mod- figure 9-2 dsp56k block diagram program control unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pll components motorola pll clock oscillator 9 - 5 the charge pump loop filter receives signals from the pd, and either increases or decreases the phase based on the pd signals. an external capacitor is connected to the pcap pin (described in section 9.3) and determines the pll operation. (see the appro- priate technical data sheet for more detailed information about a particular device?s phase and frequency.) after the pll locks on to the proper phase/frequency, it reverts to the narrow bandwidth mode, which is useful for tracking small changes due to frequency drift of the extal clock. 9.2.2 voltage controlled oscillator (vco) the vco can oscillate at frequencies from the minimum speed specified in a device?s technical data sheet (typically10 mhz) up to the device?s maximum allowed clock input frequency. 9.2.3 frequency multiplier inside the pll, the frequency multiplier divides the vco output frequency by its division factor (n). if the frequency multiplier?s output frequency is different from the extal fre- quency, the charge pump loop filter generates an error signal. the error signal causes the vco to adjust its frequency until the two input signals to the phase detector have the same phase and frequency. at this point (phase lock) the vco will be running at n times the extal frequency, where n is the multiplication factor for the frequency multiplier. the programmable multiplication factor ranges from 1 to 4096 9.2.4 low power divider (lpd) the low power divider (lpd) divides the output frequency of the vco by any power of 2 from 2 0 to 2 15 . since the lpd is not in the closed loop of the pll, changes in the divide factor will not cause a loss of lock condition. this fact is particularly useful for utilizing the lpd in low power consumption modes when the chip is not involved in intensive calcula- tions. this can result in significant power saving. when the chip is required to exit the low power mode, it can immediately do so with no time needed for clock recovery or pll lock. 9.2.5 pll control register (pctl) the pll control register (pctl) is a 24-bit read/write register which directs the operation of the on-chip pll. it is mapped into the processor?s internal x memory at x:$fffd. the pctl control bits are described in the following sections. 9.2.5.1 pctl multiplication factor bits (mf0-mf11) - bits 0-11 the multiplication factor bits mf0-mf11 define the multiplication factor (mf) that will be applied to the pll input frequency. the mf can be any integer from 1 to 4096. table 9-1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pll components 9 - 6 pll clock oscillator motorola shows how to program the mf0-mf11 bits. the vco will oscillate at a frequency of mf x f ext , where f ext is the extal clock frequency. the multiplication factor must be chosen to ensure that the resulting vco output frequency will lay in the range specified in the device?s technical data sheet. any time a new value is written into the mf0-mf11 bits, the pll will lose the lock condition. after a time delay, the pll will relock. the mf0-mf11 bits are set to a pre-determined value during hardware reset; the value is implementation dependent and may be found in each dsp56k family member?s user manual. table 9-1 multiplication factor bits mf0-mf11 9.2.5.2 pctl division factor bits (df0-df3) - bits 12-15 the division factor bits df0-df3 define the divide factor (df) of the low power divider. these bits specify any power of two divide factor in the range from 2 0 to 2 15 . table 9-2 mf11-mf0 multiplication factor mf $000 1 $001 2 $002 3 $ffe 4095 $fff 4096 0 1 2 6 7 8 9 10 11 3 4 5 12 13 14 18 19 20 21 22 23 15 16 17 mf0 mf1 mf2 mf3 mf4 mf5 mf6 mf7 mf8 mf9 mf10 mf11 df0 df1 df2 df3 xtld pstp pen csrc ckos ** cod0 ** reserved bits, read as zero, should be written with zero for future compatibility. cod1 figure 9-3 pll control register (pctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pll components motorola pll clock oscillator 9 - 7 shows the programming of the df0-df3 bits. changing the value of the df0-df3 bits will not cause a loss of lock condition. whenever possible, changes of the operating fre- quency of the chip (for example, to enter a low power mode) should be made by chang- ing the value of the df0-df3 bits rather than changing the mf0-mf11 bits. for mf 4, changing df0-df3 may lengthen the instruction cycle following the pll control register update; this is done in order to keep synchronization between extal and the internal chip clock. for mf>4 such synchronization is not guaranteed and the instruction cycle is not lengthened. note that ckout is synchronized with the internal clock in all cases. the df bits are cleared (division by one) by hardware reset. table 9-2 division factor bits df0-df3 9.2.5.3 pctl xtal disable bit (xtld) - bit 16 the xtal disable (xtld) bit controls the on-chip crystal oscillator xtal output. when xtld is cleared, the xtal output pin is active permitting normal operation of the crystal oscillator. when xtld is set, the xtal output pin is held in the high (1) state, disabling the on-chip crystal oscillator. if the on-chip crystal oscillator is not used (extal is driven from an external clock source), it is recommended that xtld be set (disabling xtal) to minimize rfi noise and power dissipation. the xtld bit is cleared by hardware reset. 9.2.5.4 pctl stop processing state bit (pstp) - bit 17 the pstp bit controls the behavior of the pll and of the on-chip crystal oscillator during the stop processing state. when pstp is set, the pll and the on-chip crystal oscillator will remain operating while the chip is in the stop processing state, enabling rapid recovery from the stop state. when pstp is cleared, the pll and the on-chip crystal oscillator will be disabled when the chip enters the stop processing. for minimal power consumption during the stop state, at the cost of longer recovery time, pstp should be df3-df0 division factor df $0 2 0 $1 2 1 $2 2 2 $e 2 14 $f 2 15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pll components 9 - 8 pll clock oscillator motorola cleared. to enable rapid recovery when exiting the stop state, at the cost of higher power consumption in the stop state, pstp should be set. pstp is cleared by hard- ware reset. 9.2.5.5 pctl pll enable bit (pen) - bit 18 the pen bit enables the pll operation. when this bit is set, the pll is enabled and the internal clocks will be derived from the pll vco output. when this bit is cleared, the pll is disabled and the internal clocks are derived directly from the clock connected to the extal pin. when the pll is disabled, the vco does not operate in order to minimize power consumption. the plock pin is asserted when pen is cleared. the pen bit may be set by software but it cannot be reset by software. during hardware reset this bit receives the value of the pinit pin. the only way to clear pen is to hold the pinit pin low during hardware reset. a relationship exists between pstp and pen where pen adjusts pstp?s control of the pll operation. when pstp is set and pen (see table 9-3) is cleared, the on-chip crys- tal oscillator remains operating in the stop state, but the pll is disabled. this power saving feature enables rapid recovery from the stop state when the user operates the chip with an on-chip oscillator and with the pll disabled. table 9-3 pstp and pen relationship 9.2.5.6 pctl clock output disable bits (cod0-cod1) - bits 19-20 the cod0-cod1 bits control the output buffer of the clock at the ckout pin. table 9-4 specifies the effect of cod0-cod1 on the ckout pin. when both cod0 and cod1 are set, the ckout pin is held in the high (1) state. if the ckout pin is not connected to external circuits, it is recommended that both cod1 and cod0 be set (disabling clock output) to minimize rfi noise and power dissipation. if the ckout output is low at the moment the cod0-cod1 bits are set, it will complete the low cycle and then be disabled high. if the programmer re-enables the ckout output before it reaches the high logic level during the disabling process, the ckout operation will be unaffected. the cod0-cod1 bits are cleared by hardware reset. operation during stop pstp pen pll oscillator recovery power consumption 0 x disabled disabled long minimal 1 0 disabled enabled rapid lower 1 1 enabled enabled rapid higher f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pll pins motorola pll clock oscillator 9 - 9 table 9-4 clock output disable bits cod0-cod1 9.2.5.7 pctl chip clock source bit (csrc) - bit 21 the csrc bit specifies whether the clock for the chip is taken from the output of the vco or is taken from the output of the low power divider (lpd). when csrc is set, the clock for the chip is taken from the vco. when csrc is cleared, the clock for the chip is taken from the output of the lpd. see section 9.4.8 for restrictions. csrc is cleared by hard- ware reset. 9.2.5.8 pctl ckout clock source bit (ckos) - bit 22 the ckos bit specifies whether the ckout clock output is taken from the output of the vco or is taken from the output of the low power divider (lpd). when ckos is set, the ckout clock output is taken from the vco. when ckos is cleared, the ckout clock output is taken from the output of the lpd. if the pll is disabled (pen=0), ckout is tak- en from extal. see section 9.4.8 for restrictions. ckos is cleared by hardware reset. 9.2.5.9 pctl reserved bit - bit 23 this bit is reserved for future expansion. it reads as zero and should be written with zero for future compatibility. 9.3 pll pins some of the pll pins need not be implemented. the specific pll pin configuration for each dsp56k chip implementation is available in the respective device?s user?s manual. the following pins are dedicated to the pll operation: pvcc vcc dedicated to the analog pll circuits. the voltage should be well regulated and the pin should be provided with an extremely low impedance path to the vcc power rail. pvcc should be bypassed to pgnd by a 0.1 m f capacitor located as close as possible to the chip package. pgnd gnd dedicated to the analog pll circuits. the pin should be provided with an extremely low impedance path to ground. pvcc should be bypassed to pgnd by a 0.1 m f capacitor located as close as possible to the chip package. cod1 cod0 ckout pin 0 0 clock out enabled, full strength output buffer 0 1 clock out enabled, 2/3 strength output buffer 1 0 clock out enabled, 1/3 strength output buffer 1 1 clock out disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pll pins 9 - 10 pll clock oscillator motorola clvcc vcc for the ckout output. the voltage should be well regulated and the pin should be provided with an extremely low impedance path to the vcc power rail. clvcc should be bypassed to clgnd by a 0.1 m f capacitor located as close as possible to the chip package. clgnd gnd for the ckout output. the pin should be provided with an extremely low impedance path to ground. clvcc should be bypassed to clgnd by a 0.1 m f capacitor located as close as possible to the chip package. pcap off-chip capacitor for the pll filter. one terminal of the capacitor is connected to pcap while the other terminal is connected to pvcc. the capacitor value is specified in the particular device?s technical data sheet. ckout this output pin provides a 50% duty cycle output clock synchronized to the internal processor clock when the pll is enabled and locked. when the pll is disabled, the output clock at ckout is derived from, and has the same frequency and duty cycle as, extal. note: if the pll is enabled and the multiplication factor is less than or equal to 4, then ckout is synchronized to extal. ckp this input pin defines the polarity of the ckout signal. strapping ckp through a resistor to gnd will make the ckout polarity the same as the extal polarity. strapping ckp through a resistor to vcc will make the ckout polarity the inverse of the extal polarity. the ckout clock polarity is internally latched at the end of the hardware reset, so that any changes of the ckp pin logic state after deassertion of reset will not affect the ckout clock polarity. pinit during the assertion of hardware reset, the value at the pinit input pin is written into the pen bit of the pll control register. after hardware reset is deasserted, the pinit pin is ignored. plock the plock output originates from the phase detector. the chip asserts plock when the pll is enabled and has locked on the proper phase and frequency of extal. the plock output is deasserted by the chip if the pll is enabled and has not locked on the proper phase and frequency. plock is asserted if the pll is disabled. plock is a reliable indicator of the pll lock state only after exiting the hardware reset state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pll operation considerations motorola pll clock oscillator 9 - 11 9.4 pll operation considerations the following paragraphs discuss pll operation considerations. 9.4.1 operating frequency the operating frequency of the chip is governed by the frequency control bits in the pll control register as follows: where: df is the division factor defined by the df0-df3 bits f chip is the chip operating frequency f ext is the external input frequency to the chip at the extal pin f vco is the output frequency of the vco mf is the multiplication factor defined by the mf0-mf11 bits the chip frequency is derived from the output of the low power divider. if the low power divider is bypassed, the equation is the same but the division factor should be assumed to be equal to one. 9.4.2 hardware reset hardware reset causes the initialization of the pll. the following considerations apply: 1. the mf0-mf11 bits in the pctl register are set to their pre-determined hard- ware reset value. the df0-df3 bits and the chip clock source bit in the pctl register are cleared. this causes the chip clock frequency to be equal to the external input frequency (extal) multiplied by the multiplication factor defined by mf0-mf11. 2. during hardware reset assertion, the pinit pin value is written into the pen bit in the pctl register. if the pinit pin is asserted (setting pen), the pll acquires the proper phase/frequency. while hardware reset is asserted, the internal chip clock will be driven by the extal pin until the pll achieves lock (if enabled). if the pinit pin is deasserted during hardware reset assertion, the pen bit is cleared, the pll is deactivated and the internal chip clock is driven by the extal pin. 3. plock is a reliable indicator of the pll lock state only after exiting the hard- ware reset state. f chip f ext mf df --------------------------- fvco df ------------- - == f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pll operation considerations 9 - 12 pll clock oscillator motorola 4. for all input frequencies which would result in a vco output frequency lower than the minimum specified in the device?s technical data sheet (typically 10 mhz), pinit must be cleared during hardware reset, disabling pll operation. otherwise, proper operation of the pll cannot be guaranteed. if the resulting vco clock frequency would be less than the minimum and the user wishes to operate with the pll enabled, the user must issue an instruction which loads the pctl control register with a multiplication factor that would bring the vco frequency above 10 mhz and would enable the pll operation. until this instruction is executed, the pll is disabled, which may cause a large skew (<15nsec) between the external input clock and the internal processor clock. if internal low frequency of operation is desired with the pll enabled, the vco output frequency may be divided down by using the internal low power divider. 5. the ckp pin only affects the ckout clock polarity during the hardware reset state. at the end of the hardware reset state, the ckp state is internally latched. 9.4.3 operation with pll disabled 1. if the pll is disabled, the plock pin is asserted. 2. if the pll is disabled, the internal chip clock and ckout are driven from the extal input. 9.4.4 changing the mf0-mf11 bits changes to the mf0-mf11 bits cause the following to occur: 1. the pll will lose the lock condition, the plock pin will be deasserted. 2. the pll acquires the proper phase/frequency. until this occurs the internal chip clock phases will be frozen. this ensures that the clock used by the chip is a clock that has reached a stable frequency. 3. when lock occurs, plock is asserted and the pll drives the internal chip clock and ckout. 4. while pll has not locked, ckout is held low if ckp is cleared. ckout is held high if ckp is set. 9.4.5 change of df0-df3 bits changes to the df0-df3 bits do not cause a loss of lock condition. the internal clocks will immediately revert to the frequency prescribed by the new divide factor. for mf 4, changing df0-df3 may lengthen the instruction cycle or ckout pulse following the pll control register update in order to keep synchronization between extal and the internal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pll operation considerations motorola pll clock oscillator 9 - 13 chip clock. (here, t3 is equal to the phase described by the new divide factor plus the time required to wait for a synchronizing pulse, which is less than 1.5etc.) for mf>4, such synchronization is not guaranteed and the instruction cycle is not lengthened. if the df0-df3 bits are changed by the same instruction that changes the mf0-mf11 bits, the lpd divider factor changes before the detection of the change in the multiplica- tion factor. this means that the detection of loss of lock will occur after the lpd has started dividing by the new division factor. 9.4.6 loss of lock the pll distinguishes between cases where mf>4 and cases where mf 4. if mf 4, the pll will detect loss of lock if a skew of 2.5 to 4.5 ns develops between the two clock inputs to the phase detector. if mf>4, the pll will detect loss of lock when there is a discrepancy of one clock cycle between the two clock inputs to the phase detector. when either of these two conditions occurs, the following also occur: 1. plock will be deasserted, indicating that loss of lock condition has occurred. 2. the pll will re-acquire the proper phase/frequency. when lock occurs, plock will be asserted. 9.4.7 stop processing state if the pstp bit is cleared, executing the stop instruction will disable the on-chip crystal oscillator and the pll. in this state the chip consumes the least possible power. when recovering from the stop state, the recovery time will be 16 or 64k external clock cycles (according to bit 6 in the operating mode register) plus the time needed for the pll to achieve lock. if the pstp bit is set, executing the stop instruction will leave the on-chip crystal oscil- lator (if xtld=0) and the pll loop (if pen=1) operating, but will disable the clock to the lpd and the rest of the dsp. when recovering from the stop state, the recovery time will be only three clock cycles. 9.4.8 ckout considerations the ckout clock output is held high while disabled, which is also while the cod0-cod1 bits are set. if the ckout clock output is low at the moment the cod0-cod1 bits are set, then the ckout clock output will complete the low cycle and then be disabled high. if the programmer re-enables the ckout clock output before it reaches the high logic level dur- ing the disabling process, the ckout operation will be unaffected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pll operation considerations 9 - 14 pll clock oscillator motorola while the pll is regaining lock, the ckout clock output remains at the same logic level it held when the pll lost lock, which is when the clocks were frozen in the dsp. when the chip enters the wait processing state, the core phases are disabled but ck- out continues to operate. when pll is disabled, ckout will be fed from extal. if df>1 and ckos 1 csrc, then the programmer must change either ckos or csrc be- fore taking any action that causes the pll to lose and subsequently regain lock, such as changing the multiplication factor, enabling pll operation, or recovering from the stop state with pstp=0. any change of the ckos or csrc bits must be done while df=1. 9.4.9 synchronization among extal, ckout, and the internal clock low clock skew between extal and ckout is guaranteed only if mf 4. the synchro- nization between ckout and the internal chip activity and port a timing is guaranteed in all cases where ckos=csrc and the bits have never differed from one another. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10- 2 on-chip emulation (once) motorola section 10 on-chip emulation (once) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents 10 - 3 on-chip emulation (once) motorola section 10.1 introduction ......................................................................3 section 10.2 on-chip emulation (once) pins ......................................3 section 10.3 once controller and serial interface ..................6 section 10.4 once memory breakpoint logic ..................................11 section 10.5 once trace logic ..............................................................13 section 10.6 methods of entering the debug mode ....................14 section 10.7 pipeline information and global data bus register .......................................................................16 section 10.8 program address bus history buffer ....................18 section 10.9 serial protocol description ......................................19 section 10.10 dsp56k target site debug system requirements ..................................................................19 section 10.11 using the once .................................................................20 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
on-chip emulation introduction 10- 4 on-chip emulation (once) motorola 10.1 on-chip emulation introduction the dsp56k on-chip emulation (once) circuitry provides a sophisticated debugging tool that allows simple, inexpensive, and speed independent access to the processor?s inter- nal registers and peripherals. once tells application programmers exactly what the status is within the registers, memory locations, buses, and even the last five instructions that were executed. once capabilities are accessible through a standard set of pins which are the same on all of the members of the dsp56k processor family. figure 10-1 shows the components of the once circuitry. once is shown as part of the dsp56k central pro- cessing module in figure 10-2. 10.2 on-chip emulation (once) pins the following paragraphs describe the once pins associated with the once controller and serial interface component shown in figure 10-1. 10.2.1 debug serial input/chip status 0 (dsi/os0) serial data or commands are provided to the once controller through the dsi/os0 pin when it is an input. the data received on the dsi pin will be recognized only when the dsp56k has entered the debug mode of operation. data is latched on the falling edge of the dsck serial clock (described in section 10.2.2). data is always shifted into the once serial port most significant bit (msb) first. when the dsi/os0 pin is an output, it works in conjunction with the os1 pin to provide chip status information (see table 10-1). the pab fifo breakpoint registers and comparators pipeline information breakpoint and trace logic once controller and serial interface pab yab xab . . pdb pil gdb dso dr dsi/os0 dsck/os1 . figure 10-1 once block diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
on-chip emulation (once) pins motorola on-chip emulation (once) 10 - 5 dsi/os0 pin is an output when the processor is not in debug mode. when switching from output to input, the pin is three-stated. during hardware reset, this pin is defined as an out- put and it is driven low. note: to avoid possible glitches, an external pull-down resistor should be attached to this pin. clock generator peripheral pins internal data bus switch program ram/rom expansion program interrupt controller program decode controller program address generator ya b xab pa b ydb xdb pdb gdb modc/nmi modb/irqb reset data alu 24x24 + 56 ? 56-bit mac two 56-bit accumulators external address bus switch bus control external data b u s switch address data 16 bits 24 bits port a moda/irqa pll x memory ram/rom expansion y memory ram/rom expansion address generation unit once peripheral modules expansion area control 24-bit 56k mod- figure 10-2 dsp56k block diagram program control unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
on-chip emulation (once) pins 10- 6 on-chip emulation (once) motorola 10.2.2 debug serial clock/chip status 1 (dsck/os1) the dsck/os1 pin supplies the serial clock to the once when it is an input. the serial clock provides pulses required to shift data into and out of the once serial port. (data is clocked into the once on the falling edge and is clocked out of the once serial port on the rising edge.) the debug serial clock frequency must be no greater than 1/8 of the pro- cessor clock frequency. when an output, this pin, in conjunction with the os0 pin, provides information about the chip status (see table 10-1). the dsck/os1 pin is an out- put when the chip is not in debug mode. when switching from output to input, the pin is three-stated. during hardware reset, this pin is defined as an output and it is driven low. note: to avoid possible glitches, an external pull-down resistor should be attached to this pin. 10.2.3 debug serial output (dso) serial data is read from the once through the dso pin, as specified by the last command received from the external command controller. data is always shifted out the once serial port most significant bit (msb) first. data is clocked out of the once serial port on the ris- ing edge of dsck. the dso pin also provides acknowledge pulses to the external command controller. when the chip enters the debug mode, the dso pin will be pulsed low to indicate (ac- knowledge) that the once is waiting for commands. after receiving a read command, the dso pin will be pulsed low to indicate that the requested data is available and the once serial port is ready to receive clocks in order to deliver the data. after receiving a write command, the dso pin will be pulsed low to indicate that the once serial port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided. during hardware reset and when the processor is idle, the dso pin is held high. table 10-1 chip status information os1 os0 status 0 0 normal state 0 1 stop or wait state 1 0 chip waits for bus mastership 1 1 chip waits for end of memory wait states (due to wt assertion or bcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
once controller and serial interface motorola on-chip emulation (once) 10 - 7 10.2.4 debug request input (dr ) the debug request input (dr ) allows the user to enter the debug mode of operation from the external command controller. when dr is asserted, it causes the dsp56k to finish the current instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the dsi line. while in debug mode, the dr pin lets the user reset the once controller by asserting it and deasserting it after receiving acknowledge. it may be necessary to reset the once controller in cases where synchronization between the once controller and external circuitry is lost. dr must be deasserted after the once responds with an acknowledge on the dso pin and before sending the first once command. asserting dr will cause the chip to exit the stop or wait state. 10.3 once controller and serial interface the once controller and serial interface contains the following blocks: once command register, bit counter, once decoder, and the status/control register. figure 10-3 illustrates a block diagram of the once controller and serial interface 10.3.1 once command register (ocr) the ocr is an 8-bit shift register that receives its serial data from the dsi pin. it holds the 8-bit commands to be used as input for the once decoder. the command register is shown in figure 10-4. once command register dsi dsck bit counter status and control register dso mode select once decoder bit 7 bit 23 isdebug isbkpt isswdbg isdr istrace reg write reg read . . . . . figure 10-3 once controller and serial interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
once controller and serial interface 10- 8 on-chip emulation (once) motorola 10.3.1.1 register select (rs4-rs0) bits 0-4 the register select bits define which register is source (destination) for the read (write) operation. table 10-2 indicates the once register addresses. table 10-2 once register addressing rs4-rs0 register selected 00000 once status and control register (oscr) 00001 memory breakpoint counter (ombc) 00010 reserved 00011 trace counter (otc) 00100 reserved 00101 reserved 00110 memory upper limit register (omulr) 00111 memory lower limit register (omllr) 01000 gdb register (ogdbr) 01001 pdb register (opdbr) 01010 pab register for fetch (opabfr) 01011 pil register (opilr) 01100 clear memory breakpoint counter (ombc) 01101 reserved 01110 clear trace counter (otc) 01111 reserved 10000 reserved 10001 program address bus fifo and increment counter 10010 reserved 10011 pab register for decode (opabdr) 101xx reserved 11xx0 reserved 11x0x reserved 110xx reserved 11111 no register selected rs0 0 rs1 1 rs2 2 rs3 3 rs4 4 ex 5 go 6 r/w 7 figure 10-4 once command register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
once controller and serial interface motorola on-chip emulation (once) 10 - 9 10.3.1.2 exit command (ex) bit 5 if the ex bit is set, the processor will leave the debug mode and resume normal operation. the exit command is executed only if the go command is issued, and the operation is write to opdbr or read/write to no register selected. otherwise the ex bit is ignored. 10.3.1.3 go command (go) bit 6 if the go bit is set, the chip will execute the instruction which resides in the pil register. to execute the instruction, the processor leaves the debug mode, and the status is reflect- ed in the os0-os1 pins. the processor will return to the debug mode immediately after executing the instruction if the ex bit is cleared. the processor goes on to normal opera- tion if the ex bit is set. the go command is executed only if the operation is write to opdbr or read/write to no register selected. otherwise the go bit is ignored. 10.3.1.4 read/write command (r/w) bit 7 the r/w bit specifies the direction of data transfer. the table below describes the options defined by the r/w bit. 10.3.2 once bit counter (obc) the obc is a 5-bit counter associated with shifting in and out the data bits. the obc is incremented by the falling edges of the dsck. the obc is cleared during hardware reset and whenever the dsp56k acknowledges that the debug mode has been entered. the obc supplies two signals to the once decoder: one indicating that the first 8 bits were ex action 0 remain in debug mode 1 leave debug mode go action 0 inactive (no action taken) 1 execute instruction in pil r/w action 0 write the data associated with the command into the register specited by rs4-rs0 1 read the data contained in the register specited by rs4-rs0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
once controller and serial interface 10- 10 on-chip emulation (once) motorola shifted in (so a new command is available) and the second indicating that 24 bits were shifted in (the data associated with that command is available) or that 24 bits were shifted out (the data required by a read command was shifted out). 10.3.3 once decoder (odec) the odec supervises the entire once activity. it receives as input the 8-bit command from the ocr, two signals from obc (one indicating that 8 bits have been received and the other that 24 bits have been received), and two signals indicating that the processor was halted. the odec generates all the strobes required for reading and writing the se- lected once registers. 10.3.4 once status and control register (oscr) the status and control register is a 16-bit register used to select the events that will put the chip in debug mode and to indicate the reason for entering debug mode. the control bits are read/write while the status bits are read only. see figure 10-5. 10.3.4.1 memory breakpoint control (bc0-bc3) bits 0-3 these control bits enable memory breakpoints. they allow memory breakpoints to occur when a memory address is within the low and high memory address registers and will se- lect whether the breakpoint will be recognized for read, write, or fetch (program space) accesses. these bits are cleared on hardware reset. see table 10-3 for the definition of the bc0-bc3 bits. when bc3-bc0=0001, program memory breakpoints are enabled for any fetch access to the program space (true and false fetches, fetches of 2 nd word, etc.). explicit program memory accesses resulting from movep and movem instructions to/from program memory space are ignored. when bc3-bc0=0010, program memory breakpoints are enabled for any read access to the program space (movep and movem instructions from p: memory space, true and false fetches, fetches of 2 nd word, etc.). explicit program memory write accesses resulting from movep and movem instructions to p: memory space are ignored. * reserved, read as zero, should be written with zero for future compatibility. bc0 0 bc1 1 bc2 2 bc3 3 tme 4 * 5 swo 8 mbo 9 to 10 11 * .... * 7 * 6 15 figure 10-5 once status and control register (oscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
once controller and serial interface motorola on-chip emulation (once) 10 - 11 when bc3-bc0=0011, program memory breakpoints are enabled for any read or write access to the program space (any kind of move, true and false fetches, fetches of sec- ond word, etc.). when bc3-bc0=0100, program memory breakpoints are enabled only for fetches of the first instruction word of instructions that are actually executed. aborted instructions and prefetched instructions that are discarded (such as jump targets that are not taken) are ignored by the breakpoint logic. when bc3-bc0=0101, 0110 or 0111, program memory breakpoints are enabled only for explicit program memory access resulting from movep or movem instructions to/from p: memory space. 10.3.4.2 trace mode enable (tme) bit 4 the tme control bit, when set, enables the trace mode of operation (see section 10.5). this bit is cleared on hardware reset. 10.3.4.3 reserved (bits 5-7, 11-15) these bits are reserved for future use. they read as zero and should be written with zero for future compatibility. table 10-3 memory breakpoint control table bc3 bc2 bc1 bc0 description 0 0 0 0 breakpoint disabled 0 0 0 1 breakpoint on any fetch (including aborted instructions) 0 0 1 0 breakpoint on any p read (any fetch or move) 0 0 1 1 breakpoint on any p access (any fetch, p move r/w) 0 1 0 0 breakpoint on executed fetches only 0 1 0 1 breakpoint on p space write 0 1 1 0 breakpoint on p space read (no fetches) 0 1 1 1 breakpoint on p space write or read (no fetches) 1 0 0 0 reserved 1 0 0 1 breakpoint on x space write 1 0 1 0 breakpoint on x space read 1 0 1 1 breakpoint on x space write or read 1 1 0 0 reserved 1 1 0 1 breakpoint on y space write 1 1 1 0 breakpoint on y space read 1 1 1 1 breakpoint on y space write or read f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
once memory breakpoint logic 10- 12 on-chip emulation (once) motorola 10.3.4.4 software debug occurrence (swo) bit 8 this read-only status bit is set when the processor enters debug mode of operation as a result of the execution of the debug or debugcc instruction with condition true. this bit is cleared on hardware reset or when leaving the debug mode with the go and ex bits set. 10.3.4.5 memory breakpoint occurrence (mbo) bit 9 this read-only status bit is set when a memory breakpoint occurs. this bit is cleared on hardware reset or when leaving the debug mode with the go and ex bits set. 10.3.4.6 trace occurrence (to) bit 10 this read-only status bit is set when the processor enters debug mode of operation, when the trace counter is zero and the trace mode has been armed. this bit is cleared on hard- ware reset or when leaving the debug mode with the go and ex bits set. 10.4 once memory breakpoint logic memory breakpoints may be set on program memory or data memory locations. also, the breakpoint does not have to be in a specific memory address but within an address range of where the program may be executing. this significantly increases the programmer?s ability to monitor what the program is doing in real-time. the breakpoint logic contains a latch for the addresses, registers that store the upper and lower address limit, comparators, and a breakpoint counter. figure 10-6 illustrates the block diagram of the once memory breakpoint logic. address comparators help to determine where a program may be getting lost or when data is being written to areas that should not be written to. they are also useful in halting a program at a specific point to examine/change registers or memory. using address com- parators to set breakpoints enables the user to set breakpoints in ram or rom in any op- erating mode. memory accesses are monitored according to the contents of the oscr. the low address comparator will generate a logic true signal when the address on the bus is greater than or equal to the contents of the lower limit register. the high address com- parator will generate a logic true signal when the address on the bus is less than or equal to the contents of the upper limit register. if the low address comparator and high address comparator both issue a logic true signal, the address is within the address range and the breakpoint counter is decremented if the contents are greater than zero. if zero, the counter is not decremented and the breakpoint exception occurs (isbkpt asserted). 10.4.1 memory address latch (omal) the memory address latch is a 16-bit register that latches the pab, xab or yab on every instruction cycle according to the bc3-bc0 bits in oscr. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
once memory breakpoint logic motorola on-chip emulation (once) 10 - 13 10.4.2 memory upper limit register (omulr) the 16-bit memory upper limit register stores the memory breakpoint upper limit. the omulr can be read or written through the once serial interface. before enabling break- points, omulr must be loaded by the external command controller. 10.4.3 memory lower limit register (omllr) the 16-bit memory lower limit register stores the memory breakpoint lower limit. the omllr can be read or written through the once serial interface. before enabling break- . memory address latch pab xab yab memory bus select lower limit register low address comparator upper limit register high address comparator higher dsi dso dsck breakpoint counter or equal lower or equal memory breakpoint selection bc3-bc0 dec breakpoint count=0 isbkpt occurred . . . . . . . figure 10-6 once memory breakpoint logic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
once trace logic 10- 14 on-chip emulation (once) motorola points, omllr must be loaded by the external command controller. 10.4.4 memory high address comparator (omhc) the omhc compares the current memory address (stored in omal) with the omulr contents. if omulr is higher than or equal to omal then the comparator delivers a signal indicating that the address is lower than or equal to the upper limit. 10.4.5 memory low address comparator (omlc) the omlc compares the current memory address (stored in omal) with the omllr con- tents. if omllr is lower than or equal to omal then the comparator delivers a signal in- dicating that the address is higher than or equal to the lower limit. 10.4.6 memory breakpoint counter (ombc) the 24-bit ombc is loaded with a value equal to the number of times, minus one, that a memory access event should occur before a memory breakpoint is declared. the memory access event is specified by the bc3-bc0 bits in the oscr register and by the memory upper and lower limit registers. on each occurrence of the memory access event, the breakpoint counter is decremented. when the counter has reached the value of zero and a new occurrence takes place, the chip will enter the debug mode. the ombc can be read, written, or cleared through the once serial interface. anytime the upper or lower limit registers are changed, or a different breakpoint event is selected in the oscr, the breakpoint counter must be written afterward. this assures that the once breakpoint logic is reset and that no previous events will affect the new break- point event selected. the breakpoint counter is cleared by hardware reset. 10.5 once trace logic the once trace logic allows the user to execute instructions in single or multiple steps before the chip returns to the debug mode and awaits once commands from the debug serial port. (the once trace logic is independent of the trace facility of the dsp56000/56001, which is operated through the trace interrupt discussed in section 7.3.3.3, and started by setting the trace bit in the processor?s status register discussed in section 5.4.2.12). the once trace logic block diagram is shown in figure 10-7. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
once trace logic motorola on-chip emulation (once) 10 - 15 the trace counter allows more than one instruction to be executed in real time before the chip returns to the debug mode of operation. this feature helps the software developer debug sections of code which do not have a normal flow or are getting hung up in infinite loops. the trace counter also enables the user to count the number of instructions exe- cuted in a code segment. to initiate the trace mode of operation, the counter is loaded with a value, the program counter is set to the start location of the instruction(s) to be executed real-time, the tme bit is set in the oscr, and the processor exits the debug mode by executing the appro- priate command issued by the external command controller. upon exiting the debug mode, the counter is decremented after each execution of an in- struction. interrupts are serviceable, and all instructions executed (including fast interrupt services and the execution of each repeated instruction) will decrement the trace counter. upon decrementing the trace counter to zero, the processor will re-enter the debug mode, the trace occurrence bit to in the oscr will be set, and the dso pin will be toggled to indicate that the processor has entered debug mode and is requesting service (istrace asserted). 10.5.1 trace counter (otc) the otc is a 24-bit counter that can be read, written, or cleared through the once serial interface. if n instructions are to be executed before entering the debug mode, the trace counter should be loaded with n-1. the trace counter is cleared by hardware reset. dsi dso dsck trace counter dec end of instruction count=0 istrace . . figure 10-7 once trace logic block diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
methods of entering the debug mode 10- 16 on-chip emulation (once) motorola 10.6 methods of entering the debug mode the chip acknowledges having entered the debug mode by pulsing low the dso line, in- forming the external command controller that the chip has entered the debug mode and is waiting for commands.the following paragraphs discuss conditions that bring the pro- cessor into the debug mode. 10.6.1 external debug request during reset holding the dr line asserted during the assertion of reset causes the chip to enter the debug mode. after receiving the acknowledge, the external command controller must deassert the d r line before sending the first command. note that in this case the chip does not execute any instruction before entering the debug mode. 10.6.2 external debug request during normal activity holding the dr line asserted during normal chip activity causes the chip to finish the ex- ecution of the current instruction and then enter the debug mode. after receiving the ac- knowledge, the external command controller must deassert the d r line before sending the first command. note that in this case the chip completes the execution of the current instruction and stops after the newly fetched instruction enters the instruction latch. this process is the same for any newly fetched instruction including instructions fetched by the interrupt processing, or those that will be aborted by the interrupt processing. 10.6.3 external debug request during stop asserting dr when the chip is in the stop state (i. e., has executed a stop instruction) and keeping it asserted until an acknowledge pulse in dso is produced causes the chip to exit the stop state and enter the debug mode. after receiving the acknowledge, the ex- ternal command controller must deassert d r before sending the first command. note that in this case, the chip completes the execution of the stop instruction and halts after the next instruction enters the instruction latch. 10.6.4 external debug request during wait asserting d r when the chip is in the wait state (i. e., has executed a wait instruction) and keeping it asserted until an acknowledge pulse in dso is produced causes the chip to exit the wait state and enter the debug mode. after receiving the acknowledge, the ex- ternal command controller must deassert dr before sending the first command. note that in this case, the chip completes the execution of the wait instruction and halts after the next instruction enters the instruction latch. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pipeline information and global data bus register motorola on-chip emulation (once) 10 - 17 10.6.5 software request during normal activity upon executing the debug or debugcc instruction when the specified condition is true, the chip enters the debug mode after the instruction following the debug instruction has entered the instruction latch. 10.6.6 enabling trace mode when the trace mode mechanism is enabled and the trace counter is greater than zero, the trace counter is decremented after each instruction execution. the completed execu- tion of an instruction when the trace counter is zero will cause the chip to enter the debug mode. note: only instructions actually executed cause the trace counter to decrement, i.e. an aborted instruction will not decrement the trace counter and will not cause the chip to enter the debug mode. 10.6.7 enabling memory breakpoints when the memory breakpoint mechanism is enabled with a breakpoint counter value of zero, the chip enters the debug mode after completing the execution of the instruction that caused the memory breakpoint to occur. in case of breakpoints on executed program memory fetches, the breakpoint will be acknowledged immediately after the execution of the fetched instruction. in case of breakpoints on data memory addresses (accesses to x, y or p memory spaces by move instructions), the breakpoint will be acknowledged after the completion of the instruction following the instruction that accessed the specified address. 10.7 pipeline information and global data bus register a number of on-chip registers store the chip pipeline status to restore the pipeline and re- sume normal chip activity upon return from the debug mode. figure 10-8 shows the block diagram of the pipeline information registers with the exception of the program address bus (pab) registers, which are shown in figure 10-9. 10.7.1 program data bus register (opdbr) the opdbr is a 24-bit latch that stores the value of the program data bus which was gen- erated by the last program memory access before the chip entered the debug mode. opdbr can be read or written through the once serial interface. it is affected by the op- erations performed during the debug mode and must be restored by the external com- mand controller when the chip returns to normal mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
program address bus history buffer 10- 18 on-chip emulation (once) motorola 10.7.2 pipeline instruction latch register (opilr) the opilr is a 24-bit latch that stores the value of the instruction latch before the debug mode is entered. opilr can only be read through the once serial interface. this register is affected by the operations performed during the debug mode and must be restored by the external command controller when returning to normal mode. since there is no direct write access to this register, this task is accomplished in the first write to opdbr after en- tering the debug mode or after executing the go command; the data from opdbr is transferred to opilr only in these cases. 10.7.3 global data bus register (ogdbr) the ogdbr is a 24-bit latch that can only be read through the once serial interface. ogdbr is not actually required from a pipeline status restore point of view but is required as a means of passing information between the chip and the external command controller. ogdbr is mapped on the x internal i/o space at address $fffc. whenever the external command controller needs the contents of a register or memory location, it will force the chip to execute an instruction that brings that information to ogdbr. then, the contents of ogdbr will be delivered serially to the external command controller by the command read gdb register. 10.8 program address bus history buffer there are two read-only pab registers which give pipeline information when the debug mode is entered. the opabfr register tells which opcode address is in the fetch stage of the pipeline and opabdr tells which opcode is in the decode stage. to ease debug- ging activity and keep track of program flow, a first-in-first-out (fifo) buffer stores the pdb register (opdbr) gdb register (ogdbr) dsi dso dsck pil register (opilr) pil pdb gdb figure 10-8 once pipeline information and gdb registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
program address bus history buffer motorola on-chip emulation (once) 10 - 19 addresses of the last five instructions that were executed. 10.8.1 pab register for fetch (opabfr) the opabfr is a 16-bit register that stores the address of the last instruction that was fetched before the debug mode was entered. the opabfr can only be read through the once serial interface. this register is not affected by the operations performed during the debug mode. 10.8.2 pab register for decode (opabdr) the opabdr is a 16-bit register that stores the address of the instruction currently in the instruction latch. this is the instruction that would have been decoded if the chip would not have entered the debug mode. opabdr can only be read through the serial interface. fetch address (opabfr) pab pab fifo register 0 decode address (opabdr) circular buffer pointer pab fifo shift register dso dsck pab fifo register 1 pab fifo register 2 pab fifo register 3 pab fifo register 4 figure 10-9 once pab fifo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial protocol description 10- 20 on-chip emulation (once) motorola this register is not affected by the operations performed during the debug mode. 10.8.3 pab fifo the pab fifo stores the addresses of the last five instructions that were executed. the fifo is implemented as a circular buffer containing five 16-bit registers and one 3-bit counter. all the registers have the same address but any read access to the fifo address will cause the counter to increment, making it point to the next fifo register. the registers are serially available to the external command controller through their common fifo ad- dress. figure 10-9 shows the block diagram of the pab fifo. the fifo is not affected by the operations performed during the debug mode except for the fifo pointer incre- ment when reading the fifo. when entering the debug mode, the fifo counter will be pointing to the fifo register containing the address of the oldest of the five executed in- structions. the first fifo read will obtain the oldest address and the following fifo reads will get the other addresses from the oldest to the newest (the order of execution). to ensure fifo coherence, a complete set of five reads of the fifo must be performed because each read increments the fifo pointer, thus making it point to the next location. after five reads the pointer will point to the same location it pointed to before starting the read procedure. 10.9 serial protocol description the following protocol permits an efficient means of communication between the once?s external command controller and the dsp56k chip. before starting any debugging activ- ity, the external command controller must wait for an acknowledge on the dso line, indi- cating that the chip has entered the debug mode. the external command controller com- municates with the chip by sending 8-bit commands that may be accompanied by 24 bits of data. both commands and data are sent or received most significant bit first. after send- ing a command, the external command controller must wait for the processor to acknowl- edge execution of the command before it may send a new command. when accessing once 16-bit registers, the register contents appear in the 16 most sig- nificant bits in the 24-bit data field, and the 8 least significant bits are zeroed. 10.9.1 once commands the once commands may be classified as follows: read commands (when the chip will deliver the required data). write commands (when the chip will receive data and write the data in one of the once registers). commands that do not have data transfers associated with them. the commands are 8 bits long and have the format shown in figure 10-4. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dsp56k target site debug system requirements motorola on-chip emulation (once) 10 - 21 10.10 dsp56k target site debug system requirements a typical dsp56k debug environment consists of a target system where the dsp56k re- sides in the user defined hardware. the debug serial port interfaces to the external com- mand controller over a 6-wire link which includes the 4 once wires, a ground, and a reset wire. the reset wire is optional and is only used to reset the dsp56k and its associated circuitry. the external command controller acts as the medium between the dsp56k target system and a host computer. the external command controller circuit acts as a dsp56k serial debug port driver and host computer command interpreter. the controller issues com- mands based on the host computer inputs from a user interface program which commu- nicates with the user. 10.11 using the once the following notations are used: ack = wait for acknowledge on the dso pin clk = issue 24 clocks to read out data from the selected register 10.11.1 begin debug activity most of the debug activities have the following beginning: 1. ack 2. save pipeline information: a. send command read pdb register (10001001) b. ack c. clk d. send command read pil register (10001011) e. ack f. clk 3. read pab fifo and fetch/decode info (this step is optional): a. send command read pab address for fetch (10001010) b. ack c. clk d. send command read pab address for decode (10010011) e. ack f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
using the once 10- 22 on-chip emulation (once) motorola f. clk g. send command read fifo register and increment counter (10010001) h. ack i. clk j. send command read fifo register and increment counter (10010001) k. ack l. clk m. send command read fifo register and increment counter (10010001) n. ack o. clk p. send command read fifo register and increment counter (10010001) q. ack r. clk s. send command read fifo register and increment counter (10010001) t. ack u. clk 10.11.2 displaying a specified register 1. send command write pdb register, go, no ex (01001001). the once con- troller selects pdb as destination for serial data. 2. ack 3. send the 24-bit dsp56k opcode: move reg,x:ogdb after 24 bits have been received, the pdb register drives the pdb. the once con- troller releases the chip from the debug mode, the chip executes the move instruction, and the contents of the register specified in the instruction are loaded in the gdb register. the signal that marks the end of the instruction returns the chip to the debug mode. 4. ack 5. send command read gdb register (10001000) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
using the once motorola on-chip emulation (once) 10 - 23 the once controller selects gdb as source for serial data. 6. ack 7. clk 10.11.3 displaying x memory area starting from address xxxx this command uses r0 to minimize serial traffic. 1. send command write pdb register, go, no ex (01001001). the once controller selects pdb as destination for serial data. 2. ack 3. send the 24-bit dsp56k opcode: move r0,x:ogdb after 24 bits have been received the pdb register drives the pdb. the once con- troller releases the chip from the debug mode and the contents of r0 are loaded in the gdb register. the signal that marks the end of the instruction returns the chip to the debug mode. 4. ack 5. send command read gdb register (10001001) the once controller selects gdb as source for serial data. 6. ack 7. clk the external command controller generates 24 clocks that shift out the contents of the gdb register. the value of r0 is thus saved and should be restored before ex- iting the debug mode. 8. send command write pdb register, no go, no ex (00001001) once controller selects pdb as destination for serial data. 9. ack 10. send the 24-bit dsp56k opcode: move #$xxxx,r0 after 24 bits have been received, the pdb register drives the pdb. the once con- troller causes the processor to load the opcode. 11. ack 12. send command write pdb register, go, no ex (01001001) the once controller selects pdb as destination for serial data. 13. ack 14. send the 24-bit 2 nd word of: move #$xxxx,r0 (the xxxx field). after 24 bits have been received, the pdb register drives the pdb. the once con- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
using the once 10- 24 on-chip emulation (once) motorola troller releases the chip from the debug mode and the instruction starts execution. the signal that marks the end of the instruction returns the chip to the debug mode. 15. ack 16. send command write pdb register, go, no ex (01001001) the once controller selects pdb as destination for serial data. 17. ack 18. send the 24-bit dsp56k opcode: move x:(r0)+,x:ogdb after 24 bits have been received, the pdb register drives the pdb. the once con- troller releases the chip from the debug mode and the contents of x:(r0) are loaded in the gdb register. the signal that marks the end of the instruction re- turns the chip to the debug mode. 19. ack 20. send command read gdb register (10001000) the once controller selects gdb as source for serial data. 21. ack 22. clk 23. send command no register selected, go, no ex (01011111) the once controller releases the chip from the debug mode and the instruction is executed again in a repeat-like fashion. the signal that marks the end of the instruction returns the chip to the debug mode. 24. ack 25. send command read gdb register (10001000) the once controller selects gdb as source for serial data. 26. ack 27. clk 28. repeat from step 23 until the entire memory area is examined. 29. after finishing reading the memory, r0 should to be restored as follows. 30. send command write pdb register, no go, no ex (00001001) once controller selects pdb as destination for serial data. 31. ack 32. send the 24-bit dsp56k opcode: move #saved_r0,r0 after 24 bits have been received, the pdb register drives the pdb. the once con- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
using the once motorola on-chip emulation (once) 10 - 25 troller causes the processor to load the opcode. 33. ack 34. send command write pdb register, go, no ex (01001001) the once controller selects pdb as destination for serial data. 35. ack 36. send the 24-bit second word of: move #saved_r0,r0 (the saved_r0 field). after 24 bits have been received, the pdb register drives the pdb. the once con- troller releases the chip from the debug mode and the instruction starts execution. the signal that marks the end of the instruction returns the chip to the debug mode. 37. ack f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
using the once 10- 26 on-chip emulation (once) motorola 10.11.4 executing a single-word dsp56k instruction while in debug mode 1. send command write pdb register, go, no ex (01001001). the once controller selects pdb as destination for serial data. 2. ack 3. send the single-word 24-bit dsp56k opcode to be executed. after 24 bits have been received, the pdb register drives the pdb. the once con- troller releases the chip from the debug mode and the chip executes the instruction. the signal that marks the end of the instruction returns the chip to the debug mode. some dsp56k instructions should not be executed in this state: do, rep, ille- gal or any opcode that is considered illegal, and debug. 4. ack 10.11.5 executing a two-word dsp56k instruction while in debug mode 1. send command write pdb register, no go, no ex (00001001). the once controller selects pdb as destination for serial data. 2. ack 3. send the first instruction word (24-bit dsp56k opcode) after 24 bits have been received, the pdb register drives the pdb. the once con- troller causes the processor to load the opcode. some dsp56k instructions should not be executed in this state: do, rep, ille- gal or any opcode that is considered illegal, and debug. 4. ack 5. send command write pdb register, go, no ex (01001001) the once controller selects pdb as destination for serial data. 6. ack 7. send the second 24-bit instruction word. after 24 bits have been received, the pdb register drives the pdb. the once con- troller releases the chip from the debug mode and the instruction starts execution. the signal that marks the end of the instruction returns the chip to the debug mode. 8. ack 10.11.6 returning from debug mode to normal mode there are two cases for returning from the debug mode in a single processor: control is returned to the program that was running before debug was initiated. jump to a different program location is executed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
using the once motorola on-chip emulation (once) 10 - 27 10.11.6.1 case 1: return to the previous program (return to normal mode) 1. send command write pdb register, no go, no ex (00001001) the once controller selects the pdb as the destination for serial data. also, the once controller selects the on-chip pab register as the source for the pab bus. 2. ack 3. send the 24 bits of the saved pil (instruction latch) value. after the 24 bits have been received, the pdb register drives the pdb. the once controller causes the pil to latch the pdb value. in this way, the pil is restored to the same state as before entering the debug mode. 4. ack 5. send command write pdb register, go, ex (01101001) the once controller selects pdb as destination for the serial data to follow. 6. ack 7. send the 24 bits of the saved pdb value. after the 24 bits have been received, the pdb register drives the pdb. in this way, the pdb is restored to the same state as before entering the debug mode. the ex bit causes the once controller to release the chip from the debug mode and the status bits in oscr are cleared. the go bit causes the chip to start executing instructions. 10.11.6.2 case 2: jump to a new program (go from address $xxxx) 1. send command write pdb register, no go, no ex (00001001) the once controller selects pdb as destination for serial data. also, the once controller selects the on-chip pab register as the source for the pab bus. 2. ack 3. send 24 bits of the opcode of a two-word jump instruction instead of the saved pil value. after the 24 bits have been received, the pdb register drives the pdb. the once controller causes the pil to latch the pdb value. in this way, the instruction latch will contain the opcode of the jump instruction which will cause the change in the program flow. 4. ack 5. send command write pdb register, go, ex (01101001) the once controller selects pdb as destination for serial data. 6. ack 7. send 24 bits of the jump target absolute address ($xxxxxx). after 24 bits have been received, the pdb register drives the pdb. in this way, the pdb contains the second word of the jump as required for the jump instruction ex- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
using the once 10- 28 on-chip emulation (once) motorola ecution. the ex bit causes the once controller to release the chip from the debug mode and the status bits in oscr are cleared. the go bit causes the chip to start executing the jump instruction which will then cause the chip to continue instruction execution from the target address. note that the trace counter will count the jump instruction so the current trace counter may need to be corrected if the trace mode is enabled. 10.11.7 debugging multiprocessor systems with a single external command controller in multiprocessor systems, each processor may be individually debugged as described above. when simultaneous exit of the debug state is desired for more than one processor, each processor must first be loaded with the required pil and pdb values where process- ing should proceed. this is accomplished by the following sequence as applied to each processor: 1. send command write pdb register, no go, no ex (00001001) the once controller selects pdb as destination for serial data. also, the once controller selects the on-chip pab register as the source for the pab bus. 2. ack 3. send 24 bits of either the opcode of a 2-word jump instruction or the saved pil val- ue. after the 24 bits have been received, the pdb register drives the pdb. the once controller causes the pil to latch the pdb value. 4. ack 5. send command write pdb register, no go, no ex (00001001) the once controller selects pdb as destination for serial data. 6. ack 7. send 24 bits of either the jump target absolute address ($xxxxxx) or the saved pdb value. after 24 bits have been received, the pdb register drives the pdb. 8. ack at this point, all processors should have the required pil and pdb values while still in de- bug mode. to return all processors to the normal execution state simultaneously, the fol- lowing command should be issued to all processors in parallel: 9. send command no register selected, go, ex (01111111) the once controller releases the chips from the debug mode and instruction exe- cution is resumed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
using the once motorola on-chip emulation (once) 10 - 29 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola additional support 11 - 1 section 11 additional support dr. bub electronic bulletin board audio: codec routines: dtmf routines: fast fourier transforms: filters: floating-point routines: functions: lattice filters: matrix operations: reed-solomon encoder: sorting routines: speech: standard i/o equates: tools and utilities: motorola dsp news motorola field application engineers design hotline e 1-800-521-6274 dsp applications assistance e (512) 891-3230 dsp marketing information e (512) 891-2030 dsp third-party support information e (512) 891-3098 dsp university support e (512) 891-3098 dsp training courses e (602) 994-6900 motorola dsp product support dsp56000clasx assembler/simulator c language compiler dsp56000adsx application development system motorola dsp ola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents 11- 2 additional support motorola section 11.1 user support .....................................................................3 section 11.2 motorola dsp product support ...............................4 11.2.1 dsp56000clasx assembler/simulator ...........................................4 11.2.2 macro cross assembler features: ....................................................4 11.2.3 simulator features: ...........................................................................5 11.2.4 dsp56kccx language compiler features: .....................................5 section 11.3 dsp56kadsx application development system ......6 11.3.1 dsp56kads application development system hardware features: .....................................6 11.3.2 dsp56kadsx application development system software features: .......................................6 11.3.3 support integrated circuits: 7 section 11.4 dr. bub electronic bulletin board .............................7 section 11.5 motorola dsp news .........................................................16 section 11.6 motorola field application engineers ...................16 section 11.7 design hotlinee 1-800-521-6274 .......................................16 section 11.8 dsp help line e (512) 891-3230 ..........................................16 section 11.9 marketing informatione (512) 891-2030 ......................16 section 11.10 third-party support information e (512) 891-3098 16 section 11.11 university support e (512) 891-3098 ...........................16 section 11.12 training courses e (602) 897-3665 or (800) 521-6274 .17 section 11.13 reference books and manuals .................................17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
user support motorola additional support 11 - 3 11.1 user support user support from the conception of a design through completion is available from motorola and third-party companies as shown in the following list: motorola third party design data sheets data acquisition packages application notes filter design packages application bulletins operating system software software examples simulator prototyping assembler logic analyzer with linker dsp56000/dsp56001 rom packages c compiler in-circuit emulators simulator data acquisition cards application development dsp development system cards system (ads) operating system software in-circuit emulator debug software cable for ads design application development data acquisition packages verification system (ads) logic analyzer with in-circuit emulator dsp56000/dsp56001 rom packages simulator data acquisition cards dsp development system cards application-specific development tools debug software f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola dsp product support 11 - 4 additional support motorola the following is a partial list of the support available for the dsp56000/dsp56001. addi- tional information can be obtained through dr. bub or the appropriate support telephone service. 11.2 motorola dsp product support dsp56000clasx design-in software package which includes: relocatable macro assembler linker simulator (simulates single or multiple dsp56k processors)) librarian dsp56kccx gnu c compiler dsp56000/dsp56001 applications development system (ads) support integrated circuits dsp bulletin board (dr. bub) motorola dsp newsletter motorola field application engineers (faes) see your local telephone directory for the motorola semiconductor sector sales oftce telephone number. design hotline applications assistance marketing information third-party support information university support information 11.2.1 dsp56000clasx assembler/simulator the macro cross assembler and simulator run on: 1. ibm ? pcs (-386 or higher) under dos 2.x and 3.x 2. macintosh ? ii under mac os 4.1 or later 3. sun-4 ? under unix ? bsd 4.2 4. next ? under mach 11.2.2 macro cross assembler features: production of relocatable object modules compatible with linker program when in relocatable mode production of absolute tles compatible with simulator program when in absolute mode supports full instruction set, memory spaces, and parallel data transfer telds of f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola dsp product support motorola additional support 11 - 5 the dsp56k family of processors modular programming features: local labels, sections, and external detnition/ref- erence directives nested macro processing capability with support for macro libraries complex expression evaluation including boolean operators built-in functions for data conversion, string comparison, and common transcen- dental math functions directives to detne circular and bit-reversed buffers extensive error checking and reporting 11.2.3 simulator features: simulation of all dsp56k family members simulation of multiple dsp56ks linkable object code modules: enondisplay simulator library edisplay simulator library c language source code for: escreen management functions eterminal i/o functions esimulation examples single stepping through object programs up to 99 conditional or unconditional breakpoints program patching using a single-line assembler/disassembler instruction, clock cycle, and histogram counters session and/or command logging for later reference ascii input/output tles for peripherals help-tle and help-line display of simulator commands loading and saving of tles to/from simulator memory macro command detnition and execution display enable/disable of registers and memory hexadecimal/decimal/binary calculator 11.2.4 dsp56kccx language compiler features: gnu - ansi standard structures/unions floating point f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dsp56kadsx application development system 11 - 6 additional support motorola in-line assembler language code compatibility full function preprocessor for: emacro definition/expansion efile inclusion econditional compilation full error detection and reporting 11.3 dsp56kadsx application development system 11.3.1 dsp56kads application development system hardware features: processor speed independent multiple (up to 8) application development module (adm) support with program- mable adm addresses 8k/32kx24 user-contgurable ram for dsp56k code development 1kx24 monitor rom expandable to 4kx24 96-pin euro-card connector making all dsp56k pins accessible in-circuit emulation capabilities when used with the dsp56kemultrcabl cable separate berg pin connectors for alternate accessing of serial or host/dma ports adm can be used in stand-alone contguration no external power supply needed when connected to a host platform 11.3.2 dsp56kadsx application development system software features: single/multiple stepping through dsp56k object programs up to 99 conditional or unconditional breakpoints program patching using a single-line assembler/disassembler session and/or command logging for later reference loading and saving tles to/from adm memory macro command detnition and execution display enable/disable of registers and memory debug commands supporting multiple adms hexadecimal/decimal/binary calculator host operating system commands from within ads user interface program multiple os i/o tle access from dsp56k object programs fully compatible with the dsp56kclasx design-in software package on-line help screens for each command and dsp56k register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board motorola additional support 11 - 7 11.3.3 support integrated circuits: 8kx24 static ram e mc56824 dsp56adc16 16-bit, sigma-delta 100-khz analog-to-digital converter dsp56401 aes/ebu processor dsp56200 fir tlter 11.4 dr. bub electronic bulletin board dr. bub is an electronic bulletin board which provides free source code for a large variety of topics that can be used to develop applications with motorola dsp products. the soft- ware library contains files including ffts, fir filters, iir filters, lattice filters, matrix alge- bra routines, companding routines, floating-point routines, and others. in addition, the latest product information and documentation (including information on new products and improvements to existing products) is posted. questions about motorola dsp prod- ucts posted on dr. bub are answered promptly. access to dr. bub is through calling (512) 891-3771 using a modem set to 8 data bits, no parity, and 1 stop bit . dr. bub will automatically set the data transfer rate to match your modem (9600, 4800, 2400, 1200 or 300 bps). a partial list of the software available on dr. bub follows. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board 11 - 8 additional support motorola audio: rvb1.asm 1.0 easy-to-read reverberation routine 17056 rvb2.asm 1.0 same as rvb1.asm but optimized 15442 stereo.hlp 1.0 help file for stereo.asm 620 dge.asm 1.0 digital graphic equalizer code from 14880 codec routines: loglin.asm 1.0 companded codec to linear pcm data 4572 conversion loglin.hlp help for loglin.asm 1479 loglint.asm 1.0 test program for loglin.asm 2184 loglint.hlp help for loglint.asm 1993 linlog.asm 1.1 linear pcm to companded codec data 4847 conversion linlog.hlp help for linlog.asm 1714 dtmf routines: clear.cmd 1.0 explained in read.me file 119 data.lod 1.0 421 det.asm 1.0 subroutine used in iir dtmf 5923 dtmf.asm 1.0 main routine used in iir dtmf 10685 dtmf.mem 1.0 memory for dtmf routine 48 dtmfmstr.asm 1.0 main routine for multichannel dtmf 7409 dtmfmstr.mem 1.0 memory for multichannel dtmf routine 41 dtmftwo.asm 1.0 10256 ex56.bat 1.0 94 genxd.lod 1.0 data file 183 genyd.lod 1.0 data file 180 goertzel.asm 1.0 goertzel routine 4393 goertzel.lnk 1.0 link file for goertzel routine 6954 goertzel.lst 1.0 list file for goertzel routine 11600 load.cmd 1.0 46 tstgoert.mem 1.0 memory for goertzel routine 384 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board motorola additional support 11 - 9 sub.asm 1.0 subroutine linked for use in iir dtmf 2491 read.me 1.0 instructions 738 fast fourier transforms: sincos.asm 1.2 sine-cosine table generator for ffts 1185 sincos.hlp help for sincos.asm 887 sinewave.asm 1.1 full-cycle sine wave table generator 1029 generator macro sinewave.hlp for sinewave.asm 1395 fftr2a.asm 1.1 radix 2, in-place, dit fft (smallest) 3386 fftr2a.hlp help for fftr2a.asm 2693 fftr2at.asm 1.1 test program for ffts (fftr2a.asm) 999 fftr2at.hlp help for fftr2at.asm 563 fftr2b.asm 1.1 radix 2, in-place, dit fft (faster) 4290 fftr2b.hlp help for fftr2b.asm 3680 fftr2c.asm 1.2 radix 2, in-place, dit fft (even faster) 5991 fftr2c.hlp help for fftr2c.asm 3231 fftr2d.asm 1.0 radix 2, in-place, dit fft (using 3727 dsp56001 sine-cosine rom tables) fftr2d.hlp help for fftr2d.asm 3457 fftr2dt.asm 1.0 test program for fftr2d.asm 1287 fftr2dt.hlp help for fftr2dt.asm 614 fftr2e.asm 1.0 1024 point, non-in-place, fft (3.39ms) 8976 fftr2e.hlp help for fftr2e.asm 5011 fftr2et.asm 1.0 test program for fftr2e.asm 984 fftr2et.hlp help for fftr2et.asm 408 dct1.asm 1.1 discrete cosine transform using fft 5493 dct1.hlp 1.1 help file for dct1.asm 970 fftr2cc.asm 1.0 radix 2, in-place decimation-in-time 6524 complex fft macro fftr2cc.hlp 1.0 help file for fftr2cc.asm 3533 fftr2cn.asm 1.0 radix 2, decimation-in-time complex fft 6584 macro with normally ordered input/output document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board 11 - 10 additional support motorola fftr2cn.hlp 1.0 help file for fftr2cn.asm 2468 fftr2en.asm 1.0 1024 point, not-in-place, complex fft 9723 macro with normally ordered input/output fftr2en.hlp 1.0 help file for fftr2en.asm 4886 dhit1.asm 1.0 routine to compute hilbert transform 1851 in the frequency domain dhit1.hlp 1.0 help file for dhit1.asm 1007 fftr2bf.asm 1.0 radix-2, decimation-in-time fft with 13526 block floating point fftr2bf.hlp 1.0 help file for fftr2bf.asm 1578 fftr2aa.asm 1.0 fft program for automatic scaling 3172 filters: fir.asm 1.0 direct form fir filter 545 fir.hlp help for fir.asm 2161 firt.asm 1.0 test program for fir.asm 1164 iir1.asm 1.0 direct form second order all pole 656 iir filter iir1.hlp help for iir1.asm 1786 iir1t.asm 1.0 test program for iir1.asm 1157 iir2.asm 1.0 direct form second order all pole 801 iir filter with scaling iir2.hlp help for iir2.asm 2286 iir2t.asm 1.0 test program for iir2.asm 1311 iir3.asm 1.0 direct form arbitrary order all 776 pole iir filter iir3.hlp help for iir3.asm 2605 iir3t.asm 1.0 test program for iir3.asm 1309 iir4.asm 1.0 second order direct canonic iir filter 713 (biquad iir filter) iir4.hlp help for iir4.asm 2255 iir4t.asm 1.0 test program for iir4.asm 1202 iir5.asm 1.0 second order direct canonic iir filter 842 with scaling (biquad iir filter) iir5.hlp help for iir5.asm 2803 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board motorola additional support 11 - 11 iir5t.asm 1.0 test program for iir5.asm 1289 iir6.asm 1.0 arbitrary order direct canonic iir 923 filter iir6.hlp help for iir6.asm 3020 iir6t.asm 1.0 test program for iir6.asm 1377 iir7.asm 1.0 cascaded biquad iir filters 900 iir7.hlp help for iir7.asm 3947 iir7t.asm 1.0 test program for iir7.asm 1432 lms.hlp 1.0 lms adaptive filter algorithm 5818 transiir.asm 1.0 implements the transposed iir filter 1981 transiir.hlp 1.0 help file for transiir.asm 974 floating-point routines: fpdef.hlp 2.0 storage format and arithmetic 10600 representation definition fpcalls.hlp 2.1 subroutine calling conventions 11876 fplist.asm 2.0 test file that lists all subroutines 1601 fprevs.hlp 2.0 latest revisions of floating-point lib 1799 fpinit.asm 2.0 library initialization subroutine 2329 fpadd.asm 2.0 floating point add 3860 fpsub.asm 2.1 floating point subtract 3072 fpcmp.asm 2.1 floating point compare 2605 fpmpy.asm 2.0 floating point multiply 2250 fpmac.asm 2.1 floating point multiply-accumulate 2712 fpdiv.asm 2.0 floating point divide 3835 fpsqrt.asm 2.0 floating point square root 2873 fpneg.asm 2.0 floating point negate 2026 fpabs.asm 2.0 floating point absolute value 1953 fpscale.asm 2.0 floating point scaling 2127 fpfix.asm 2.0 floating to fixed point conversion 3953 fpfloat.asm 2.0 fixed to floating point conversion 2053 fpceil.asm 2.0 floating point ceil subroutine 1771 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board 11 - 12 additional support motorola fpfloor.asm 2.0 floating point floor subroutine 2119 durbin.asm 1.0 solution for lpc coefficients 5615 durbin.hlp 1.0 help file for durbin.asm 2904 fpfrac.asm 2.0 floating point fraction subroutine 1862 functions: log2.asm 1.0 log base 2 by polynomial 1118 approximation log2.hlp help for log2.asm 719 log2t.asm 1.0 test program for log2.asm 1018 log2nrm.asm 1.0 normalizing base 2 logarithm macro 2262 log2nrm.hlp help for log2nrm.asm 676 log2nrmt.asm 1.0 test program for log2nrm.asm 1084 exp2.asm 1.0 exponential base 2 by polynomial 926 approximation exp2.hlp help for exp2.asm 759 exp2t.asm 1.0 test program for exp2.asm 1019 sqrt1.asm 1.0 square root by polynomial 991 approximation, 7 bit accuracy sqrt1.hlp help for sqrt1.asm 779 sqrt1t.asm 1.0 test program for sqrt1.asm 1065 sqrt2.asm 1.0 square root by polynomial 899 approximation, 10 bit accuracy sqrt2.hlp help for sqrt2.asm 776 sqrt2t.asm 1.0 test program for sqrt2.asm 1031 sqrt3.asm 1.0 full precision square root macro 1388 sqrt3.hlp help for sqrt3.asm 794 sqrt3t.asm 1.0 test program for sqrt3.asm 1053 tli.asm 1.1 linear table lookup/interpolation 3253 routine for function generation tli.hlp 1.1 help for tli.asm 1510 bingray.asm 1.0 binary to gray code conversion macro 601 bingrayt.asm 1.0 test program for bingray.asm 991 rand1.asm 1.1 pseudo random sequence generator 2446 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board motorola additional support 11 - 13 rand1.hlp help for rand1.asm 704 lattice filters: latfir1.asm 1.0 lattice fir filter macro 1156 latfir1.hlp help for latfir1.asm 6327 latfir1t.asm 1.0 test program for latfir1.asm 1424 latfir2.asm 1.0 lattice fir filter macro 1174 (modified modulo count) latfir2.hlp help for latfir2.asm 1295 latfir2t.asm 1.0 test program for latfir2.asm 1423 latiir.asm 1.0 lattice iir filter macro 1257 latiir.hlp help for latiir.asm 6402 latiirt.asm 1.0 test program for latiir.asm 1407 latgen.asm 1.0 generalized lattice fir/iir 1334 filter macro latgen.hlp help for latgen.asm 5485 latgent.asm 1.0 test program for latgen.asm 1269 latnrm.asm 1.0 normalized lattice iir filter macro 1407 latnrm.hlp help for latnrm.asm 7475 latnrmt.asm 1.0 test program for latnrm.asm 1595 matrix operations: matmul1.asm 1.0 [1x3][3x3]=[1x3] matrix multiplication 1817 matmul1.hlp help for matmul1.asm 527 matmul2.asm 1.0 general matrix multiplication, c=ab 2650 matmul2.hlp help for matmul2.asm 780 matmul3.asm 1.0 general matrix multiply-accumulate, 2815 c=ab+q matmul3.hlp 1.0 help for matmul3.asm 865 reed-solomon encoder: readme.rs 1.0 instructions for reed-solomon coding 5200 rscd.asm 1.0 reed-solomon coder for dsp56000 simulator 5822 newc.c 1.0 reed-solomon coder coded in c 4075 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board 11 - 14 additional support motorola table1.asm 1.0 include file for r-s coder 7971 table2.asm 1.0 include file for r-s coder 4011 sorting routines: sort1.asm 1.0 array sort by straight selection 1312 sort1.hlp help for sort1.asm 1908 sort1t.asm 1.0 test program for sort1.asm 689 sort2.asm 1.1 array sort by heapsort method 2183 sort2.hlp help for sort2.asm 2004 sort2t.asm 1.0 test program for sort2.asm 700 speech: lgsol1.asm 2.0 leroux-gueguen solution for parcor 4861 (lpc) coefficients lgsol1.hlp help for lgsol1.asm 3971 durbin1.asm 1.2 durbin solution for parcor 6360 (lpc) coefficients durbin1.hlp help for durbin1.asm 3616 adpcm.asm 1.0 32 kbps ccitt adpcm speech coder 120512 adpcm.hlp 1.0 help file for adpcm.asm 14817 adpcmns.asm 1.0 nonstandard adpcm source code 54733 adpcmns.hlp 1.0 help file for adpcmns.asm 9952 standard i/o equates: ioequ.asm 1.1 motorola standard i/o equate file 8774 ioequlc.asm 1.1 lower case version of ioequ.asm 8788 intequ.asm 1.0 standard interrupt equate file 1082 intequlc.asm 1.0 lower case version of intequ.asm 1082 tools and utilities: srec.c 4.10 utility to convert dsp56000 omf format 38975 to srec. srec.doc 4.10 manual page for srec.c. 7951 srec.h 4.10 include file for srec.c 3472 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board motorola additional support 11 - 15 srec.exe 4.10 srec executable for ibm pc 22065 sloader.asm 1.1 serial loader from the sci port for the 3986 dsp56001 sloader.hlp 1.1 help for sloader.asm 2598 sloader.p 1.1 serial loader s-record file for download 736 to eprom parity.asm 1.0 parity calculation of a 24-bit number in 1641 accumulator a parity.hlp 1.0 help for parity.asm 936 parityt.asm 1.0 test program for parity.asm 685 parityt.hlp 1.0 help for parityt.asm 259 dspbug ordering information for free debug 882 monitor for dsp56000/dsp56001 the following is a list of current dsp56200 related software: p1 1.0 information on 56200 filter software 6343 p2 1.0 interrupt driven adaptive filter flowchart. 10916 p3 1.0 c code implementation of p2 25795 p4 1.0 polled i/o adaptive filter flowchart 10361 p5 1.0 c code implementation of p4 24806 p6 1.1 interrupt driven dual fir filter flowchart. 9535 p7 1.0 c code implementation of p6 28489 p8 1.0 polled i/o dual fir filter flowchart 9656 p9 1.0 c code implementation of p8 28525 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola dsp news 11 - 16 additional support motorola 11.5 motorola dsp news the motorola dsp news is a quarterly newsletter providing information on new products, application briefs, questions and answers, dsp product information, third-party product news, etc. this newsletter is free and is available upon request by calling the marketing information phone number listed below. 11.6 motorola field application engineers information and assistance for dsp applications is available through the local motorola field office. see your local telephone directory for telephone numbers or call (512)891- 2030. 11.7 design hotlinee 1-800-521-6274 this is the motorola number for information about any motorola product. 11.8 dsp help line e (512) 891-3230 design assistance for specific dsp applications is available by calling this number. 11.9 marketing informatione (512) 891-2030 marketing information, including brochures, application notes, manuals, price quotes, etc., for motorola dsp-related products is available by calling this number. 11.10 third-party support information e (512) 891-3098 information about third-party manufacturers who use and support motorola dsp products is available by calling this number. third-party support includes: filter design software logic analyzer support boards for vme, ibm-pc/xt/at, macii boards development systems data conversion cards operating system software debug software additional information is available on dr. bub and in dsp news. 11.11 university support e (512) 891-3098 information concerning university support programs and university discounts for all motorola dsp products is available by calling this number. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
training courses e (602) 897-3665 or (800) 521-6274 motorola additional support 11 - 17 11.12 training courses e (602) 897-3665 or (800) 521-6274 there are two dsp56000 family training courses available: 1. introduction to the dsp5600x (mtta5) is a 4.5-hour audio-tape course on the dsp56k family architecture and programming. 2. introduction to the dsp5600x (mtt31) is a four-day instructor-led course and laboratory which covers the details of the dsp5600x architecture and programming. additional information is available by writing to: motorola sps training and technical operations mail drop el524 p. o. box 21007 phoenix, arizona 85036 or by calling the number above. a technical training catalog is available which describes these courses and gives the current training schedule and prices. 11.13 reference books and manuals a list of dsp-related books is included here as an aid for the engineer who is new to the field of dsp. this is a partial list of dsp references intended to help the new user find useful information in some of the many areas of dsp applications. many of the books could be included in several categories but are not repeated. general dsp: advanced topics in signal processing jae s. lim and alan v. oppenheim englewood cliffs, nj: prentice-hall, inc., 1988 applications of digital signal processing a. v. oppenheim englewood cliffs, nj: prentice-hall, inc., 1978 discrete-time signal processing a. v. oppenheim and r. w. schafer englewood cliffs, nj: prentice-hall, inc., 1989 digital processing of signals theory and practice maurice bellanger new york, ny: john wiley and sons, 1984 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals 11 - 18 additional support motorola digital signal processing alan v. oppenheim and ronald w. schafer englewood cliffs, nj: prentice-hall, inc., 1975 digital signal processing: a system design approach david j. defatta, joseph g. lucas, and william s. hodgkiss new york, ny: john wiley and sons, 1988 foundations of digital signal processing and data analysis j. a. cadzow new york, ny: macmillan publishing company, 1987 handbook of digital signal processing d. f. elliott san diego, ca: academic press, inc., 1987 introduction to digital signal processing john g. proakis and dimitris g. manolakis new york, ny: macmillan publishing company, 1988 multirate digital signal processing r. e. crochiere and l. r. rabiner englewood cliffs, nj: prentice-hall, inc., 1983 signal processing algorithms s. stearns and r. davis englewood cliffs, nj: prentice-hall, inc., 1988 signal processing handbook c.h. chen new york, ny: marcel dekker, inc., 1988 signal processing e the modern approach james v. candy new york, ny: mcgraw-hill company, inc., 1988 theory and application of digital signal processing rabiner, lawrence r., gold and bernard englewood cliffs, nj: prentice-hall, inc., 1975 digital audio and filters: adaptive filter and equalizers b. mulgrew and c. cowan higham, ma: kluwer academic publishers, 1988 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals motorola additional support 11 - 19 adaptive signal processing b. widrow and s. d. stearns englewood cliffs, nj: prentice-hall, inc., 1985 art of digital audio, the john watkinson stoneham. ma: focal press, 1988 designing digital filters charles s. williams englewood cliffs, nj: prentice-hall, inc., 1986 digital audio signal processing an anthology john strawn william kaufmann, inc., 1985 digital coding of waveforms n. s. jayant and peter noll englewood cliffs, nj: prentice-hall, inc., 1984 digital filters: analysis and design andreas antoniou new york, ny: mcgraw-hill company, inc., 1979 digital filters and signal processing leland b. jackson higham, ma: kluwer academic publishers, 1986 digital signal processing richard a. roberts and clifford t. mullis new york, ny: addison-welsey publishing company, inc., 1987 introduction to digital signal processing roman kuc new york, ny: mcgraw-hill company, inc., 1988 introduction to adaptive filters simon haykin new york, ny: macmillan publishing company, 1984 musical applications of microprocessors (second edition) h. chamberlin hasbrouck heights, nj: hayden book co., 1985 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals 11 - 20 additional support motorola c programming language: c: a reference manual samuel p. harbison and guy l. steele prentice-hall software series, 1987. programming language - c american national standards institute, ansi document x3.159-1989 american national standards institute, inc., 1990 the c programming language brian w. kernighan, and dennis m. ritchie prentice-hall, inc., 1978. controls: adaptive control k. astrom and b. wittenmark new york, ny: addison-welsey publishing company, inc., 1989 adaptive filtering prediction & control g. goodwin and k. sin englewood cliffs, nj: prentice-hall, inc., 1984 automatic control systems b. c. kuo englewood cliffs, nj: prentice-hall, inc., 1987 computer controlled systems: theory & design k. astrom and b. wittenmark englewood cliffs, nj: prentice-hall, inc., 1984 digital control systems b. c. kuo new york, ny: holt, reinholt, and winston, inc., 1980 digital control system analysis & design c. phillips and h. nagle englewood cliffs, nj: prentice-hall, inc., 1984 issues in the implementation of digital feedback compensators p. moroney cambridge, ma: the mit press, 1983 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals motorola additional support 11 - 21 graphics: cgm and cgi d. b. arnold and p. r. bono new york, ny: springer-verlag, 1988 computer graphics (second edition) d. hearn and m. pauline baker englewood cliffs, nj: prentice-hall, inc., 1986 fundamentals of interactive computer graphics j. d. foley and a. van dam reading ma: addison-wesley publishing company inc., 1984 geometric modeling michael e. morteson new york, ny: john wiley and sons, inc. gks theory and practice p. r. bono and i. herman (eds.) new york, ny: springer-verlag, 1987 illumination and color in computer generated imagery roy hall new york, ny: springer-verlag postscript language program design glenn c. reid - adobe systems, inc. reading ma: addison-wesley publishing company, inc., 1988 microcomputer displays, graphics, and animation bruce a. artwick englewood cliffs, nj: prentice-hall, inc., 1985 principles of interactive computer graphics william m. newman and roger f. sproull new york, ny: mcgraw-hill company, inc., 1979 procedural elements for computer graphics david f. rogers new york, ny: mcgraw-hill company, inc., 1985 renderman interface, the pixar san rafael, ca. 94901 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals 11 - 22 additional support motorola image processing: digital image processing william k. pratt new york, ny: john wiley and sons, 1978 digital image processing (second edition) rafael c. gonzales and paul wintz reading, ma: addison-wesley publishing company, inc., 1977 digital image processing techniques m. p. ekstrom new york, ny: academic press, inc., 1984 digital picture processing azriel rosenfeld and avinash c. kak new york, ny: academic press, inc., 1982 science of fractal images, the m. f. barnsley, r. l. devaney, b. b. mandelbrot, h. o. peitgen, d. saupe, and r. f. voss new york, ny: springer-verlag motorola dsp manuals: motorola dsp56000 linker/librarian reference manual motorola, inc., 1991. motorola dsp56000 macro assembler reference manual motorola, inc., 1991. motorola dsp56000 simulator reference manual motorola, inc., 1991. motorola dsp56000/dsp56001 user?s manual motorola, inc.,1990. numerical methods: algorithms (the construction, proof, and analysis of programs) p. berliout and p. bizard new york, ny: john wiley and sons, 1986 matrix computations g. h. golub and c. f. van loan john hopkins press, 1983 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals motorola additional support 11 - 23 numerical recipes in c - the art of scientific programming william h. press, brian p. flannery, saul a. teukolsky, and william t. vetterling cambridge university press, 1988 number theory in science and communication manfred r. schroeder new york, ny: springer-verlag, 1986 pattern recognition: pattern classification and scene analysis r. o. duda and p. e. hart new york, ny: john wiley and sons, 1973 classification algorithms mike james new york, ny: wiley-interscience, 1985 spectral analysis: statistical spectral analysis, a nonprobabilistic theory william a. gardner englewood cliffs, nj: prentice-hall, inc., 1988 the fast fourier transform and its applications e. oran brigham englewood cliffs, nj: prentice-hall, inc., 1988 the fast fourier transform and its applications r. n. bracewell new york, ny: mcgraw-hill company, inc., 1986 speech: adaptive filters e structures, algorithms, and applications michael l. honig and david g. messerschmitt higham, ma: kluwer academic publishers, 1984 digital coding of waveforms n. s. jayant and p. noll englewood cliffs, nj: prentice-hall, inc., 1984 digital processing of speech signals lawrence r. rabiner and r. w. schafer englwood cliffs, nj: prentice-hall, inc., 1978 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals 11 - 24 additional support motorola linear prediction of speech j. d. markel and a. h. gray, jr. new york, ny: springer-verlag, 1976 speech analysis, synthesis, and perception j. l. flanagan new york, ny: springer-verlag, 1972 speech communication e human and machine d. o?shaughnessy reading, ma: addison-wesley publishing company, inc., 1987 telecommunications: digital communication edward a. lee and david g. messerschmitt higham, ma: kluwer academic publishers, 1988 digital communications john g. proakis new york, ny: mcgraw-hill publishing co., 1983 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola additional support 12 - 1 section 12 additional support dr. bub electronic bulletin board audio codec routines dtmf routines fast fourier transforms filters floating-point routines functions lattice filters matrix operations reed-solomon encoder sorting routines speech standard i/o equates tools and utilities motorola dsp news motorola field application engineers design hotline e 1-800-521-6274 dsp applications assistance e (512) 891-3230 dsp marketing information e (512) 891-2030 dsp third-party support information e (512) 891-3098 dsp university support e (512) 891-3098 dsp training courses e (602) 994-6900 motorola dsp product support dsp56100clasx assembler/simulator c language compiler dsp56156adsx application development system motorola dsp ola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents 12 - 2 additional support motorola 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.2 third party support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3 motorola dsp product support . . . . . . . . . . . . . . . . . . . . . 12-4 12.4 support integrated circuits . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.5 motorola dsp news . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.6 motorola field application engineers . . . . . . . . . . . . . . . 12-7 12.7 dsp applications help line e (512) 891-3230 . . . . . . . . . . . . . 12-7 12.8 design hotline e 1-800-521-6274 . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.9 dsp marketing information e (512) 891-2030 . . . . . . . . . . . . 12-7 12.10 dsp third-party support information e (512) 891-3098 . 12-7 12.11 dsp university support e (512) 891-3098 . . . . . . . . . . . . . . . . 12-7 12.12 dsp training courses e (602) 897-3665 or (800) 521-6274 . . . 12-8 12.13 dr. bub electronic bulletin board . . . . . . . . . . . . . . . . . . . . 12-8 12.14 reference books and manuals . . . . . . . . . . . . . . . . . . . . . . . 12-18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction motorola additional support 12 - 3 12.1 introduction this section is intended as a guide to the dsp support services and products offered by motorola. this includes training, development hardware and software tools, telephone support, etc. 12.2 third party support user support from the conception of a design through completion is available from motor- ola and third-party companies as shown in the following list: motorola third party design data sheets data acquisition packages application notes filter design packages application bulletins operating system software software examples simulator prototyping assembler logic analyzer with linker dsp561xx rom packages c compiler data acquisition cards simulator dsp development system application development cards system (ads) operating system software in-circuit emulator debug software cable for ads design application development data acquisition packages verification system (ads) logic analyzer with in-circuit emulator dsp561xx rom packages simulator data acquisition cards dsp development system cards application-specific development tools debug software specific information on the companies that offer these products is available by calling the dsp third party information number given in section 12.10. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola dsp product support 12 - 4 additional support motorola the following is a partial list of the support available for the dsp561xx. additional information on dsp56100 family members can be obtained through dr. bub or the appropriate support telephone service. 12.3 motorola dsp product support dsp56100clasx design-in software package which includes: relocatable macro assembler linker simulator (simulates single or multiple dsp561xxs) librarian dsp561xx applications development system (ads) support integrated circuits dsp bulletin board (dr. bub) motorola dsp newsletter motorola technical service engineers (tses) see your local telephone directory for the motorola semiconductor sector sales oftce telephone number. design hotline applications assistance marketing information third-party support information university support information 12.3.1 dsp56100clasx assembler/simulator 12.3.1.1 macro cross assembler and simulator platforms 1. ibm ? pcs and clones using an 80386 or upward compatible processor 2. macintosh ? computers with a nu-bus ? expansion port 3. sun computer 12.3.1.2 macro cross assembler features production of relocatable object modules compatible with linker program when in relocatable mode production of absolute tles compatible with simulator program when in absolute mode supports full instruction set, memory spaces, and parallel data transfer telds of the dsp561xx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola dsp product support motorola additional support 12 - 5 modular programming features: local labels, sections, and external detnition/ref- erence directives nested macro processing capability with support for macro libraries complex expression evaluation including boolean operators built-in functions for data conversion, string comparison, and common transcen- dental math functions directives to detne circular and bit-reversed buffers extensive error checking and reporting 12.3.1.3 simulator features simulation of all dsp56100 family dsps simulation of multiple dsp56100 family dsps linkable object code modules: enondisplay simulator library edisplay simulator library c language source code for: escreen management functions eterminal i/o functions esimulation examples single stepping through object programs conditional or unconditional breakpoints program patching using a single-line assembler/disassembler instruction, clock cycle, and histogram counters session and/or command logging for later reference ascii input/output tles for peripherals help-line display and expanded on-line help for simulator commands loading and saving of tles to/from simulator memory macro command detnition and execution display enable/disable of registers and memory hexadecimal/decimal/binary calculator 12.3.2 application development systems application development systems (ads) are available for all family members. up- grading an ads to run a different motorola dsp is done by purchasing and plug- ging in a new application development module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
support integrated circuits 12 - 6 additional support motorola 12.3.2.1 dsp561xxadsx application development system hardware features full-speed operation multiple application development module (adm) support with programmable adm addresses user-contgurable ram for dsp561xx code development expandable monitor rom 96-pin euro-card connector making all pins accessible in-circuit emulation capabilities using once separate berg pin connectors for alternate accessing of serial or host/dma ports adm can be used in stand-alone contguration no external power supply needed when connected to a host platform 3v emulation support in target environments 12.3.2.2 dsp561xxadsx application development system software features full-speed operation single/multiple stepping through dsp561xx object programs up to 99 conditional or unconditional breakpoints program patching using a single-line assembler/disassembler session and/or command logging for later reference loading and saving tles to/from adm memory macro command detnition and execution display enable/disable of registers and memory debug commands supporting multiple adms hexadecimal/decimal/binary calculator host operating system commands from within ads user interface program multiple os i/o tle access from dsp561xx object programs fully compatible with the dsp56100clasx design-in software package on-line help screens for each command and dsp561xx register 12.4 support integrated circuits dsp56adc16 16-bit, 100-khz analog-to-digital converter dsp56401 aes/ebu processor dsp56200 fir tlter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola dsp news motorola additional support 12 - 7 12.5 motorola dsp news the motorola dsp news is a quarterly newsletter providing information on new products, application briefs, questions and answers, dsp product information, third-party product news, etc. this newsletter is free and is available upon request by calling the marketing information phone number listed below. 12.6 motorola field application engineers information and assistance for dsp applications is available through the local motorola field office. see your local telephone directory for telephone numbers or call (512)891- 2030. 12.7 dsp applications help line e (512) 891-3230 design assistance for specific dsp applications is available by calling this number. 12.8 design hotline e 1-800-521-6274 this is the motorola number for information pertaining to any motorola product. 12.9 dsp marketing information e (512) 891-2030 marketing information including brochures, application notes, manuals, price quotes, etc. for motorola dsp-related products are available by calling this number. 12.10 dsp third-party support information e (512) 891-3098 information concerning third-party manufacturers using and supporting motorola dsp products is available by calling this number. third-party support includes: filter design software logic analyzer support boards for vme, ibm-pc/xt/at, macii, sparc, hp300 development systems data conversion cards operating system software debug software additional information is available on dr. bub and in dsp news. 12.11 dsp university support e (512) 891-3098 information concerning university support programs and university discounts for all motorola dsp products is available by calling this number. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dsp training courses e (602) 897-3665 or (800) 521-6274 12 - 8 additional support motorola 12.12 dsp training courses e (602) 897-3665 or (800) 521-6274 training information on the dsp56100 family members is available by writing: motorola sps training and technical operations mail drop el524 p. o. box 21007 phoenix, arizona 85036 or by calling the number above. a technical training catalog is available which describes these courses and gives the current training schedule and prices. 12.13 dr. bub electronic bulletin board dr. bub is an electronic bulletin board providing free source code for a large variety of topics that can be used to develop applications with motorola dsp products. the software library includes files including ffts, fir filters, iir filters, lattice filters, matrix algebra routines, companding routines, floating-point routines, and others. in addition, the latest product information and documentation (including information on new products and improvements on existing products) is posted. questions concerning motorola dsp products posted on dr. bub are answered promptly. dr. bub is open 24-hour a day, 7 days per week and offers the dsp community informa- tion on motorola?s dsp products, including: public domain source code for motorola?s dsp products including the dsp56000 family, the dsp56100 family and the dsp96002 announcements about new products and policies technical discussion groups monitored by dsp application engineers confidential mail service calendar of events for motorola dsp complete list of motorola dsp literature and ordering information information about the third-party and university support programs. to logon to the bulletin board, follow these instructions: 1. set the character format on your modem to 8 data bits, no parity, 1 stop bit, then dial (512) 891-3771. dr. bub will automatically set the data transfer rate to match your modem (9600, 4800, 2400, 1200 or 300 bps). 2. once the connection has been established, you will see the dr. bub login prompt (you may have to press the carriage return a couple times). if you just want to browse the system, login as guest. if you would like all the privileges that are normally allowed on the system, enter new at the login prompt. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board motorola additional support 12 - 9 3. if you open a new account, you will be asked to answer some questions such as name, address, phone number, etc. after answering these questions, you will have immediate access to all features of the system including download privilege, electronic mail and participation in discussion groups. 4. you will have an hour of access time for each call (upload and download time doesn?t count against you) and you can call as often as you like. if you need more time on line, just send an electronic mail request to the system operator (sysop). the following is a partial list of the software available on dr. bub. 12.13.1 audio rvb1.asm 1.0 easy-to-read reverberation routine 17056 rvb2.asm 1.0 same as rvb1.asm but optimized 15442 stereo.asm 1.0 code for c-quam am stereo decoder 4830 stereo.hlp 1.0 help file for stereo.asm 620 dge.asm 1.0 digital graphic equalizer code from 14880 12.13.2 benchmarks appendix b.1 through b.2.26 dsp56116 (dsp56100 family) benchmarks 44436 appendix b.3 through b.3.9 dsp56116 (dsp56100 family) benchmarks 6329 12.13.3 codec routines loglin.asm 1.0 companded codec to linear pcm data 4572 conversion loglin.hlp help for loglin.asm 1479 loglint.asm 1.0 test program for loglin.asm 2184 loglint.hlp help for loglint.asm 1993 linlog.asm 1.1 linear pcm to companded codec data 4847 conversion linlog.hlp help for linlog.asm 1714 12.13.4 dtmf routines clear.cmd 1.0 explained in read.me file 119 data.lod 1.0 421 det.asm 1.0 subroutine used in iir dtmf 5923 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board 12 - 10 additional support motorola dtmf.asm 1.0 main routine used in iir dtmf 10685 dtmf.mem 1.0 memory for dtmf routine 48 dtmfmstr.asm 1.0 main routine for multichannel dtmf 7409 dtmfmstr.mem 1.0 memory for multichannel dtmf routine 41 dtmftwo.asm 1.0 10256 ex56.bat 1.0 94 genxd.lod 1.0 data file 183 genyd.lod 1.0 data file 180 goertzel.asm 1.0 goertzel routine 4393 goertzel.lnk 1.0 link file for goertzel routine 6954 goertzel.lst 1.0 list file for goertzel routine 11600 load.cmd 1.0 46 tstgoert.mem 1.0 memory for goertzel routine 384 sub.asm 1.0 subroutine linked for use in iir dtmf 2491 read.me 1.0 instructions 738 12.13.5 fast fourier transforms sincos.asm 1.2 sine-cosine table generator for ffts 1185 sincos.hlp help for sincos.asm 887 sinewave.asm 1.1 full-cycle sine wave table generator 1029 generator macro sinewave.hlp for sinewave.asm 1395 fftr2a.asm 1.1 radix 2, in-place, dit fft (smallest) 3386 fftr2a.hlp help for fftr2a.asm 2693 fftr2at.asm 1.1 test program for ffts (fftr2a.asm) 999 fftr2at.hlp help for fftr2at.asm 563 fftr2b.asm 1.1 radix 2, in-place, dit fft (faster) 4290 fftr2b.hlp help for fftr2b.asm 3680 fftr2c.asm 1.2 radix 2, in-place, dit fft (even faster) 5991 fftr2c.hlp help for fftr2c.asm 3231 fftr2d.asm 1.0 radix 2, in-place, dit fft (using 3727 dsp56001 sine-cosine rom tables) fftr2d.hlp help for fftr2d.asm 3457 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board motorola additional support 12 - 11 fftr2dt.asm 1.0 test program for fftr2d.asm 1287 fftr2dt.hlp help for fftr2dt.asm 614 fftr2e.asm 1.0 1024 point, non-in-place, fft (3.39ms) 8976 fftr2e.hlp help for fftr2e.asm 5011 fftr2et.asm 1.0 test program for fftr2e.asm 984 fftr2et.hlp help for fftr2et.asm 408 dct1.asm 1.1 discrete cosine transform using fft 5493 dct1.hlp 1.1 help file for dct1.asm 970 fftr2cc.asm 1.0 radix 2, in-place decimation-in-time 6524 complex fft macro fftr2cc.hlp 1.0 help file for fftr2cc.asm 3533 fftr2cn.asm 1.0 radix 2, decimation-in-time complex fft 6584 macro with normally ordered input/output fftr2cn.hlp 1.0 help file for fftr2cn.asm 2468 fftr2en.asm 1.0 1024 point, not-in-place, complex fft 9723 macro with normally ordered input/output fftr2en.hlp 1.0 help file for fftr2en.asm 4886 dhit1.asm 1.0 routine to compute hilbert transform 1851 in the frequency domain dhit1.hlp 1.0 help file for dhit1.asm 1007 fftr2bf.asm 1.0 radix-2, decimation-in-time fft with 13526 block floating point fftr2bf.hlp 1.0 help file for fftr2bf.asm 1578 fftr2aa.asm 1.0 fft program for automatic scaling 3172 12.13.6 filters fir.asm 1.0 direct form fir filter 545 fir.hlp help for fir.asm 2161 firt.asm 1.0 test program for fir.asm 1164 iir1.asm 1.0 direct form second order all pole 656 iir filter iir1.hlp help for iir1.asm 1786 iir1t.asm 1.0 test program for iir1.asm 1157 iir2.asm 1.0 direct form second order all pole 801 iir filter with scaling document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board 12 - 12 additional support motorola iir2.hlp help for iir2.asm 2286 iir2t.asm 1.0 test program for iir2.asm 1311 iir3.asm 1.0 direct form arbitrary order all 776 pole iir filter iir3.hlp help for iir3.asm 2605 iir3t.asm 1.0 test program for iir3.asm 1309 iir4.asm 1.0 second order direct canonic iir filter 713 (biquad iir filter) iir4.hlp help for iir4.asm 2255 iir4t.asm 1.0 test program for iir4.asm 1202 iir5.asm 1.0 second order direct canonic iir filter 842 with scaling (biquad iir filter) iir5.hlp help for iir5.asm 2803 iir5t.asm 1.0 test program for iir5.asm 1289 iir6.asm 1.0 arbitrary order direct canonic iir 923 filter iir6.hlp help for iir6.asm 3020 iir6t.asm 1.0 test program for iir6.asm 1377 iir7.asm 1.0 cascaded biquad iir filters 900 iir7.hlp help for iir7.asm 3947 iir7t.asm 1.0 test program for iir7.asm 1432 lms.hlp 1.0 lms adaptive filter algorithm 5818 transiir.asm 1.0 implements the transposed iir filter 1981 transiir.hlp 1.0 help file for transiir.asm 974 12.13.7 floating-point routines fpdef.hlp 2.0 storage format and arithmetic 10600 representation definition fpcalls.hlp 2.1 subroutine calling conventions 11876 fplist.asm 2.0 test file that lists all subroutines 1601 fprevs.hlp 2.0 latest revisions of floating-point lib 1799 fpinit.asm 2.0 library initialization subroutine 2329 fpadd.asm 2.0 floating point add 3860 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board motorola additional support 12 - 13 fpsub.asm 2.1 floating point subtract 3072 fpcmp.asm 2.1 floating point compare 2605 fpmpy.asm 2.0 floating point multiply 2250 fpmac.asm 2.1 floating point multiply-accumulate 2712 fpdiv.asm 2.0 floating point divide 3835 fpsqrt.asm 2.0 floating point square root 2873 fpneg.asm 2.0 floating point negate 2026 fpabs.asm 2.0 floating point absolute value 1953 fpscale.asm 2.0 floating point scaling 2127 fpfix.asm 2.0 floating to fixed point conversion 3953 fpfloat.asm 2.0 fixed to floating point conversion 2053 fpceil.asm 2.0 floating point ceil subroutine 1771 fpfloor.asm 2.0 floating point floor subroutine 2119 durbin.asm 1.0 solution for lpc coefficients 5615 durbin.hlp 1.0 help file for durbin.asm 2904 fpfrac.asm 2.0 floating point fraction subroutine 1862 12.13.8 functions log2.asm 1.0 log base 2 by polynomial 1118 approximation log2.hlp help for log2.asm 719 log2t.asm 1.0 test program for log2.asm 1018 log2nrm.asm 1.0 normalizing base 2 logarithm macro 2262 log2nrm.hlp help for log2nrm.asm 676 log2nrmt.asm 1.0 test program for log2nrm.asm 1084 exp2.asm 1.0 exponential base 2 by polynomial 926 approximation exp2.hlp help for exp2.asm 759 exp2t.asm 1.0 test program for exp2.asm 1019 sqrt1.asm 1.0 square root by polynomial 991 approximation, 7 bit accuracy sqrt1.hlp help for sqrt1.asm 779 sqrt1t.asm 1.0 test program for sqrt1.asm 1065 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board 12 - 14 additional support motorola sqrt2.asm 1.0 square root by polynomial 899 approximation, 10 bit accuracy sqrt2.hlp help for sqrt2.asm 776 sqrt2t.asm 1.0 test program for sqrt2.asm 1031 sqrt3.asm 1.0 full precision square root macro 1388 sqrt3.hlp help for sqrt3.asm 794 sqrt3t.asm 1.0 test program for sqrt3.asm 1053 tli.asm 1.1 linear table lookup/interpolation 3253 routine for function generation tli.hlp 1.1 help for tli.asm 1510 bingray.asm 1.0 binary to gray code conversion macro 601 bingrayt.asm 1.0 test program for bingray.asm 991 rand1.asm 1.1 pseudo random sequence generator 2446 rand1.hlp help for rand1.asm 704 12.13.9 lattice filters latfir1.asm 1.0 lattice fir filter macro 1156 latfir1.hlp help for latfir1.asm 6327 latfir1t.asm 1.0 test program for latfir1.asm 1424 latfir2.asm 1.0 lattice fir filter macro 1174 (modified modulo count) latfir2.hlp help for latfir2.asm 1295 latfir2t.asm 1.0 test program for latfir2.asm 1423 latiir.asm 1.0 lattice iir filter macro 1257 latiir.hlp help for latiir.asm 6402 latiirt.asm 1.0 test program for latiir.asm 1407 latgen.asm 1.0 generalized lattice fir/iir 1334 filter macro latgen.hlp help for latgen.asm 5485 latgent.asm 1.0 test program for latgen.asm 1269 latnrm.asm 1.0 normalized lattice iir filter macro 1407 latnrm.hlp help for latnrm.asm 7475 latnrmt.asm 1.0 test program for latnrm.asm 1595 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board motorola additional support 12 - 15 12.13.10 matrix operations matmul1.asm 1.0 [1x3][3x3]=[1x3] matrix multiplication 1817 matmul1.hlp help for matmul1.asm 527 matmul2.asm 1.0 general matrix multiplication, c=ab 2650 matmul2.hlp help for matmul2.asm 780 matmul3.asm 1.0 general matrix multiply-accumulate, 2815 c=ab+q matmul3.hlp 1.0 help for matmul3.asm 865 12.13.11 reed-solomon encoder readme.rs 1.0 instructions for reed-solomon coding 5200 rscd.asm 1.0 reed-solomon coder for dsp56000 simulator 5822 newc.c 1.0 reed-solomon coder coded in c 4075 table1.asm 1.0 include file for r-s coder 7971 table2.asm 1.0 include file for r-s coder 4011 12.13.12 sorting routines sort1.asm 1.0 array sort by straight selection 1312 sort1.hlp help for sort1.asm 1908 sort1t.asm 1.0 test program for sort1.asm 689 sort2.asm 1.1 array sort by heapsort method 2183 sort2.hlp help for sort2.asm 2004 sort2t.asm 1.0 test program for sort2.asm 700 12.13.13 speech lgsol1.asm 2.0 leroux-gueguen solution for parcor 4861 (lpc) coefficients lgsol1.hlp help for lgsol1.asm 3971 durbin1.asm 1.2 durbin solution for parcor 6360 (lpc) coefficients durbin1.hlp help for durbin1.asm 3616 adpcm.asm 1.0 32 kbits/s ccitt adpcm speech coder 120512 adpcm.hlp 1.0 help file for adpcm.asm 14817 adpcmns.asm 1.0 nonstandard adpcm source code 54733 adpcmns.hlp 1.0 help file for adpcmns.asm 9952 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dr. bub electronic bulletin board 12 - 16 additional support motorola g722.zip 1.11 g.722 speech processing code 235864 (pkzip file for pc) g722.tar.z 1.11 g.722 speech processing code 339297 (compressed tar file for unix) 12.13.14 standard i/o equates ioequ16.asm 1.1 dsp56100 standard i/o equate file 10329 ioequ.asm 1.1 motorola standard i/o equate file 8774 ioequlc.asm 1.1 lower case version of ioequ.asm 8788 intequ.asm 1.0 standard interrupt equate file 1082 intequlc.asm 1.0 lower case version of intequ.asm 1082 12.13.15 tools and utilities srec.c 4.10 utility to convert dsp56000 omf format 38975 to srec. srec.doc 4.10 manual page for srec.c. 7951 srec.h 4.10 include file for srec.c 3472 srec.exe 4.10 srec executable for ibm pc 22065 sloader.asm 1.1 serial loader from the sci port for the 3986 dsp56001 sloader.hlp 1.1 help for sloader.asm 2598 sloader.p 1.1 serial loader s-record file for download 736 to eprom parity.asm 1.0 parity calculation of a 24-bit number in 1641 accumulator a parity.hlp 1.0 help for parity.asm 936 parityt.asm 1.0 test program for parity.asm 685 parityt.hlp 1.0 help for parityt.asm 259 dspbug ordering information for free debug 882 monitor for dsp56000/dsp56001 12.13.16 current dsp56200 related software p1 1.0 information on 56200 filter software 6343 p2 1.0 interrupt driven adaptive filter flowchart. 10916 p3 1.0 c code implementation of p2 25795 p4 1.0 polled i/o adaptive filter flowchart 10361 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals motorola additional support 12 - 17 p5 1.0 c code implementation of p4 24806 p6 1.1 interrupt driven dual fir filter flowchart. 9535 p7 1.0 c code implementation of p6 28489 p8 1.0 polled i/o dual fir filter flowchart 9656 p9 1.0 c code implementation of p8 28525 12.14 reference books and manuals a list of dsp-related books is included here as an aid for the engineer who is new to the field of dsp. this is a partial list of dsp references intended to help the new user find useful information in some of the many areas of dsp applications. many books could be included in several categories but are not repeated. 12.14.1 general dsp advanced topics in signal processing jae s. lim and alan v. oppenheim englewood cliffs, nj: prentice-hall, inc., 1988 applications of digital signal processing a. v. oppenheim englewood cliffs, nj: prentice-hall, inc., 1978 discrete-time signal processing a. v. oppenheim and r. w. schafer englewood cliffs, nj: prentice-hall, inc., 1989 digital processing of signals theory and practice maurice bellanger new york, ny: john wiley and sons, 1984 digital signal processing alan v. oppenheim and ronald w. schafer englewood cliffs, nj: prentice-hall, inc., 1975 digital signal processing: a system design approach david j. defatta, joseph g. lucas, and william s. hodgkiss new york, ny: john wiley and sons, 1988 foundations of digital signal processing and data analysis j. a. cadzow new york, ny: macmillan publishing company, 1987 document id version synopsis size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals 12 - 18 additional support motorola handbook of digital signal processing d. f. elliott san diego, ca: academic press, inc., 1987 introduction to digital signal processing john g. proakis and dimitris g. manolakis new york, ny: macmillan publishing company, 1988 multirate digital signal processing r. e. crochiere and l. r. rabiner englewood cliffs, nj: prentice-hall, inc., 1983 signal processing algorithms s. stearns and r. davis englewood cliffs, nj: prentice-hall, inc., 1988 signal processing handbook c.h. chen new york, ny: marcel dekker, inc., 1988 signal processing e the modern approach james v. candy new york, ny: mcgraw-hill company, inc., 1988 theory and application of digital signal processing rabiner, lawrence r., gold and bernard englewood cliffs, nj: prentice-hall, inc., 1975 12.14.2 digital audio and filters adaptive filter and equalizers b. mulgrew and c. cowan higham, ma: kluwer academic publishers, 1988 adaptive signal processing b. widrow and s. d. stearns englewood cliffs, nj: prentice-hall, inc., 1985 art of digital audio, the john watkinson stoneham. ma: focal press, 1988 designing digital filters charles s. williams englewood cliffs, nj: prentice-hall, inc., 1986 digital audio signal processing an anthology john strawn william kaufmann, inc., 1985 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals motorola additional support 12 - 19 digital coding of waveforms n. s. jayant and peter noll englewood cliffs, nj: prentice-hall, inc., 1984 digital filters: analysis and design andreas antoniou new york, ny: mcgraw-hill company, inc., 1979 digital filters and signal processing leland b. jackson higham, ma: kluwer academic publishers, 1986 digital signal processing richard a. roberts and clifford t. mullis new york, ny: addison-welsey publishing company, inc., 1987 introduction to digital signal processing roman kuc new york, ny: mcgraw-hill company, inc., 1988 introduction to adaptive filters simon haykin new york, ny: macmillan publishing company, 1984 musical applications of microprocessors (second edition) h. chamberlin hasbrouck heights, nj: hayden book co., 1985 12.14.3 c programming language c: a reference manual samuel p. harbison and guy l. steele prentice-hall software series, 1987. programming language - c american national standards institute, ansi document x3.159-1989 american national standards institute, inc., 1990 the c programming language brian w. kernighan, and dennis m. ritchie prentice-hall, inc., 1978. 12.14.4 controls adaptive control k. astrom and b. wittenmark new york, ny: addison-welsey publishing company, inc., 1989 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals 12 - 20 additional support motorola adaptive filtering prediction & control g. goodwin and k. sin englewood cliffs, nj: prentice-hall, inc., 1984 automatic control systems b. c. kuo englewood cliffs, nj: prentice-hall, inc., 1987 computer controlled systems: theory & design k. astrom and b. wittenmark englewood cliffs, nj: prentice-hall, inc., 1984 digital control systems b. c. kuo new york, ny: holt, reinholt, and winston, inc., 1980 digital control system analysis & design c. phillips and h. nagle englewood cliffs, nj: prentice-hall, inc., 1984 issues in the implementation of digital feedback compensators p. moroney cambridge, ma: the mit press, 1983 12.14.5 graphics cgm and cgi d. b. arnold and p. r. bono new york, ny: springer-verlag, 1988 computer graphics (second edition) d. hearn and m. pauline baker englewood cliffs, nj: prentice-hall, inc., 1986 fundamentals of interactive computer graphics j. d. foley and a. van dam reading ma: addison-wesley publishing company inc., 1984 geometric modeling michael e. morteson new york, ny: john wiley and sons, inc. gks theory and practice p. r. bono and i. herman (eds.) new york, ny: springer-verlag, 1987 illumination and color in computer generated imagery roy hall new york, ny: springer-verlag f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals motorola additional support 12 - 21 postscript language program design glenn c. reid - adobe systems, inc. reading ma: addison-wesley publishing company, inc., 1988 microcomputer displays, graphics, and animation bruce a. artwick englewood cliffs, nj: prentice-hall, inc., 1985 principles of interactive computer graphics william m. newman and roger f. sproull new york, ny: mcgraw-hill company, inc., 1979 procedural elements for computer graphics david f. rogers new york, ny: mcgraw-hill company, inc., 1985 renderman interface, the pixar san rafael, ca. 94901 12.14.6 image processing digital image processing william k. pratt new york, ny: john wiley and sons, 1978 digital image processing (second edition) rafael c. gonzales and paul wintz reading, ma: addison-wesley publishing company, inc., 1977 digital image processing techniques m. p. ekstrom new york, ny: academic press, inc., 1984 digital picture processing azriel rosenfeld and avinash c. kak new york, ny: academic press, inc., 1982 science of fractal images, the m. f. barnsley, r. l. devaney, b. b. mandelbrot, h. o. peitgen, d. saupe, and r. f. voss new york, ny: springer-verlag 12.14.7 motorola dsp manuals motorola dsp linker/librarian reference manual motorola, inc., 1992. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals 12 - 22 additional support motorola motorola dsp assembler reference manual motorola, inc., 1992. motorola dsp simulator reference manual motorola, inc., 1992. motorola dsp56000/dsp56001 user?s manual motorola, inc.,1990. motorola dsp56100 family manual motorola, inc.,1992. motorola dsp56156 user?s manual motorola, inc.,1992. motorola dsp56166 user?s manual motorola, inc.,1992. motorola dsp96002 user?s manual motorola, inc.,1989. 12.14.8 numerical methods algorithms (the construction, proof, and analysis of programs) p. berliout and p. bizard new york, ny: john wiley and sons, 1986 matrix computations g. h. golub and c. f. van loan john hopkins press, 1983 numerical recipes in c - the art of scientific programming william h. press, brian p. flannery, saul a. teukolsky, and william t. vetterling cambridge university press, 1988 number theory in science and communication manfred r. schroeder new york, ny: springer-verlag, 1986 12.14.9 pattern recognition pattern classification and scene analysis r. o. duda and p. e. hart new york, ny: john wiley and sons, 1973 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals motorola additional support 12 - 23 classification algorithms mike james new york, ny: wiley-interscience, 1985 spectral analysis: statistical spectral analysis, a nonprobabilistic theory william a. gardner englewood cliffs, nj: prentice-hall, inc., 1988 the fast fourier transform and its applications e. oran brigham englewood cliffs, nj: prentice-hall, inc., 1988 the fast fourier transform and its applications r. n. bracewell new york, ny: mcgraw-hill company, inc., 1986 12.14.10 speech adaptive filters e structures, algorithms, and applications michael l. honig and david g. messerschmitt higham, ma: kluwer academic publishers, 1984 digital coding of waveforms n. s. jayant and p. noll englewood cliffs, nj: prentice-hall, inc., 1984 digital processing of speech signals lawrence r. rabiner and r. w. schafer englwood cliffs, nj: prentice-hall, inc., 1978 linear prediction of speech j. d. markel and a. h. gray, jr. new york, ny: springer-verlag, 1976 speech analysis, synthesis, and perception j. l. flanagan new york, ny: springer-verlag, 1972 speech communication e human and machine d. o?shaughnessy reading, ma: addison-wesley publishing company, inc., 1987 12.14.11 telecommunications digital communication edward a. lee and david g. messerschmitt higham, ma: kluwer academic publishers, 1988 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reference books and manuals 12 - 24 additional support motorola digital communications john g. proakis new york, ny: mcgraw-hill publishing co., 1983 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola instruction set details a - 1 appendix a instruction set details bit field manipulation bftstl bftsth bfclr bfset bfchg loop doloop do forever enddo brkcc move lea move move(c) move(i) move(m) move(p) move(s) arithmetic abs adc add asl asl4 asr asr4 asr16 clr clr24 cmp cmpm dec dec24 div dmac ext imac impy inc inc24 mac macr mpy mpyr mpy(su,uu) mac(su,uu) neg negc norm rnd sbc sub subl swap tcc tfr tfr2 tst tst2 zero logical and andi eor lsl lsr not or ori rol ror program control bcc bsr bra bscc debug debugcc jcc jmp jsr jscc nop rep repcc reset rti rts stop swi wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents a - 2 instruction set details motorola section a.1 appendix a introduction .................................................3 section a.2 instruction guide ..............................................................3 section a.3 notation .................................................................................4 section a.4 addressing modes .............................................................10 a.4.1 addressing mode modifiers ................................................................13 section a.5 condition code computation ........................................14 section a.6 parallel move descriptions .........................................15 section a.7 instruction descriptions ...............................................17 section a.8 instruction timing .............................................................224 section a.9 instruction sequence restrictions ..........................235 a.9.1 restrictions near the end of do loops ..............................................236 a.9.2 other do restrictions .........................................................................237 a.9.3 enddo restrictions ...........................................................................237 a.9.4 rti and rts restrictions ...................................................................238 a.9.5 sp and ssh/ssl manipulation restrictions .......................................238 a.9.6 r, n, and m register restrictions ......................................................240 a.9.7 fast interrupt routines .......................................................................240 a.9.8 rep restrictions .................................................................................241 section a.10 instruction encoding ....................................................241 a.10.1 partial encodings for use in instruction encoding ............................242 a.10.2 instruction encoding for the parallel move portion of an instruction ....................................................................246 a.10.3 instruction encoding for instructions which do not allow parallel moves .........................................................................248 a.10.4 parallel instruction encoding of the operation code ........................259 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
appendix a introduction motorola instruction set details a - 3 a.1 appendix a introduction this appendix contains detailed information about each instruction in the dsp56k instruction set. it presents an instruction guide to help the user understand the individual instruction descriptions and follows with sections on notation and addressing modes. the instructions are then discussed in alphabetical order. a.2 instruction guide the following information is included in each instruction description with the goal of mak- ing each description self-contained: 1. name and mnemonic: the mnemonic is highlighted in bold type for easy refer- ence. 2. assembler syntax and operation: for each instruction syntax, the corresponding operation is symbolically described. if there are several operations indicated on a single line in the operation field, those operations do not necessarily occur in the order shown but are generally assumed to occur in parallel. if a parallel data move is allowed, it will be indicated in parenthesis in both the assembler syntax and oper- ation fields. if a letter in the mnemonic is optional, it will be shown in parenthesis in the assembler syntax field. 3. description: a complete text description of the instruction is given together with any special cases and/or condition code anomalies of which the user should be aware when using that instruction. 4. example: an example of the use of the instruction is given. the example is shown in dsp56k assembler source code format. most arithmetic and logical instruction examples include one or two parallel data moves to illustrate the many types of par- allel moves that are possible. the example includes a complete explanation, which discusses the contents of the registers referenced by the instruction (but not those referenced by the parallel moves) both before and after the execution of the instruc- tion. most examples are designed to be easily understood without the use of a cal- culator. 5. condition codes: the status register is depicted with the condition code bits which can be affected by the instruction highlighted in bold type. not all bits in the status register are used. those which are reserved are indicated with a double asterisk and are read as zeros. 6. instruction format: the instruction fields, the instruction opcode, and the instruc- tion extension word are specified for each instruction syntax. when the extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
notation a - 4 instruction set details motorola word is optional, it is so indicated. the values which can be assumed by each of the variables in the various instruction fields are shown under the instruction field?s heading. note that the symbols used in decoding the various opcode fields of an instruction are completely arbitrary . furthermore, the opcode symbols used in one instruction are completely independent of the opcode symbols used in a dif- ferent instruction. 7. timing: the number of oscillator clock cycles required for each instruction syntax is given. this information provides the user a basis for comparison of the execution times of the various instructions in oscillator clock cycles. refer to table a-1 and section a.8 for a complete explanation of instruction timing, including the meaning of the symbols aio, ap, ax, ay, axy, ea, jx, mv, mvb, mvc, mvm, mvp, rx, wio, wp, wx, and wy. 8. memory: the number of program memory words required for each instruction syn- tax is given. this information provides the user a basis for comparison of the num- ber of program memory locations required for each of the various instructions in 24- bit program memory words. refer to table a-1 and section a.8 for a complete explanation of instruction memory requirements, including the meaning of the sym- bols ea and mv. a.3 notation each instruction description contains symbols used to abbreviate certain operands and operations. table a-1 lists the symbols used and their respective meanings. depending on the context, registers refer to either the register itself or the contents of the register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
notation motorola instruction set details a - 5 xn input register x1 or x0 (24 bits) yn input register y1 or y0 (24 bits) an accumulator registers a2, a1, a0 (a2 ? 8 bits, a1 and a0 ? 24 bits) bn accumulator registers b2, b1, b0 (b2 ? 8 bits, b1 and b0 ? 24 bits) x input register x = x1: x0 (48 bits) y input register y = y1: y0 (48 bits) a accumulator a = a2: a1: a0 (56 bits) * b accumulator b = b2: b1: b0 (56 bits) * ab accumulators a and b = a1: b1 (48 bits) * ba accumulators b and a = b1: a1 (48 bits) * a10 accumulator a = a1: a0 (48 bits) b10 accumulator b= b1:b0 (48 bits) * note: in data move operations, shifting and limiting are performed when this register is specited as a source operand. when specited as a destination operand, sign extension and possibly zeroing are performed. data alu registers operands table a-1 instruction description notation rn address registers r0 - r7 (16 bits) nn address offset registers n0 - n7 (16 bits) mn address moditer registers m0 - m7 (16 bits) address alu registers operands f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
notation a - 6 instruction set details motorola ea effective address eax effective address for x bus eay effective address for y bus xxxx absolute address (16 bits) xxx short jump address (12 bits) aa absolute short address (6 bits, zero extended) pp i/o short address (6 bits, ones extended) <. . .> specites the contents of the specited address x: x memory reference y: y memory reference l: long memory reference = x:y p: program memory reference address operands pc program counter register (16 bits) mr mode register (8 bits) ccr condition code register (8 bits) sr status register = mr:ccr (16 bits) omr operating mode register (8 bits) la hardware loop address register (16 bits) lc hardware loop counter register (16 bits) sp system stack pointer register (6 bits) ssh upper portion of the current top of the stack (16 bits) ssl lower portion of the current top of the stack (16 bits) ss system stack ram = ssh: ssl (15 locations by 32 bits) program control unit registers operands table a-1 instruction description notation (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
notation motorola instruction set details a - 7 s, sn source operand register d, dn destination operand register d [n] bit n of d destination operand register #n immediate short data (5 bits) #xx immediate short data (8 bits) #xxx immediate short data (12 bits) #xxxxxx immediate data (24 bits) miscellaneous operands - negation operator ? logical not operator (overbar) push push specited value onto the system stack (ss) operator pull pull specited value from the system stack (ss) operator read read the top of the system stack (ss) operator purge delete the top value on the system stack (ss) operator | | absolute value operator unary operators + addition operator - subtraction operator * multiplication operator ? , / division operator + logical inclusive or operator logical and operator ? logical exclusive or operator t is transferred to operator : concatenation operator binary operators table a-1 instruction description notation (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
notation a - 8 instruction set details motorola << i/o short addressing mode force operator < short addressing mode force operator > long addressing mode force operator # immediate addressing mode operator #> immediate long addressing mode force operator #< immediate short addressing mode force operator addressing mode operators dm double precision multiply bit indicating if the chip is in double precision multiply mode lf loop flag bit indicating when a do loop is in progress t trace mode bit indicating if the tracing function has been enabled s1, s0 scaling mode bits indicating the current scaling mode i1, i0 interrupt mask bits indicating the current interrupt priority level mode register (mr) symbols s block floating point scaling bit indicating data growth detection l limit bit indicating arithmetic over?ow and/or data shifting/limiting e extension bit indicating if the integer portion of a or b is in use u unnormalized bit indicating if the a or b result is unnormalized n negative bit indicating if bit 55 of the a or b result is set z zero bit indicating if the a or b result equals zero v over?ow bit indicating if arithmetic over?ow has occurred in a or b c carry bit indicating if a carry or borrow occurred in a or b result condition code register (ccr) symbols standard definitions (table a-5 in section a.5 describes exceptions) table a-1 instruction description notation (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
notation motorola instruction set details a - 9 aio time required to access an i/o operand ap time required to access a p memory operand ax time required to access an x memory operand ay time required to access a y memory operand axy time required to access xy memory operands ea time or number of words required for an effective address jx time required to execute part of a jump-type instruction mv time or number of words required for a move-type operation mvb time required to execute part of a bit manipulation instruction mvc time required to execute part of a movec instruction mvm time required to execute part of a movem instruction mvp time required to execute part of a movep instruction rx time required to execute part of an rti or rts instruction wio number of wait states used in accessing external i/o wp number of wait states used in accessing external p memory wx number of wait states used in accessing external x memory wy number of wait states used in accessing external y memory instruction timing symbols ( ) optional letter, operand, or operation ( ? ) any arithmetic or logical instruction which allows parallel moves ext extension register portion of an accumulator (a2 or b2) ls least signitcant lsp least signitcant portion of an accumulator (a0 or b0) ms most signitcant msp most signitcant portion of a n accumulator (a1 or b1) r rounding constant s/l shifting and/or limiting on a data alu register sign ext sign extension of a data alu register zero zeroing of a data alu register other symbols table a-1 instruction description notation (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing modes a - 10 instruction set details motorola a.4 addressing modes the addressing modes are grouped into three categories: register direct, address regis- ter indirect, and special. these addressing modes are summarized in table a-2. all address calculations are performed in the address alu to minimize execution time and loop overhead. addressing modes, which specify whether the operands are in registers, in memory, or in the instruction itself (such as immediate data), provide the specific address of the operands. the register direct addressing mode can be subclassified according to the specific regis- ter addressed. the data registers include x1, x0, y1, y0, x, y, a2, a1, a0, b2, b1, b0, a, and b. the control registers include sr, omr, sp, ssh, ssl, la, lc, ccr, and mr. address register indirect modes use an address register rn (r0er7) to point to locations in x, y, and p memory. the contents of the rn address register (rn) is the effective address (ea) of the specified operand, except in the indexed by offset mode where the effective address (ea) is (rn+nn). address register indirect modes use an address mod- ifier register mn to specify the type of arithmetic to be used to update the address regis- ter rn. if an addressing mode specifies an address offset register nn, the given address offset register is used to update the corresponding address register rn. the rn address register may only use the corresponding address offset register nn and the correspond- ing address modifier register mn. for example, the address register r0 may only use the n0 address offset register and the m0 address modifier register during actual address computation and address register update operations. this unique implementation allows the user to easily address a wide variety of dsp-oriented data structures. all address register indirect modes use at least one set of address registers (rn, nn, and mn), and the xy memory reference uses two sets of address registers, one for the x memory space and one for the y memory space. the special addressing modes include immediate and absolute addressing modes as well as implied references to the program counter (pc), the system stack (ssh or ssl), and program (p) memory. addressing modes may also be categorized by the ways in which they can be used. table a-2 and table a-3 show the various categories to which each addressing mode belongs. these addressing mode categories may be combined so that additional, more restrictive classifications may be defined. for example, the instruction descriptions may use a memory alterable classification, which refers to addressing modes that are both memory addressing modes and alterable addressing modes. thus, memory alterable addressing modes use address register indirect and absolute addressing modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing modes motorola instruction set details a - 11 addressing mode uses mn moditer operand reference scdapxylxy register direct data or control register no x x x address register rn no x address moditer register mn no x address offset register nn no x address register indirect no update no xxxx x postincrement by 1 yes xxxx x postdecrement by 1 yes xxxx x postincrement by offset nn yes xxxx x postdecrement by offset nn yes xxxx indexed by offset nn yes xxxx predecrement by 1 yes xxxx special immediate data no x absolute address no xxxx immediate short data no x short jump address no x absolute short address no xxxx table a-2 dsp56k addressing modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing modes a - 12 instruction set details motorola addressing mode mode mmm reg rrr addressing categories assembler syntax upma register direct data or control register ? ? x (see table a-1) address register ? ? x rn address offset register ? ? x nn address moditer register ? ? x mn address register indirect no update 100 rn x x x (rn) postincrement by 1 011 rn xxxx (rn) + postdecrement by 1 010 rn xxxx (rn) - postincrement by offset nn 001 rn xxxx (rn) + nn postdecrement by offset nn 000 rn x x x (rn) - nn indexed by offset nn 101 rn x x (rn + nn) predecrement by 1 111 rn x x - (rn) special immediate data 110 100 x #xxxxxx absolute address 110 000 x x xxxx immediate short data ? ? #xx short jump address ? ? x xxx absolute short address ? ? x aa i/o short address ? ? x pp implicit ? ? x update mode (u) e modites address registers without any associated data move. parallel mode (p) e used in instructions where two effective addresses are required. memory mode (m) e refers to operands in memory using an effective addressing teld. alterable mode (a) e refers to alterable or writable registers or memory. table a-3 dsp56k addressing mode encoding f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing modes motorola instruction set details a - 13 the address register indirect addressing modes require that the offset register number be the same as the address register number. the assembler syntax n may be used instead of nn in the address register indirect memory addressing modes. if n is spec- ified, the offset register number is the same as the address register number. a.4.1 addressing mode modifiers the addressing mode selected in the instruction word is further specified by the contents of the address modifier register mn. the addressing mode update modifiers (m0em7) are shown in table a-4. there are no restrictions on the use of modifier types with any address register indirect addressing mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
addressing modes a - 14 instruction set details motorola binary m0-m7 hex m0-m7 addressing mode arithmetic 0000 0000 0000 0000 0000 reverse carry (bit reverse) 0000 0000 0000 0001 0001 modulo 2 00000000 0000 0010 0002 modulo 3 ::: 0111 1111 1111 1110 7ffe modulo 32767 0111 1111 1111 1111 7fff modulo 32768 1000 0000 0000 0000 8000 reserved 1000 0000 0000 0001 8001 multiple wrap-around modulo 2 1000 0000 0000 0010 8002 reserved 1000 0000 0000 0011 8003 multiple wrap-around modulo 4 : : reserved 1000 0000 0000 0111 8007 multiple wrap-around modulo 8 : : reserved 1000 0000 0000 1111 800f multiple wrap-around modulo 2 4 : : reserved 1000 0000 0001 1111 801f multiple wrap-around modulo 2 5 : : reserved 1000 0000 0011 1111 803f multiple wrap-around modulo 2 6 : : reserved 1000 0000 0111 1111 807f multiple wrap-around modulo 2 7 : : reserved 1000 0000 1111 1111 80ff multiple wrap-around modulo 2 8 : : reserved 1000 0001 1111 1111 81ff multiple wrap-around modulo 2 9 : : reserved 1000 0011 1111 1111 83ff multiple wrap-around modulo 2 10 : : reserved 1000 0111 1111 1111 87ff multiple wrap-around modulo 2 11 : : reserved 1000 1111 1111 1111 8fff multiple wrap-around modulo 2 12 : : reserved 1001 1111 1111 1111 9fff multiple wrap-around modulo 2 13 : : reserved 1011 1111 1111 1111 bfff multiple wrap-around modulo 2 14 : : reserved 1111 1111 1111 1111 ffff linear (modulo 2 15 ) table a-4 addressing mode modifier summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
condition code computation motorola instruction set details a - 15 a.5 condition code computation the condition code register (ccr) portion of the status register (sr) consists of eight defined bits: s ? scaling bit n ? negative bit l ? limit bit z ? zero bit e ? extension bit v ? overflow bit u ? unnormalized bit c ? carry bit the e, u, n, z, v, and c bits are true condition code bits that reflect the condition of the result of a data alu operation . these condition code bits are not latched and are not affected by address alu calculations or by data transfers over the x, y, or global data buses. the l bit is a latching overflow bit which indicates that an overflow has occurred in the data alu or that data limiting has occurred when moving the contents of the a and/or b accumulators. the s bit is a latching bit used in block floating point oper- ations to indicate the need to scale the number in a or b. see section 5 e program control unit for information on the mr portion of the status register. the standard definition of the condition code bits follows. exceptions to these stan- dard definitions are given in the notes which follow table a-5. mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
condition code computation a - 16 instruction set details motorola s (scaling bit) the scaling bit (s) is used to detect data growth, which is required in block floating point fft operation. typically, the bit is tested after each pass of a radix 2 decimation-in-time fft and, if it is set, the appropriate scaling mode should be activated in the next pass. the block floating point fft algorithm is described in the motorola application note apr4/d, implemen- tation of fast fourier transforms on motorola?s dsp56000/ dsp56001 and dsp96002 digital signal processors. this bit is computed according to the logical equations below when an instruction or a parallel move moves the result of accumulator a or b to xdb or ydb. it is a sticky bit, cleared only by an instruc- tion that specifically clears it. the following logical equations are used to compute the scaling bit based upon the scaling mode bits: l (limit bit) set if the overflow bit v is set or if an instruction or a parallel move causes the data shifter/limiters to perform a limiting opera- tion. not affected otherwise. this bit is latched and must be reset by the user. e (extension bit) cleared if all the bits of the signed integer portion of the a or b result are the same e i.e., the bit patterns are either 00 . . . 00 or 11 . . . 11. set otherwise. the signed integer portion is defined by the scaling mode as shown in the following table: if s1=0 and s0=0 (no scaling) then s = (a46 xor a45) or (b46 xor b45) if s1=0 and s0=1 (scale down) then s = (a47 xor a46) or (b47 xor b46) if s1=1 and s0=0 (scale up) then s = (a45 xor a44) or (b45 xor b44) if s1=1 and s0=1 (reserved) then the s flag is undefined. where ai and bi means bit i in accumulator a or b. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
condition code computation motorola instruction set details a - 17 s1 s0 scaling mode signed integer portion 0 0 no scaling bits 55, 54, . . . . 48, 47 0 1 scale down bits 55, 54, . . . . 49, 48 1 0 scale up bits 55, 54, . . . . 47, 46 note that the signed integer portion of an accumulator is not necessarily the same as the extension register portion of that accumulator. the signed integer portion of an accu- mulator consists of the ms 8, 9, or 10 bits of that accumulator, depending on the scaling mode being used. the extension register portion of an accumulator (a2 or b2) is always the ms 8 bits of that accumulator. the e bit refers to the signed integer portion of an accu- mulator and not the extension register portion of that accumulator. for example, if the current scaling mode is set for no scaling (i.e., s1=s0=0), the signed integer portion of the a or b accumulator consists of bits 47 through 55 . if the a accumulator contained the signed 56-bit value $00:800000:000000 as a result of a data alu operation , the e bit would be set (e=1) since the 9 ms bits of that accumulator were not all the same (i.e., nei- ther 00 . . 00 nor 11 . . 11). this means that data limiting will occur if that 56-bit value is specified as a source operand in a move-type operation. this limiting operation will result in either a positive or negative, 24-bit or 48-bit saturation constant being stored in the specified destination. the only situation in which the signed integer portion of an accumulator and the extension register portion of an accumulator are the same is in the scale down scaling mode (i.e., s1=0 and s0=1). u (unnormalized bit) set if the two ms bits of the msp portion of the a or b result are the same. cleared otherwise. the msp portion is defined by the scal- ing mode. the u bit is computed as follows: s1 s0 scaling mode u bit computation 0 0 no scaling u=(bit 47 ? bit 46 ) 0 1 scale down u=(bit 48 ? bit 47 ) 1 0 scale up u=(bit 46 ? bit 45 ) n (negative bit) set if the ms bit 55 of the a or b result is set. cleared otherwise. z (zero bit) set if the a or b result equals zero. cleared otherwise. v (overflow bit) set if an arithmetic overflow occurs in the 56-bit a or b result. this indicates that the result cannot be represented in the 56-bit accu- mulator; thus, the accumulator has overflowed. cleared otherwise. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
condition code computation a - 18 instruction set details motorola c (carry bit) set if a carry is generated out of the ms bit of the a or b result of an addition or if a borrow is generated out of the ms bit of the a or b result of a subtraction. the carry or borrow is generated out of bit 55 of the a or b result. cleared otherwise. table a-5 shows how each condition code bit is affected by each instruction. exceptions to the standard definitions given above are indicated by a number or a ?. consult the corresponding note for the special definition that applies in each particular case. although many of the instructions allow optional parallel moves, table a-5 applies when there are no parallel moves associated with an instruction. with this restriction, the states of the condition code bits are determined only by the execution of the instruction itself. however, the s and l bits may be determined differently than shown in the table when a parallel move is associated with the instruction. when using an optional parallel move, refer to the individual instruction?s detailed description in section a.7 to see how the s and l bits are determined. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
condition code computation motorola instruction set details a - 19 the following notes apply to table a-5: table a-5 condition code computations for instructions (no parallel move) mnemonic s l e u n z v c notes mnemonic s l e u n z v c notes abs ? 333333 ? lsr ????19111 adc ? 3333333 lua ? ??????? add ? 3333333 mac ? 333 3 3 3 ? addl ? 33333 2 3 macr ? 333 3 3 3 ? addr ? 3333333 move 33 ?????? and ? ? ? ? 8 9 1 ? movec ? ? ? ? ? ? ? ? 13 andi ? ? ? ? ? ? ? ? 3 movem ? ? ? ? ? ? ? ? 13 asl ? 33333 2 4 movep ? ? ? ? ? ? ? ? 13 asr ? ? 3333 1 5 mpy ? ? 3333 1? bchg ? ? ? ? ? ? ? ? 14 mpyr ? ? 3333 1? bclr ? ? ? ? ? ? ? ? 14 neg ? 333 3 3 3 ? bset ? ? ? ? ? ? ? ? 14 nop ? ? ? ? ? ? ? ? btst ? ? ? ? ? ? ? ? 14 norm ? 333 3 3 2? clr ? ? 3333 1 ? not ? ? ? ? 8 9 1 ? cmp ? 3333333 or ????891? cmpm ? 3333333 ori ???????? 6 debug ? ? ? ? ? ? ? ? rep 33 ?????? debugcc ? ? ? ? ? ? ? ? reset ? ? ? ? ? ? ? ? dec ? 3333333 rnd ? 333 3 3 3 ? div ? 3 ????2 7 rol ? ??? 8 9 1 10 do 33 ?????? ror ? ??? 8 9 1 11 enddo ? ? ? ? ? ? ? ? rti ? ? ? ? ? ? ? ? 12 eor ????8 9 1 ? rts ? ??????? illegal ? ? ? ? ? ? ? ? sbc ? 333 3 3 3 3 inc ? 3333333 stop ? ??????? jcc ? ? ? ? ? ? ? ? sub ? 333 3 3 3 3 jclr ? ? ? ? ? ? ? ? 14 subl ? 333 3 3 2 3 jmp ? ? ? ? ? ? ? ? subr ? 333 3 3 3 3 jscc ? ? ? ? ? ? ? ? swi ? ? ? ? ? ? ? ? jsclr ? ? ? ? ? ? ? ? 14 tcc ? ? ? ? ? ? ? ? jset ? ? ? ? ? ? ? ? 14 tfr ? ? ? ? ? ? ? ? jsr ? ??????? tst ? ? 3333 1? jsset ? ? ? ? ? ? ? ? 14 wait ? ? ? ? ? ? ? ? lsl ????89110 where: 3 set according to the standard definition of the operation ? not affected by the operation ? or # set according to a special detnition (refer to the following notes) and can be a 0 or 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
parallel move descriptions a - 20 instruction set details motorola 1. the bit is cleared. 2. v ? set if an arithmetic overflow occurs in the 56-bit a or b result or if the ms bit of the destination operand is changed as a result of the left shift. cleared otherwise. 3. for destination operand ccr, the bits are cleared if the corresponding bits in the immediate data are cleared. otherwise they are not affected. for other destination operands, the bits are not affected. 4. c ? set if bit 55 of the source operand was set prior to instruction execution. cleared otherwise. 5. c ? set if bit 0 of the source operand was set prior to instruction execution. cleared otherwise. 6. for destination operand ccr, the bits are set if the corresponding bits in the imme- diate data are set. otherwise, they are not affected. for other destination operands, the bits are not affected. 7. c ? set if bit 55 of the result is cleared. cleared otherwise. 8. n ? set if bit 47 of the a or b result is set. cleared otherwise. 9. z ? set if bits 47 - 24 of the a or b result are zero. cleared otherwise. 10. c ? set if bit 47 of the source operand was set prior to instruction execution. cleared otherwise. 11. c ? set if bit 24 of the source operand was set prior to instruction execution. cleared otherwise. 12. set according to the value pulled from the stack. 13. for destination operand sr, the bits are set according to the corresponding bit of the source operand. if sr is not specified as a destination operand, the l bit is set if data limiting occurred and the s bit is computed according to the definition. (see section a.5.) otherwise, the bits are unaffected. 14. due to complexity, refer to the detailed description of the instruction. a.6 parallel move descriptions many of the instructions in the dsp56k instruction set allow optional parallel data bus movement. section a.7 indicates the parallel move option in the instruction syntax with the statement ?parallel move). the move instruction is equivalent to a nop with paral- lel moves. therefore, a detailed description of each parallel move is given with the move instruction details in section a.7, beginning on page a-160. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 21 a.7 instruction descriptions the following section describes each instruction in the dsp56k instruction set in com- plete detail. the format of each instruction description is given in section a.2. instruc- tions which allow parallel moves include the notation (parallel move) in both the assembler syntax and the operation fields. the example given with each instruction discusses the contents of all the registers and memory locations referenced by the opcode-operand portion of that instruction but not those referenced by the parallel move portion of that instruction. refer to page a-160 for a complete discussion of parallel moves, including examples which discuss the contents of all the registers and memory locations referenced by the parallel move portion of an instruction. note: whenever an instruction uses an accumulator as both a destination operand for a data alu operation and as a source for a parallel move operation, the parallel move operation occurs first and will use the data that exists in the accumulator before the exe- cution of the data alu operation has occurred. whenever a bit in the condition code register is defined according to the standard defini- tion given in section a.5, a brief definition will be given in normal text in the condition code section of that instruction description. whenever a bit in the condition code register is defined according to a special definition for some particular instruction, the special definition of that bit will be given in the condition code section of that instruction in bold text to alert the user to any special conditions concerning its use. the definition and thus the computation of both the e (extension) and u (unnormalized) bits of the condition code register (ccr) varies according to the scaling mode being used. refer to section a.5 for complete details. note: the signed integer portion of an accumulator is not necessarily the same as ei- ther the a2 or b2 extension register portion of that accumulator. the signed integer portion of an accumulator is defined according to the scaling mode being used and can consist of the ms 8, 9, or 10 bits of an accumulator. refer to section a.5 for complete details. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 22 instruction set details motorola operation: assembler syntax: | d | t d (parallel move) abs d (parallel move) description: take the absolute value of the destination operand d and store the result in the destination accumulator. example: : abs a1 #$123456,x0 a,y0 ;take abs. value, set up x0, save value : explanation of example: prior to execution, the 56-bit a accumulator contains the value $ff:ffffff:fffff2. since this is a negative number, the execution of the abs instruction takes the twos complement of that value and returns $00:000000:00000e. note: for the case in which the d operand equals $80:000000:000000 (-256.0), the abs instruction will cause an overflow to occur since the result cannot be correctly ex- pressed using the standard 56-bit, fixed-point, twos-complement data representation. data limiting does not occur (i.e., a is not set to the limiting value of $7f:ffffff:ffffff). condition codes : s ? computed according to the definition in a.5 condition code computation. l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z? set if a or b result equals zero v ? set if overflow has occurred in a or b result note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 for complete details. abs absolute value abs before execution after execution a a $ff:ffffff:fffff2 $00:000000:00000e mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 23 instruction format: abs d opcode: instruction fields: d d a 0 b 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words 23 8 7 4 3 0 data bus move field 0010 d110 optional effective address extension abs absolute value abs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 24 instruction set details motorola operation: assembler syntax: s+c+d t d (parallel move) adc s,d (parallel move) description: add the source operand s and the carry bit c of the condition code register to the destination operand d and store the result in the destination accumulator. long words (48 bits) may be added to the (56-bit) destination accumulator. note: the carry bit is set correctly for multiple precision arithmetic using long-word op- erands if the extension register of the destination accumulator (a2 or b2) is the sign extension of bit 47 of the destination accumulator (a or b). example: : move l:<$0,x ;get a 48-bit ls long-word operand in x move l:<$1,a ;get other ls long word in a (sign ext.) move l:<$2,y ;get a 48-bit ms long-word operand in y add x,a l:<$3,b ;add ls words; get other ms word in b adc y,b a10,l:<$4 ;add ms words with carry, save ls sum move b10,l:<$5 ;save ms sum : explanation of example: this example illustrates long-word double-precision (96-bit) addition using the adc instruction. prior to execution of the add and adc instructions, the double-precision 96-bit value $000000:000001:800000:000000 is loaded into the y and x registers (y:x), respectively. the other double-precision 96-bit value $000000:000001:800000:000000 is loaded into the b and a accumulators (b:a), respec- tively. since the 48-bit value loaded into the a accumulator is automatically sign extended to 56 bits and the other 48-bit long-word operand is internally sign extended to 56 bits during instruction execution, the carry bit will be set correctly after the execution of the add x,a instruction. the adc y,b instruction then produces the correct ms 56-bit adc add long with carry adc before execution after execution a a $ff:800000:000000 $ff:000000:000000 x x $800000:000000 $800000:000000 b b $00:000000:000001 $00:000000:000003 y y $000000:000001 $000000:000001 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 25 result. the actual 96-bit result is stored in memory using the a10 and b10 operands (instead of a and b) because shifting and limiting is not desired. condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z? set if a or b result equals zero v ? set if overflow has occurred in a or b result c ? set if a carry (or borrow) occurs from bit 55 of a or b result. note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 for complete details. instruction format: adc s,d opcode: instruction fields: s,d j d x,a 0 0 x,b 0 1 y,a 1 0 y,b 1 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words adc add long with carry adc mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 8 7 4 3 0 data bus move field 001j d001 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 26 instruction set details motorola operation: assembler syntax: s+d t d (parallel move add s,d (parallel move) description: add the source operand s to the destination operand d and store the result in the destination accumulator. words (24 bits), long words (48 bits), and accumu- lators (56 bits) may be added to the destination accumulator. note: the carry bit is set correctly using word or long-word source operands if the ex- tension register of the destination accumulator (a2 or b2) is the sign extension of bit 47 of the destination accumulator (a or b). thus, the carry bit is always set correctly using accumulator source operands, but can be set incorrectly if a1, b1, a10, or b10 are used as source operands and a2 and b2 are not replicas of bit 47. example: : add x0,a a,x1 a,y:(r1)+l ;24-bit add, set up x1, save prev. result : explanation of example: prior to execution, the 24-bit x0 register contains the value $ffffff and the 56-bit a accumulator contains the value $00:000100:000000. the add instruction automatically appends the 24-bit value in the x0 register with 24 ls zeros, sign extends the resulting 48-bit long word to 56 bits, and adds the result to the 56-bit a accumulator. thus, 24-bit operands are added to the msp portion of a or b (a1 or b1) because all arithmetic instructions assume a fractional, twos complement data representation. note that 24-bit operands can be added to the lsp portion of a or b (a0 or b0) by loading the 24-bit operand into x0 or y0, forming a 48-bit word by loading x1 or y1 with the sign extension of x0 or y0 and executing an add x,a or add y,a instruc- tion. add add add before execution after execution x0 x0 $ffffff a a $00:000100:000000 $00:0000ff:000000 $ffffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 27 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z ? set if a or b result equals zero v ? set if overflow has occurred in a or b result c ? set if a carry (or borrow) occurs from bit 55 of a or b result. note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 for complete details. instruction format: add s,d opcode: instruction fields: s,d j j j d s,d j j j d s,d j j j d b,a 0 0 1 0 x0,a 1 0 0 0 y1,a 1 1 1 0 a,b 0 0 1 1 x0,b 1 0 0 1 y1,b 1 1 1 1 x,a 0 1 0 0 y0,a 1 0 1 0 x,b 0 1 0 1 y0,b 1 0 1 1 y,a 0 1 1 0 x1,a 1 1 0 0 y,b 0 1 1 1 x1,b 1 1 0 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 8 7 4 3 0 data bus move field 0jjj d000 optional effective address extension add add add f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 28 instruction set details motorola operation: assembler syntax: s+2 * d t d (parallel move) addl s,d (parallel move) description: add the source operand s to two times the destination operand d and store the result in the destination accumulator. the destination operand d is arithmeti- cally shifted one bit to the left, and a zero is shifted into the ls bit of d prior to the addi- tion operation. the carry bit is set correctly if the source operand does not overflow as a result of the left shift operation. the overflow bit may be set as a result of either the shift- ing or addition operation (or both). this instruction is useful for efficient divide and deci- mation in time (dit) fft algorithms. example: : addl a,b #$0,r0 ;a+2 * b t b, set up addr. reg. r0 : explanation of example: prior to execution, the 56-bit accumulator contains the value $00:000000:000123, and the 56-bit b accumulator contains the value $00:005000:000000. the addl a,b instruction adds two times the value in the b accu- mulator to the value in the a accumulator and stores the 56-bit result in the b accumula- tor. addl shift left and add accumulators addl before execution after execution a a $00:000000:000123 b b $00:005000:000000 $00:00a000:000123 $00:000000:000123 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 29 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z? set if a or b result equals zero v ? set if overflow has occurred in a or b result or if the ms bit of the destination operand is changed as a result of the instruction?s left shift c ? set if a carry (or borrow) occurs from bit 55 of a or b result. note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 for complete details. instruction format: addl s,d opcode: instruction fields: s,d d b,a 0 a,b 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 8 7 4 3 0 data bus move field 0001 d010 optional effective address extension addl shift left and add accumulators addl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 30 instruction set details motorola operation: assembler syntax: s+d / 2 t d (parallel move) addr s,d (parallel move) description: add the source operand s to one-half the destination operand d and store the result in the destination accumulator. the destination operand d is arithmetically shifted one bit to the right while the ms bit of d is held constant prior to the addition oper- ation. in contrast to the addl instruction, the carry bit is always set correctly, and the overflow bit can only be set by the addition operation and not by an overflow due to the initial shifting operation. this instruction is useful for efficient divide and decimation in time (dit) fft algorithms. example: : addr b,a x0,x:(r1)+n1 y0,y:(r4)e ;b+a / 2 t a, save x0 and y0 : explanation of example: prior to execution, the 56-bit a accumulator contains the value $80:000000:2468ac, and the 56-bit b accumulator contains the value $00:013570:000000. the addr b,a instruction adds one-half the value in the a accu- mulator to the value in the b accumulator and stores the 56-bit result in the a accumula- tor. addr shift right and add accumulators addr before execution after execution a a $80:000000:2468ac b b $00:013570:000000 $00:013570:000000 $c0:013570:123456 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 31 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z? set if a or b result equals zero v ? set if overflow has occurred in a or b result c ? set if a carry (or borrow) occurs from bit 55 of a or b result. note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 for complete details. instruction format: addr s,d opcode: instruction fields: s,d d b,a 0 a,b 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 8 7 4 3 0 data bus move field 0000 d010 optional effective address extension addr shift right and add accumulators addr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 32 instruction set details motorola operation: assembler syntax: s d[47:24] t d[47:24] (parallel move) and s,d (parallel move) where denotes the logical and operator description: logically and the source operand s with bits 47e24 of the destination operand d and store the result in bits 47e24 of the destination accumulator. this instruc- tion is a 24-bit operation. the remaining bits of the destination operand d are not affected. example: : and x0,a1 (r5)en5 ;and x0 with a1, update r5 using n5 : explanation of example: prior to execution, the 24-bit x0 register contains the value $ff0000, and the 56-bit a accumulator contains the value $00:123456:789abc. the and x0,a instruction logically ands the 24-bit value in the x0 register with bits 47e24 of the a accumulator (a1) and stores the result in the a accumulator with bits 55e48 and 23e0 unchanged. condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting occurs during parallel move n ? set if bit 47 of a or b result is set z? set if bits 47e24 of a or b result are zero v ? always cleared and logical and and before execution after execution x0 x0 $ff0000 a a $00:123456:789abc $00:120000:789abc $ff0000 mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu nz v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 33 instruction format: and s,d opcode: instruction fields: s j j d d x0 0 0 a 0 (only a1 is changed) x1 1 0 b 1 (only b1 is changed) y0 0 1 y1 1 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words 23 8 7 4 3 0 data bus move field 01jj d110 optional effective address extension and logical and and f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 34 instruction set details motorola operation: assembler syntax: #xx d t d and(i) #xx,d where denotes the logical and operator description: logically and the 8-bit immediate operand (#xx) with the contents of the destination control register d and store the result in the destination control register. the condition codes are affected only when the condition code register (ccr) is specified as the destination operand. restrictions: the andi #xx,mr instruction cannot be used immediately before an enddo or rti instruction and cannot be one of the last three instructions in a do loop (at la-2, la-1, or la). the andi #xx,ccr instruction cannot be used immediately before an rti instruction. example: : and #$fe,ccr ;clear carry bit c in cond. code register : explanation of example: prior to execution, the 8-bit condition code register (ccr) contains the value $31. the and #$fe,ccr instruction logically ands the immediate 8- bit value $fe with the contents of the condition code register and stores the result in the condition code register. andi and immediate with control register andi before execution after execution ccr ccr $31 $30 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 35 condition codes: for ccr operand: s ? cleared if bit 7 of the immediate operand is cleared l ? cleared if bit 6 of the immediate operand is cleared e ? cleared if bit 5 of the immediate operand is cleared u ? cleared if bit 4 of the immediate operand is cleared n ? cleared if bit 3 of the immediate operand is cleared z ? cleared if bit 2 of the immediate operand is cleared v ? cleared if bit 1 of the immediate operand is cleared c ? cleared if bit 0 of the immediate operand is cleared for mr and omr operands: the condition codes are not affected using these oper- ands. instruction format: and(i) #xx,d opcode: instruction fields: #xx=8-bit immediate short data ? i i i i i i i i de e mr 0 0 ccr 0 1 omr 1 0 timing: 2 oscillator clock cycles memory: 1 program word andi and immediate with control register andi mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 16 15 8 7 0 00000000iiiiiiii101110ee f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 36 instruction set details motorola assembler syntax: asl d (parallel move) description: arithmetically shift the destination operand d one bit to the left and store the result in the destination accumulator. the ms bit of d prior to instruction execution is shifted into the carry bit c and a zero is shifted into the ls bit of the destination accumu- lator d. if a zero shift count is specified, the carry bit is cleared. the difference between asl and lsl is that asl operates on the entire 56 bits of the accumulator and therefore sets the v bit if the number overflowed. example: : asl a (r3)e ;multiply a by 2, update r3 : explanation of example: prior to execution, the 56-bit a accumulator contains the value $a5:012345:012345. the execution of the asl a instruction shifts the 56-bit value in the a accumulator one bit to the left and stores the result back in the a accumulator. asl arithmetic shift accumulator left asl 55 47 23 0 c 0 (parallel move) operation: before execution after execution a a $a5:012345:012345 sr sr $0300 $0373 $4a:02468a:02468a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 37 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z? set if a or b result equals zero v ? set if bit 55 of a or b result is changed due to left shift c ? set if bit 55 of a or b was set prior to instruction execution note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 for complete details. instruction format: asl d opcode: instruction fields: dd a0 b1 timing: 2+mv oscillator clock cycles memory: 1+mv program words mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 8 7 4 3 0 data bus move field 0011 d010 optional effective address extension asl arithmetic shift accumulator left asl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 38 instruction set details motorola assembler syntax: asr d (parallel move) description: arithmetically shift the destination operand d one bit to the right and store the result in the destination accumulator. the ls bit of d prior to instruction execution is shifted into the carry bit c, and the ms bit of d is held constant. example: : asr b x:e(r3),r3 ;divide b by 2, update r3, load r3 : explanation of example: prior to execution, the 56-bit b accumulator contains the value $a8:a86420:a86421. the execution of the asr b instruction shifts the 56-bit value in the b accumulator one bit to the right and stores the result back in the b accu- mulator. asr arithmetic shift accumulator right asr 55 47 23 0 c (parallel move) operation: before execution after execution b b $a8:a86420:a86421 sr sr $0300 $0329 $d4:543210:543210 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 39 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting occurs during parallel move e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z? set if a or b result equals zero v ? always cleared c ? set if bit 0 of a or b was set prior to instruction execution note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 for complete details. instruction format: asr d opcode: instruction fields: dd a0 b1 timing: 2+mv oscillator clock cycles memory: 1+mv program words mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 8 7 4 3 0 data bus move field 0010 d010 optional effective address extension asr arithmetic shift accumulator right asr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 40 instruction set details motorola operation: assembler syntax: d[n] t c; bchg #n,x:ea d[n ] t d[n] d[n] t c; bchg #n,x:aa d[n ] t d[n] d[n] t c; bchg #n,x:pp d[n ] t d[n] d[n] t c; bchg #n,y:ea d[n ] t d[n] d[n] t c; bchg #n,y:aa d[n ] t d[n] d[n] t c; bchg #n,y:pp d[n ] t d[n] d[n] t c; bchg #n,d d[n ] t d[n] description: test the n th bit of the destination operand d, complement it, and store the result in the destination location. the state of the n th bit is stored in the carry bit c of the condition code register. the bit to be tested is selected by an immediate bit number from 0e23. this instruction performs a read-modify-write operation on the destination location using two destination accesses before releasing the bus. this instruction provides a test- and-change capability which is useful for synchronizing multiple processors using a shared memory. this instruction can use all memory alterable addressing modes. example: : bchg #$7,x:<<$ffe2 ;test and change bit 7 in i/o port b ddr : bchg bit test and change bchg before execution after execution x:$ffe2 x;$ffe2 $000000 sr sr $0300 $0300 $000080 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 41 explanation of example: prior to execution, the 24-bit x location x:$ffe2 (i/o port b data direction register) contains the value $000000. the execution of the bchg #$7,x:<<$ffe2 instruction tests the state of the 7th bit in x:$ffe2, sets the carry bit c accordingly, and then complements the 7th bit in x:$ffe2. condition codes: ccr condition codes: for destination operand sr: c ? changed if bit 0 is specified. not affected otherwise. v ? changed if bit 1 is specified. not affected otherwise. z ? changed if bit 2 is specified. not affected otherwise. n ? changed if bit 3 is specified. not affected otherwise. u ? changed if bit 4 is specified. not affected otherwise. e ? changed if bit 5 is specified. not affected otherwise. l ? changed if bit 6 is specified. not affected otherwise. s ? changed if bit 7 is specified. not affected otherwise. for destination operand a or b: s ?computed according to the definition. see notes on page a-47. l ? set if data limiting has occurred. see notes on page a-47. e ? not affected u ? not affected n ? not affected z ? not affected v ? not affected c ? set if bit tested is set. cleared otherwise. mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc bchg bit test and change bchg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 42 instruction set details motorola for other destination operands: s ? not affected l ? not affected e ? not affected u ? not affected n ? not affected z ? not affected v ? not affected c ? set if bit tested is set. cleared otherwise. mr status bits: for destination operand sr: i0 ? changed if bit 8 is specified. not affected otherwise. i1 ? changed if bit 9 is specified. not affected otherwise. s0 ? changed if bit 10 is specified. not affected otherwise. s1 ? changed if bit 11 is specified. not affected otherwise. t ? changed if bit 13 is specified. not affected otherwise. dm ? changed if bit 14 is specified. not affected otherwise lf ? changed if bit 15 is specified. not affected otherwise. for other destination operands: i0 ? not affected i1 ? not affected s0 ? not affected s1 ? not affected t ? not affected dm ? not affected lf ? not affected bchg bit test and change bchg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 43 instruction format: bchg #n,x:ea bchg #n,y:ea opcode: instruction fields: #n=bit number=bbbbb, ea=6-bit effective address=mmmrrr effective addressing mode m m m r r r memory spaces bit number bbbbb (rn)-nn 0 0 0 r r r x memory 0 00000 (rn)+nn 0 0 1 r r r y memory 1 (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r 10111 (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 where rrr refers to an address register r0-r7 timing: 4+mvb oscillator clock cycles memory: 1+ea program words 23 16 15 8 7 0 optional effective address extension 0000101 1 01mmmrrr0s0bbbbb bchg bit test and change bchg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 44 instruction set details motorola instruction format: bchg #n,x:aa bchg #n,y:aa opcode: instruction fields: #n=bit number=bbbbb, aa=6-bit absolute short address=aaaaaa absolute short address aaaaaa memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 4+mvb oscillator clock cycles memory: 1+ea program words bchg bit test and change bchg 23 16 15 8 7 0 0000101100aaaaaa0s0bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 45 instruction format: bchg #n,x:pp bchg #n,y:pp opcode: instruction fields: #n=bit number=bbbbb, ea=6-bit i/o short address=pppppp i/o short address pppppp memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 4+mvb oscillator clock cycles memory: 1+ea program words bchg bit test and change bchg 23 16 15 8 7 0 0000101110pppppp0s0bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 46 instruction set details motorola instruction format: bchg #n,d opcode: instruction fields: #n=bit number=bbbbb, d=destination register=dddddd xxxx=16-bit absolute address in extension word destination register d d d d d d bit number bbbbb 4 registers in data alu 0 0 0 1 d d 00000 8 accumulators in data alu 0 0 1 d d d 8 address registers in agu 0 1 0 t t t 10111 8 address offset registers in agu 0 1 1 n n n 8 address modifier registers in agu 1 0 0 f f f 8 program controller registers 1 1 1 g g g see section a.10 and table a-18 for specific register encodings. bchg bit test and change bchg 23 16 15 8 7 0 0000101 111dddddd0 1 0bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 47 notes: if a or b is specified as the destination operand, the following sequence of events takes place: 1. the s bit is computed according to its definition (see section a.5) 2. the accumulator value is scaled according to the scaling mode bits s0 and s1 in the status register (sr). 3. if the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the l bit is set. 4. the resulting 24 bit value is placed back into a1 or b1. a0 or b0 is cleared and the sign of a1 or b1 is extended into a2 or b2. 5. the bit test and change is performed on a1 or b1, and the c bit is set if the bit tested is set. timing: 4+mvb oscillator clock cycles memory: 1+ea program words bchg bit test and change bchg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 48 instruction set details motorola operation: assembler syntax: d[n] t c; bclr #n,x:ea 0 t d[n] d[n] t c; bclr #n,x:aa 0 t d[n] d[n] t c; bclr #n,x:pp 0 t d[n] d[n] t c; bclr #n,y:ea 0 t d[n] d[n] t c; bclr #n,y:aa 0 t d[n] d[n] t c; bclr #n,y:pp 0 t d[n] d[n] t c; bclr #n,d 0 t d[n] description: test the n th bit of the destination operand d, clear it and store the result in the destination location. the state of the n th bit is stored in the carry bit c of the condition code register. the bit to be tested is selected by an immediate bit number from 0e23. this instruction performs a read-modify-write operation on the destination location using two destination accesses before releasing the bus. this instruction provides a test-and- clear capability which is useful for synchronizing multiple processors using a shared memory. this instruction can use all memory alterable addressing modes. example: : bclr #$e,x:<<$ffe4 ;test and clear bit 14 in i/o port b data reg. : bclr bit test and clear bclr before execution after execution x:$ffe4 x:$ffe4 $ffffff sr sr $0300 $0301 $ffbfff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 49 explanation of example: prior to execution, the 24-bit x location x:$ffe4 (i/o port b data register) contains the value $ffffff. the execution of the bclr #$e,x:<<$ffe4 instruction tests the state of the 14th bit in x:$ffe4, sets the carry bit c accordingly, and then clears the 14th bit in x:$ffe4. condition codes: ccr condition codes: for destination operand sr: c ? cleared if bit 0 is specified. not affected otherwise. v ? cleared if bit 1 is specified. not affected otherwise. z ? cleared if bit 2 is specified. not affected otherwise. n ? cleared if bit 3 is specified. not affected otherwise. u ? cleared if bit 4 is specified. not affected otherwise. e ? cleared if bit 5 is specified. not affected otherwise. l ? cleared if bit 6 is specified. not affected otherwise. s ? cleared if bit 7 is specified. not affected otherwise. for destination operand a or b: s ?computed according to the definition. see notes on page a-55. l ? set if data limiting has occurred. see notes on page a-55. e ? not affected u ? not affected n ? not affected z ? not affected v ? not affected c ? set if bit tested is set. cleared otherwise. mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc bclr bit test and clear bclr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 50 instruction set details motorola for other destination operands: c ? set if bit tested is set. cleared otherwise. v ? not affected z ? not affected n ? not affected u ? not affected e ? not affected l ? not affected s ? not affected mr status bits: for destination operand sr: i0 ? cleared if bit 8 is specified. not affected otherwise. i1 ? cleared if bit 9 is specified. not affected otherwise. s0 ? cleared if bit 10 is specified. not affected otherwise. s1 ? cleared if bit 11 is specified. not affected otherwise. t ? cleared if bit 13 is specified. not affected otherwise. dm ? cleared if bit 14 is specified. not affected otherwise lf ? cleared if bit 15 is specified. not affected otherwise. for other destination operands: i0 ? not affected i1 ? not affected s0 ? not affected s1 ? not affected t ? not affected dm ? not affected lf ? not affected bclr bit test and clear bclr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 51 instruction format: bclr #n,x:ea bclr #n,y:ea opcode: instruction fields: #n=bit number=bbbbb, ea=6-bit effective address=mmmrrr effective addressing mode m m m r r r memory spaces bit number bbbbb (rn)-nn 0 0 0 r r r x memory 0 00000 (rn)+nn 0 0 1 r r r y memory 1 (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r 10111 (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 where rrr refers to an address register r0-r7 timing: 4+mvb oscillator clock cycles memory: 1+ea program words 23 16 15 8 7 0 optional effective address extension 0000101 0 01mmmrrr0s0bbbbb bclr bit test and clear bclr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 52 instruction set details motorola instruction format: bclr #n,x:aa bclr #n,y:aa opcode: instruction fields: #n=bit number=bbbbb, aa=6-bit absolute short address=aaaaaa absolute short address aaaaaa memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 4+mvb oscillator clock cycles memory: 1+ea program words bclr bit test and clear bclr 23 16 15 8 7 0 0000101000aaaaaa0s0bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 53 instruction format: bclr #n,x:pp bclr #n,y:pp opcode: instruction fields: #n=bit number=bbbbb, ea=6-bit i/o short address=pppppp i/o short address pppppp memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 4+mvb oscillator clock cycles memory: 1+ea program words bclr bit test and clear bclr 23 16 15 8 7 0 0000101010pppppp0s0bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 54 instruction set details motorola instruction format: bclr #n,d opcode: instruction fields: #n=bit number=bbbbb, d=destination register=dddddd xxxx=16-bit absolute address in extension word destination register d d d d d d bit number bbbbb 4 registers in data alu 0 0 0 1 d d 00000 8 accumulators in data alu 0 0 1 d d d 8 address registers in agu 0 1 0 t t t 10111 8 address offset registers in agu 0 1 1 n n n 8 address modifier registers in agu 1 0 0 f f f 8 program controller registers 1 1 1 g g g see section a.10 and table a-18 for specific register encodings. bclr bit test and clear bclr 23 16 15 8 7 0 0000101 011dddddd0 1 0bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 55 notes: if a or b is specified as the destination operand, the following sequence of events takes place: 1. the s bit is computed according to its definition (see section a.5) 2. the accumulator value is scaled according to the scaling mode bits s0 and s1 in the status register (sr). 3. if the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the l bit is set. 4. the resulting 24 bit value is placed back into a1 or b1. a0 or b0 is cleared and the sign of a1 or b1 is extended into a2 or b2. 5. the bit test and clear is performed on a1 or b1, and the c bit is set if the bit tested is set. timing: 4+mvb oscillator clock cycles memory: 1+ea program words bclr bit test and clear bclr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 56 instruction set details motorola operation: assembler syntax: d[n] t c; bset #n,x:ea 1 t d[n] d[n] t c; bset #n,x:aa 1 t d[n] d[n] t c; bset #n,x:pp 1 t d[n] d[n] t c; bset #n,y:ea 1 t d[n] d[n] t c; bset #n,y:aa 1 t d[n] d[n] t c; bset #n,y:pp 1 t d[n] d[n] t c; bset #n,d 1 t d[n] description: test the n th bit of the destination operand d, set it, and store the result in the destination location. the state of the n th bit is stored in the carry bit c of the condition code register. the bit to be tested is selected by an immediate bit number from 0e23. this instruction performs a read-modify-write operation on the destination location using two destination accesses before releasing the bus. this instruction provides a test-and- set capability which is useful for synchronizing multiple processors using a shared mem- ory. this instruction can use all memory alterable addressing modes. example: : bset #$0,x:<<$ffe5 ;test and clear bit 14 in i/o port b data reg. : bset bit test and set before execution after execution x:$ffe5 x:$ffe5 $000000 sr sr $0300 $0300 $000001 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 57 explanation of example: prior to execution, the 24-bit x location x:$ffe5 (i/o port c data register) contains the value $000000. the execution of the bset #$0,x:<<$ffe5 instruction tests the state of the 0 th bit in x:$ffe5, sets the carry bit c accordingly, and then sets the 0th bit in x:$ffe5. condition codes: ccr condition codes: for destination operand sr: c ? set if bit 0 is specified. not affected otherwise. v ? set if bit 1 is specified. not affected otherwise. z ? set if bit 2 is specified. not affected otherwise. n ? set if bit 3 is specified. not affected otherwise. u ? set if bit 4 is specified. not affected otherwise. e ? set if bit 5 is specified. not affected otherwise. l ? set if bit 6 is specified. not affected otherwise. s ? set if bit 7 is specified. not affected otherwise. for destination operand a or b: s ?computed according to the definition. see notes on page a-63. l ? set if data limiting has occurred. see notes on page a-63. e ? not affected u ? not affected n ? not affected z ? not affected v ? not affected c ? set if bit tested is set. cleared otherwise. mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc bset bit test and set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 58 instruction set details motorola for other destination operands: c ? set if bit tested is set. cleared otherwise. v ? not affected z ? not affected n ? not affected u ? not affected e ? not affected l ? not affected s ? not affected mr status bits: for destination operand sr: i0 ? set if bit 8 is specified. not affected otherwise. i1 ? set if bit 9 is specified. not affected otherwise. s0 ? set if bit 10 is specified. not affected otherwise. s1 ? set if bit 11 is specified. not affected otherwise. t ? set if bit 13 is specified. not affected otherwise. dm ? set if bit 14 is specified. not affected otherwise lf ? set if bit 15 is specified. not affected otherwise. for other destination operands: i0 ? not affected i1 ? not affected s0 ? not affected s1 ? not affected t ? not affected dm ? not affected lf ? not affected bset bit test and set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 59 instruction format: bset #n,x:ea bset #n,y:ea opcode: instruction fields: #n=bit number=bbbbb, ea=6-bit effective address=mmmrrr effective addressing mode m m m r r r memory spaces bit number bbbbb (rn)-nn 0 0 0 r r r x memory 0 00000 (rn)+nn 0 0 1 r r r y memory 1 (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r 10111 (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 where rrr refers to an address register r0-r7 timing: 4+mvb oscillator clock cycles memory: 1+ea program words bset bit test and set 23 16 15 8 7 0 optional effective address extension 0000101 0 01mmmrrr0s1bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 60 instruction set details motorola instruction format: bset #n,x:aa bset #n,y:aa opcode: instruction fields: #n=bit number=bbbbb, aa=6-bit absolute short address=aaaaaa absolute short address aaaaaa memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 4+mvb oscillator clock cycles memory: 1+ea program words bset bit test and set 23 16 15 8 7 0 0000101000aaaaaa0s1bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 61 instruction format: bset #n,x:pp bset #n,y:pp opcode: instruction fields: #n=bit number=bbbbb, ea=6-bit i/o short address=pppppp i/o short address pppppp memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 4+mvb oscillator clock cycles memory: 1+ea program words bset bit test and set 23 16 15 8 7 0 0000101010pppppp0s1bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 62 instruction set details motorola instruction format: bset #n,d opcode: instruction fields: #n=bit number=bbbbb, d=destination register=dddddd xxxx=16-bit absolute address in extension word destination register d d d d d d bit number bbbbb 4 registers in data alu 0 0 0 1 d d 00000 8 accumulators in data alu 0 0 1 d d d 8 address registers in agu 0 1 0 t t t 10111 8 address offset registers in agu 0 1 1 n n n 8 address modifier registers in agu 1 0 0 f f f 8 program controller registers 1 1 1 g g g see section a.10 and table a-18 for specific register encodings. bset bit test and set 23 16 15 8 7 0 0000101 011dddddd0 1 1bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 63 notes: if a or b is specified as the destination operand, the following sequence of events takes place: 1. the s bit is computed according to its definition (see section a.5) 2. the accumulator value is scaled according to the scaling mode bits s0 and s1 in the status register (sr). 3. if the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the l bit is set. 4. the resulting 24 bit value is placed back into a1 or b1. a0 or b0 is cleared and the sign of a1 or b1 is extended into a2 or b2. 5. the bit test and set is performed on a1 or b1, and the c bit is set if the bit tested is set. timing: 4+mvb oscillator clock cycles memory: 1+ea program words bset bit test and set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 64 instruction set details motorola operation: assembler syntax: d[n] t c; btst #n,x:ea d[n] t c; btst #n,x:aa d[n] t c; btst #n,x:pp d[n] t c; btst #n,y:ea d[n] t c; btst #n,y:aa d[n] t c; btst #n,y:pp d[n] t c; btst #n,d description: test the n th bit of the destination operand d. the state of the n th bit is stored in the carry bit c of the condition code register. the bit to be tested is selected by an immediate bit number from 0e23. this instruction is useful for performing serial to par- allel conversion when used with the appropriate rotate instructions. this instruction can use all memory alterable addressing modes. example: : btst #$0,x:<<$ffee ;read ssi serial input flag if1 into c bit rol a ;rotate carry bit c into lsb of a1 : explanation of example: prior to execution, the 24-bit x location x:$ffee (i/o ssi sta- tus register) contains the value $000002. the execution of the btst #$1,x:<<$ffee instruction tests the state of the 1st bit (serial input flag if1) in x:$ffee and sets the carry bit c accordingly. this instruction sequence illustrates serial to parallel conversion using the carry bit c and the 24-bit a1 register. btst bit test btst before execution after execution x:$ffee x:$ffee $000002 sr sr $0300 $0301 $000002 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 65 condition codes: ccr condition codes: for destination operand a or b: c ? set if bit tested is set. cleared otherwise. v ? not affected z ? not affected n ? not affected u ? not affected e ? not affected l ? set if data limiting has occurred. see notes on page a-69. s ? computed according to the definition. see notes on page a-69. for other destination operands: c ? set if bit tested is set. cleared otherwise. v ? not affected z ? not affected n ? not affected u ? not affected e ? not affected l ? not affected s ? not affected mr status bits are not affected. sp ? stack pointer: for destination operand ssh: sp ? decrement by 1. for other destination operands: not affected mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc btst bit test btst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 66 instruction set details motorola instruction format: btst #n,x:ea btst #n,y:ea opcode: instruction fields: #n=bit number=bbbbb, ea=6-bit effective address=mmmrrr effective addressing mode m m m r r r memory spaces bit number bbbbb (rn)-nn 0 0 0 r r r x memory 0 00000 (rn)+nn 0 0 1 r r r y memory 1 (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r 10111 (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 where rrr refers to an address register r0-r7 timing: 4+mvb oscillator clock cycles memory: 1+ea program words 23 16 15 8 7 0 optional effective address extension 0000101 1 01mmmrrr0s1bbbbb btst bit test btst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 67 instruction format: btst #n,x:aa btst #n,y:aa opcode: instruction fields: #n=bit number=bbbbb, aa=6-bit absolute short address=aaaaaa absolute short address aaaaaa memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 4+mvb oscillator clock cycles memory: 1+ea program words btst bit test btst 23 16 15 8 7 0 0000101100aaaaaa0s1bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 68 instruction set details motorola instruction format: btst #n,x:pp btst #n,y:pp opcode: instruction fields: #n=bit number=bbbbb, ea=6-bit i/o short address=pppppp i/o short address pppppp memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 4+mvb oscillator clock cycles memory: 1+ea program words 23 16 15 8 7 0 0000101110pppppp0s1bbbbb btst bit test btst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 69 instruction format: btst #n,d opcode: instruction fields: #n=bit number=bbbbb, d=destination register=dddddd, xxxx=16-bit absolute address in extension word destination register d d d d d d bit number bbbbb 4 registers in data alu 0 0 0 1 d d 00000 8 accumulators in data alu 0 0 1 d d d 8 address registers in agu 0 1 0 t t t 10111 8 address offset registers in agu 0 1 1 n n n 8 address modifier registers in agu 1 0 0 f f f 8 program controller registers 1 1 1 g g g see section a.10 and table a-18 for specific register encodings. notes: if a or b is specified as the destination operand, the following sequence of events takes place: 1. the s bit is computed according to its definition (see section a.5) 2. the accumulator value is scaled according to the scaling mode bits s0 and s1 in the status register (sr). 3. if the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the l bit is set. 4. the bit test is performed on the resulting 24-bit value and the c bit is set if the bit tested is set. the original contents of a or b are not changed. timing: 4+mvb oscillator clock cycles memory: 1+ea program words btst bit test btst 23 16 15 8 7 0 0000101 111dddddd0 1 1bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 70 instruction set details motorola operation: assembler syntax: 0 t d (parallel move) clr d (parallel move) description: clear the destination accumulator. this is a 56-bit clear instruction. example: : clr a #$7f,n ;clear a, set up n0 addr. reg. : explanation of example: prior to execution, the 56-bit a accumulator contains the value $12:345678:9abcde. the execution of the clr a instruction clears the 56-bit a accumulator to zero. condition codes : s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move e ? always cleared u ? always set n ? always cleared z? always set v ? always cleared clr clear accumulator clr before execution after execution a a $12:345678:9abcde $00:000000:000000 mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 71 instruction format: clr d opcode: instruction fields: dd a0 b1 timing: 2+mv oscillator clock cycles memory: 1+mv program words 23 8 7 4 3 0 data bus move field 0001 d011 optional effective address extension clr clear accumulator clr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 72 instruction set details motorola operation: assembler syntax: s2 e s1(parallel move) cmp s1, s2 (parallel move) description: subtract the source one operand, s1, from the source two accumulator, s2, and update the condition code register. the result of the subtraction operation is not stored. note: this instruction subtracts 56-bit operands. when a word is specified as s1, it is sign extended and zero filled to form a valid 56-bit operand. for the carry to be set cor- rectly as a result of the subtraction, s2 must be properly sign extended. s2 can be improperly sign extended by writing a1 or b1 explicitly prior to executing the compare so that a2 or b2, respectively, may not represent the correct sign extension. this note par- ticularly applies to the case where it is extended to compare 24-bit operands such as x0 with a1. example: : cmp y0,b x0,x:(r6)+n6 y1,y:(r0)e ;comp. y0 and b, save x0, y1 : explanation of example: prior to execution, the 56-bit b accumulator contains the value $00:000020:000000 and the 24-bit y0 register contains the value $000024. the execution of the cmp y0,b instruction automatically appends the 24-bit value in the y0 register with 24 ls zeros, sign extends the resulting 48-bit long word to 56 bits, subtracts the result from the 56-bit b accumulator and updates the condition code register. cmp compare cmp before execution after execution b b $00:000020:000000 y0 y0 $000024 $000024 $00:000020:000000 sr sr $0300 $0319 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 73 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z? set if a or b result equals zero v ? set if overflow has occurred in a or b result c ? set if a carry (or borrow) occurs from bit 55 of a or b result. note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 for complete details. instruction format: cmp s1, s2 opcode: instruction fields: s1,s2 j j j d s1,s2 j j j d b,a 0 0 0 0 y0,b 1 0 1 1 a,b 0 0 0 1 x1,a 1 1 0 0 x0,a 1 0 0 0 x1,b 1 1 0 1 x0,b 1 0 0 1 y1,a 1 1 1 0 y0,a 1 0 1 0 y1,b 1 1 1 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 8 7 4 3 0 data bus move field 0jjj d101 optional effective address extension cmp compare cmp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 74 instruction set details motorola operation: assembler syntax: |s2| e |s1|(parallel move) cmpm s1, s2 (parallel move) description: subtract the absolute value (magnitude) of the source one operand, s1, from the absolute value of the source two accumulator, s2, and update the condition code register. the result of the subtraction operation is not stored. note: this instruction subtracts 56-bit operands. when a word is specified as s1, it is sign extended and zero filled to form a valid 56-bit operand. for the carry to be set cor- rectly as a result of the subtraction, s2 must be properly sign extended. s2 can be improperly sign extended by writing a1 or b1 explicitly prior to executing the compare so that a2 or b2, respectively, may not represent the correct sign extension. this note par- ticularly applies to the case where it is extended to compare 24-bit operands such as x0 with a1. example: : cmpm x1,a ba,l:e(r4) ;comp. y0 and b, save x0, y1 : explanation of example: prior to execution, the 56-bit a accumulator contains the value $00:000006:000000, and the 24-bit x1 register contains the value $fffff7. the execution of the cmpm x1,a instruction automatically appends the 24-bit value in the x1 register with 24 ls zeros, sign extends the resulting 48-bit long word to 56 bits, takes the absolute value of the resulting 56-bit number, subtracts the result from the absolute value of the contents of the 56-bit a accumulator, and updates the condition code regis- ter. cmpm compare magnitude cmpm before execution after execution a a $00:000006:000000 x1 x1 $fffff7 $fffff7 $00:000006:000000 sr sr $0300 $0319 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 75 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during a parallel move e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z? set if a or b result equals zero v ? set if overflow has occurred in a or b result c ? set if a carry (or borrow) occurs from bit 55 of a or b result. note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 for complete details. instruction format: cmpm s1, s2 opcode: instruction fields: s1,s2 j j j d s1,s2 j j j d s1,s2 j j j d b,a 0 0 0 0 x0,b 1 0 0 1 x1,a 1 1 0 0 a,b 0 0 0 1 y0,a 1 0 1 0 x1,b 1 1 0 1 x0,a 1 0 0 0 y0,b 1 0 1 1 y1,a 1 1 1 0 y1,b 1 1 1 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words cmpm compare magnitude cmpm mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l eu n z v c 23 8 7 4 3 0 data bus move field 0jjj d111 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 76 instruction set details motorola operation: assembler syntax: enter the debug mode debug description: enter the debug mode and wait for once commands. example: : debug ;enter the debug mode : explanation of example: upon executing the debug instruction, the chip enters the debug mode after the instruction following the debug instruction has entered the instruction latch. entering the debug mode is acknowledged by the chip by pulsing low the dso line. this informs the external command controller that the chip has entered the debug mode and is waiting for commands. condition codes: the condition codes are not affected by this instruction instruction format: debug debug enter debug mode debug mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 77 opcode: timing: 4 oscillator clock cycles memory: 1 program word debug enter debug mode debug 23 16 15 8 7 0 000000000000001000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 78 instruction set details motorola operation: assembler syntax: if cc, then enter the debug mode debugcc description: if the specified condition is true, enter the debug mode and wait for once commands. if the specified condition is false, continue with the next instruction. the term cc may specify the following conditions: cc mnemonic condition cc (hs) ? carry clear (higher or same) c=0 cs (lo) ? carry set (lower) c=1 ec ? extension clear e=0 eq ? equal z=1 es ? extension set e=1 ge ? greater than or equal n ? v=0 gt ? greater than z+(n ? v)=0 lc ? limit clear l=0 le ? less than or equal z+(n ? v)=1 ls ? limit set l=1 lt ? less than n ? v=1 mi ? minus n=1 ne ? not equal z=0 nr ? normalized z+(u e )=1 pl ? plus n=0 nn ? not normalized z+(u e )=0 where u denotes the logical complement of u, + denotes the logical or operator, denotes the logical and operator, and ? denotes the logical exclusive or operator condition codes: the condition codes are not affected by this instruction. debugcc enter debug mode conditionally debugcc mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 79 example: : cmp y0, b ; compare register y0 with the b accumulator. debugge ; enter the debug mode if ; the previous test result is greater than. : explanation of example: the results of the comparison between y0 and b will be recorded in the status register bits. the conditional debug instruction looks at the condi- tions (for greater than or equal in this case) and if they are met (n ? v=0) then the debug instruction will be executed. the chip enters the debug mode after the instruc- tion following the debug instruction has entered the instruction latch. the chip pulses low the dso line to inform the external command controller that it has entered the debug mode and that the chip is waiting for commands. instruction format: debugcc opcode: instruction fields: mnemonic c c c c mnemonic c c c c cc (hs) 0 0 0 0 cs (lo) 1 0 0 0 ge 0 001 lt 1001 ne 0 010 eq 1010 pl 0 011 mi 1011 nn 0 100 nr 1100 ec 0 101 es 1101 lc 0 110 ls 1110 gt 0 111 le 1111 timing: 4 oscillator clock cycles memory: 1 program word debugcc enter debug mode conditionally debugcc 23 16 15 8 7 0 00000000000000110000cccc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 80 instruction set details motorola operation: assembler syntax: de1 t d dec d description: decrement by one the specified operand and store the result in the destina- tion accumulator. one is subtracted from the lsb of d. example: : dec a ;decrement the content of a accumulator by one : explanation of example: one is subtracted from the content of the a accumulator. condition codes: l ? set if overflow has occurred in result. not affected otherwise e ? set if the signed integer portion of result is in use u? set if result is unnormalized n ? set if bit 55 of result is set z ? set if result equals zero v ? set if overflow has occurred in result c ? set if a borrow occurs from bit 55 of result dec decrement by one dec mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s leunzvc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 81 instruction format: dec d opcode: instruction fields: dd a0 b1 timing: 2 oscillator clock cycles memory: 1 program word dec decrement by one dec 23 16 15 8 7 0 00000000000000000000101d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 82 instruction set details motorola operation: if d[55] ? s[23]=1, assembler syntax: div s,d description: divide the destination operand d by the source operand s and store the result in the destination accumulator d. the 48-bit dividend must be a positive fraction which has been sign extended to 56-bits and is stored in the full 56-bit destination accumula- tor d. the 24-bit divisor is a signed fraction and is stored in the source operand s. each div iteration calculates one quotient bit using a nonrestoring fractional division algorithm (see description on the next page). after the execution of the first div instruc- tion, the destination operand holds both the partial remainder and the formed quotient. the partial remainder occupies the high-order portion of the destination accumulator d and is a signed fraction. the formed quotient occupies the low-order portion of the desti- nation accumulator d (a0 or b0) and is a positive fraction. one bit of the formed quotient is shifted into the ls bit of the destination accumulator at the start of each div iteration. the formed quotient is the true quotient if the true quotient is positive. if the true quotient is negative, the formed quotient must be negated. valid results are obtained only when |d| < |s| and the operands are interpreted as fractions. note that this condition ensures that the magnitude of the quotient is less than one (i.e., is fractional) and pre- cludes division by zero. div divide interation div 55 47 23 0 c+s then 55 47 23 0 ces else destination accumulator d destination accumulator d where ? denotes the logical exclusive or operator d d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 83 the div instruction calculates one quotient bit based on the divisor and the previous par- tial remainder. to produce an n-bit quotient, the div instruction is executed n times where n is the number of bits of precision desired in the quotient, 1 n 24. thus, for a full-precision (24 bit) quotient, 24 div iterations are required. in general, executing the div instruction n times produces an n-bit quotient and a 48-bit remainder which has (48en) bits of precision and whose n ms bits are zeros. the partial remainder is not a true remainder and must be corrected due to the nonrestoring nature of the division algo- rithm before it may be used. therefore, once the divide is complete, it is necessary to reverse the last div operation and restore the remainder to obtain the true remainder. the div instruction uses a nonrestoring fractional division algorithm which consists of the following operations (see the previous operation diagram): 1. compare the source and destination operand sign bits: an exclusive or operation is performed on bit 55 of the destination operand d and bit 23 of the source operand s; 2. shift the partial remainder and the quotient: the 55-bit destination accumu- lator d is shifted one bit to the left. the carry bit c is moved into the ls bit (bit 0) of the accumulator; 3. calculate the next quotient bit and the new partial remainder: the 24-bit source operand s (signed divisor) is either added to or subtracted from the msp portion of the destination accumulator (a1 or b1), and the result is stored back into the msp portion of that destination accumulator. if the result of the exclusive or operation previously described was a 1 (i.e., the sign bits were different), the source operand s is added to the accumulator. if the result of the exclusive or operation was a 0 (i.e., the sign bits were the same), the source operand s is subtracted from the accumulator. due to the automatic sign extension of the 24-bit signed divisor, the addition or subtraction opera- tion correctly sets the carry bit c of the condition code register with the next quotient bit. div divide interation div f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 84 instruction set details motorola example: (4-quadrant division, 24-bit signed quotient, 48-bit signed remainder) abs a a,b ;make dividend positive, copy a1 to b1 eor x0,b b,x:$0 ;save rem. sign in x:$0, quo. sign in n and #$fe,ccr ;clear carry bit c (quotient sign bit) rep #$18 ;form a 24-bit quotient div x0,a ;form quotient in a0, remainder in a1 tfr a,b ;save quotient and remainder in b1,b0 jpl savequo ;go to savequo if quotient is positive neg b ;complement quotient if n bit set savequo tfr x0,b b0,x1 ;save quo. in x1, get signed divisor abs b ;get absolute value of signed divisor add a,b ;restore remainder in b1 jclr #23,x:$0,done ;go to done if remainder is positive move #$0,b0 ;clear ls 24 bits of b neg b ;complement remainder if negative done . . . . . . . explanation of example: prior to execution, the 56-bit a accumulator contains the 56- bit, sign-extended fractional dividend d (d=$00.0e66d7:f2832c=0.112513535894635 approx.) and the 24-bit x0 register contains the 24-bit, signed fractional divisor s (s=$123456=0.142222166061401). since |d|<|s|, the execution of the previous divide routine stores the correct 24-bit signed quotient in the 24-bit x1 register (a/ x0=0.79111111164093=$654321=x1). the partial remainder is restored by reversing the last div operation and adding back the absolute value of the signed divisor in x0 to the partial remainder in a1. this produces the correct ls 24 bits of the 48-bit signed remained in the 24-bit b1 register. note that the remainder is really a 48-bit value which has 24 bits of precision. thus, the correct 48-bit remainder is $000000:000100 which equals 0.0000000000018190 approximately. div divide interation div before execution after execution a a $00:0e66d7:f2832c x0 x0 $123456 $123456 $ff:edccaa:654321 x1 x1 $000000 $654321 b b $00:000000:000000 $00:000100:654321 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 85 note that the divide routine used in the previous example assumes that the sign- extended 56-bit signed fractional dividend is stored in the a accumulator and that the 24- bit signed fractional divisor is stored in the x0 register. this routine produces a full 24-bit signed quotient and a 48-bit signed remainder. this routine may be greatly simplified for the case in which only positive, fractional oper- ands are used to produce a 24-bit positive quotient and a 48-bit positive remainder, as shown in the following example: 1-quadrant division, 24-bit unsigned quotient, 48-bit unsigned remainder and #$fe,ccr ;clear carry bit c (quotient sign bit) rep #$18 ;form a 24-bit quotient and remainder div x0,a ;form quotient in a0, remainder in a1 add x0,a ;restore remainder in a1 note that this routine assumes that the 56-bit positive, fractional, sign-extended dividend is stored in the a accumulator and that the 24-bit positive, fractional divisor is stored in the x0 register. after execution, the 24-bit positive fractional quotient is stored in the a0 register; the ls 24 bits of the 48-bit positive fractional remainder are stored in the a1 reg- ister. there are many variations possible when choosing a suitable division routine for a given application. the selection of a suitable division routine normally involves specification of the following items: 1. the number of bits of precision in the dividend; 2. the number of bits of precision n in the quotient; 3. whether the value of n is fixed or is variable; 4. whether the operands are unsigned or signed; 5. whether or not the remainder is to be calculated. div divide interation div f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 86 instruction set details motorola a complete discussion of the various division routines is beyond the scope of this man- ual. for a more complete discussion of these routines, refer to the application note enti- tled fractional and integer arithmetic using the dsp56001 . for extended precision division (i.e., for n-bit quotients where n>24), the div instruction is no longer applicable, and a user-defined n-bit division routine is required. for further information on division algorithms, refer to pages 524e530 of theory and application of digital signal processing by rabiner and gold (prentice-hall, 1975), pages 190e199 of computer architecture and organization by john hayes (mcgraw-hill, 1978), pages 213e223 of computer arithmetic: principles, architecture, and design by kai hwang (john wiley and sons, 1979), or other references as required. condition codes : l ? set if overflow bit v is set v ? set if the ms bit of the destination operand is changed as a result of the instruction?s left shift operation c ? set if bit 55 of the result is cleared. div divide interation div mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l eu n z vc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 87 instruction format: div s,d opcode: instruction fields: s,d j j d s,d j j d x0,a 0 0 0 x1,a 1 0 0 x0,b 0 0 1 x1,b 1 0 1 y0,a 0 1 0 y1,a 1 1 0 y0,b 0 1 1 y1,b 1 1 1 timing: 2 oscillator clock cycles memory: 1 program word 23 16 15 8 7 0 000000011000000001jjd000 div divide interation div f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 88 instruction set details motorola operation: assembler syntax: sp+1 t sp;la t ssh;lc t ssl;x:ea t lc do x:ea,expr sp+1 t sp;pc t ssh;sr t ssl;expr e1 t la 1 t lf sp+1 t sp;la t ssh;lc t ssl;x:aa t lc do x:aa,expr sp+1 t sp;pc t ssh;sr t ssl;expr e1 t la 1 t lf sp+1 t sp;la t ssh;lc t ssl;y:ea t lc do y:ea,expr sp+1 t sp;pc t ssh;sr t ssl;expr e1 t la 1 t lf sp+1 t sp;la t ssh;lc t ssl;y:aa t lc do y:aa,expr sp+1 t sp;pc t ssh;sr t ssl;expr e1 t la 1 t lf sp+1 t sp;la t ssh;lc t ssl;#xxx t lc do #xxx,expr sp+1 t sp;pc t ssh;sr t ssl;expr e1 t la 1 t lf sp+1 t sp;la t ssh;lc t ssl;s t lc do s,expr sp+1 t sp;pc t ssh;sr t ssl;expr e1 t la 1 t lf end of loop: ssl(lf) t sr;spe1 t sp ssh t la;ssl t lc;sp e 1 t sp description: begin a hardware do loop that is to be repeated the number of times spec- ified in the instruction?s source operand and whose range of execution is terminated by the destination operand (previously shown as expr). no overhead other than the execu- tion of this do instruction is required to set up this loop. do loops can be nested and the loop count can be passed as a parameter. during the first instruction cycle, the current contents of the loop address (la) and the loop counter (lc) registers are pushed onto the system stack. the do instruction?s source operand is then loaded into the loop counter (lc) register. the lc register con- tains the remaining number of times the do loop will be executed and can be accessed from inside the do loop subject to certain restrictions. if lc equals zero, the do loop is do start hardware loop do f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 89 executed 65,536 times. all address register indirect addressing modes may be used to generate the effective address of the source operand. if immediate short data is speci- fied, the 12 ls bits of lc are loaded with the 12-bit immediate value, and the four ms bits of lc are cleared. during the second instruction cycle, the current contents of the program counter (pc) register and the status register (sr) are pushed onto the system stack. the stacking of the la, lc, pc, and sr registers is the mechanism which permits the nesting of do loops. the do instruction?s destination operand (shown as expr) is then loaded into the loop address (la) register. this 16-bit operand is located in the instruction?s 24-bit abso- lute address extension word as shown in the opcode section. the value in the program counter (pc) register pushed onto the system stack is the address of the first instruction following the do instruction (i.e., the first actual instruction in the do loop). this value is read (i.e., copied but not pulled) from the top of the system stack to return to the top of the loop for another pass through the loop. during the third instruction cycle, the loop flag (lf) is set. this results in the pc being repeatedly compared with la to determine if the last instruction in the loop has been fetched. if la equals pc, the last instruction in the loop has been fetched and the loop counter (lc) is tested. if lc is not equal to one, it is decremented by one and ssh is loaded into the pc to fetch the first instruction in the loop again. if lc equals one, the end-of-loop processing begins. when executing a do loop, the instructions are actually fetched each time through the loop. therefore, a do loop can be interrupted. do loops can also be nested. when do loops are nested, the end-of-loop addresses must also be nested and are not allowed to be equal. the assembler generates an error message when do loops are improperly nested. nested do loops are illustrated in the example. note: the assembler calculates the end-of-loop address to be loaded into la (the abso- lute address extension word) by evaluating the end-of-loop expression expr and sub- tracting one. this is done to accommodate the case where the last word in the do loop is a two-word instruction. thus, the end-of-loop expression expr in the source code must represent the address of the instruction after the last instruction in the loop as shown in the example. during the end-of-loop processing, the loop flag (lf) from the lower portion (ssl) of sp is written into the status register (sr), the contents of the loop address (la) register are restored from the upper portion (ssh) of (spe1), the contents of the loop counter (lc) are restored from the lower portion (ssl) of (spe1) and the stack pointer (sp) is decre- mented by two. instruction fetches now continue at the address of the instruction follow- do start hardware loop do f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 90 instruction set details motorola ing the last instruction in the do loop. note that lf is the only bit in the status register (sr) that is restored after a hardware do loop has been exited. note: the loop flag (lf) is cleared by a hardware reset. restrictions: the end-of-loop comparison previously described actually occurs at instruction fetch time. that is, la is being compared with pc when the instruction at lae 2 is being executed. therefore, instructions which access the program controller regis- ters and/or change program flow cannot be used in locations lae2, lae1, or la. proper do loop operation is not guaranteed if an instruction starting at address lae2 , lae1 , or la specifies one of the program controller registers sr, sp, ssl, la, lc, or (implicitly) pc as a destination register. similarly, the ssh program controller register may not be specified as a source or destination register in an instruction starting at address lae2, lae1, or la. additionally, the ssh register cannot be specified as a source register in the do instruction itself and la cannot be used as a target for jumps to subroutine (i.e., jsr, jscc, jsset, or jsclr to la). a do instruction cannot be repeated using the rep instruction. the following instructions cannot begin at the indicated position(s) near the end of a do loop: at lae2, lae1, and la do movec from ssh movem from ssh movep from ssh movec to la, lc, sr, sp, ssh, or ssl movem to la, lc, sr, sp, ssh, or ssl movep to la, lc, sr, sp, ssh, or ssl andi mr ori mr two-word instructions which read lc, sp, or ssl at lae1 single-word instructions (except rep) which read lc, sp, or ssl, jclr, jset, two-word jmp, two-word jcc do start hardware loop do f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 91 at la any two-word instruction* jcc rep jclr reset jset rti jmp rts jscc stop jsr wait *this restriction applies to the situation in which the dsp56k simulator?s single-line assembler is used to change the last instruction in a do loop from a one- word instruction to a two-word instruction. other restrictions: do ssh,xxxx jsr to (la) whenever the loop flag (lf) is set jscc to (la) whenever the loop flag (lf) is set jsclr to (la) whenever the loop flag (lf) is set jsset to (la) whenever the loop flag (lf) is set a do instruction cannot be repeated using the rep instruction. note: due to instruction pipelining, if an agu register (mn, nn, or rn) is directly changed with a move-type instruction, the new contents may not be available for use until the second following instruction. see the restrictions discussed in a.9.6 - r, n, and m regis- ter restrictions on page a-310.this restriction also applies to the situation in which the last instruction in a do loop changes an address register and the first instruction at the top of the do loop uses that same address register. the top instruction becomes the fol- lowing instruction because of the loop construct. similarly, since the do instruction accesses the program controller registers, the do instruction must not be immediately preceded by any of the following instructions: immediately before do movec to la, lc, ssh, ssl, or sp movem to la, lc, ssh, ssl, or sp movep to la, lc, ssh, ssl, or sp movec from ssh movem from ssh movep from ssh do start hardware loop do f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 92 instruction set details motorola example: : do #cnt1, end1 ;begin outer do loop : do #cnt2, end2 ;begin inner do loop : : move a,x:(r0)+ : end2 ;last instruction in inner loop add a,b x:(r1)+,x0 ;(in outer loop) end1 : ;last instruction in outer loop : ;first instruction after outer loop explanation of example: this example illustrates a nested do loop. the outer do loop will be executed cnt1 times while the inner do loop will be executed (cnt1 * cnt2) times. note that the labels end1 and end2 are located at the first instruction past the end of the do loop, as mentioned above, and are nested properly. condition codes: for source operand a or b: lf ? set when a do loop is in progress s ? computed according to the definition. see notes on page a-97. l ? set if data limiting occurred. see notes on page a-97. for other source operands: lf ? set when a do loop is in progress do start hardware loop do mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 93 instruction format: do x:ea, expr do y:ea, expr opcode: instruction fields: ea=6-bit effective address=mmmrrr, expr=16-bit absolute address in 24-bit extension word effective addressing mode m m m r r r memory spaces (rn)-nn 0 0 0 r r r x memory 0 (rn)+nn 0 0 1 r r r y memory 1 (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r where rrr refers to an address register r0-r7 timing: 6+mv oscillator clock cycles memory: 2 program words do start hardware loop do 23 20 19 16 15 8 7 0 0000011 001mmmrrr 0 s 000000 absolute address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 94 instruction set details motorola instruction format: do x:aa, expr do y:aa, expr opcode: instruction fields: ea=6-bit effective short address=aaaaaa, expr=16-bit absolute address in 24-bit extension word absolute short address aaaaaa memory spaces 000000 x memory 0 y memory 1 111111 timing: 6+mv oscillator clock cycles memory: 2 program words do start hardware loop do 23 20 19 16 15 8 7 0 0000011000aaaaaa0s000000 absolute address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 95 instruction format: do #xxx, expr opcode: instruction fields: #xxx=12-bit immediate short data = hhhhiiiiiiii, expr=16-bit absolute address in 24-bit extension word immediate short data hhhh i i i i i i i i 000000000000 111111111111 timing: 6+mv oscillator clock cycles memory: 2 program words 23 20 19 16 15 8 7 0 00000110iiiiiiii1000hhhh absolute address extension do start hardware loop do f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 96 instruction set details motorola instruction format: do s, expr opcode: instruction fields: s=6-bit source operand = dddddd, expr=16-bit absolute address in 24-bit extension word s source d d d d d d s/l source d ddddd x0 000100 no sr 111001 x1 000101 no omr 111010 y0 000110 no sp* 111011 y1 000111 no ssl** 111101 a0 001000 no la 111110 b0 001001 no lc 111111 a2 001010 no r0-r7 010r r r b2 001100 no n0-n7 011nnn a1 001101 no m0-m7 100mmm a 001110 yes [see notes on page a-97] b 001111 yes [see notes on page a-97] where rrr=rn register where nnn=nn register where mmm=mn register *for do sp, expr the actual value that will be loaded into the loop counter (lc) is the value of the stack pointer (sp) before the execution of the do instruction, incremented by 1. thus, if sp=3, the execution of the do sp,expr instruction will load the loop counter (lc) with the value lc=4. **for do ssl, expr the loop counter (lc) will be loaded with its previous value which was saved on the stack by the do instruction itself. 23 20 19 16 15 8 7 0 0000011 011ddddddd0 000000 absolute address extension do start hardware loop do f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 97 notes: if a or b is specified as the destination operand, the following sequence of events takes place: 1. the s bit is computed according to its definition (see section a.5) 2. the accumulator value is scaled according to the scaling mode bits s0 and s1 in the status register (sr). 3. if the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the l bit is set. 4. the ls 16 bits of the resulting 24 bit value is loaded into the loop counter (lc). the original contents of a or b are not changed. timing: 6+mv oscillator clock cycles memory: 2 program words do start hardware loop do f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 98 instruction set details motorola operation: assembler syntax: ssl(lf) t sr;sp e 1 t sp enddo ssh t la; ssl t lc;sp e1 t sp description: terminate the current hardware do loop before the current loop counter (lc) equals one. if the value of the current do loop counter (lc) is needed, it must be read before the execution of the enddo instruction. initially, the loop flag (lf) is restored from the system stack and the remaining portion of the status register (sr) and the program counter (pc) are purged from the system stack. the loop address (la) and the loop counter (lc) registers are then restored from the system stack. restrictions: due to pipelining and the fact that the enddo instruction accesses the program controller registers, the enddo instruction must not be immediately preceded by any of the following instructions: immediately before enddo movec to la, lc, sr, ssh, ssl, or sp movem to la, lc, sr, ssh, ssl, or sp movep to la, lc, sr, ssh, ssl, or sp movec from ssh movem from ssh movep from ssh ori mr andi mr rep also, the enddo instruction cannot be the last (la) instruction in a do loop. example: : do y0,next ;exec. loop ending at next (y0) times : movec lc,a ;get current value of loop counter (lc) cmp y1,a ;compare loop counter with value in y1 jne onward ;go to onward if lc not equal to y1 enddo ;lc equal to y1, restore all do registers jmp next ;go to next onward : ;lc not equal to y1, continue do loop : ;(last instruction in do loop) next move #$123456,x1 ;(first instruction after do loop) enddo end current do loop enddo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 99 explanation of example: this example illustrates the use of the enddo instruction to terminate the current do loop. the value of the loop counter (lc) is compared with the value in the y1 register to determine if execution of the do loop should continue. note that the enddo instruction updates certain program controller registers but does not automatically jump past the end of the do loop. thus, if this action is desired, a jmp instruction (i.e., jmp next as previously shown) must be included after the enddo instruction to transfer program control to the first instruction past the end of the do loop. condition codes: the condition codes are not affected by this instruction. instruction format: enddo opcode: instruction fields: none timing: 2 oscillator clock cycles memory: 1 program word mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c 23 16 15 8 7 0 000000000000000010001100 enddo end current do loop enddo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 100 instruction set details motorola operation: assembler syntax: s ? d[47:24] t d[47:24] (parallel move) eor s,d (parallel move) where ? denotes the logical exclusive or operator description: logically exclusive or the source operand s with bits 47e24 of the desti- nation operand d and store the result in bits 47e24 of the destination accumulator. this instruction is a 24-bit operation. the remaining bits of the destination operand d are not affected. example: : eor y1,b1 (r2)+ ;exclusive or y1 with b1, update r2 : explanation of example: prior to execution, the 24-bit y1 register contains the value $000003, and the 56-bit b accumulator contains the value $00:000005:000000. the eor y1,b instruction logically exclusive ors the 24-bit value in the y1 register with bits 47e24 of the b accumulator (b1) and stores the result in the b accumulator with bits 55e 48 and 23e0 unchanged. condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move n ? set if bit 47 of a or b result is set z? set if bits 47 - 24 of a or b result are zero v ? always cleared eor logical exclusive or eor before execution after execution y1 y1 $000003 b b $00:000005:000000 $00:000006:000000 $000003 mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu nz v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 101 instruction format: eor s,d opcode: instruction fields: s j j d d x0 0 0 a 0 x1 1 0 b 1 y0 0 1 y1 1 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words 23 8 7 4 3 0 data bus move field 01jj d011 optional effective address extension eor logical exclusive or eor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 102 instruction set details motorola operation: assembler syntax: begin illegal instruction illegal exception processing description: the illegal instruction is executed as if it were a nop instruction. nor- mal instruction execution is suspended and illegal instruction exception processing is ini- tiated. the interrupt vector address is located at address p:$3e. the interrupt priority level (i1, i0) is set to 3 in the status register if a long interrupt service routine is used. the purpose of the illegal instruction is to force the dsp into an illegal instruction excep- tion for test purposes. if a fast interrupt is used with the illegal instruction, an infinite loop will be formed (an illegal instruction interrupt normally returns to the illegal instruc- tion) which can only be broken by a hardware reset. therefore, only long interrupts should be used. exiting an illegal instruction is a fatal error. the long exception routine should indicate this condition and cause the system to be restarted. if the illegal instruction is in a do loop at la and the instruction at lae1 is being inter- rupted, then lc will be decremented twice due to the same mechanism that causes lc to be decremented twice if jsr, rep, etc. are located at la. this is why jsr, rep, etc. at la are restricted. clearly restrictions cannot be imposed on illegal instructions. since rep is uninterruptable, repeating an illegal instruction results in the interrupt not being initiated until after completion of the rep. after servicing the interrupt, program control will return to the address of the second word following the illegal instruction. of course, the illegal interrupt service routine should abort further processing, and the processor should be reinitialized. example: : illegal ;begin illegal exception processing : explanation of example: the illegal instruction suspends normal instruction execu- tion and initiates illegal exception processing. illegal illegal instruction interrupt illegal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 103 condition codes: the condition codes are not affected by this instruction. instruction format: illegal opcode: instruction fields: none timing: 8 oscillator clock cycles memory: 1 program word mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c 23 16 15 8 7 0 000000000000000000000101 illegal illegal instruction interrupt illegal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 104 instruction set details motorola operation: assembler syntax: d+1 t d inc d description: increment by one the specified operand and store the result in the destina- tion accumulator. one is added from the lsb of d. example: : inc b ;increment the content of the b accumulator by one : explanation of example: one is added to the content of the b accumulator. condition codes: l ? set if overflow has occurred in a or b result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z ? set if a or b result equals zero v ? set if overflow has occurred in a or b result c ? set if a carry is generated from bit 55 of a or b result inc increment by one inc mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s leunzvc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 105 instruction format: inc d opcode: instruction fields: dd a0 b1 timing: 2 oscillator clock cycles memory: 1 program word inc increment by one inc 23 16 15 8 7 0 00000000000000000000100d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 106 instruction set details motorola operation: assembler syntax: if cc, then 0xxx t pc jcc xxx else pc+1 t pc if cc, then ea t pc jcc xxx else pc+1 t pc description: jump to the location in program memory given by the instruction?s effective address if the specified condition is true. if the specified condition is false, the program counter (pc) is incremented and the effective address is ignored. however, the address register specified in the effective address field is always updated independently of the specified condition. all memory alterable addressing modes may be used for the effec- tive address. a fast short jump addressing mode may also be used. the 12-bit data is zero extended to form the effective address. see section a.9 for restrictions. the term cc may specify the following conditions: cc mnemonic condition cc (hs) ? carry clear (higher or same) c=0 cs (lo) ? carry set (lower) c=1 ec ? extension clear e=0 eq ? equal z=1 es ? extension set e=1 ge ? greater than or equal n ? v=0 gt ? greater than z+(n ? v)=0 lc ? limit clear l=0 le ? less than or equal z+(n ? v)=1 ls ? limit set l=1 lt ? less than n ? v=1 mi ? minus n=1 ne ? not equal z=0 nr ? normalized z+(u e )=1 pl ? plus n=0 nn ? not normalized z+(u e )=0 where u denotes the logical complement of u, + denotes the logical or operator, denotes the logical and operator, and ? denotes the logical exclusive or operator jcc jump conditionally jcc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 107 restrictions: a jcc instruction used within a do loop cannot begin at the address la within that do loop. a jcc instruction cannot be repeated using the rep instruction. example: : jnn e (r4) ;jump to p:(r4) e1 if not normalized : explanation of example: in this example, program execution is transferred to the address p:(r4)e1 if the result is not normalized. note that the contents of address regis- ter r4 are predecremented by 1, and the resulting address is then loaded into the pro- gram counter (pc) if the specified condition is true. if the specified condition is not true, no jump is taken, and the program counter is incremented by one. condition codes: the condition codes are not affected by this instruction. instruction format: jcc xxx opcode: jcc jump conditionally jcc mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c 23 16 15 8 7 0 00001110ccccaaaaaaaaaaaa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 108 instruction set details motorola instruction fields: cc=4-bit condition code=cccc, xxx=12-bit short jump address=aaaaaaaaaaaa mnemonic c c c c mnemonic c c c c cc (hs) 0 0 0 0 cs (lo) 1 0 0 0 ge 0 001 lt 1001 ne 0 010 eq 1010 pl 0 011 mi 1011 nn 0 100 nr 1100 ec 0 101 es 1101 lc 0 110 ls 1110 gt 0 111 le 1111 timing: 4+jx oscillator clock cycles memory: 1+ea program words instruction format: jcc ea opcode: instruction fields: cc=4-bit condition code=cccc, ea=6-bit effective address=mmmrrr jcc jump conditionally jcc 23 16 15 8 7 0 optional effective address extension 0000101 0 11mmmrrr1010cccc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 109 effective addressing mode m m m r r r (rn)-nn 0 0 0 r r r (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 where rrr refers to an address register r0-r7 mnemonic c c c c mnemonic c c c c cc (hs) 0 0 0 0 cs (lo) 1 0 0 0 ge 0 001 lt 1001 ne 0 010 eq 1010 pl 0 011 mi 1011 nn 0 100 nr 1100 ec 0 101 es 1101 lc 0 110 ls 1110 gt 0 111 le 1111 timing: 4+jx oscillator clock cycles memory: 1+ea program words jcc jump conditionally jcc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 110 instruction set details motorola operation: assembler syntax: if s[n]=0, then xxxx t pc jclr #n,x:ea,xxxx else pc+1 t pc if s[n]=0, then xxxx t pc jclr #n,x:aa,xxxx else pc+1 t pc if s[n]=0, then xxxx t pc jclr #n,x:pp,xxxx else pc+1 t pc if s[n]=0, then xxxx t pc jclr #n,y:ea,xxxx else pc+1 t pc if s[n]=0, then xxxx t pc jclr #n,y:aa,xxxx else pc+1 t pc if s[n]=0, then xxxx t pc jclr #n,y:pp,xxxx else pc+1 t pc if s[n]=0, then xxxx t pc jclr #n,s,xxxx else pc+1 t pc description: jump to the 16-bit absolute address in program memory specified in the instruction?s 24-bit extension word if the n th bit of the source operand s is clear. the bit to be tested is selected by an immediate bit number from 0e23. if the specified memory bit is not clear, the program counter (pc) is incremented and the absolute address in the extension word is ignored. however, the address register specified in the effective address field is always updated independently of the state of the n th bit. all address reg- ister indirect addressing modes may be used to reference the source operand s. abso- lute short and i/o short addressing modes may also be used. jclr jump if bit clear jclr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 111 restrictions: a jclr instruction cannot be repeated using the rep instruction. a jclr located at la, lae1, or lae2 of the do loop cannot specify the program control- ler registers sr, sp, ssh, ssl, la, or lc as its target. jclr ssh or jclr ssl cannot follow an instruction that changes the sp. example: : jclr #$5,x:<<$fff1,$1234 ;go to p:$1234 if bit 5 in sci ssr is clear : explanation of example: in this example, program execution is transferred to the address p:$1234 if bit 5 (pe) of the 8-bit read-only x memory location x:$fff1 (i/o sci interface status register) is a zero. if the specified bit is not clear, no jump is taken, and the program counter (pc) is incremented by one. condition codes: for destination operand a or b: s ?computed according to the definition. see notes on page a-115. l ? set if data limiting has occurred. see notes on page a-115. e ? not affected u ? not affected n ? not affected z ? not affected v ? not affected c ? not affected for other source operands: the condition codes are not affected. jclr jump if bit clear jclr mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 112 instruction set details motorola instruction format: jclr #n,x:ea,xxxx jclr #n,y:ea,xxxx opcode: instruction fields: #n=bit number=bbbbb, ea=6-bit effective address=mmmrrr xxxx=16-bit absolute address in extension word effective addressing mode m m m r r r memory spaces bit number bbbbb (rn)-nn 0 0 0 r r r x memory 0 00000 (rn)+nn 0 0 1 r r r y memory 1 (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r 10111 (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r where rrr refers to an address register r0-r7 timing: 6+jx oscillator clock cycles memory: 2 program words jclr jump if bit clear jclr 23 16 15 8 7 0 absolute address extension 0000101 0 01mmmrrr1s0bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 113 instruction format: jclr #n,x:aa,xxxx jclr #n,y:aa,xxxx opcode: instruction fields: #n=bit number=bbbbb, aa=6-bit absolute short address=aaaaaa xxxx=16-bit absolute address in extension word absolute short address aaaaaa memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 6+jx oscillator clock cycles memory: 2 program words jclr jump if bit clear jclr 23 16 15 8 7 0 absolute address extension 0000101 0 00a aaaaa 1s0bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 114 instruction set details motorola instruction format: jclr #n,x:pp,xxxx jclr #n,y:pp,xxxx opcode: instruction fields: #n=bit number=bbbbb, pp=6-bit i/o short address=pppppp xxxx=16-bit absolute address in extension word i/o short address pppppp memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 6+jx oscillator clock cycles memory: 2 program words jclr jump if bit clear jclr 23 16 15 8 7 0 absolute address extension 0000101 0 10p ppppp 1s0bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 115 instruction format: jclr #n,s,xxxx opcode: instruction fields: #n=bit number=bbbbb, s=source register=dddddd xxxx=16-bit absolute address in extension word source register d d d d d d bit number bbbbb 4 registers in data alu 0 0 0 1 d d 00000 8 accumulators in data alu 0 0 1 d d d 8 address registers in agu 0 1 0 t t t 10111 8 address offset registers in agu 0 1 1 n n n 8 address modifier registers in agu 1 0 0 f f f 8 program controller registers 1 1 1 g g g see section a.10 and table a-18 for specific register encodings. notes: if a or b is specified as the destination operand, the following sequence of events takes place: 1. the s bit is computed according to its definition (see section a.5) 2. the accumulator value is scaled according to the scaling mode bits s0 and s1 in the status register (sr). 3. if the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the l bit is set. 4. the bit test is performed on the resulting 24-bit value, and the jump is taken if the bit tested is clear. the original contents of a or b are not changed. timing: 6+jx oscillator clock cycles memory: 2 program words jclr jump if bit clear jclr 23 16 15 8 7 0 absolute address extension 0000101 0 11d ddddd000bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 116 instruction set details motorola operation: assembler syntax: 0xxx t pc jmp xxx ea t pc jmp ea description: jump to the location in program memory given by the instruction?s effective address. all memory alterable addressing modes may be used for the effective address. a fast short jump addressing mode may also be used. the 12-bit data is zero extended to form the effective address. restrictions: a jmp instruction used within a do loop cannot begin at the address la within that do loop. a jmp instruction cannot be repeated using the rep instruction. example: : jmp (r1+n1) ;jump to program address p:(r1+n1) : explanation of example: in this example, program execution is transferred to the pro- gram address p:(r1+n1). condition codes: the condition codes are not affected by this instruction. instruction format: jmp xxx opcode: jmp jump jmp mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c 23 16 15 8 7 0 000011000000aaaaaaaaaaaa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 117 instruction fields: xxx=12-bit short jump address=aaaaaaaaaaaa timing: 4+jx oscillator clock cycles memory: 1+ea program words instruction format: jmp ea opcode: instruction fields: ea=6-bit effective address=mmmrrr effective addressing mode m m m r r r (rn)-nn 0 0 0 r r r (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 where rrr refers to an address register r0-r7 timing: 4+jx oscillator clock cycles memory: 1+ea program words jmp jump jmp 23 16 15 8 7 0 0000101 011mmmrrr 1 0 000000 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 118 instruction set details motorola operation: assembler syntax: if cc, then sp+1 t sp; pc t ssh; sr t ssl; 0xxx t pc jscc xxx else pc+1 t pc if cc, then sp+1 t sp; pc t ssh; sr t ssl; ea t pc jscc ea else pc+1 t pc description: jump to the subroutine whose location in program memory is given by the instruction?s effective address if the specified condition is true. if the specified condition is true, the address of the instruction immediately following the jscc instruction (pc) and the system status register (sr) are pushed onto the system stack. program execution then continues at the specified effective address in program memory. if the specified condition is false, the program counter (pc) is incremented, and any extension word is ignored. however, the address register specified in the effective address field is always updated independently of the specified condition. all memory alterable addressing modes may be used for the effective address. a fast short jump addressing mode may also be used. the 12-bit data is zero extended to form the effective address. the term cc may specify the following conditions: cc mnemonic condition cc (hs) ? carry clear (higher or same) c=0 cs (lo) ? carry set (lower) c=1 ec ? extension clear e=0 eq ? equal z=1 es ? extension set e=1 ge ? greater than or equal n ? v=0 gt ? greater than z+(n ? v)=0 lc ? limit clear l=0 le ? less than or equal z+(n ? v)=1 ls ? limit set l=1 lt ? less than n ? v=1 mi ? minus n=1 ne ? not equal z=0 nr ? normalized z+(u e )=1 pl ? plus n=0 nn ? not normalized z+(u e )=0 jscc jump to subroutine conditionally jscc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 119 where u denotes the logical complement of u, + denotes the logical or operator, denotes the logical and operator, and ? denotes the logical exclusive or operator restrictions: a jscc instruction used within a do loop cannot specify the loop address (la) as its target. a jscc instruction used within in a do loop cannot begin at the address la within that do loop. a jscc instruction cannot be repeated using the rep instruction. example: : jsls (r3+n3) ;jump to subroutine at p:(r3+n3) if limit set (l=1) : explanation of example: in this example, program execution is transferred to the sub- routine at address p:(r3+n3) in program memory if the limit bit is set (l=1). both the return address (pc) and the status register (sr) are pushed onto the system stack prior to transferring program control to the subroutine if the specified condition is true. if the specified condition is not true, no jump is taken and the program counter is incremented by 1. condition codes: the condition codes are not affected by this instruction. jscc jump to subroutine conditionally jscc mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 120 instruction set details motorola instruction format: jscc xxx opcode: instruction fields: cc=4-bit condition code=cccc, xxx=12-bit short jump address=aaaaaaaaaaaa mnemonic c c c c mnemonic c c c c cc (hs) 0 0 0 0 cs (lo) 1 0 0 0 ge 0 001 lt 1001 ne 0 010 eq 1010 pl 0 011 mi 1011 nn 0 100 nr 1100 ec 0 101 es 1101 lc 0 110 ls 1110 gt 0 111 le 1111 timing: 4+jx oscillator clock cycles memory: 1+ea program words jscc jump to subroutine conditionally jscc 23 16 15 8 7 0 00001111ccccaaaaaaaaaaaa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 121 instruction format: jscc ea opcode: instruction fields: cc=4-bit condition code=cccc, ea=6-bit effective address=mmmrrr effective addressing mode mmmr r r mnemonic c c c c mnemonic c c c c (rn)enn 000r r r cc (hs) 0 0 0 0 cs (lo) 1 0 0 0 (rn)+nn0 001r r r ge 000 1 lt 1 00 1 (rn)e 010r r r ne 001 0 eq 1 01 0 (rn)+ 011r r r pl 001 1 mi 1 01 1 (rn) 100r r r nn 010 0 nr 1 10 0 (rn+nn) 101r r r ec 010 1 es 1 10 1 e(rn) 111r r r lc 011 0 ls 1 11 0 absolute address 11000 0 gt 011 1 le 1 11 1 where rrr refers to an address register r0er7 timing: 4+jx oscillator clock cycles memory: 1+ea program words jscc jump to subroutine conditionally jscc 23 16 15 8 7 0 optional effective address extension 0000101 1 11mmmrrr1010cccc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 122 instruction set details motorola operation: assembler syntax if s[n]=0, jsclr #n,x:ea,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc f s[n]=0, jsclr #n,x:aa,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc if s[n]=0, jsclr #n,x:pp,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc if s[n]=0, jsclr #n,y:ea,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc if s[n]=0, jsclr #n,y:aa,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc if s[n]=0, jsclr #n,y:pp,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc if s[n]=0, jsclr #n,s,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc description: jump to the subroutine at the 16-bit absolute address in program memory specified in the instruction?s 24-bit extension word if the n th bit of the source operand s is clear. the bit to be tested is selected by an immediate bit number from 0e23. if the n th bit of the source operand s is clear, the address of the instruction immediately following the jsclr instruction (pc) and the system status register (sr) are pushed onto the system stack. program execution then continues at the specified absolute address in the instruc- tion?s 24-bit extension word. if the specified memory bit is not clear, the program counter (pc) is incremented and the extension word is ignored. however, the address register jsclr jump to subroutine if bit clear jsclr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 123 specified in the effective address field is always updated independently of the state of the n th bit. all address register indirect addressing modes may be used to reference the source operand s. absolute short and i/o short addressing modes may also be used . restrictions: a jsclr instruction used within a do loop cannot specify the loop address (la) as its target. a jsclr located at la, lae1, or lae2 of a do loop, cannot specify the program control- ler registers sr, sp, ssh, ssl, la, or lc as its target. jsclr ssh or jsclr ssl cannot follow an instruction that changes the sp. a jsclr instruction cannot be repeated using the rep instruction. example: : jsclr #$1,y:<<$ffe3,$1357 ;go sub. at p:$1357 if bit 1 in y:$ffe3 is clear : explanation of example: in this example, program execution is transferred to the sub- routine at absolute address p:$1357 in program memory if bit 1 of the external i/o loca- tion y:<<$ffe3 is a zero. if the specified bit is not clear, no jump is taken and the program counter (pc) is incremented by 1. jsclr jump to subroutine if bit clear jsclr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 124 instruction set details motorola condition codes: for destination operand a or b: s ?computed according to the definition. see notes on page a-129. l ? set if data limiting has occurred. see notes on page a-129. e ? not affected u ? not affected n ? not affected z ? not affected v ? not affected c ? not affected for other source operands: the condition codes are not affected. jsclr jump to subroutine if bit clear jsclr mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 125 instruction format: jsclr #n,x:ea,xxxx jsclr #n,y:ea,xxxx opcode: instruction fields: #n=bit number=bbbbb, ea=6-bit effective address=mmmrrr, xxxx=16-bit absolute address in extension word effective addressing mode m m m r r r memory spaces bit number bbbbb (rn)-nn 0 0 0 r r r x memory 0 00000 (rn)+nn 0 0 1 r r r y memory 1 (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r 10111 (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r where rrr refers to an address register r0-r7 timing: 6+jx oscillator clock cycles memory: 2 program words 23 16 15 8 7 0 absolute address extension 0000101 1 01mmmrrr1s0bbbbb jsclr jump to subroutine if bit clear jsclr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 126 instruction set details motorola instruction format: jsclr #n,x:aa,xxxx jsclr #n,y:aa,xxxx opcode: instruction fields: #n=bit number=bbbbb, aa=6-bit absolute short address=aaaaaa, xxxx=16-bit absolute address in extension word absolute short address aaaaaa memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 6+jx oscillator clock cycles memory: 2 program words 23 16 15 8 7 0 absolute address extension 0000101 1 00a aaaaa 1s0bbbbb jsclr jump to subroutine if bit clear jsclr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 127 instruction format: jsclr #n,x:pp,xxxx jsclr #n,y:pp,xxxx opcode: instruction fields: #n=bit number=bbbbb, pp=6-bit i/o short address=pppppp, xxxx=16-bit absolute address in extension word i/o short address aaaaaa memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 6+jx oscillator clock cycles memory: 2 program words 23 16 15 8 7 0 absolute address extension 0000101 1 10p ppppp 1s0bbbbb jsclr jump to subroutine if bit clear jsclr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 128 instruction set details motorola instruction format: jsclr #n,s,xxxx opcode: instruction fields: #n=bit number=bbbbb, s=source register=dddddd, xxxx=16-bit absolute address in extension word source register d d d d d d bit number bbbbb 4 registers in data alu 0 0 0 1 d d 00000 8 accumulators in data alu 0 0 1 d d d 8 address registers in agu 0 1 0 t t t 10111 8 address offset registers in agu 0 1 1 n n n 8 address modifier registers in agu 1 0 0 f f f 8 program controller registers 1 1 1 g g g see section a.10 and table a-18 for specific register encodings. jsclr jump to subroutine if bit clear jsclr 23 16 15 8 7 0 absolute address extension 0000101 1 11d ddddd000bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 129 notes: if a or b is specified as the destination operand, the following sequence of events takes place: 1. the s bit is computed according to its definition (see section a.5) 2. the accumulator value is scaled according to the scaling mode bits s0 and s1 in the status register (sr). 3. if the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the l bit is set. 4. the bit test is performed on the resulting 24-bit value, and the jump to sub- routine is taken if the bit tested is clear. the original contents of a or b are not changed. timing: 6+jx oscillator clock cycles memory: 2 program words jsclr jump to subroutine if bit clear jsclr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 130 instruction set details motorola operation: assembler syntax: if s[n]=0, then xxxx t pc jset #n,x:ea,xxxx else pc+1 t pc if s[n]=1, then xxxx t pc jset #n,x:ea,xxxx else pc+1 t pc if s[n]=1, then xxxx t pc jset #n,x:aa,xxxx else pc+1 t pc if s[n]=1, then xxxx t pc jset #n,x:pp,xxxx else pc+1 t pc if s[n]=1, then xxxx t pc jset #n,y:ea,xxxx else pc+1 t pc if s[n]=1, then xxxx t pc jset #n,y:aa,xxxx else pc+1 t pc if s[n]=1, then xxxx t pc jset #n,y:pp,xxxx else pc+1 t pc if s[n]=1, then xxxx t pc jset #n,s,xxxx else pc+1 t pc description: jump to the 16-bit absolute address in program memory specified in the instruction?s 24-bit extension word if the n th bit of the source operand s is set. the bit to be tested is selected by an immediate bit number from 0e23. if the specified memory bit is not set, the program counter (pc) is incremented, and the absolute address in the extension word is ignored. however, the address register specified in the effective address field is always updated independently of the state of the n th bit. all address reg- ister indirect addressing modes may be used to reference the source operand s. abso- lute short and i/o short addressing modes may also be used. jset jump if bit set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 131 restrictions: a jset instruction used within a do loop cannot specify the loop address (la) as its target. a jset located at la, lae1, or lae2 of a do loop cannot specify the program controller registers sr, sp, ssh, ssl, la, or lc as its target. jset ssh or jset ssl cannot follow an instruction that changes the sp. a jset instruction cannot be repeated using the rep instruction. example: : jset #12,x:<<$fff2,$4321 ;$4321 t (pc) if bit 12 (sci cod) is set : explanation of example: in this example, program execution is transferred to the address p:$4321 if bit 12 (sci cod) of the 16-bit read/write i/o register x:$fff2 is a one. if the specified bit is not set, no jump is taken and the program counter (pc) is incre- mented by 1. condition codes: for destination operand a or b: s ?computed according to the definition. see notes on page a-135. l ? set if data limiting has occurred. see notes on page a-135. e ? not affected u ? not affected n ? not affected z ? not affected v ? not affected c ? not affected for other source operands: the condition codes are not affected. jset jump if bit set mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 132 instruction set details motorola instruction format: jset #n,x:ea,xxxx jset #n,y:ea,xxxx opcode: instruction fields: #n=bit number=bbbbb, ea=6-bit effective address=mmmrrr xxxx=16-bit absolute address in extension word effective addressing mode m m m r r r memory spaces bit number bbbbb (rn)-nn 0 0 0 r r r x memory 0 00000 (rn)+nn 0 0 1 r r r y memory 1 (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r 10111 (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r where rrr refers to an address register r0-r7 timing: 6+jx oscillator clock cycles memory: 2 program words 23 16 15 8 7 0 absolute address extension 0000101 0 01mmmrrr1s1bbbbb jset jump if bit set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 133 instruction format: jset #n,x:aa,xxxx jset #n,y:aa,xxxx opcode: instruction fields: #n=bit number=bbbbb, aa=6-bit absolute short address=aaaaaa, xxxx=16-bit absolute address in extension word absolute short address aaaaaa memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 6+jx oscillator clock cycles memory: 2 program words 23 16 15 8 7 0 absolute address extension 0000101 0 00a aaaaa 1s1bbbbb jset jump if bit set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 134 instruction set details motorola instruction format: jset #n,x:pp,xxxx jset #n,y:pp,xxxx opcode: instruction fields: #n=bit number=bbbbb, pp=6-bit i/o short address=pppppp, xxxx=16-bit absolute address in extension word i/o short address pppppp memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 6+jx oscillator clock cycles memory: 2 program words jset jump if bit set 23 16 15 8 7 0 absolute address extension 0000101 0 10p ppppp 1s1bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 135 instruction format: jset #n,s,xxxx opcode: instruction fields: #n=bit number=bbbbb, s=source register=dddddd, xxxx=16-bit absolute address in extension word source register d d d d d d bit number bbbbb 4 registers in data alu 0 0 0 1 d d 00000 8 accumulators in data alu 0 0 1 d d d 8 address registers in agu 0 1 0 t t t 10111 8 address offset registers in agu 0 1 1 n n n 8 address modifier registers in agu 1 0 0 f f f 8 program controller registers 1 1 1 g g g see section a.10 and table a-18 for specific register encodings. notes: if a or b is specified as the destination operand, the following sequence of events takes place: 1. the s bit is computed according to its definition (see section a.5) 2. the accumulator value is scaled according to the scaling mode bits s0 and s1 in the status register (sr). 3. if the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the l bit is set. 4. the bit test is performed on the resulting 24-bit value, and the jump is taken if the bit tested is set. the original contents of a or b are not changed. timing: 6+jx oscillator clock cycles memory: 2 program words 23 16 15 8 7 0 absolute address extension 0000101 0 11d ddddd001bbbbb jset jump if bit set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 136 instruction set details motorola operation: assembler syntax: sp+1 t sp; pc t ssh; sr t ssl; 0xxx t pc jsr xxx sp+ t sp; pc t ssh; sr t ssl; ea t pc jsr ea description: jump to the subroutine whose location in program memory is given by the instruction?s effective address. the address of the instruction immediately following the jsr instruction (pc) and the system status register (sr) is pushed onto the system stack. program execution then continues at the specified effective address in program memory. all memory alterable addressing modes may be used for the effective address. a fast short jump addressing mode may also be used. the 12-bit data is zero extended to form the effective address. restrictions: a jsr instruction used within a do loop cannot specify the loop address (la) as its target. a jsr instruction used within a do loop cannot begin at the address la within that do loop. a jsr instruction cannot be repeated using the rep instruction. example: : jsr (r5)+ ;jump to subroutine at (r5), update r5 : explanation of example: in this example, program execution is transferred to the sub- routine at address p:(r5) in program memory, and the contents of the r5 address regis- ter are then updated. condition codes: the condition codes are not affected by this instruction. jsr jump to subroutine jsr mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 137 instruction format: jsr xxx opcode: instruction fields: xxx=12-bit short jump address=aaaaaaaaaaaa timing: 4+jx oscillator clock cycles memory: 1+ea program words instruction format: jsr ea opcode: instruction fields: ea=6-bit effective address=mmmrrr effective addressing mode m m m r r r (rn)-nn 0 0 0 r r r (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 where rrr refers to an address register r0-r7 timing: 4+jx oscillator clock cycles memory: 1+ea program words 23 16 15 8 7 0 000011010000aaaaaaaaaaaa jsr jump to subroutine jsr 23 16 15 8 7 0 optional effective address extension 0000101 1 11mmmrrr10000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 138 instruction set details motorola operation: assembler syntax if s[n]=1, jsset #n,x:ea,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc if s[n]=1, jsset #n,x:aa,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc if s[n]=1, jsset #n,x:pp,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc if s[n]=1, jsset #n,y:ea,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc if s[n]=1, jsset #n,y:aa,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc if s[n]=1, jsset #n,y:pp,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc if s[n]=1, jsset #n,s,xxxx then sp+1 t sp; pc t ssh; sr t ssl; xxxx t pc else pc+1 t pc description: jump to the subroutine at the 16-bit absolute address in program memory specified in the instruction?s 24-bit extension word if the n th bit of the source operand s is set. the bit to be tested is selected by an immediate bit number from 0e23. if the n th bit of the source operand s is set, the address of the instruction immediately following the jsset instruction (pc) and the system status register (sr) are pushed onto the system stack. program execution then continues at the specified absolute address in the instruc- tion?s 24-bit extension word. if the specified memory bit is not set, the program counter (pc) is incremented, and the extension word is ignored. however, the address register specified in the effective address field is always updated independently of the state of the jsset jump to subroutine if bit set jsset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 139 n th bit. all address register indirect addressing modes may be used to reference the source operand s. absolute short and i/o short addressing modes may also be used. restrictions: a jsset instruction used within a do loop cannot specify the loop address (la) as its target. a jsset located at la, lae1, or lae2 of a do loop, cannot specify the program control- ler registers sr, sp, ssh, ssl, la, or lc as its target. jsset ssh or jsset ssl cannot follow an instruction that changes the sp. a jsset instruction cannot be repeated using the rep instruction. example: : jsset #$17,y:<$3f,$100 ;go to sub. at p:$0100 if bit 23 in y:$3f is set : explanation of example: in this example, program execution is transferred to the sub- routine at absolute address p:$0100 in program memory if bit 23 of y memory location y:$003f is a one. if the specified bit is not set, no jump is taken and the program counter (pc) is incremented by 1. condition codes: for destination operand a or b: s ?computed according to the definition. see notes on page a-143. l ? set if data limiting has occurred. see notes on page a-143. e ? not affected u ? not affected n ? not affected z ? not affected v ? not affected c ? not affected for other source operands: the condition codes are not affected. jsset jump to subroutine if bit set jsset mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 140 instruction set details motorola instruction format: jsset #n,x:ea,xxxx jsset #n,y:ea,xxxx opcode: instruction fields: #n=bit number=bbbbb, ea=6-bit effective address=mmmrrr, xxxx=16-bit absolute address in extension word effective addressing mode m m m r r r memory spaces bit number bbbbb (rn)-nn 0 0 0 r r r x memory 0 00000 (rn)+nn 0 0 1 r r r y memory 1 (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r 10111 (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r where rrr refers to an address register r0-r7 timing: 6+jx oscillator clock cycles memory: 2 program words jsset jump to subroutine if bit set jsset 23 16 15 8 7 0 absolute address exten- 0000101 1 01mmmrrr1s1bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 141 instruction format: jsset #n,x:aa,xxxx jsset #n,y:aa,xxxx opcode: instruction fields: #n=bit number=bbbbb, aa=6-bit absolute short address=aaaaaa, xxxx=16-bit absolute address in extension word absolute short address aaaaaa memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 6+jx oscillator clock cycles memory: 2 program words 23 16 15 8 7 0 absolute address extension 0000101 1 00a aaaaa 1s1bbbbb jsset jump to subroutine if bit set jsset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 142 instruction set details motorola instruction format: jsset #n,x:pp,xxxx jsset #n,y:pp,xxxx opcode: instruction fields: #n=bit number=bbbbb, pp=6-bit i/o short address=pppppp, xxxx=16-bit absolute address in extension word i/o short address pppppp memory spaces bit number bbbbb 000000 x memory 0 00000 y memory 1 10111 111111 timing: 6+jx oscillator clock cycles memory: 2 program words 23 16 15 8 7 0 absolute address extension 0000101 1 10p ppppp 1s1bbbbb jsset jump to subroutine if bit set jsset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 143 instruction format: jsset #n,s,xxxx opcode: instruction fields: #n=bit number=bbbbb, s=source register=dddddd, xxxx=16-bit absolute address in extension word source register d d d d d d bit number bbbbb 4 registers in data alu 0 0 0 1 d d 00000 8 accumulators in data alu 0 0 1 d d d 8 address registers in agu 0 1 0 t t t 10111 8 address offset registers in agu 0 1 1 n n n 8 address modifier registers in agu 1 0 0 f f f 8 program controller registers 1 1 1 g g g see section a.10 and table a-18 for specific register encodings. notes: if a or b is specified as the destination operand, the following sequence of events takes place: 1. the s bit is computed according to its definition (see section a.5) 2. the accumulator value is scaled according to the scaling mode bits s0 and s1 in the status register (sr). 3. if the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the l bit is set. 4. the bit test is performed on the resulting 24-bit value, and the jump to sub- routine is taken if the bit tested is set. the original contents of a or b are not changed. timing: 6+jx oscillator clock cycles memory: 2 program words jsset jump to subroutine if bit set jsset 23 16 15 8 7 0 absolute address extension 0000101 1 11d ddddd001bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 144 instruction set details motorola assembler syntax: lsl d (parallel move) description: logically shift bits 47e24 of the destination operand d one bit to the left and store the result in the destination accumulator. prior to instruction execution, bit 47 of d is shifted into the carry bit c, and a zero is shifted into bit 24 of the destination accu- mulator d. this instruction is a 24-bit operation. the remaining bits of the destination operand d are not affected. if a zero shift count is specified, the carry bit is cleared. the difference between lsl and asl is that lsl operates on only a1 or b1 and always clears the v bit. example: : lsl b1 #$7f,r0 ;shift b1 one bit to the left, set up r0 : explanation of example: prior to execution, the 56-bit b accumulator contains the value $00:f01234:13579b. the execution of the lsl b instruction shifts the 24-bit value in the b1 register one bit to the left and stores the result back in the b1 register. lsl logical shift left lsl 47 24 c 0 (parallel move) operation: before execution after execution b b $00:f01234:13579b sr sr $0300 $0309 $00:e02468:13579b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 145 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move n ? set if bit 47 of a or b result is set z ? set if bits 47e24 of a or b result are zero v ? always cleared c ? set if bit 47 of a or b was set prior to instruction execution instruction format: lsl d opcode: instruction fields: d d a 0 b 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu nz vc 23 8 7 4 3 0 data bus move field 0011 d011 optional effective address extension lsl logical shift left lsl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 146 instruction set details motorola assembler syntax: lsr d (parallel move) description: logically shift bits 47e24 of the destination operand d one bit to the right and store the result in the destination accumulator. prior to instruction execution, bit 24 of d is shifted into the carry bit c, and a zero is shifted into bit 47 of the destination accu- mulator d. this instruction is a 24-bit operation. the remaining bits of the destination operand d are not affected. example: : lsr a1 a1,n4 ;shift a1 one bit to the right, set up n4 : explanation of example: prior to execution, the 56-bit a accumulator contains the value $37:444445:828180. the execution of the lsr a instruction shifts the 24-bit value in the a1 register one bit to the right and stores the result back in the a1 register. lsr logical shift right lsr 47 24 0 c (parallel move) operation: before execution after execution a a $37:444445:828180 sr sr $0300 $0301 $37:222222:828180 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 147 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move n ? always cleared z? set if bits 47e24 of a or b result are zero v ? always cleared c ? set if bit 24 of a or b was set prior to instruction execution instruction format: lsr d opcode: instruction fields: d d a 0 b 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu nz vc 23 8 7 4 3 0 data bus move field 0010 d011 optional effective address extension lsr logical shift right lsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 148 instruction set details motorola operation: assembler syntax: ea t d lua ea,d description: load the updated address into the destination address register d. the source address register and the update mode used to compute the updated address are specified by the effective address (ea). note that the source address register speci- fied in the effective address is not updated. all update addressing modes may be used. note: this instruction is considered to be a move-type instruction. due to instruction pipelining, if an agu register (mn, nn, or rn) is directly changed with this instruction, the new contents may not be available for use until the second following instruction. see the restrictions discussed in a.9.6 - r, n, and m register restrictions on page a-310. example: : lua (r0)+n0,r1 ;update r1 using (r0)+n0 : explanation of example: prior to execution, the 16-bit address register r0 contains the value $0003, the 16-bit address register n0 contains the value $0005, and the 16-bit address register r1 contains the value $0004. the execution of the lua (r0)+n0,r1 instruction adds the contents of the r0 register to the contents of the n0 register and stores the resulting updated address in the r1 address register. normally n0 would be added to r0 and deposited in r0. however, for an lua instruction, the contents of both the r0 and n0 address registers are not affected. lua load updated address lua before execution after execution r0 r0 n0 n0 r1 r1 $0004 $0008 $0005 $0003 $0005 $0003 m0 m0 $ffff $ffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 149 condition codes: the condition codes are not affected by this instruction. instruction format: lua ea,d opcode: instruction fields: ea=5-bit effective address=mmrrr, d=4-bit destination address register=dddd effective addressing mode m m m r r r dest. addr. reg. d d d d d (rn)-nn 0 0 0 r r r r0er7 0 n n n (rn)+nn 0 0 1 r r r n0en7 1 n n n (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r where rrr refers to a source address register r0er7 where nnn refers to a destination address register r0er7 or n0en7 timing: 4 oscillator clock cycles memory: 1 program word mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c 23 16 15 8 7 0 00000100010mmrrr0001dddd lua load updated address lua f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 150 instruction set details motorola operation: assembler syntax: d s1 * s2 t d (parallel move) mac ( )s1,s2,d (parallel move) d s1 * s2 t d (parallel move) mac ( )s2,s1,d (parallel move) d (s1 * 2 -n ) t d ( no parallel move) mac ( )s,#n,d ( no parallel move) description: multiply the two signed 24-bit source operands s1 and s2 ( or the signed 24-bit source operand s by the positive 24-bit immediate operand 2 -n ) and add/subtract the product to/from the specified 56-bit destination accumulator d. the e sign option is used to negate the specified product prior to accumulation. the default sign option is +. note: when the processor is in the double precision multiply mode, the following instructions do not execute in the normal way and should only be used as part of the double precision multiply algorithm shown in section 3.4 double precision multi- ply mode: mpy y0, x0, a mpy y0, x0, b mac x1, y0, a mac x1, y0, b mac x0, y1, a mac x0, y1, b mac y1, x1, a mac y1, x1, b all other data alu instructions are executed as nop?s when the processor is in the dou- ble precision multiply mode. example 1: : mac x0,x0,a x:(r2)+n2,y1 ;square x0 and store in a, update y1 and r2 : explanation of example 1: prior to execution, the 24-bit x0 register contains the value of $123456 (0.142222166), and the 56-bit a accumulator contains the value $00:100000:000000 (0.125). the execution of the mac x0,x0,a instruction squares the 24-bit signed value in the x0 register and adds the resulting 48-bit product to the 56-bit a accumulator (x0 * x0+la=0.145227144519197 approximately= $00:1296cd:9619c8=a). mac signed multiply-accumulate mac before execution after execution x0 x0 $123456 a a $00:100000:00000 $00:1296cd:9619c8 $123456 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 151 condition codes: s ? computed according to the definition in a.5 condition code computation. l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z? set if a or b result equals zero v ? set if overflow has occurred in a or b result note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 for complete details. instruction format 1: mac ( )s1,s2,d mac ( )s2,s1,d opcode: 1 instruction fields: s1 * s2 q q q sign k d d x0 x0 0 0 0 + 0 a 0 y0 y0 0 0 1 e 1 b 1 x1 x0 0 1 0 y1 y0 0 1 1 x0 y1 1 0 0 y0 x0 1 0 1 x1 y0 1 1 0 y1 x1 1 1 1 note: only the indicated s1 * s2 combinations are valid. x1 * x1 and y1 * y1 are not valid. mac signed multiply-accumulate mac mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 8 7 4 3 0 data bus move field 1qqq dk10 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 152 instruction set details motorola timing: 2+mv oscillator clock cycles memory: 1+mv program words example 2: : mac x0, #3, a ; : explanation of example 2: the content of x0 ($654321) is multiplied by 2 -3 and then added to the content of the a accumulator ($00:100000:000000). the result is then placed in the a accumulator. the net effect of this operation is to divide the content of x0 by 2 3 and add the result to the accumulator. an alternate interpretation is that x0 is right shift ed 3 places and filled with the sign bit (0 for a positive number and 1 for a neg- ative number) and then the result is added to the accumulator. instruction format 2: mac ( )s,#n,d opcode 2: instruction fields: s q q sign k d d y1 0 0 + 0 a 0 x0 0 1 e 1 b 1 y0 1 0 x1 1 1 mac signed multiply-accumulate mac before execution after execution x0 $654321 a a $00:100000:000000 $00:1ca864:200000 $654321 x0 23 16 15 8 7 0 00000001000s ssss 11qqdk10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 153 n sssss constant 1 00001 010000000000000000000000 2 00010 001000000000000000000000 3 00011 000100000000000000000000 4 00100 000010000000000000000000 5 00101 000001000000000000000000 6 00110 000000100000000000000000 7 00111 000000010000000000000000 8 01000 000000001000000000000000 9 01001 000000000100000000000000 10 01010 000000000010000000000000 11 01011 000000000001000000000000 12 01100 000000000000100000000000 13 01101 000000000000010000000000 14 01110 000000000000001000000000 15 01111 000000000000000100000000 16 10000 000000000000000010000000 17 10001 000000000000000001000000 18 10010 000000000000000000100000 19 10011 000000000000000000010000 20 10100 000000000000000000001000 21 10101 000000000000000000000100 22 10110 000000000000000000000010 23 10111 000000000000000000000001 timing: 2 oscillator clock cycles memory: 1 program word mac signed multiply-accumulate mac f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 154 instruction set details motorola operation: assembler syntax: d s1 * s2+r t d (parallel move) macr ( )s1,s2,d (parallel move) d s1 * s2+r t d (parallel move) macr ( )s2,s1,d (parallel move) d (s1 * 2 -n )+r t d ( no parallel move) macr ( )s,#n,d ( no parallel move) description: multiply the two signed 24-bit source operands s1 and s2 ( or the signed 24-bit source operand s by the positive 24-bit immediate operand 2 -n ), add/subtract the product to/from the specified 56-bit destination accumulator d, and then round the result using convergent rounding. the rounded result is stored in the destination accumulator d. the e sign option negates the specified product prior to accumulation. the default sign option is +. the contribution of the ls bits of the result is rounded into the upper portion of the desti- nation accumulator (a1 or b1) by adding a constant to the ls bits of the lower portion of the accumulator (a0 or b0). the value of the constant added is determined by the scal- ing mode bits s0 and s1 in the status register. once rounding has been completed, the ls bits of the destination accumulator d (a0 or b0) are loaded with zeros to maintain an unbiased accumulator value which may be reused by the next instruction. the upper por- tion of the accumulator (a1 or b1) contains the rounded result which may be read out to the data buses. refer to the rnd instruction for more complete information on the con- vergent rounding process. example 1: : macr x0,y0,b b,x0 y:(r4)+n4,y0 ;x0 * y0+b t b, and b, update x0,y0,r4 : macr signed multiply-accumulate and round macr before execution after execution x0 x0 y0 y0 b b $00:100000:000000 $00:1296ce:000000 $987654 $100000 $123456 $123456 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 155 explanation of example 1: prior to execution, the 24-bit x0 register contains the value $123456 (0.142222166), the 24-bit y0 register contains the value $123456 (0.142222166), and the 56-bit b accumulator contains the value $00:100000:000000 (0.125). the execution of the macr x0,y0,b instruction multiples the 24-bit signed value in the x0 register by the 24-bit signed value in the y0 register, adds the resulting product to the 56-bit b accumulator, rounds the result into the b1 portion of the accumu- lator, and then zeros the b0 portion of the accumulator (x0 * y0+b=0.145227144519197 approximately =$00:1296cd:9619c8, which is rounded to the value $00:1296ce:000000=0.145227193832397=b). condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z? set if a or b result equals zero v ? set if overflow has occurred in a or b result note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 for complete details. instruction format 1: macr ( )s1,s2,d macr ( )s2,s1,d opcode 1: macr signed multiply-accumulate and round macr mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz v c 23 8 7 4 3 0 data bus move field 1qqq dk11 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 156 instruction set details motorola instruction fields 1: s1 * s2 q q q sign k d d x0 x0 0 0 0 + 0 a 0 y0 y0 0 0 1 e 1 b 1 x1 x0 0 1 0 y1 y0 0 1 1 x0 y1 1 0 0 y0 x0 1 0 1 x1 y0 1 1 0 y1 x1 1 1 1 note: only the indicated s1 * s2 combinations are valid. x1 * x1 and y1 * y1 are not valid. timing: 2+mv oscillator clock cycles memory: 1+mv program words example 2: : macr -y0, #10, b ; : explanation of example 2 : the content of y0 ($654321) is negated, multiplied by 2 -10 , added to the content of the b accumulator ($00:100000:000000), placed in the b accu- mulator and then rounded to a single precision number (24 bits in b1). the net effect of this operation is to negate the content of y0, divide the result by 2 10 and add the result to the accumulator. an alternate interpretation is that y0 is negated, right shift ed 10 places, filled with the sign bit (0 for a positive number and 1 for a negative number), the result is added to the accumulator and then rounded to a single precision number. macr signed multiply-accumulate and round macr before execution after execution y0 $654321 b b $00:100000:000000 $00:0fe6af:000000 $654321 y0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 157 instruction format 2: macr ( )s,#n,d opcode 2: i nstruction fields 2: s q q sign k d d y1 0 0 + 0 a 0 x0 0 1 e 1 b 1 y0 1 0 x1 1 1 n sssss constant 1 00001 010000000000000000000000 2 00010 001000000000000000000000 3 00011 000100000000000000000000 4 00100 000010000000000000000000 5 00101 000001000000000000000000 6 00110 000000100000000000000000 7 00111 000000010000000000000000 8 01000 000000001000000000000000 9 01001 000000000100000000000000 10 01010 000000000010000000000000 11 01011 000000000001000000000000 12 01100 000000000000100000000000 13 01101 000000000000010000000000 14 01110 000000000000001000000000 15 01111 000000000000000100000000 16 10000 000000000000000010000000 17 10001 000000000000000001000000 18 10010 000000000000000000100000 19 10011 000000000000000000010000 20 10100 000000000000000000001000 21 10101 000000000000000000000100 22 10110 000000000000000000000010 23 10111 000000000000000000000001 timing: 2 oscillator clock cycles memory: 1 program word 23 16 15 8 7 0 00000001000s ssss 11qqdk11 macr signed multiply-accumulate and round macr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 158 instruction set details motorola operation: assembler syntax: s t d move s,d description: move the contents of the specified data source s to the specified destina- tion d. this instruction is equivalent to a data alu nop with a parallel data move. when a 56-bit accumulator (a or b) is specified as a source operand s, the accumulator value is optionally shifted according to the scaling mode bits s0 and s1 in the system status register (sr). if the data out of the shifter indicates that the accumulator extension register is in use and the data is to be moved into a 24- or 48-bit destination, the value stored in the destination d is limited to a maximum positive or negative saturation con- stant to minimize truncation error. limiting does not occur if an individual 24-bit accumu- lator register (a1, a0, b1, or b0) is specified as a source operand instead of the full 56-bit accumulator (a or b). this limiting feature allows block floating-point operations to be performed with error detection since the l bit in the condition code register is latched. when a 56-bit accumulator (a or b) is specified as a destination operand d, any 24-bit source data to be moved into that accumulator is automatically extended to 56 bits by sign extending the ms bit of the source operand (bit 23) and appending the source oper- and with 24 ls zeros. similarly, any 48-bit source data to be loaded into a 56-bit accu- mulator is automatically sign extended to 56 bits. note that for 24-bit source operands both the automatic sign-extension and zeroing features may be disabled by specifying the destination register to be one of the individual 24-bit accumulator registers (a1 or b1). similarly, for 48-bit source operands, the automatic sign-extension feature may be disabled by using the long memory move addressing mode and specifying a10 or b10 as the destination operand. example: : move x0,a1 ;move x0 to a1 without sign ext. or zeroing : move move data move a a $ff:ffffff:ffffff $ff:234567:ffffff before execution after execution x0 x0 $234567 $234567 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 159 explanation of example: prior to execution, the 56-bit a accumulator contains the value $ff:ffffff:ffffff, and the 24-bit x0 register contains the value $234567. the execution of the move x0,a1 instruction moves the 24-bit value in the x0 register into the 24-bit a1 register without automatic sign extension and without automatic zeroing. condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move. instruction format: move s,d opcode: instruction fields: see parallel move descriptions for data bus move field encoding. timing: 2+mv oscillator clock cycles memory: 1+mv program words mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu n z v c 23 8 7 4 3 0 data bus move field 0000 0000 optional effective address extension move move data move f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 160 instruction set details motorola parallel move descriptions: thirty of the sixty-two instructions allow an optional paral- lel data bus movement over the x and/or y data bus. this allows a data alu operation to be executed in parallel with up to two data bus moves during the instruction cycle. ten types of parallel moves are permitted, including register to register moves, register to memory moves, and memory to register moves. however, not all addressing modes are allowed for each type of memory reference. addressing mode restrictions which apply to specific types of moves are noted in the individual move operation descriptions. the fol- lowing section contains detailed descriptions about each type of parallel move operation. when a 56-bit accumulator (a or b) is specified as a source operand s, the accumulator value is optionally shifted according to the scaling mode bits s0 and s1 in the system status register (sr). if the data out of the shifter indicates that the accumulator extension register is in use and the data is to be moved into a 24- or 48-bit destination, the value stored in the destination d is limited to a maximum positive or negative saturation con- stant to minimize truncation error. limiting does not occur if an individual 24-bit accumu- lator register (a1, a0, b1, or b0) is specified as a source operand instead of the full 56-bit accumulator (a or b). this limiting feature allows block floating-point operations to be performed with error detection since the l bit in the condition code register is latched. note: whenever an instruction uses an accumulator as both a destination operand for a data alu operation and as a source for a parallel move operation, the parallel move operation occurs first and will use the data that exists in the accumulator before the execution of the data alu operation has occurred. move move data move f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 161 when a 56-bit accumulator (a or b) is specified as a destination operand d, any 24-bit source data to be moved into that accumulator is automatically extended to 56 bits by sign extending the ms bit of the source operand (bit 23) and appending the source oper- and with 24 ls zeros. similarly, any 48-bit source data to be loaded into a 56-bit accu- mulator is automatically sign extended to 56 bits. note that for 24-bit source operands both the automatic sign-extension and zeroing features may be disabled by specifying the destination register to be one of the individual 24-bit accumulator registers (a1 or b1). similarly, for 48-bit source operands, the automatic sign-extension feature may be disabled by using the long memory move addressing mode and specifying a10 or b10 as the destination operand. note that the symbols used in decoding the various opcode fields of an instruction or par- allel move are completely arbitrary . furthermore, the opcode symbols used in one instruction or parallel move are completely independent of the opcode symbols used in a different instruction or parallel move. move move data move f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 162 instruction set details motorola operation: assembler syntax: (. . . . . ) (. . . . .) where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. description: many (30 of the total 66) instructions in the dsp56k instruction set allow parallel moves. the parallel moves have been divided into 10 opcode categories. this category is a parallel move nop and does not involve data bus move activity. example: : add x0,a ;add x0 to a (no parallel move) : explanation of example: this is an example of an instruction which allows parallel moves but does not have one. condition codes: the condition codes are affected by the instruction, not the move. no parallel data move mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 163 instruction format: ( . . . . . ) opcode: instruction format: (defined by instruction) timing: mv oscillator clock cycles memory: mv program words no parallel data move 23 16 15 8 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 164 instruction set details motorola operation: assembler syntax: ( . . . . . ), #xx t d ( . . . . . ) #xx,d where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. description: move the 8-bit immediate data value (#xx) into the destination operand d. if the destination register d is a0, a1, a2, b0, b1, b2, r0er7, or n0en7, the 8-bit imme- diate short operand is interpreted as an unsigned integer and is stored in the specified destination register. that is, the 8-bit data is stored in the eight ls bits of the destination operand, and the remaining bits of the destination operand d are zeroed. if the destination register d is x0, x1, y0, y1, a, or b, the 8-bit immediate short operand is interpreted as a signed fraction and is stored in the specified destination register. that is, the 8-bit data is stored in the eight ms bits of the destination operand, and the remaining bits of the destination operand d are zeroed. if the arithmetic or logical opcode-operand portion of the instruction specifies a given destination accumulator, that same accumulator or portion of that accumulator may not be specified as a destination d in the parallel data bus move operation. thus, if the opcode-operand portion of the instruction specifies the 56-bit a accumulator as its desti- nation, the parallel data bus move portion of the instruction may not specify a0, a1, a2, or a as its destination d. similarly, if the opcode-operand portion of the instruction speci- fies the 56-bit b accumulator as its destination, the parallel data bus move portion of the instruction may not specify b0, b1, b2, or b as its destination d. that is, duplicate des- tinations are not allowed within the same instruction. note: due to instruction pipelining, if an agu register (mn, nn, or rn) is directly changed with this instruction, the new contents may not be available for use until the second fol- lowing instruction. see the restrictions discussed in a.9.6 - r, n, and m register restric- tions on page a-310. i immediate short data move i f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 165 example: : abs b #$18,r1 ;take absolute value of b, #$18 t r1 : explanation of example: prior to execution, the 16-bit address register r1 contains the value $0000. the execution of the parallel move portion of the instruction, #$18,r1, moves the 8-bit immediate short operand into the eight ls bits of the r1 register and zeros the remaining eight ms bits of that register. the 8-bit value is interpreted as an unsigned integer since its destination is the r1 address register. before execution after execution r1 r1 $0000 $0018 i immediate short data move i f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 166 instruction set details motorola condition codes: the condition codes are not affected by this type of parallel move. instruction format: ( . . . . . ) #xx,d opcode: instruction fields: #xx=8-bit immediate short data=iiiiiiii mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c 23 16 15 8 7 0 0 0 1 d d d d d i i i i i i i i instruction opcode i immediate short data move i f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 167 dd d d d d d d sign ext zero x0 0 0 1 0 0 no no x1 0 0 1 0 1 no no y0 0 0 1 1 0 no no y1 0 0 1 1 1 no no a0 0 1 0 0 0 no no b0 0 1 0 0 1 no no a2 0 1 0 1 0 no no b2 0 1 0 1 1 no no a1 0 1 1 0 0 no no b1 0 1 1 0 1 no no a 01110 a2 a0 b 01111 b2 b0 r0-r7 1 0 r r r n0-n7 1 1 n n n where rrr=rn number where nnn=nn number timing: mv oscillator clock cycles memory: mv program words i immediate short data move i f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 168 instruction set details motorola operation: assembler syntax: ( . . . . . ); s t d ( . . . . . ) s,d where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. description: move the source register s to the destination register d. if the arithmetic or logical opcode-operand portion of the instruction specifies a given destination accumulator, that same accumulator or portion of that accumulator may not be specified as a destination d in the parallel data bus move operation. thus, if the opcode-operand portion of the instruction specifies the 56-bit a accumulator as its desti- nation, the parallel data bus move portion of the instruction may not specify a0, a1, a2, or a as its destination d. similarly, if the opcode-operand portion of the instruction speci- fies the 56-bit b accumulator as its destination, the parallel data bus move portion of the instruction may not specify b0, b1, b2, or b as its destination d. that is, duplicate des- tinations are not allowed within the same instruction . if the opcode-operand portion of the instruction specifies a given source or destination register, that same register or portion of that register may be used as a source s in the parallel data bus move operation. this allows data to be moved in the same instruction in which it is being used as a source operand by a data alu operation. that is, duplicate sources are allowed within the same instruction . when a 24-bit source operand is moved into a 16-bit destination register, the 16 ls bits of the 24-bit source operand are stored in the 16-bit destination register. when a 16-bit source operand is moved into a 24-bit destination register, the 16 ls bits of the destina- tion register are loaded with the contents of the 16-bit source operand, and the eight ms bits of the 24-bit destination register are zeroed. note: the move a,b operation will result in a 24-bit positive or negative saturation con- stant being stored in the b1 portion of the b accumulator if the signed integer portion of the a accumulator is in use. note: due to instruction pipelining, if an agu register (mn, nn, or rn) is directly changed with this instruction, the new contents may not be available for use until the second fol- lowing instruction. see the restrictions discussed in a.9.6 - r, n, and m register restric- tions on page a-310. r register to register data move r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 169 example: : macrex0,y0,a y1,n5 ;ex0 * y0+a t a, move y1 t n5 : explanation of example: prior to execution, the 24-bit y1 register contains the value $001234 and the 16-bit address offset register n5 contains the value $0000. the execu- tion of the parallel move portion of the instruction, y1,n5, moves the 16 ls bits of the 24- bit value in the y1 register into the 16-bit n5 register. n5 n5 $0000 $1234 before execution after execution y1 y1 $001234 $001234 r register to register data move r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 170 instruction set details motorola condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move instruction format: ( . . . . . ) s,d opcode: r register to register data move r mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l eu n z v c 23 16 15 8 7 0 0 0 1 0 0 0 e e e e e d d d d d instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 171 instruction fields: eeeee s d d s or d d d d d d s/l sign ext zero x0 0 0 1 0 0 no no no x1 0 0 1 0 1 no no no y0 0 0 1 1 0 no no no y1 0 0 1 1 1 no no no a0 0 1 0 0 0 no no no b0 0 1 0 0 1 no no no a2 0 1 0 1 0 no no no b2 0 1 0 1 1 no no no a1 0 1 1 0 0 no no no b1 0 1 1 0 1 no no no a 0 1 1 1 0 yes a2 a0 b 0 1 1 1 1 yes b2 b0 r0-r7 1 0 r r r n0-n7 1 1 n n n where rrr=rn number where nnn=nn number timing: mv oscillator clock cycles memory: mv program words r register to register data move r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 172 instruction set details motorola operation: assembler syntax: ( . . . . . ); ea t rn ( . . . . . ) ea where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. description: update the specified address register according to the specified effective addressing mode. all update addressing modes may be used. example: : rnd b (r3)+n3 ;round value in b into b1, r3+n3 t r3 : explanation of example: prior to execution, the 16-bit address register r3 contains the value $0007, and the 16-bit address offset register n3 contains the value $0004. the execution of the parallel move portion of the instruction, (r3)+n3, updates the r3 address register according to the specified effective addressing mode by adding the value in the r3 register to the value in the n3 register and storing the 16-bit result back in the r3 address register. condition codes: the condition codes are not affected by this type of parallel move. u address register update u n3 n3 $0004 $0004 before execution after execution r3 r3 $0007 $000b mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 173 instruction format: ( . . . . . ) ea opcode: instruction fields: ea=5-bit effective address=mmrrr effective addressing mode m m r r r (rn)-nn 0 0 r r r (rn)+nn 0 1 r r r (rn)- 1 0 r r r (rn)+ 1 1 r r r where rrr refers to an address register r0-r7 timing: mv oscillator clock cycles memory: mv program words 23 16 15 8 7 0 0 0 1 0 0 0 0 0 0 1 0 m m r r r instruction opcode u address register update u f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 174 instruction set details motorola operation: assembler syntax: ( . . . . . ); x:ea t d ( . . . . . ) x:ea,d ( . . . . . ); x:aa t d ( . . . . . ) x:aa,d ( . . . . . ); s t x:ea ( . . . . . ) s,x:ea ( . . . . . ); s t x:aa ( . . . . . ) s,x:aa ( . . . . . ); #xxxxxx t d ( . . . . . ) #xxxxxx,d where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. description: move the specified word operand from/to x memory. all memory address- ing modes, including absolute addressing and 24-bit immediate data, may be used. absolute short addressing may also be used. if the arithmetic or logical opcode-operand portion of the instruction specifies a given destination accumulator, that same accumulator or portion of that accumulator may not be specified as a destination d in the parallel data bus move operation. thus, if the opcode-operand portion of the instruction specifies the 56-bit a accumulator as its desti- nation, the parallel data bus move portion of the instruction may not specify a0, a1, a2, or a as its destination d. similarly, if the opcode-operand portion of the instruction speci- fies the 56-bit b accumulator as its destination, the parallel data bus move portion of the instruction may not specify b0, b1, b2, or b as its destination d. that is, duplicate des- tinations are not allowed within the same instruction . if the opcode-operand portion of the instruction specifies a given source or destination register, that same register or portion of that register may be used as a source s in the parallel data bus move operation. this allows data to be moved in the same instruction in which it is being used as a source operand by a data alu operation. that is, duplicate sources are allowed within the same instruction . when a 24-bit source operand is moved into a 16-bit destination register, the 16 ls bits of the 24-bit source operand are stored in the 16-bit destination register. when a 16-bit source operand is moved into a 24-bit destination register, the 16 ls bits of the destina- tion register are loaded with the contents of the 16-bit source operand, and the eight ms bits of the 24-bit destination register are zeroed. x: x memory data move x: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 175 note :due to instruction pipelining, if an agu register (mn, nn, or rn) is directly changed with this instruction, the new contents may not be available for use until the second fol- lowing instruction. see the restrictions discussed in a.9.6 - r, n, and m register restric- tions on page a-page 310. example: : asl a r2,x:e(r2) ;a * 2 t a, save updated r2 in x:(r2) : explanation of example: prior to execution, the 16-bit r2 address register contains the value $1001, and the 24-bit x memory location x:$1000 contains the value $000000. the execution of the parallel move portion of the instruction, r2,x:e(r2), predecrements the r2 address register and then uses the r2 address register to move the updated con- tents of the r2 address register into the 24-bit x memory location x:$1000. condition codes: s ? computed according to the definition in a.5 condition code computation. l ? set if data limiting has occurred during parallel move. note: the move a,x:ea operation will result in a 24-bit positive or negative saturation constant being stored in the specified 24-bit x memory location if the signed integer por- tion of the a accumulator is in use. x:$1000 x:$1000 $000000 $001000 before execution after execution r2 r2 $1001 $1000 x: x memory data move x: mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 176 instruction set details motorola instruction format: ( . . . . . ) x:ea,d ( . . . . . ) s,x:ea ( . . . . . ) #xxxxxx,d opcode: instruction fields: ea=6-bit effective address=mmmrrr effective register w addressing mode m m m r r r read s 0 (rn)-nn 0 0 0 r r r write d 1 (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 immediate data 1 1 0 1 0 0 23 16 15 8 7 0 optional effective address extension 0 1 d d 0 d d d w 1 m m m r r r instruction opcode x: x memory data move x: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 177 sd d s,d d d d d d s/l sign ext zero x0 0 0 1 0 0 no no no x1 0 0 1 0 1 no no no y0 0 0 1 1 0 no no no y1 0 0 1 1 1 no no no a0 0 1 0 0 0 no no no b0 0 1 0 0 1 no no no a2 0 1 0 1 0 no no no b2 0 1 0 1 1 no no no a1 0 1 1 0 0 no no no b1 0 1 1 0 1 no no no a 0 1 1 1 0 yes a2 a0 b 0 1 1 1 1 yes b2 b0 r0-r7 1 0 r r r n0-n7 1 1 n n n where rrr=rn number where nnn=nn number timing: mv oscillator clock cycles memory: mv program words x: x memory data move x: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 178 instruction set details motorola instruction format: ( . . . . . ) x:aa,d ( . . . . . ) s,x:aa opcode: instruction fields: aa=6-bit absolute short address=aaaaaa register w absolute short address a a a a a a read s 0 0 0 0 0 0 0 write d 1 1 1 1 1 1 1 23 16 15 8 7 0 0 1 d d 0 d d d w 0 a a a a a a instruction opcode x: x memory data move x: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 179 sd d s,d d d d d d s/l sign ext zero x0 0 0 1 0 0 no no no x1 0 0 1 0 1 no no no y0 0 0 1 1 0 no no no y1 0 0 1 1 1 no no no a0 0 1 0 0 0 no no no b0 0 1 0 0 1 no no no a2 0 1 0 1 0 no no no b2 0 1 0 1 1 no no no a1 0 1 1 0 0 no no no b1 0 1 1 0 1 no no no a 0 1 1 1 0 yes a2 a0 b 0 1 1 1 1 yes b2 b0 r0-r7 1 0 r r r n0-n7 1 1 n n n where rrr=rn number where nnn=nn number timing: mv oscillator clock cycles memory: mv program words x: x memory data move x: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 180 instruction set details motorola operation: assembler syntax: class i class i ( . . . . . ); x:ea t d1; s2 t d2 ( . . . . . ) x:ea,d1 s2,d2 ( . . . . . ); s1 t x:ea; s2 t d2 ( . . . . . ) s1,x:ea s2,d2 ( . . . . . ); #xxxxxx t d1; s2 t d2 ( . . . . . ) #xxxxxx,d1 s2,d2 class ii class ii ( . . . . . ); a t x:ea; x0 t a ( . . . . . ) a,x:ea x0,a ( . . . . . ); b t x:ea; x0 t b ( . . . . . ) b,x:ea x0,b where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. description: class i: move a one-word operand from/to x memory and move another word operand from an accumulator (s2) to an input register (d2). all memory addressing modes, including absolute addressing and 24-bit immediate data, may be used. the reg- ister to register move (s2,d2) allows a data alu accumulator to be moved to a data alu input register for use as a data alu operand in the following instruction. class ii: move one-word operand from a data alu accumulator to x memory and one- word operand from data alu register x0 to a data alu accumulator. one effective address is specified. all memory addressing modes, excluding long absolute addressing and long immediate data, may be used. for both class i and class ii x:r parallel data moves, if the arithmetic or logical opcode- operand portion of the instruction specifies a given destination accumulator, that same accumulator or portion of that accumulator may not be specified as a destination d1 in the parallel data bus move operation. thus, if the opcode-operand portion of the instruc- tion specifies the 56-bit a accumulator as its destination, the parallel data bus move por- tion of the instruction may not specify a0, a1, a2, or a as its destination d1. similarly, if the opcode-operand portion of the instruction specifies the 56-bit b accumulator as its destination, the parallel data bus move portion of the instruction may not specify b0, b1, b2, or b as its destination d1. that is, duplicate destinations are not allowed within the same instruction . x:r x memory and register data move x:r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 181 if the opcode-operand portion of the instruction specifies a given source or destination register, that same register or portion of that register may be used as a source s1 and/or s2 in the parallel data bus move operation. this allows data to be moved in the same instruction in which it is being used as a source operand by a data alu operation. that is, duplicate sources are allowed within the same instruction . note that s1 and s2 may specify the same register. class i example: : cmpm y0,a a,x:$1234 a,y0 ;compare a,y0 mag., save a, update y0 : explanation of the class i example: prior to execution, the 56-bit a accumulator con- tains the value $00:800000:000000, the 24-bit x memory location x:$1234 contains the value $000000, and the 24-bit y0 register contains the value $000000. the execution of the parallel move portion of the instruction, a,x:$1234 a,y0, moves the 24-bit limited positive saturation constant $7fffff into both the x:$1234 memory location and the y0 register since the signed portion of the a accumulator was in use. before execution after execution y0 y0 $000000 $7fffff a a $00:800000:000000 $00:800000:000000 x:$1234 x:$1234 $000000 $7fffff x:r x memory and register data move x:r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 182 instruction set details motorola class ii example: : mac x0,y0,a b,x:(r1)+ x0,b ;multiply x0 and y0 and accumulate in a : ;move b to x memory location pointed to ;by r1 and postincrement r1 ;move x0 to b explanation of the class ii example: prior to execution, the 24-bit registers x0 and y0 contain $400000 and $600000, respectively. the 56-bit accumulators a and b contain the values $00:000000:000000 and $ff:7fffff:000000, respectively. the 24-bit x memory location x:$1234 contains the value $000000, and the 16-bit r1 register con- tains the value $1234. execution of the parallel move portion of the instruction (b,x:(r1)+x0,b) moves the 24-bit limited value of b ($800000) into the x:$1234 memory location and the x0 register ($400000) into accumulator b1 ($400000), sign extends b1 into b2 ($00), and zero fills b0 ($000000). it also increments r1 to $1235. before execution after execution x0 x0 $400000 $400000 y0 y0 $600000 $600000 a a $00:000000:000000 $00:300000:000000 b b $ff:7fffff:000000 $00:400000:000000 x:$1234 x:$1234 $000000 $800000 r1 r1 $1234 $1235 x:r x memory and register data move x:r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 183 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move. class i instruction format: ( . . . . . ) x:ea,d1 s2,d2 ( . . . . . ) s1,x:ea s2, d2 ( . . . . . ) #xxxxxx, s2,d2 opcode: instruction fields: ea=6-bit effective address=mmmrrr effective register w addressing mode m m m r r r read s 0 (rn)-nn 0 0 0 r r r write d 1 (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 immediate data 1 1 0 1 0 0 where rrr refers to an address register r0er7 mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c 23 16 15 8 7 0 optional effective address extension 0 0 0 1 f f d f w 0 m m m r r r instruction opcode x:r x memory and register data move x:r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 184 instruction set details motorola s1 d1 d1 s2 d2 d2 s1,d1 f f s/l sign ext zero s2 d s/l d2 f sign ext zero x0 0 0 no no no a 0 yes y0 0 no no x1 0 1 no no no b 1 yes y1 1 no no a 1 0 yes a2 a0 b 1 1 yes b2 b0 timing: mv oscillator clock cycles memory: mv program words x:r x memory and register data move x:r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 185 class ii instruction format: ( . . . . . ) a t x:ea x0 t a ( . . . . . ) b t x:ea x0 t b opcode: instruction fields: ea=6-bit effective address=mmmrrr effective addressing mode m m m r r r (rn)-nn 0 0 0 r r r (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r where rrr refers to an address register r0er7 sd d s d s/l sign ext zero d move opcode x0 no n/a n/a 0 a t x:ea x0 t a y0 no n/a n/a 1 b t x:ea x0 t b a yes a2 a0 b yes b2 b0 timing: mv oscillator clock cycles memory: mv program words 23 16 15 8 7 0 optional effective address extension 0 0 0 0 1 0 0 d 0 0 m m m r r r instruction opcode x:r x memory and register data move x:r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 186 instruction set details motorola operation: assembler syntax: ( . . . . . ); y:ea t d ( . . . . . ) y:ea,d ( . . . . . ); y:aa t d ( . . . . . ) y:aa,d ( . . . . . ); s t y:ea ( . . . . . ) s,y:ea ( . . . . . ); s t y:aa ( . . . . . ) s,y:aa ( . . . . . ); #xxxxxx t d ( . . . . . ) #xxxxxx,d where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. description: move the specified word operand from/to y memory. all memory address- ing modes, including absolute addressing and 24-bit immediate data, may be used. absolute short addressing may also be used. if the arithmetic or logical opcode-operand portion of the instruction specifies a given destination accumulator, that same accumulator or portion of that accumulator may not be specified as a destination d in the parallel data bus move operation. thus, if the opcode-operand portion of the instruction specifies the 56-bit a accumulator as its desti- nation, the parallel data bus move portion of the instruction may not specify a0, a1, a2, or a as its destination d. similarly, if the opcode-operand portion of the instruction speci- fies the 56-bit b accumulator as its destination, the parallel data bus move portion of the instruction may not specify b0, b1, b2, or b as its destination d. that is, duplicate des- tinations are not allowed within the same instruction . if the opcode-operand portion of the instruction specifies a given source or destination register, that same register or portion of that register may be used as a source s in the parallel data bus move operation. this allows data to be moved in the same instruction in which it is being used as a source operand by a data alu operation. that is, duplicate sources are allowed within the same instruction . when a 24-bit source operand is moved into a 16-bit destination register, the 16 ls bits of the 12-bit source operand are stored in the 16-bit destination register. when a 16-bit source operand is moved into a 24-bit destination register, the 16 ls bits of the destina- tion register are loaded with the contents of the 16-bit source operand, and the eight ms bits of the 24-bit destination register are zeroed. y: y memory data move y: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 187 note: this parallel data move is considered to be a move-type instruction. due to instruction pipelining, if an agu register (mn, nn, or rn) is directly changed with this instruction, the new contents may not be available for use until the second following instruction. see the restrictions discussed in a.9.6 - r, n, and m register restrictions on page a-page 310. example: : eor x0,b #$123456,a ;exclusive or x0 and b, update a accumulator : explanation of example: prior to execution, the 56-bit a accumulator contains the value $ff:ffffff:ffffff. the execution of the parallel move portion of the instruc- tion, #$123456,a, moves the 24-bit immediate value $123456 into the 24-bit a1 register, then sign extends that value into the a2 portion of the accumulator, and zeros the lower 24-bit a0 portion of the accumulator. condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move. y: y memory data move y: before execution after execution a $ff:ffffff:ffffff a $00:123456:000000 mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 188 instruction set details motorola note: the move a,y:ea operation will result in a 24-bit positive or negative saturation constant being stored in the specified 24-bit y memory location if the signed integer por- tion of the a accumulator is in use. instruction format: ( . . . . . ) y:ea,d ( . . . . . ) s,y:ea ( . . . . . ) #xxxxxx,d opcode: instruction fields: ea=6-bit effective address=mmmrrr effective register w addressing mode m m m r r r read s 0 (rn)-nn 0 0 0 r r r write d 1 (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 immediate data 1 1 0 1 0 0 where rrr refers to an address register r0er7 y: y memory data move y: 23 16 15 8 7 0 optional effective address extension 0 1 d d 1 d d d w 1 m m m r r r instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 189 sd d s,d d d d d d s/l sign ext zero x0 0 0 1 0 0 no no no x1 0 0 1 0 1 no no no y0 0 0 1 1 0 no no no y1 0 0 1 1 1 no no no a0 0 1 0 0 0 no no no b0 0 1 0 0 1 no no no a2 0 1 0 1 0 no no no b2 0 1 0 1 1 no no no a1 0 1 1 0 0 no no no b1 0 1 1 0 1 no no no a 0 1 1 1 0 yes a2 a0 b 0 1 1 1 1 yes b2 b0 r0-r7 1 0 r r r n0-n7 1 1 n n n where rrr=rn number where nnn=nn number timing: mv oscillator clock cycles memory: mv program words y: y memory data move y: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 190 instruction set details motorola instruction format: ( . . . . . ) y:aa,d ( . . . . . ) s,y:aa opcode: instruction fields: aa=6-bit absolute short address=aaaaaa register w absolute short address aaaaaa read s 0 000000 write d 1 111111 y: y memory data move y: 23 16 15 8 7 0 0 1 d d 1 d d d w 0 a a a a a a instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 191 sd d s,d d d d d d s/l sign ext zero x0 0 0 1 0 0 no no no x1 0 0 1 0 1 no no no y0 0 0 1 1 0 no no no y1 0 0 1 1 1 no no no a0 0 1 0 0 0 no no no b0 0 1 0 0 1 no no no a2 0 1 0 1 0 no no no b2 0 1 0 1 1 no no no a1 0 1 1 0 0 no no no b1 0 1 1 0 1 no no no a 0 1 1 1 0 yes a2 a0 b 0 1 1 1 1 yes b2 b0 r0-r7 1 0 r r r n0-n7 1 1 n n n where rrr=rn number where nnn=nn number timing: mv oscillator clock cycles memory: mv program words y: y memory data move y: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 192 instruction set details motorola operation: assembler syntax: class i class i ( . . . . . ); s1 t d1; y:ea t d2 ( . . . . . ) s1,d1 y:ea,d2 ( . . . . . ); s1 t d1; s2 t y:ea ( . . . . . ) s1,d1 s2,y:ea ( . . . . . ); s1 t d1; #xxxxxx t d2 ( . . . . . ) s1,d1 #xxxxxx,d2 class ii class ii ( . . . . . ); y0 t a; a t y:ea ( . . . . . ) y0,a a,y:ea ( . . . . . ); y0 t b; b t y:ea ( . . . . . ) y0,b b,y:ea where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. description: class i: move a one-word operand from an accumulator (s1) to an input register (d1) and move another word operand from/to y memory. all memory addressing modes, including absolute addressing and 24-bit immediate data, may be used. the reg- ister to register move (s1,d1) allows a data alu accumulator to be moved to a data alu input register for use as a data alu operand in the following instruction. class ii: move one-word operand from a data alu accumulator to y memory and one- word operand from data alu register y0 to a data alu accumulator. one effective address is specified. all memory addressing modes, excluding long absolute addressing and long immediate data, may be used. class ii move operations have been added to the r:y parallel move (and a similar feature has been added to the x:r parallel move) as an added feature available in the first quarter of 1989. for both class i and class ii r:y parallel data moves, if the arithmetic or logical opcode- operand portion of the instruction specifies a given destination accumulator, that same accumulator or portion of that accumulator may not be specified as a destination d2 in the parallel data bus move operation. thus, if the opcode-operand portion of the instruc- tion specifies the 56-bit a accumulator as its destination, the parallel data bus move por- tion of the instruction may not specify a0, a1, a2, or a as its destination d2. similarly, if the opcode-operand portion of the instruction specifies the 56-bit b accumulator as its destination, the parallel data bus move portion of the instruction may not specify b0, b1, b2, or b as its destination d2. that is, duplicate destinations are not allowed within the same instruction. r:y register and y memory data move r:y f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 193 if the opcode-operand portion of the instruction specifies a given source or destination register, that same register or portion of that register may be used as a source s1 and/or s2 in the parallel data bus move operation. this allows data to be moved in the same instruction in which it is being used as a source operand by a data alu operation. that is, duplicate sources are allowed within the same instruction . note that s1 and s2 may specify the same register. class i example: : addl b,a b,x1 y:(r6)en6,b ;2 * a+b t a, update x1,b and r6 : explanation of the class i example : prior to execution, the 56-bit b accumulator con- tains the value $80:123456:789abc, the 24-bit x1 register contains the value $000000, the 16-bit r6 address register contains the value $2020, the 16-bit n6 address offset register contains the value $0020 and the 24-bit y memory location y:$2020 contains the value $654321. the execution of the parallel move portion of the instruction, b,x1 y:(r6)en6,b, moves the 24-bit limited negative saturation constant $800000 into the x1 register since the signed integer portion of the b accumulator was in use, uses the value in the 16-bit r6 address register to move the 24-bit value in the y memory location y:$2020 into the 56-bit b accumulator with automatic sign extension of the upper portion of the accumulator (b2) and automatic zeroing of the lower portion of the accumulator (b0), and finally uses the contents of the 16-bit n6 address offset register to update the value in the 16-bit r6 address register. the contents of the n6 address offset register are not affected. r:y register and y memory data move r:y before execution after execution b b $80:123456:789abc $00:654321:000000 x1 x1 $000000 $800000 r6 r6 $2020 $2000 n6 n6 $0020 $0020 y:$2020 y:$2020 $654321 $654321 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 194 instruction set details motorola class ii example: : mac x0,y0,a y0,b b,y:(r1)+ ;multiply x0 and y0 and accumulate in a : ;move b to y memory location pointed to ;by r1 and postincrement r1 ;move y0 to b explanation of the class ii example : prior to execution, the 24-bit registers, x0 and y0, contain $400000 and $600000, respectively. the 56-bit accumulators a and b con- tain the values $00:000000:000000 and $00:800000:000000 (+1.0000), respectively. the 24-bit y memory location y:$1234 contains the value $000000, and the 16-bit r1 register contains the value $1234. execution of the parallel move portion of the instruc- tion (y0,b b,y:(r1)+) moves the y0 register ($600000) into accumulator b1 ($600000), sign extends b1 into b2 ($00), and zero fills b0 ($000000). it also moves the 24-bit lim- ited value of b ($7fffff) into the y:$1234 memory location and increments r1 to $1235. r:y register and y memory data move r:y before execution after execution x0 x0 $400000 $400000 y0 y0 $600000 $600000 a a $00:000000:000000 $00:300000:000000 b b $00:800000:000000 $00:600000:000000 y:$1234 y:$1234 $000000 $7fffff r1 r1 $1234 $1235 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 195 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move. class i instruction format: ( . . . . . ) s1,d1 y:ea,d2 ( . . . . . ) s1,d1 s2,y:ea ( . . . . . ) s1,d1 #xxxxxx,d2 opcode: mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c r:y register and y memory data move r:y 23 16 15 8 7 0 optional effective address extension 0 0 0 1 d e f f w 1 m m m r r r instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 196 instruction set details motorola instruction fields: ea=6-bit effective address=mmmrrr effective register w addressing mode m m m r r r read s2 0 (rn)-nn 0 0 0 r r r write d2 1 (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 immediate data 1 1 0 1 0 0 where rrr refers to an address register r0er7 s1 d1 d1 s2 d2 d2 s1 d s/l d1 e sign ext zero s2,d2 f f s/l sign ext zero a 0 yes x0 0 no no y0 0 0 no no no b 1 yes x1 1 no no y1 0 1 no no no a 1 0 yes a2 a0 b 1 1 yes b2 b0 timing: mv oscillator clock cycles memory: mv program words r:y register and y memory data move r:y f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 197 class ii instruction format: ( . . . . . ) y0 t a a t y:ea ( . . . . . ) y0 t b b t y:ea opcode: instruction fields: ea=6-bit effective address=mmmrrr effective addressing mode m m m r r r (rn)-nn 0 0 0 r r r (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r where rrr refers to an address register r0er7 src dest dest s, d s/l sign ext zero d move opcode x0 no n/a n/a 0 y0 t aa t y:ea y0 no n/a n/a 1 y0 t bb t y:ea a yes a2 a0 b yes b2 b0 timing: mv oscillator clock cycles memory: mv program words r:y register and y memory data move r:y 23 16 15 8 7 0 optional effective address extension 0000100d10mmmrrr instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 198 instruction set details motorola operation: assembler syntax: ( . . . . . ); x:ea t d1; y:ea t d2 ( . . . . . ) l:ea,d ( . . . . . ); x:aa t d1; y:aa t d2 ( . . . . . ) l:aa,d ( . . . . . ); s1 t x:ea; s2 t y:ea ( . . . . . ) s,l:ea ( . . . . . ); s1 t x:aa; s2 t y:aa ( . . . . . ) s,l:aa where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. description: move one 48-bit long-word operand from/to x and y memory. two data alu registers are concatenated to form the 48-bit long-word operand. this allows effi- cient moving of both double-precision (high:low) and complex (real:imaginary) data from/ to one effective address in l (x:y) memory. the same effective address is used for both the x and y memory spaces; thus, only one effective address is required. note that the a, b, a10, and b10 operands reference a single 48-bit signed (double-precision) quantity while the x, y, ab, and ba operands reference two separate (i.e., real and imaginary) 24-bit signed quantities. all memory alterable addressing modes may be used. absolute short addressing may also be used. if the arithmetic or logical opcode-operand portion of the instruction specifies a given destination accumulator, that same accumulator or portion of that accumulator may not be specified as a destination d in the parallel data bus move operation. thus, if the opcode-operand portion of the instruction specifies the 56-bit a accumulator as its desti- nation, the parallel data bus move portion of the instruction may not specify a, a10, ab, or ba as destination d. similarly, if the opcode-operand portion of the instruction speci- fies the 56-bit b accumulator as its destination, the parallel data bus move portion of the instruction may not specify b, b10, ab, or ba as its destination d. that is, duplicate des- tinations are not allowed within the same instruction. if the opcode-operand portion of the instruction specifies a given source or destination register, that same register or portion of that register may be used as a source s in the parallel data bus move operation. this allows data to be moved in the same instruction in which it is being used as a source operand by a data alu operation. that is, duplicate sources are allowed within the same instruction. note: the operands a10, b10, x, y, ab, and ba may be used only for a 48-bit long memory move as previously described. these operands may not be used in any other type of instruction or parallel move. l: long memory data move l: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 199 example: : cmp y0,b a,l:$1234 ;compare y0 and b, save 48-bit a1:a0 value : explanation of example: prior to execution, the 56-bit a accumulator contains the value $01:234567:89abcd, the 24-bit x memory location x:$1234 contains the value $000000, and the 24-bit y memory location y:$1234 contains the value $000000. the execution of the parallel move portion of the instruction, a,l:$1234, moves the 48-bit lim- ited positive saturation constant $7fffff:ffffff into the specified long memory loca- tion by moving the ms 24 bits of the 48-bit limited positive saturation constant ($7fffff) into the 24-bit x memory location x:$1234 and by moving the ls 24 bits of the 48-bit lim- ited positive saturation constant ($ffffff) into the 24-bit y memory location y:$1234 since the signed integer portion of the a accumulator was in use. condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move. note: the move a,l:ea operation will result in a 48-bit positive or negative saturation constant being stored in the specified 24-bit x and y memory locations if the signed inte- ger portion of the a accumulator is in use. the move ab,l:ea operation will result in either one or two 24-bit positive and/or negative saturation constant(s) being stored in the specified 24-bit x and/or y memory location(s) if the signed integer portion of the a and/ or b accumulator(s) is in use. l: long memory data move l: before execution after execution a $01:234567:89abcd x:$1234 x:$1234 $000000 $7fffff $01:234567:89abcd a y:$1234 $:000000 $ffffff y:$1234 mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 200 instruction set details motorola instruction format: ( . . . . . ) l:ea,d ( . . . . . ) s,l:ea opcode: instruction fields: ea=6-bit effective address=mmmrrr effective register w addressing mode m m m r r r read s 0 (rn)-nn 0 0 0 r r r write d 1 (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 0 r r r absolute address 1 1 0 0 0 0 where rrr refers to an address register r0er7 sdd s s1 s2 s/l d d1 d2 sign ext zero l l l a10 a1 a0 no a10 a1 a0 no no 0 0 0 b10 b1 b0 no b10 b1 b0 no no 0 0 1 x x1 x0 no x x1 x0 no no 0 1 0 y y1 y0 no y y1 y0 no no 0 1 1 aa1a0yes aa1a0 a2 no 100 bb1b0yes bb1b0 b2 no 101 ab a b yes ab a b a2,b2 a0,b0 1 1 0 ba b a yes ba b a b2,a2 b0,a0 1 1 1 timing: mv oscillator clock cycles memory: mv program words l: long memory data move l: 23 16 15 8 7 0 optional effective address extension 0 1 0 0 l 0 l l w 1 m m m r r r instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 201 instruction format: ( . . . . . ) l:aa,d ( . . . . . ) s,l:aa opcode: instruction fields: aa=6-bit absolute short address=aaaaaa register w absolute short address aaaaaa read s 0 000000 write d 1 111111 sdd s s1 s2 s/l d d1 d2 sign ext zero l l l a10 a1 a0 no a10 a1 a0 no no 0 0 0 b10 b1 b0 no b10 b1 b0 no no 0 0 1 x x1 x0 no x x1 x0 no no 0 1 0 y y1 y0 no y y1 y0 no no 0 1 1 aa1a0yes aa1a0 a2 no 100 bb1b0yes bb1b0 b2 no 101 ab a b yes ab a b a2,b2 a0,b0 1 1 0 ba b a yes ba b a b2,a2 b0,a0 1 1 1 timing: mv oscillator clock cycles memory: mv program words l: long memory data move l: 23 16 15 8 7 0 0 1 0 0 l 0 l l w 0 a a a a a a instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 202 instruction set details motorola operation: assembler syntax: ( . . . . . ); x: t d1; y: t d2 ( . . . . . ) x:,d1 y:,d2 ( . . . . . ); x: t d1; s2 t y: ( . . . . . ) x:,d1 s2,y: ( . . . . . ); s1 t x:; y: t d2 ( . . . . . ) s1,x: y:,d2 ( . . . . . ); s1 t x:; s2 t y: ( . . . . . ) s1,x: s2,y: where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. description: move a one-word operand from/to x memory and move another word operand from/to y memory. note that two independent effective addresses are specified ( and ) where one of the effective addresses uses the lower bank of address registers (r0er3) while the other effective address uses the upper bank of address reg- isters (r4er7). all parallel addressing modes may be used. if the arithmetic or logical opcode-operand portion of the instruction specifies a given destination accumulator, that same accumulator or portion of that accumulator may not be specified as a destination d1 or d2 in the parallel data bus move operation. thus, if the opcode-operand portion of the instruction specifies the 56-bit a accumulator as its destination, the parallel data bus move portion of the instruction may not specify a as its destination d1 or d2. similarly, if the opcode-operand portion of the instruction specifies the 56-bit b accumulator as its destination, the parallel data bus move portion of the instruction may not specify b as its destination d1 or d2. that is, duplicate destina- tions are not allowed within the same instruction . d1 and d2 may not specify the same register. if the opcode-operand portion of the instruction specifies a given source or destination register, that same register or portion of that register may be used as a source s1 and/or s2 in the parallel data bus move operation. this allows data to be moved in the same instruction in which it is being used as a source operand by a data alu operation. that is, duplicate sources are allowed within the same instruction . note that s1 and s2 may specify the same register. x: y: xy memory data move x: y: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 203 example: : mpyr x1,y0,a x1,x:(r0)+ y0,y:(r4)+n4 ;x1 * y0 t a,save x1 and y0 : explanation of example: prior to execution, the 24-bit x1 register contains the value $123123, the 24-bit y0 register contains the value $456456, the 16-bit r0 address regis- ter contains the value $1000, the 16-bit r4 address register contains the value $0100, the 16-bit n4 address offset register contains the value $0023, the 24-bit x memory loca- tion x:$1000 contains the value $000000, and the 24-bit y memory location y:$0100 contains the value $000000. the execution of the parallel move portion of the instruction, x1,x:(r0)+ y0,y:(r4)+n4, moves the 24-bit value in the x1 register into the 24-bit x memory location x:$1000 using the 16-bit r0 address register, moves the 24-bit value in the y0 register into the 24-bit y memory location y:$0100 using the 16-bit r4 address register, updates the 16-bit value in the r0 address register, and updates the 16-bit r4 address register using the 16-bit n4 address offset register. the contents of the n4 address offset register are not affected. condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move. x: y: xy memory data move x: y: before execution after execution x1 x1 $123123 $123123 y0 y0 $456456 $456456 r0 r0 $1000 $1001 r4 r4 $0100 $0123 x:$1000 x:$1000 $000000 $123123 n4 n4 $0023 $0023 y:$0100 y:$0100 $000000 $456456 mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 204 instruction set details motorola note: the move a,x: b,y: operation will result in one or two 24-bit positive and/or negative saturation constant(s) being stored in the specified 24-bit x and/or y memory location(s) if the signed integer portion of the a and/or b accumulator(s) is in use. instruction format: ( . . . . . ) x:,d1 y:,d2 ( . . . . . ) x:,d1 s2,y: ( . . . . . ) s1,x: y:,d2 ( . . . . . ) s1,x: s2,y: opcode: instruction fields: x:=6-bit x effective address=wmmrrr (r0er3 or r4er7) y:=5-bit y effective address=wmmrr (r4er7 or r0er3) x effective addressing mode m m r r r (rn)+nn 0 1 s s s (rn)- 1 0 s s s (rn)+ 1 1 s s s (rn) 0 0 s s s where sss refers to an address register r0er7 x: y: xy memory data move x: y: 23 16 15 8 7 0 1 w m m e e f f w r r m m r r r instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 205 s1 d1 d1 y effective register w s1, d1 e e s/l sign ext zero addressing mode m m r r read s1 0 x0 0 0 no no no (rn) +nn 0 1 t t write d1 1 x1 0 1 no no no (rn) - 1 0 t t a 1 0 yes a2 a0 (rn) + 1 1 t t b 1 1 yes b2 b0 (rn) 0 0 t t where tt refers to an address register r4 - r7 or r0 - r3 which is in the opposite address register bank from the one used in the x effective address, previously described s2 d2 d2 register w s2, d2 f f s/l sign ext zero read s2 0 y0 0 0 no no no write d2 1 y1 0 1 no no no a 1 0 yes a2 a0 b 1 1 yes b2 b0 timing: mv oscillator clock cycles memory: mv program words x: y: xy memory data move x: y: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 206 instruction set details motorola operation: assembler syntax: x:ea t d1 move(c) x:ea,d1 x:aa t d1 move(c) x:aa,d1 s1 t x:ea move(c) s1,x:ea s1 t x:aa move(c) s1,x:aa y:ea t d1 move(c) y:ea,d1 y:aa t d1 move(c) y:aa,d1 s1 t y:ea move(c) s1,y:ea s1 t y:aa move(c) s1,y:aa s1 t d2 move(c) s1,d2 s2 t d1 move(c) s2,d1 #xxxx t d1 move(c) #xxxx,d1 #xx t d1 move(c) #xx,d1 description: move the contents of the specified source control register s1 or s2 to the specified destination or move the specified source to the specified destination control register d1 or d2. the control registers s1 and d1 are a subset of the s2 and d2 regis- ter set and consist of the address alu modifier registers and the program controller reg- isters. these registers may be moved to or from any other register or memory space. al memory addressing modes, as well as an immediate short addressing mode, may be used. if the system stack register ssh is specified as a source operand, the system stack pointer (sp) is postdecremented by 1 after ssh has been read. if the system stack reg- ister ssh is specified as a destination operand, the system stack pointer (sp) is prein- cremented by 1 before ssh is written. this allows the system stack to be efficiently extended using software stack pointer operations. when a 56-bit accumulator (a or b) is specified as a source operand, the accumulator value is optionally shifted according to the scaling mode bits s0 and s1 in the system status register (sr). if the data out of the shifter indicates that the accumulator extension movec move control register movec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 207 register is in use, and the data is to be moved into a 24-bit destination, the value stored in the destination is limited to a maximum positive or negative saturation constant to min- imize truncation error. if the data is to be moved into a 16-bit destination and the accu- mulator extension register is in use, the value is limited to a maximum positive or negative saturation constant whose ls 16 bits are then stored in the 16-bit destination register. limiting does not occur if an individual 24-bit accumulator register (a1, a0, b1, or b0) is specified as a source operand instead of the full 56-bit accumulator (a or b). this limiting feature allows block floating-point operations to be performed with error detection since the l bit in the condition code register is latched. when a 56-bit accumulator (a or b) is specified as a destination operand, any 24-bit source data to be moved into that accumulator is automatically extended to 56 bits by sign extending the ms bit of the source operand (bit 23) and appending the source oper- and with 24 ls zeros. whenever a 16-bit source operand is to be moved into a 24-bit destination, the 16-bit value is stored in the ls 16 bits of the 24-bit destination, and the ms 8 bits of that destination are zeroed. similarly, whenever a 16-bit source operand is to be moved into a 56-bit accumulator, the 16-bit value is moved into the ls 16 bits of the msp portion of the accumulator (a1 or b1), the ms 8 bits of the msp portion of that accumulator are zeroed, and the resulting 24-bit value is extended to 56 bits by sign extending the ms bit and appending the result with 24 ls zeros. note that for 24-bit source operands both the automatic sign-extension and zeroing features may be dis- abled by specifying the destination register to be one of the individual 24-bit accumulator registers (a1 or b1). note: due to instruction pipelining, if an agu register (mn, nn, or rn) is directly changed with this instruction, the new contents may not be available for use until the second fol- lowing instruction. see the restrictions discussed in a.9.6 - r, n, and m register restric- tions on page a-page 310. restrictions: the following restrictions represent very unusual operations which proba- bly would never be used but are listed only for completeness. a movec instruction used within a do loop which specifies ssh as the source oper- and or la, lc, sr, sp, ssh, or ssl as the destination operand cannot begin at the address la e 2, la e 1, or la within that do loop. movec move control register movec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 208 instruction set details motorola a movec instruction which specifies ssh as the source operand or la, lc, ssh, ssl, or sp as the destination operand cannot be used immediately before a do instruc- tion. a movec instruction which specifies ssh as the source operand or la, lc, sr, ssh, ssl, or sp as the destination operand cannot be used immediately before an enddo instruction. a movec instruction which specifies ssh as the source operand or sr, ssh, ssl, or sp as the destination operand cannot be used immediately before an rti instruction. a movec instruction which specifies ssh as the source operand or ssh, ssl, or sp as the destination operand cannot be used immediately before an rts instruction. a movec instruction which specified sp as the destination operand cannot be used immediately before a movec, movem, or movep instruction which specifies ssh or ssl as the source operand. a movec ssh, ssh instruction is illegal and cannot be used. example: : movec lc,x0 ;move lc into x0 : explanation of example: prior to execution, the 16-bit loop counter (lc) register con- tains the value $0100, and the 24-bit x0 register contains the value $123456. the execu- tion of the movec lc,x0 instruction moves the contents of the 16-bit lc register into the 16 ls bits of the 24-bit x0 register and zeros the 8 ms bits of the x0 register. movec move control register movec before execution after execution lc $0100 x0 x0 $123456 $000100 lc $0100 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 209 condition codes: for d1 or d2=sr operand: s ? set according to bit 7 of the source operand l ? set according to bit 6 of the source operand e ? set according to bit 5 of the source operand u ? set according to bit 4 of the source operand n ? set according to bit 3 of the source operand z ? set according to bit 2 of the source operand v ? set according to bit 1 of the source operand c ? set according to bit 0 of the source operand for d1 and d2 1 sr operand: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during the move instruction format: move(c) x:ea,d1 move(c) s1,x:ea move(c) y:ea,d1 move(c) s1,y:ea move(c) #xxxx,d1 opcode: instruction fields: ea=6-bit effective address=mmmrrr mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc movec move control register movec 23 16 15 8 7 0 optional effective address extension 00000101w1mmmrrr0s1ddddd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 210 instruction set details motorola effective register w addressing mode m m m r r r read s 0 (rn)-nn 0 0 0 r r r write d 1 (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 immediate data 1 1 0 1 0 0 where rrr refers to an address register r0er7 memory space s s1, d1 d d d d d x memory 0 m0em7 0 0 n n n y memory 1 sr 1 1 0 0 1 omr 1 1 0 1 0 sp 1 1 0 1 1 ssh 1 1 1 0 0 ssl 1 1 1 0 1 la 1 1 1 1 0 lc 1 1 1 1 1 where nnn = mn number (m0em7) timing: 2+mvc oscillator clock cycles memory: 1+ea program words movec move control register movec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 211 instruction format: move(c) x:aa,d1 move(c) s1,x:aa move(c) y:aa,d1 move(c) s1,y:aa opcode: instruction fields: aa=6-bit absolute short address=aaaaaa register w absolute short address aaaaaa read s 0 000000 write d 1 111111 memory space s s1, d1 d d d d d x memory 0 m0em7 0 0 n n n y memory 1 sr 1 1 0 0 1 omr 1 1 0 1 0 sp 1 1 0 1 1 ssh 1 1 1 0 0 ssl 1 1 1 0 1 la 1 1 1 1 0 lc 1 1 1 1 1 where nnn = mn number (m0em7) timing: 2+mvc oscillator clock cycles memory: 1+ea program words 23 16 15 8 7 0 00000101w0aaaaaa0s1ddddd movec move control register movec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 212 instruction set details motorola instruction format: move(c) s1,d2 move(c) s2,d1 opcode: instruction fields: register w s1, d1 d d d d d read s1 0 m0em7 0 0 n n n write d1 1 sr 1 1 0 0 1 omr 1 1 0 1 0 sp 1 1 0 1 1 memory space s ssh 1 1 1 0 0 x memory 0 ssl 1 1 1 0 1 y memory 1 la 1 1 1 1 0 lc 1 1 1 1 1 where nnn = mn number (m0em7) s2 d2 d2 s2, d2 e e e e e e s/l sign ext zero s2, d2 e e e e e e x0 0 0 0 1 0 0 no no no r0 - r7 0 1 0 n n n x1 0 0 0 1 0 1 no no no n0 - n7 0 1 1 n n n y0 0 0 0 1 1 0 no no no m0 - m7 1 0 0 n n n y1 0 0 0 1 1 1 no no no sr 1 1 1 0 0 1 a0 0 0 1 0 0 0 no no no omr 1 1 1 0 1 0 b0 0 0 1 0 0 1 no no no sp 1 1 1 0 1 1 a2 0 0 1 0 1 0 no no no ssh 1 1 1 1 0 0 b2 0 0 1 0 1 1 no no no ssl 1 1 1 1 0 1 a1 0 0 1 1 0 0 no no no la 1 1 1 1 1 0 b1 0 0 1 1 0 1 no no no lc 1 1 1 1 1 1 a 0 0 1 1 1 0 yes a2 a0 b 0 0 1 1 1 1 yes b2 b0 where nnn = rn number (r0 - r7) nn number (n0 - n7) mn number (m0 - m7) movec move control register movec 23 16 15 8 7 0 00000100w1eeeeee101ddddd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 213 timing: 2+mvc oscillator clock cycles memory: 1+ea program words instruction format: move(c) #xx,d1 opcode: instruction fields: #xx=8-bit immediate short data=i i i i i i i i d1 d d d d d m0em7 0 0 n n n sr 1 1 0 0 1 omr 1 1 0 1 0 sp 1 1 0 1 1 ssh 1 1 1 0 0 ssl 1 1 1 0 1 la 1 1 1 1 0 lc 1 1 1 1 1 where nnn = mn number (m0em7) timing: 2+mvc oscillator clock cycles memory: 1+ea program words movec move control register movec 23 16 15 8 7 0 00000101iiiiiiii101ddddd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 214 instruction set details motorola operation: assembler syntax: s t p:ea move(m) s,p:ea s t p:aa move(m) s,p:aa p:ea t d move(m) p:ea,d p:aa t d move(m) p:aa,d description: move the specified operand from/to the specified program (p) memory location . this is a powerful move instruction in that the source and destination registers s and d may be any register. all memory alterable addressing modes may be used as well as the absolute short addressing mode. if the system stack register ssh is specified as a source operand, the system stack pointer (sp) is postdecremented by 1 after ssh has been read. if the system stack reg- ister ssh is specified as a destination operand, the system stack pointer (sp) is prein- cremented by 1 before ssh is written. this allows the system stack to be efficiently extended using software stack pointer operations. when a 56-bit accumulator (a or b) is specified as a source operand s, the accumulator value is optionally shifted according to the scaling mode bits s0 and s1 in the system status register (sr). if the data out of the shifter indicates that the accumulator extension register is in use and the data is to be moved into a 24-bit destination, the value stored in the destination is limited to a maximum positive or negative saturation constant to mini- mize truncation error. if a 24-bit source operand is to be moved into a 16-bit destination register d, the 8 ms bits of the 24-bit source operand are discarded, and the 16 ls bits are stored in the 16-bit destination register. limiting does not occur if an individual 24-bit accumulator register (a1, a0, b1, or b0) is specified as a source operand instead of the full 56-bit accumulator (a or b). this limiting feature allows block floating-point opera- tions to be performed with error detection since the l bit in the condition code register is latched. when a 56-bit accumulator (a) is specified as a destination operand d, any 24-bit source data to be moved into that accumulator is automatically extended to 56 bits by sign extending the ms bit of the source operand (bit 24) and appending the source oper- and with 24 ls zeros. whenever a 16-bit source operand s is to be moved into a 24-bit destination, the 16-bit source is loaded into the ls 16 bits of the destination operand, and the remaining 8 ms bits of the destination are zeroed. note that for 24-bit source movem move program memory movem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 215 operands, both the automatic sign-extension and zeroing features may be disabled by specifying the destination register to be one of the individual 24-bit accumulator registers (a1 or b1). note: due to instruction pipelining, if an agu register (mn, nn, or rn) is directly changed with this instruction, the new contents may not be available for use until the second fol- lowing instruction. see the restrictions discussed in a.9.6 - r, n, and m register restric- tions on page a-page 310. restrictions: the following restrictions represent very unusual operations, which proba- bly would never be used but are listed only for completeness. a movem instruction used within a do loop which specifies ssh as the source oper- and or la, lc, sr, sp, ssh, or ssl as the destination operand cannot begin at the address lae2, lae1, or la within that do loop. a movem instruction which specifies ssh as the source operand or la, lc, ssh, ssl, or sp as the destination operand cannot be used immediately before a do instruction. a movem instruction which specifies ssh as the source operand or la, lc, sr, ssh, sl, or sp as the destination operand cannot be used immediately before an enddo instruction. a movem instruction which specifies ssh as the source operand or sr, ssh, ssl, or sp as the destination operand cannot be used immediately before an rti instruction. a movem instruction which specifies ssh as the source operand or ssh, ssl, or sp as the destination operand cannot be used immediately before an rts instruction. a movem instruction which specifies sp as the destination operand cannot be used immediately before a movec, movem, or movep instruction which specifies ssh or ssl as the source operand. movem move program memory movem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 216 instruction set details motorola example: : movem p:(r5+n5), lc :move p:(r5+n5) into the loop counter (lc) : explanation of example: prior to execution, the 16-bit loop counter (lc) register con- tains the value $0000, and the 24-bit program (p) memory location p:(r5+n5) contains the value $000116. the execution of the movem p:(r5+n5), lc instruction moves the 16 ls bits of the 24-bit program (p) memory location p:(r5+n5) into the 16-bit lc regis- ter. condition codes: for d=sr operand: s ? set according to bit 7 of the source operand l ? set according to bit 6 of the source operand e ? set according to bit 5 of the source operand u ? set according to bit 4 of the source operand n ? set according to bit 3 of the source operand z ? set according to bit 2 of the source operand v ? set according to bit 1 of the source operand c ? set according to bit 0 of the source operand for d 1 sr operand: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during the move before execution after execution p:(r5 + n5) $000116 lc lc $0000 $0116 $000116 p:(r5 + n5) mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc movem move program memory movem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 217 instruction format: move(m) s,p:ea move(m) p:ea,d opcode: instruction fields: ea=6-bit effective address=mmmrrr effective register w addressing mode m m m r r r read s 0 (rn)-nn 0 0 0 r r r write d 1 (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 where rrr refers to an address register r0er7 23 16 15 8 7 0 optional effective address extension 00000111w1mmmrrr10dddddd movem move program memory movem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 218 instruction set details motorola sdd s,d d d d d d d s/l sign ext zero s,d d d d d d d x0 0 0 0 1 0 0 no no no r0 - r7 0 1 0 n n n x1 0 0 0 1 0 1 no no no n0 - n7 0 1 1 n n n y0 0 0 0 1 1 0 no no no m0 - m7 1 0 0 n n n y1 0 0 0 1 1 1 no no no sr 1 1 1 0 0 1 a0 0 0 1 0 0 0 no no no omr 1 1 1 0 1 0 b0 0 0 1 0 0 1 no no no sp 1 1 1 0 1 1 a2 0 0 1 0 1 0 no no no ssh 1 1 1 1 0 0 b2 0 0 1 0 1 1 no no no ssl 1 1 1 1 0 1 a1 0 0 1 1 0 0 no no no la 1 1 1 1 1 0 b1 0 0 1 1 0 1 no no no lc 1 1 1 1 1 1 a 0 0 1 1 1 0 yes a2 a0 b 0 0 1 1 1 1 yes b2 b0 where nnn = rn number (r0 - r7) nn number (n0 - n7) mn number (m0 - m7) movem move program memory movem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 219 instruction format: move(m) s,p:aa move(m) p:aa,d opcode: instruction fields: aa=6-bit absolute short address=aaaaa register w absolute short address aaaaaa read s 0 000000 write d 1 111111 sdd s,d d d d d d d s/l sign ext zero s,d d d d d d d x0 0 0 0 1 0 0 no no no r0 - r7 0 1 0 n n n x1 0 0 0 1 0 1 no no no n0 - n7 0 1 1 n n n y0 0 0 0 1 1 0 no no no m0 - m7 1 0 0 n n n y1 0 0 0 1 1 1 no no no sr 1 1 1 0 0 1 a0 0 0 1 0 0 0 no no no omr 1 1 1 0 1 0 b0 0 0 1 0 0 1 no no no sp 1 1 1 0 1 1 a2 0 0 1 0 1 0 no no no ssh 1 1 1 1 0 0 b2 0 0 1 0 1 1 no no no ssl 1 1 1 1 0 1 a1 0 0 1 1 0 0 no no no la 1 1 1 1 1 0 b1 0 0 1 1 0 1 no no no lc 1 1 1 1 1 1 a 0 0 1 1 1 0 yes a2 a0 b 0 0 1 1 1 1 yes b2 b0 where nnn = rn number (r0 - r7) nn number (n0 - n7) mn number (m0 - m7) timing: 6+ea+ap oscillator clock cycles memory: 1+ea program words movem move program memory movem 23 16 15 8 7 0 00000111w0aaaaaa00dddddd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 220 instruction set details motorola operation: assembler syntax: x:pp t d movep x:pp,d x:pp t x:ea movep x:pp,x:ea x:pp t y:ea movep x:pp,y:ea x:pp t p:ea movep x:pp,p:ea s t x:pp movep s,x:pp #xxxxxx t x:pp movep #xxxxxx,x:pp x:ea t x:pp movep x:ea,x:pp y:ea t x:pp movep y:ea,x:pp p:ea t x:pp movep p:ea,x:pp y:pp t d movep y:pp,d y:pp t x:ea movep y:pp,x:ea y:pp t y:ea movep y:pp,y:ea y:pp t p:ea movep y:pp,p:ea s t y:pp movep s,y:pp #xxxxxx t y:pp movep #xxxxxx,y:pp x:ea t y:pp movep x:ea,y:pp y:ea t y:pp movep y:ea,y:pp p:ea t y:pp movep p:ea,y:pp description: move the specified operand from/to the specified x or y i/o peripheral . the i/o short addressing mode is used for the i/o peripheral address. all memory addressing modes may be used for the x or y memory effective address; all memory alterable addressing modes may be used for the p memory effective address. if the system stack register ssh is specified as a source operand, the system stack pointer (sp) is postdecremented by 1 after ssh has been read. if the system stack reg- movep move peripheral data movep f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 221 ister ssh is specified as a destination operand, the system stack pointer (sp) is prein- cremented by 1 before ssh is written. this allows the system stack to be efficiently extended using software stack pointer operations. when a 56-bit accumulator (a or b) is specified as a source operand s, the accumulator value is optionally shifted according to the scaling mode bits s0 and s1 in the system status register (sr). if the data out of the shifter indicates that the accumulator extension register is in use and the data is to be moved into a 24-bit destination, the value stored in the destination is limited to a maximum positive or negative saturation constant to mini- mize truncation error. if a 24-bit source operand is to be moved into a 16-bit destination register d, the 8 ms bits of the 24-bit source operand are discarded, and the 16 ls bits are stored in the 16-bit destination register. limiting does not occur if an individual 24-bit accumulator register (a1, a0, b1, or b0) is specified as a source operand instead of the full 56-bit accumulator (a or b). this limiting feature allows block floating-point opera- tions to be performed with error detection since the l bit in the condition code register is latched. when a 56-bit accumulator (a or b) is specified as a destination operand d, any 24-bit source data to be moved into that accumulator is automatically extended to 56 bits by sign extending the ms bit of the source operand (bit 23) and appending the source oper- and with 24 ls zeros. whenever a 16-bit source operand s is to be moved into a 24-bit destination, the 16-bit source is loaded into the ls 16 bits of the destination operand, and the remaining 8 ms bits of the destination are zeroed. note that for 24-bit source operands both the automatic sign-extension and zeroing features may be disabled by specifying the destination register to be one of the individual 24-bit accumulator registers (a1 or b1). note: unlike other move-type instructions, if an agu register (mn, nn, or rn) is directly changed with movep, the new contents will be available for use during the immediately following instruction. there is no instruction cycle pipeline delay associated with movep. restrictions: the following restrictions represent very unusual operations, which proba- bly would never be used but are listed only for completeness. a movep instruction used within a do loop which specifies ssh as the source oper- and or la, lc, sr, sp, ssh, or ssl as the destination operand cannot begin at the address lae2, lae1, or la within that do loop. movep move peripheral data movep f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 222 instruction set details motorola a movep instruction which specifies ssh as the source operand or la, lc, ssh, ssl, or sp as the destination operand cannot be used immediately before a do instruc- tion. a movep instruction which specifies ssh as the source operand or la, lc, sr, ssh, ssl, or sp as the destination operand cannot be used immediately before an enddo instruction. a movep instruction which specifies ssh as the source operand or sr, ssh, ssl, or sp as the destination operand cannot be used immediately before an rti instruction. a movep instruction which specifies ssh as the source operand or ssh, ssl, or sp as the destination operand cannot be used immediately before an rts instruction. a movep instruction which specifies sp as the destination operand cannot be used immediately before a movec, movem, or movep instruction which specifies ssh or ssl as the source operand. example: : movep #1113,x:<<$fffe :initialize bus control register wait states : explanation of example: prior to execution, the 16-bit, x memory-mapped, i/o bus control register (bcr) contains the value $ffff. the execution of the movep #$1113,x:<<$fffe instruction moves the value $1113 into the 16-bit bus control regis- ter x:$fffe, resulting in one wait state for all external x, external y, and external pro- gram memory accesses and three wait states for all external i/o accesses. movep move peripheral data movep before execution after execution x:$fffe (bcr) $ffff $1113 x:$fffe (bcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 223 condition codes: for d=sr operand: s ? set according to bit 7 of the source operand l ? set according to bit 6 of the source operand e ? set according to bit 5 of the source operand u ? set according to bit 4 of the source operand n ? set according to bit 3 of the source operand z ? set according to bit 2 of the source operand v ? set according to bit 1 of the source operand c ? set according to bit 0 of the source operand for d 1 sr operand: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during the move mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc movep move peripheral data movep f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 224 instruction set details motorola instruction format (x: or y: reference): movep x:ea,x:pp movep y:ea,x:pp movep #xxxxxx,x:pp movep x:pp,x:ea movep x:pp,y:ea movep x:ea,y:pp movep y:ea,y:pp movep #xxxxxx,y:pp movep y:pp,y:ea movep y:pp,y:ea opcode: movep move peripheral data movep 23 16 15 8 7 0 optional effective address extension 0000100 s w1mmmrrr1spppp pp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 225 instruction fields: ea=6-bit effective address=mmmrrr, pp=6-bit i/o short address=pppppp effective memory space s addressing mode m m m r r r x memory 0 (rn)-nn 0 0 0 r r r y memory 1 (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r peripheral space s (rn)+ 0 1 1 r r r x memory 0 (rn) 1 0 0 r r r y memory 1 (rn+nn) 1 0 1 r r r e(rn) 1 1 1 r r r peripheral w absolute address 1 1 0 0 0 0 read 0 immediate data 1 1 0 1 0 0 write 1 where rrr refers to an address register r0er7 timing: 2+mvp oscillator clock cycles memory: 1+ea program words movep move peripheral data movep f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 226 instruction set details motorola instruction format (p: reference): movep p:ea,x:pp movep x:pp,p:ea movep p:ea,y:pp movep y:pp,p:ea opcode: instruction fields: ea=6-bit effective address=mmmrrr pp=6-bit i/o short address=pppppp effective peripheral space s addressing mode m m m r r r x memory 0 (rn)-nn 0 0 0 r r r y memory 1 (rn)+nn 0 0 1 r r r (rn)- 0 1 0 r r r peripheral w (rn)+ 0 1 1 r r r read 0 (rn) 1 0 0 r r r write 1 (rn+nn) 1 0 1 r r r e(rn) 1 1 1 r r r absolute address 1 1 0 0 0 0 where rrr refers to an address register r0er7 timing: 4+mvp oscillator clock cycles memory: 1+ea program words movep move peripheral data movep 23 16 15 8 7 0 optional effective address extension 0000100 s w1mmmrrr01pppp pp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 227 instruction format (register reference): movep s,x:pp movep x:pp,d movep s,y:pp movep y:pp,d opcode: instruction fields: pp=6-bit i/o short address=pppppp peripheral space s peripheral w x memory 0 read 0 y memory 1 write 1 sdd s,d d d d d d d s/l sign ext zero s,d d d d d d d x0 0 0 0 1 0 0 no no no r0 - r7 0 1 0 n n n x1 0 0 0 1 0 1 no no no n0 - n7 0 1 1 n n n y0 0 0 0 1 1 0 no no no m0 - m7 1 0 0 n n n y1 0 0 0 1 1 1 no no no sr 1 1 1 0 0 1 a0 0 0 1 0 0 0 no no no omr 1 1 1 0 1 0 b0 0 0 1 0 0 1 no no no sp 1 1 1 0 1 1 a2 0 0 1 0 1 0 no no no ssh 1 1 1 1 0 0 b2 0 0 1 0 1 1 no no no ssl 1 1 1 1 0 1 a1 0 0 1 1 0 0 no no no la 1 1 1 1 1 0 b1 0 0 1 1 0 1 no no no lc 1 1 1 1 1 1 a 0 0 1 1 1 0 yes a2 a0 b 0 0 1 1 1 1 yes b2 b0 where nnn = rn number (r0 - r7) nn number (n0 - n7) mn number (m0 - m7) timing: 4+mvp oscillator clock cycles memory: 1+ea program words movep move peripheral data movep 23 16 15 8 7 0 0000100sw1dddddd00pppppp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 228 instruction set details motorola operation: assembler syntax: s1 * s2 t d (parallel move) mpy ( )s1,s2,d (parallel move) s1 * s2 t d (parallel move) mpy ( )s2,s1,d (parallel move) (s1 * 2 -n ) t d ( no parallel move) mpy ( )s,#n,d ( no parallel move) description: multiply the two signed 24-bit source operands s1 and s2 and store the resulting product in the specified 56-bit destination accumulator d. or, multiply the signed 24-bit source operand s by the positive 24-bit immediate operand 2 -n and add/ subtract to/from the specified 56-bit destination accumulator d. the e sign option is used to negate the specified product prior to accumulation. the default sign option is +. note: when the processor is in the double precision multiply mode, the following instructions do not execute in the normal way and should only be used as part of the double precision multiply algorithm shown in section 3.4 double precision multi- ply mode: mpy y0, x0, a mpy y0, x0, b mac x1, y0, a mac x1, y0, b mac x0, y1, a mac x0, y1, b mac y1, x1, a mac y1, x1, b all other data alu instructions are executed as nop?s when the processor is in the dou- ble precision multiply mode. example 1: : mpy ex1,y1,a #$543210,y0 ;e(x1 * y1) t a, update y0 : mpy signed multiply mpy before execution after execution x1 $800000 y1 y1 $c00000 $c00000 $800000 x1 a $00:000000:000000 $ff:c00000:000000 a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 229 explanation of example 1: prior to execution, the 24-bit x1 register contains the value $800000 (e1.0), the 24-bit y1 register contains the value $c00000, (e0.5), and the 56-bit a accumulator contains the value $00:000000:000000 (0.0). the execution of the mpy e x1,y1,a instruction multiples the 24-bit signed value in the x1 register by the 24-bit signed value in the y1 register, negates the 48-bit product, and stores the result in the 56-bit a accumulator (ex1 * y1=e0.5=$ff:c00000:000000=a). condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting occurred during parallel move e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z? set if a or b result equals zero v ? set if overflow has occurred in a or b result note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 condition code computation for complete details. instruction format 1: mpy ( ) s1,s2,d mpy ( ) s2,s1,d opcode 1: mpy signed multiply mpy mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 8 7 4 3 0 data bus move field 1qqq dk00 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 230 instruction set details motorola instruction fields 1: s1 * s2 q q q sign k d d x0 x0 0 0 0 + 0 a 0 y0 y0 0 0 1 e 1 b 1 x1 x0 0 1 0 y1 y0 0 1 1 x0 y1 1 0 0 y0 x0 1 0 1 x1 y0 1 1 0 y1 x1 1 1 1 note: only the indicated s1 * s2 combinations are valid. x1 * x1 and y1 * y1 are not valid. timing: 2+mv oscillator clock cycles memory: 1+mv program words example 2: : mpy x1, #9, a ; : explanation of example 2: the content of x1 is multiplied by 2 -9 and the result is placed in the a accumulator. the net effect of this operation is to divide the content of x1 by 2 9 and place the result in the accumulator. an alternate interpretation is that x1 is right shift ed 9 places and filled with the sign bit (0 for a positive number and 1 for a neg- ative number) and then the result is placed in the accumulator. mpy signed multiply mpy before execution after execution x1 $654321 a a $00:000000:000000 $00:0032a1:908000 $654321 x1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 231 instruction format 2: mpy ( )s,#n,d opcode 2: instruction fields: s q q sign k d d y1 0 0 + 0 a 0 x0 0 1 e 1 b 1 y0 1 0 x1 1 1 n sssss constant 1 00001 010000000000000000000000 2 00010 001000000000000000000000 3 00011 000100000000000000000000 4 00100 000010000000000000000000 5 00101 000001000000000000000000 6 00110 000000100000000000000000 7 00111 000000010000000000000000 8 01000 000000001000000000000000 9 01001 000000000100000000000000 10 01010 000000000010000000000000 11 01011 000000000001000000000000 12 01100 000000000000100000000000 13 01101 000000000000010000000000 14 01110 000000000000001000000000 15 01111 000000000000000100000000 16 10000 000000000000000010000000 17 10001 000000000000000001000000 18 10010 000000000000000000100000 19 10011 000000000000000000010000 20 10100 000000000000000000001000 21 10101 000000000000000000000100 22 10110 000000000000000000000010 23 10111 000000000000000000000001 timing: 2 oscillator clock cycles memory: 1 program word mpy signed multiply mpy 23 16 15 8 7 0 00000001000s ssss 11qqdk00 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 232 instruction set details motorola operation: assembler syntax: s1 * s2+r t d (parallel move) mpyr ( )s1,s2,d (parallel move) s1 * s2+r t d (parallel move) mpyr ( )s2,s1,d (parallel move) (s1 * 2 -n )+r t d ( no parallel move) mpyr ( )s,#n,d ( no parallel move) description: multiply the two signed 24-bit source operands s1 and s2 ( or the signed 24-bit source operand s by the positive 24-bit immediate operand 2 -n ), round the result using convergent rounding, and store it in the specified 56-bit destination accumulator d. the e sign option is used to negate the product prior to rounding. the default sign option is +. the contribution of the ls bits of the result is rounded into the upper portion of the destination accumulator (a1 or b1) by adding a constant to the ls bits of the lower portion of the accumulator (a0 or b0). the value of the constant added is determined by the scaling mode bits s0 and s1 in the status register. once the rounding has been com- pleted, the ls bits of the destination accumulator d (a0 or b0) are loaded with zeros to maintain an unbiased accumulator value which may be reused by the next instruction. the upper portion of the accumulator (a1 or b1) contains the rounded result which may be read out to the data buses. refer to the rnd instruction for more complete informa- tion on the convergent rounding process. example 1: : mpyr ey0,y0,b (r3)en3 ;square and negate y0, update r3 : explanation of example 1: prior to execution, the 24-bit y0 register contains the value $654321 (0.791111112), and the 56-bit b accumulator contains the value $00:000000:000000 (0.0). the execution of the mpyr ey0,y0,b instruction squares the 24-bit signed value in the y0 register, negates the resulting 48-bit product, rounds the result into b1, and zeros b0 (ey0 * y0=e0.625856790961748 approximately= $ff:afe3ec:b76b7e, which is rounded to the value $ff:afe3ed:000000= e0.625856757164002=b). mpyr signed multiply and round mpyr before execution after execution y0 $654321 b b $00:000000:000000 $ff:afe3ed:000000 $654321 y0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 233 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting occurred during parallel move e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z? set if a or b result equals zero v ? set if overflow has occurred in a or b result note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 condition code computation for complete details. instruction format 1: mpyr ( ) s1,s2,d mpyr ( ) s2,s1,d opcode 1: mpyr signed multiply and round mpyr mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 8 7 4 3 0 data bus move field 1qqq dk01 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 234 instruction set details motorola instruction fields 1: s1 * s2 q q q sign k d d x0 x0 0 0 0 + 0 a 0 y0 y0 0 0 1 e 1 b 1 x1 x0 0 1 0 y1 y0 0 1 1 x0 y1 1 0 0 y0 x0 1 0 1 x1 y0 1 1 0 y1 x1 1 1 1 note: only the indicated s1 * s2 combinations are valid. x1 * x1 and y1 * y1 are not valid. timing: 2+mv oscillator clock cycles memory: 1+mv program words example 2: : mpyr -y1, #14, b ; : explanation of example 2: the content of y1 is negated, multiplied by 2 -14 , rounded to a single precision number (24 bits in b1) and placed in the b accumulator. the net effect of this operation is negate the content of y1 and divide the result by 2 14 , place the result in the accumulator and then round to a single precision number. an alternate interpreta- tion is that x1 is negated and placed in the accumulator, right shift ed 14 places, filled with the sign bit (0 for a positive number and 1 for a negative number) and then rounded to a single precision number. before execution after execution y1 $654321 b b $00:000000:000000 $ff:fffe6b:000000 $654321 y1 mpyr signed multiply and round mpyr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 235 instruction format 2: mpyr ( )s,#n,d opcode 2: instruction fields 2: s q q sign k d d y1 0 0 + 0 a 0 x0 0 1 e 1 b 1 y0 1 0 x1 1 1 n sssss constant 1 00001 010000000000000000000000 2 00010 001000000000000000000000 3 00011 000100000000000000000000 4 00100 000010000000000000000000 5 00101 000001000000000000000000 6 00110 000000100000000000000000 7 00111 000000010000000000000000 8 01000 000000001000000000000000 9 01001 000000000100000000000000 10 01010 000000000010000000000000 11 01011 000000000001000000000000 12 01100 000000000000100000000000 13 01101 000000000000010000000000 14 01110 000000000000001000000000 15 01111 000000000000000100000000 16 10000 000000000000000010000000 17 10001 000000000000000001000000 18 10010 000000000000000000100000 19 10011 000000000000000000010000 20 10100 000000000000000000001000 21 10101 000000000000000000000100 22 10110 000000000000000000000010 23 10111 000000000000000000000001 timing: 2 oscillator clock cycles memory: 1 program word 23 16 15 8 7 0 00000001000s ssss 11qqdk01 mpyr signed multiply and round mpyr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 236 instruction set details motorola operation: assembler syntax: 0ed t d (parallel move) neg d (parallel move) description: negate the destination operand d and store the result in the destination accumulator. this is a 56-bit, twos-complement operation. example: : neg b x1,x:(r3)+ y:(r6)e,a ;0eb t b, update a,x1,r3,r6 : explanation of example: prior to execution, the 56-bit b accumulator contains the value $00:123456:789abc. the neg b instruction takes the twos complement of the value in the b accumulator and stores the 56-bit result back in the b accumulator. condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z ? set if a or b result equals zero v ? set if overflow has occurred in a or b result note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 condition code computation for complete details. neg negate accumulator neg before execution after execution b $00:123456:789abc $ff:edcba9:876544 b mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 sl eunz v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 237 instruction format: neg d opcode: instruction fields: d d a 0 b1 timing: 2+mv oscillator clock cycles memory: 1+mv program words neg negate accumulator neg 23 8 7 4 3 0 data bus move field 0011 d110 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 238 instruction set details motorola operation: assembler syntax: pc+1 t pc nop description: increment the program counter (pc). pending pipeline actions, if any, are completed. execution continues with the instruction following the nop. example: : nop ;increment the program counter : explanation of example: the nop instruction increments the program counter and completes any pending pipeline actions. condition codes: the condition codes are not affected by this instruction. nop no operation nop mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 239 instruction format: nop opcode: instruction fields: none timing: 2 oscillator clock cycles memory: 1 program word nop no operation nop 23 16 15 8 7 0 000000000000000000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 240 instruction set details motorola operation: assembler syntax: if e u z =1, then asl d and rne1 t rn norm rn,d else if e=1, then asr d and rn+1 t rn else nop where e denotes the logical complement of e, and where denotes the logical and operator description: perform one normalization iteration on the specified destination operand d, update the specified address register rn based upon the results of that iteration, and store the result back in the destination accumulator. this is a 56-bit operation. if the accumulator extension is not in use, the accumulator is unnormalized, and the accumu- lator is not zero, the destination operand is arithmetically shifted one bit to the left, and the specified address register is decremented by 1. if the accumulator extension register is in use, the destination operand is arithmetically shifted one bit to the right, and the specified address register is incremented by 1. if the accumulator is normalized or zero, a nop is executed and the specified address register is not affected. since the operation of the norm instruction depends on the e, u, and z condition code register bits, these bits must correctly reflect the current state of the destination accumulator prior to execut- ing the norm instruction. note that the l and v bits in the condition code register will be cleared unless they have been improperly set up prior to executing the norm instruc- tion. example: : rep #$2f ;maximum number of iterations needed norm r3,a ;perform 1 normalization iteration : explanation of example: prior to execution, the 56-bit a accumulator contains the value $00:000000:000001, and the 16-bit r3 address register contains the value $0000. the repetition of the norm r3,a instruction normalizes the value in the 56-bit accumu- lator and stores the resulting number of shifts performed during that normalization pro- norm normalize accumulator iteration norm before execution after execution a $00:000000:000001 r3 r3 $0000 $ffd2 $00:400000:000000 a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 241 cess in the r3 address register. a negative value reflects the number of left shifts performed; a positive value reflects the number of right shifts performed during the nor- malization process. condition codes: l ? set if overflow has occurred in a or b result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z ? set if a or b result equals zero v ? set if bit 55 is changed as a result of a left shift note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 condition code computation for complete details. instruction format: norm rn,d opcode: instruction fields: d d rn r r r a 0 rn n n n b1 where nnn = rn number timing: 2 oscillator clock cycles memory: 1 program word norm normalize accumulator iteration norm mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 s leunzv c 23 16 15 8 7 0 0000000111011rrr0001d101 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 242 instruction set details motorola operation: assembler syntax: d[47:24] t d[47:24] (parallel move) not d (parallel move) where ? denotes the logical not operator description: take the ones complement of bits 47e24 of the destination operand d and store the result back in bits 47e24 of the destination accumulator. this is a 24-bit opera- tion. the remaining bits of d are not affected. example: not a1 ab,l:(r2)+ ;save a1,b1, take the ones complement of a1 explanation of example: prior to execution, the 56-bit a accumulator contains the value $00:123456:789abc. the not a instruction takes the ones complement of bits 47e24 of the a accumulator (a1) and stores the result back in the a1 register. the remaining bits of the a accumulator are not affected. condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move n ? set if bit 47 of a or b result is set z ? set if bits 47-24 of a or b result are zero v ? always cleared not logical complement not before execution after execution a $00:123456:789abc $00:edcba9:789ab a mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 sl eu nz v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 243 instruction format: not d opcode: instruction fields: dd a0 b1 timing: 2+mv oscillator clock cycles memory: 1+mv program words not logical complement not 23 8 7 4 3 0 data bus move field 0001 d111 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 244 instruction set details motorola operation: assembler syntax: s+d[47:24] t d[47:24] (parallel move) or s,d (parallel move) where + denotes the logical inclusive or operator description: logically inclusive or the source operand s with bits 47e24 of the destina- tion operand d and store the result in bits 47e24 of the destination accumulator. this instruction is a 24-bit operation. the remaining bits of the destination operand d are not affected. example: : or y1,b1 ba,l:$1234 ;save a1,b1, or y1 with b : explanation of example: prior to execution, the 24-bit y1 register contains the value $ff0000, and the 56-bit b accumulator contains the value $00:123456:789abc. the or y1,b instruction logically ors the 24-bit value in the y1 register with bits 47e24 of the b accumulator (b1) and stores the result in the b accumulator with bits 55e48 and 23e0 unchanged. condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move n ? set if bit 47 of a or b result is set z ? set if bits 47-24 of a or b result are zero v ? always cleared or logical inclusive or or before execution after execution y1 $ff0000 b b $00:123456:789abc $00:ff3456:789abc $ff0000 y1 mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 sl eu nz v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 245 instruction format: or s,d opcode: instruction fields: s j j d d x0 0 0 a 0 x1 1 0 b 1 y0 0 1 y1 1 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words or logical inclusive or or 23 8 7 4 3 0 data bus move field 01jj d010 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 246 instruction set details motorola operation: assembler syntax: #xx+d t d or(i) #xx,d where + denotes the logical inclusive or operator description: logically or the 8-bit immediate operand (#xx) with the contents of the destination control register d and store the result in the destination control register. the condition codes are affected only when the condition code register is specified as the destination operand. restrictions: the ori #xx,mr instruction cannot be used immediately before an enddo or rti instruction and cannot be one of the last three instructions in a do loop (at lae2, lae1, or la). example: : or #$8,mr ;set scaling mode bit s1 to scale up : explanation of example: prior to execution, the 8-bit mode register (mr) contains the value $03. the or #$8,mr instruction logically ors the immediate 8-bit value $8 with the contents of the mode register and stores the result in the mode register. condition codes: for ccr operand: s ? set if bit 7 of the immediate operand is set l ? set if bit 6 of the immediate operand is set e ? set if bit 5 of the immediate operand is set u ? set if bit 4 of the immediate operand is set n ? set if bit 3 of the immediate operand is set z ? set if bit 2 of the immediate operand is set v ? set if bit 1 of the immediate operand is set c ? set if bit 0 of the immediate operand is set ori or immediate with control register ori before execution after execution mr $03 $0b mr mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 sl eunz vc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 247 for mr and omr operands: the condition codes are not affected using these operands. instruction format: or(i) #xx,d opcode: instruction fields: #xx=8-bit immediate short data = i i i i i i i i de e mr 0 0 ccr 0 1 omr 1 0 timing: 2 oscillator clock cycles memory: 1 program word ori or immediate with control register ori 23 16 15 8 7 0 00000000iiiiiiii111110ee f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 248 instruction set details motorola operation: assembler syntax: lc t temp; x:ea t lc rep x:ea repeat next instruction until lc=1 temp t lc lc t temp; x:aa t lc rep x:aa repeat next instruction until lc=1 temp t lc lc t temp; y:ea t lc rep y:ea repeat next instruction until lc=1 temp t lc lc t temp; y:aa t lc rep y:aa repeat next instruction until lc=1 temp t lc lc t temp; s t lc rep s repeat next instruction until lc=1 temp t lc lc t temp; #xxx t lc rep #xxx repeat next instruction until lc=1 temp t lc description: repeat the single-word instruction immediately following the rep instruction the specified number of times. the value specifying the number of times the given instruction is to be repeated is loaded into the 16-bit loop counter (lc) register. the single-word instruction is then executed the specified number of times, decrement- ing the loop counter (lc) after each execution until lc=1. when the rep instruction is in effect, the repeated instruction is fetched only one time, and it remains in the instruction register for the duration of the loop count. thus, the rep instruction is not interrupt- ible (sequential repeats are also not interruptible). the current loop counter (lc) value is stored in an internal temporary register. if lc is set equal to zero, the instruction is repeated 65,536 times. the instruction?s effective address specifies the address of the value which is to be loaded into the loop counter (lc). all address register indirect addressing modes may be used. the absolute short and the immediate short addressing modes may also be used. the four ms bits of the 12-bit immediate value are zeroed to form the 16-bit value that is to be loaded into the loop counter (lc). rep repeat next instruction rep f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 249 restrictions: the rep instruction can repeat any single-word instruction except the rep instruction itself and any instruction that changes program flow. the following instructions are not allowed to follow an rep instruction: immediately after rep do jsset jcc rep jclr rti jmp rts jset stop jscc swi jsclr wait jsr enddo also, a rep instruction cannot be the last instruction in a do loop (at la). the assem- bler will generate an error if any of the previous instructions are found immediately fol- lowing an rep instruction. example: : rep x0 ;repeat (x0) times mac x1,y1,a x:(r1)+,x1 y:(r4)+,y1 ;x1 * y1+a t a, update x1,y1 : rep repeat next instruction rep before execution after execution x0 $000100 lc lc $0000 $0000 $000100 x0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 250 instruction set details motorola explanation of example: prior to execution, the 24-bit x0 register contains the value $000100, and the 16-bit loop counter (lc) register contains the value $0000. the execu- tion of the rep x0 instruction takes the 24-bit value in the x0 register, truncates the ms 8 bits, and stores the 16 ls bits in the 16-bit loop counter (lc) register. thus, the single- word mac instruction immediately following the rep instruction is repeated $100 times. condition codes: for source operand a or b: s ? computed according to the definition. see notes on page a-255. l ? set if data limiting occurred. see notes on page a-255. for other source operands: the condition code bits are not affected. rep repeat next instruction rep mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 sl eu n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 251 instruction format: rep x:ea rep y:ea opcode: instruction fields: ea=6-bit effective address=mmmrrr, effective addressing mode m m m r r r memory space s (rn)-nn 0 0 0 r r r x memory 0 (rn)+nn 0 0 1 r r r y memory 1 (rn)- 0 1 0 r r r (rn)+ 0 1 1 r r r (rn) 1 0 0 r r r (rn+nn) 1 0 1 r r r -(rn) 1 1 1 r r r where rrr refers to an address register r0-r7 timing: 4+mv oscillator clock cycles memory: 1 program word rep repeat next instruction rep 23 16 15 8 7 0 0000011 001mmmrrr 0 s 100000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 252 instruction set details motorola instruction format: rep x:aa rep y:aa opcode: instruction fields: aa=6-bit absolute short address=aaaaaa absolute short address aaaaaa memory space s 000000 x memory 0 y memory 1 111111 timing: 4+mv oscillator clock cycles memory: 1 program word rep repeat next instruction rep 23 16 15 8 7 0 0000011000aaaaaa0s100000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 253 instruction format: rep #xxx opcode: instruction fields: #xxx=12-bit immediate short data = hhhh i i i i i i i i immediate short data hhhh i i i i i i i i i 000000000000 111111111111 timing: 4+mv oscillator clock cycles memory: 1 program word rep repeat next instruction rep 23 16 15 8 7 0 00000110iiiiiiii1010hhhh f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 254 instruction set details motorola instruction format: rep s opcode: instruction fields: s s d d d d d d s/l s d d d d d d x0 0 0 0 1 0 0 no r0 - r7 0 1 0 n n n x1 0 0 0 1 0 1 no n0 - n7 0 1 1 n n n y0 0 0 0 1 1 0 no m0 - m7 1 0 0 n n n y1 0 0 0 1 1 1 no sr 1 1 1 0 0 1 a0 0 0 1 0 0 0 no omr 1 1 1 0 1 0 b0 0 0 1 0 0 1 no sp 1 1 1 0 1 1 a2 0 0 1 0 1 0 no ssh 1 1 1 1 0 0 b2 0 0 1 0 1 1 no ssl 1 1 1 1 0 1 a1 0 0 1 1 0 0 no la 1 1 1 1 1 0 b1 0 0 1 1 0 1 no lc 1 1 1 1 1 1 a 0 0 1 1 1 0 yes (see notes on page a-255) b 0 0 1 1 1 1 yes (see notes on page a-255) where nnn = rn number (r0 - r7) nn number (n0 - n7) mn number (m0 - m7) rep repeat next instruction rep 23 16 15 8 7 0 0000011011dddddd00100000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 255 notes: if a or b is specified as the destination operand, the following sequence of events takes place: 1. the s bit is computed according to its definition (see section a.5 con- dition code computation) 2. the accumulator value is scaled according to the scaling mode bits s0 and s1 in the status register (sr). 3. if the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the l bit is set. 4. the ls 16 bits of the resulting 24 bit value is loaded into the loop counter (lc). the original contents of a or b are not changed. if the system stack register ssh is specified as a source operand, the system stack pointer (sp) is postdecremented by 1 after ssh has been read. timing: 4 oscillator clock cycles memory: 1 program word rep repeat next instruction rep f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 256 instruction set details motorola operation: assembler syntax: reset the interrupt priority register reset and all on-chip peripherals description: reset the interrupt priority register and all on-chip peripherals. this is a software reset which is not equivalent to a hardware reset since only on-chip peripher- als and the interrupt structure are affected. the processor state is not affected, and exe- cution continues with the next instruction. all interrupt sources are disabled except for the trace, stack error, nmi, illegal instruction, and hardware reset interrupts. restrictions: a reset instruction cannot be the last instruction in a do loop (at la). example: : reset ;reset all on-chip peripherals and ipr : explanation of example: the execution of the reset instruction resets all on-chip peripherals and the interrupt priority register (ipr). condition codes: the condition codes are not affected by this instruction reset reset on-chip peripheral devices reset mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 257 instruction format: reset opcode: instruction fields: none timing: 4 oscillator clock cycles memory: 1 program word reset reset on-chip peripheral devices reset 23 16 15 8 7 0 000000000000000010000100 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 258 instruction set details motorola operation: assembler syntax: d+r t d (parallel move) rnd d (parallel move) description: round the 56-bit value in the specified destination operand d and store the result in the msp portion of the destination accumulator (a1 or b1). this instruction uses a convergent rounding technique. the contribution of the ls bits of the result (a0 and b0) is rounded into the upper portion of the result (a1 or b1) by adding a rounding con- stant to the ls bits of the result. the msp portion of the destination accumulator con- tains the rounded result which may be read out to the data buses. the value of the rounding constant added is determined by the scaling mode bits s0 and s1 in the system status register (sr). a 1 is added in the rounding position as shown below: normal or standard?? rounding consists of adding a rounding constant to a given number of ls bits of a value to produce a rounded result. the rounding constant depends on the scaling mode being used as previously shown. unfortunately, when using a twos-complement data representation, this process introduces a positive bias in the statistical distribution of the roundoff error. rnd round accumulator rnd rounding rounding constant s1 s0 scaling mode position 55 - 25 24 23 22 21 - 0 0 0 no scaling 23 0. . . .0 0 1 0 0. . . .0 0 1 scale down 24 0. . . .0 1 0 0 0. . . .0 1 0 scale up 22 0. . . .0 0 0 1 0. . . .0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 259 convergent rounding differs from ??standard?? rounding in that convergent rounding attempts to remove the aforementioned positive bias by equally distributing the round-off error. the convergent rounding technique initially performs standard rounding as previ- ously described. again, the rounding constant depends on the scaling mode being used. once standard rounding has been done, the convergent rounding method tests the result to determine if all bits including and to the right of the rounding position are zero . if, and only if , this special condition is true, the convergent rounding method will clear the bit immediately to the left of the rounding position. when this special condition is true, numbers which have a 1 in the bit immediately to the left of the rounding posi- tion are rounded up ; numbers with a 0 in the bit immediately to the left of the rounding position are rounded down . thus, these numbers are rounded up half the time and rounded down the rest of the time. therefore, the roundoff error averages out to zero . the ls bits of the convergently rounded result are then cleared so that the rounded result may be immediately used by the next instruction. example: : rnd a #$123456,x1 b,y1 ;round a accumulator into a1, zero a0 : explanation of example: prior to execution, the 56-bit a accumulator contains the value $00:123456:789abc for case i, the value $00:123456:800000 for case ii, and the value $00:123455:800000 for case iii. the execution of the rnd a instruction rounds the value in the a accumulator into the msp portion of the a accumulator (a1), using convergent rounding, and then zeros the lsp portion of the a accumulator (a0). note that case ii is the special case that distinguishes convergent rounding from standard or biased rounding. rnd round accumulator rnd before execution after execution case i: a $00:123456:789ab case ii: a a $00:123456:800000 $00:123456:000000 $00:123456:000000 a case iii: a $ 00:123456:800000 $00:123456:000000 a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 260 instruction set details motorola condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z ? set if a or b result equals zero v ? set if overflow has occurred in a or b result note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 condition code computation for complete details. mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 sl eunz v c rnd round accumulator rnd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set descriptions motorola instruction set details a - 261 instruction format: rnd d opcode: instruction fields: dd a0 b1 timing: 2+mv oscillator clock cycles memory: 1+mv program words rnd round accumulator rnd 23 8 7 4 3 0 data bus move field 0001 d001 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 262 instruction set details motorola assembler syntax: rol d (parallel move) description: rotate bits 47e24 of the destination operand d one bit to the left and store the result in the destination accumulator. prior to instruction execution, bit 47 of d is shifted into the carry bit c, and, prior to instruction execution, the value in the carry bit c is shifted into bit 24 of the destination accumulator d. this instruction is a 24-bit opera- tion. the remaining bits of the destination operand d are not affected. example: : rol a1 #314,n2 ;rotate a1 one left bit, update n2 : explanation of example: prior to execution, the 56-bit a accumulator contains the value $00:000000:000000. the execution of the rol a instruction shifts the 24-bit value in the a1 register one bit to the left, shifting bit 47 into the carry bit c, rotating the carry bit c into bit 24, and storing the result back in the a1 register. rol rotate left rol 47 24 c (parallel move) operation: before execution after execution a a $00:000000:000000 sr sr $0301 $0300 $00:000001:000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 263 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move n ? set if bit 47 of a or b result is set z ? set if bits 47e24 of a or b result are zero v ? always cleared c ? set if bit 47 of a or b was set prior to instruction execution instruction format: rol d opcode: instruction fields: d d a 0 b 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words rol rotate left rol mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu nz vc 23 8 7 4 3 0 data bus move field 0011 d111 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 264 instruction set details motorola assembler syntax: ror d (parallel move) description: rotate bits 47e24 of the destination operand d one bit to the right and store the result in the destination accumulator. prior to instruction execution, bit 24 of d is shifted into the carry bit c, and, prior to instruction execution, the value in the carry bit c is shifted into bit 47 of the destination accumulator d. this instruction is a 24-bit opera- tion. the remaining bits of the destination operand d are not affected. example: : ror b1#$1234,r2 ;rotate b1 right one bit, update r2 : explanation of example: prior to execution, the 56-bit b accumulator contains the value $00:000001:222222. the execution of the ror b instruction shifts the 24-bit value in the b1 register one bit to the right, shifting bit 24 into the carry bit c, rotating the carry bit c into bit 47, and storing the result back in the b1 register. ror rotate right ror 47 24 c (parallel move) operation: before execution after execution b b $00:000001:222222 sr sr $0300 $0305 $00:000000:222222 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 265 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move n ? set if bit 47 of a or b result is set z ? set if bits 47e24 of a or b result are zero v ? always cleared c ? set if bit 24 of a or b was set prior to instruction execution. instruction format: ror d opcode: instruction fields: d d a 0 b 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words ror rotate right ror mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu nz vc 23 8 7 4 3 0 data bus move field 0010 d111 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 266 instruction set details motorola operation: assembler syntax: ssh t pc; ssl t sr; spe1 t sp rti description: pull the program counter (pc) and the status register (sr) from the system stack. the previous program counter and status register are lost. restrictions: due to pipelining in the program controller and the fact that the rti instruction accesses certain program controller registers, the rti instruction must not be immediately preceded by any of the following instructions: immediately before rti movec to sr, ssh, ssl, or sp movem to sr, ssh, ssl, or sp movep to sr, ssh, ssl, or sp movec from ssh movem from ssh movep from ssh andi mr or andi ccr ori mr or ori ccr an rti instruction cannot be the last instruction in a do loop (at la). an rti instruction cannot be repeated using the rep instruction. example: : rti ;pull pc and sr from system stack : explanation of example: the rti instruction pulls the 16-bit program counter (pc) and the 16-bit status register (sr) from the system stack and updates the system stack pointer (sp). rti return from interrupt rti f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 267 condition codes: s ? set according to the value pulled from the stack l ? set according to the value pulled from the stack e ? set according to the value pulled from the stack u ? set according to the value pulled from the stack n ? set according to the value pulled from the stack z ? set according to the value pulled from the stack v ? set according to the value pulled from the stack c ? set according to the value pulled from the stack instruction format: rti opcode: instruction fields: none timing: 4+rx oscillator clock cycles memory: 1 program word rti return from interrupt rti mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 16 15 8 7 0 000000000000000000000100 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 268 instruction set details motorola operation: assembler syntax: ssh t pc; spe1 t sp rts description: pull the program counter (pc) from the system stack. the previous pro- gram counter is lost. the status register (sr) is not affected. restrictions: due to pipelining in the program controller and the fact that the rts instruction accesses certain controller registers, the rts instruction must not be immedi- ately preceded by any of the following instructions: immediately before rts movec to ssh, ssl, or sp movem to ssh, ssl, or sp movep to ssh, ssl, or sp movec from ssh movem from ssh movep from ssh an rts instruction cannot be the last instruction in a do loop (at la). an rts instruction cannot be repeated using the rep instruction. example: : rts ;pull pc from system stack : explanation of example: the rts instruction pulls the 16-bit program counter (pc) from the system stack and updates the system stack pointer (sp). condition codes: the condition codes are not affected by this instruction. rts return from subroutine rts mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 269 instruction format: rti opcode: instruction fields: none timing: 4+rx oscillator clock cycles memory: 1 program word rts return from subroutine rts 23 16 15 8 7 0 000000000000000000001100 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 270 instruction set details motorola operation: assembler syntax: desec t d (parallel move) sbc s,d (parallel move) description: subtract the source operand s and the carry bit c of the condition code register from the destination operand d and store the result in the destination accumula- tor. long words (48 bits) may be subtracted from the (56-bit) destination accumulator. note: the carry bit is set correctly for multiple-precision arithmetic using long-word oper- ands if the extension register of the destination accumulator (a2 or b2) is the sign exten- sion of bit 47 of the destination accumulator (a or b). example: : move l:<$0,x ;get a 48-bit ls long-word operand in x move l:<$1,a ;get other ls long word in a (sign ext.) move l:<$2,y ;get a 48-bit ms long-word operand in y sub x,a l:<$3,b ;sub. ls words; get other ms word in b sbc yb a10,l:<$4 ;sub. ms words with carry; save ls dif. move b10,l:<$5 ;save ms difference : sbc subtract long with carry sbc before execution after execution a $00:000000:000000 x x $800000:000000 $800000:000000 $00:800000:000000 a b b $00:000000:000003 $00:000000:000001 y y $000000:000001 $000000:000001 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 271 explanation of example: this example illustrates long-word double-precision (96-bit) subtraction using the sbc instruction. prior to execution of the sub and sbc instruc- tions, the 96-bit value $000000:000001:800000:000000 is loaded into the y and x regis- ters (x:y), respectively. the other double-precision 96-bit value $000000:000003:000000:000000 is loaded into the b and a accumulators (b:a), respec- tively. since the 48-bit value loaded into the a accumulator is automatically sign extended to 56 bits and the other 48-bit long-word operand is internally sign extended to 56 bits during instruction execution, the carry bit will be set correctly after the execution of the sub x,a instruction. the sbc y,b instruction then produces the correct ms 56-bit result. the actual 96-bit result is stored in memory using the a10 and b10 operands (instead of a and b) because shifting and limiting is not desired. sbc subtract long with carry sbc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 272 instruction set details motorola condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z ? set if a or b result equals zero v ? set if overflow has occurred in a or b result c ? set if a carry (or borrow) occurs from bit 55 of a or b result note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 condition code computation for complete details. sbc subtract long with carry sbc mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 sl eunz vc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 273 instruction format: sbc s,d opcode: instruction fields: s,d j d x,a 0 0 x,b 0 1 y,a 1 0 y,b 1 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words 23 8 7 4 3 0 data bus move field 001j d101 optional effective address extension sbc subtract long with carry sbc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 274 instruction set details motorola operation: assembler syntax: enter the stop processing state and stop stop the clock oscillator description: enter the stop processing state. all activity in the processor is suspended until the reset or irqa pin is asserted. the clock oscillator is gated off internally. the stop processing state is a low-power standby state. during the stop state, port a is in an idle state with the control signals held inactive (i.e., rd =wr =v cc etc.), the data pins (d0ed23) are high impedance, and the address pins (a1ea15) are unchanged from the previous instruction. if the bus grant was asserted when the stop instruction was executed, port a will remain three-stated until the dsp exits the stop state. if the exit from the stop state was caused by a low level on the reset pin, then the processor will enter the reset processing state. the time to recover from the stop state using reset will depend on the oscillator used. consult the dsp56001 advance infor- mation data sheet (adi1290) for details. if the exit from the stop state was caused by a low level on the irqa pin, then the pro- cessor will service the highest priority pending interrupt and will not service the irqa interrupt unless it is highest priority. the interrupt will be serviced after an internal delay counter counts 65,536 clock cycles (or a three clock cycle delay if the stop delay bit in the omr is set to one) plus 17t (see the dsp56001 technical data sheet (adi1290) for details). during this clock stabilization count delay, all peripherals and external interrupts are cleared and re-enabled/arbitrated at the start of the 17t period following the count interval. the processor will resume program execution at the instruction following the stop instruction that caused the entry into the stop state after the interrupt has been serviced or, if no interrupt was pending, immediately after the delay count plus 17t. if the irqa pin is asserted when the stop instruction is executed, the clock will not be gated off, and the internal delay counter will be started. stop stop instruction processing stop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 275 restrictions: a stop instruction cannot be used in a fast interrupt routine. a stop instruction cannot be the last instruction in a do loop (i.e., at la). a stop instruction cannot be repeated using the rep instruction. example: : stop ;enter low-power standby mode : explanation of example: the stop instruction suspends all processor activity until the processor is reset or interrupted as previously described. the stop instruction puts the processor in a low-power standby state. condition codes: the condition codes are not affected by this instruction. instruction format: stop opcode: instruction fields: none timing: the stop instruction disables the internal clock oscillator and internal distribu- tion of the external clock. memory: 1 program word mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c stop stop instruction processing stop 23 16 15 8 7 0 000000000000000010000111 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 276 instruction set details motorola operation: assembler syntax: des t d (parallel move) sub s,d (parallel move) description: subtract the source operand s from the destination operand d and store the result in the destination operand d. words (24 bits), long words (48 bits), and accu- mulators (56 bits) may be subtracted from the destination accumulator. note: the carry bit is set correctly using word or long-word source operands if the exten- sion register of the destination accumulator (a2 or b2) is the sign extension of bit 47 of the destination accumulator (a or b). the carry bit is always set correctly using accumu- lator source operands. example: : sub x1,a x:(r2)+n2,r0 ;24-bit subtract, load r0, update r2 : explanation of example: prior to execution, the 24-bit x1 register contains the value $000003, and the 56-bit a accumulator contains the value $00:000058:242424. the sub instruction automatically appends the 24-bit value in the x1 register with 24 ls zeros, sign extends the resulting 48-bit long word to 56 bits, and subtracts the result from the 56-bit a accumulator. thus, 24-bit operands are subtracted from the msp portion of a or b (a1 or b1) because all arithmetic instructions assume a fractional, twos comple- ment data representation. note that 24-bit operands can be subtracted from the lsp por- tion of a or b (a0 or b0) by loading the 24-bit operand into x0 or y0, forming a 48-bit word by loading x1 or y1 with the sign extension of x0 or y0, and executing a sub x,a or sub y,a instruction. sub subtract sub before execution after execution x1 $000003 a a $00:000058:242424 $00:000055:242424 $000003 x1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 277 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z ? set if a or b result equals zero v ? set if overflow has occurred in a or b result c ? set if a carry (or borrow) occurs from bit 55 of a or b result note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 condition code computation for complete details. instruction format: sub s,d opcode: instruction fields: s,d j j j d s,d j j j d s,d j j j d b,a 0 0 1 0 x0,a 1 0 0 0 y1,a 1 1 1 0 a,b 0 0 1 1 x0,b 1 0 0 1 y1,b 1 1 1 1 x,a 0 1 0 0 y0,a 1 0 1 0 x,b 0 1 0 1 y0,b 1 0 1 1 y,a 0 1 1 0 x1,a 1 1 0 0 y,b 0 1 1 1 x1,b 1 1 0 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words sub subtract sub mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 sl eunz vc 23 8 7 4 3 0 data bus move field 0jjj d100 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 278 instruction set details motorola operation: assembler syntax: 2 * des t d (parallel move) subl s,d (parallel move) description: subtract the source operand s from two times the destination operand d and store the result in the destination accumulator. the destination operand d is arith- metically shifted one bit to the left, and a zero is shifted into the ls bit of d prior to the subtraction operation. the carry bit is set correctly if the source operand does not over- flow as a result of the left shift operation. the overflow bit may be set as a result of either the shifting or subtraction operation (or both). this instruction is useful for efficient divide and decimation in time (dit) fft algorithms. example: : subl a,b y:(r5+n5),r7 ;2 * bea t b, load r7, no r5 update : explanation of example: prior to execution, the 56-bit a accumulator contains the value $00:004000:000000, and the 56-bit b accumulator contains the value $00:005000:000000. the subl a,b instruction subtracts the value in the a accumulator from two times the value in the b accumulator and stores the 56-bit result in the b accu- mulator. subl shift left and subtract accumulators subl before execution after execution a $00:004000:000000 b b $00:005000:000000 $00:006000:000000 $00:004000:000000 a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 279 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z ? set if a or b result equals zero v ? set if overflow has occurred in a or b result or if the ms bit of the destination operand is changed as a result of the instruction?s left shift c ? set if a carry (or borrow) occurs from bit 55 of a or b result note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 condition code computation for complete details. instruction format: subl s,d opcode: instruction fields: s,d d b,a 0 a,b 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 sl eunz vc subl shift left and subtract accumulators subl 23 8 7 4 3 0 data bus move field 0001 d110 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 280 instruction set details motorola operation: assembler syntax: d/2es t d (parallel move) subr s,d (parallel move) description: subtract the source operand s from one-half the destination operand d and store the result in the destination accumulator. the destination operand d is arith- metically shifted one bit to the right while the ms bit of d is held constant prior to the sub- traction operation. in contrast to the subl instruction, the carry bit is always set correctly, and the overflow bit can only be set by the subtraction operation, and not by an overflow due to the initial shifting operation. this instruction is useful for efficient divide and decimation in time (dit) fft algorithms. example: : subr b,a n5,y:e(r5) ;a/2eb t a, update r5, save n5 : explanation of example: prior to execution, the 56-bit a accumulator contains the value $80:000000:2468ac, and the 56-bit b accumulator contains the value $00:000000:123456. the subr b,a instruction subtracts the value in the b accumulator from one-half the value in the a accumulator and stores the 56-bit result in the a accu- mulator. subr shift right and subtract accumulators subr before execution after execution a $80:000000:2468ac b b $00:000000:123456 $00:000000:123456 $c0:000000:000000 a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 281 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if limiting (parallel move) or overflow has occurred in result e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z ? set if a or b result equals zero v ? set if overflow has occurred in a or b result c ? set if a carry (or borrow) occurs from bit 55 of a or b result note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 condition code computation for complete details. instruction format: subr s,d opcode: instruction fields: s,d d b,a 0 a,b 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 sl eunz vc subr shift right and subtract accumulators subr 23 8 7 4 3 0 data bus move field 0000 d110 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 282 instruction set details motorola operation: assembler syntax: begin swi exception processing swi description: suspend normal instruction execution and begin swi exception process- ing. the interrupt priority level (i1,i0) is set to 3 in the status register (sr) if a long inter- rupt service routine is used. restrictions: an swi instruction cannot be used in a fast interrupt routine. an swi instruction cannot be repeated using the rep instruction. example: : swi ;begin swi exception processing : explanation of example: the swi instruction suspends normal instruction execution and initiates swi exception processing. swi software interrupt swi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 283 condition codes: the condition codes are not affected by this instruction. instruction format: swi opcode: instruction fields: none timing: 8 oscillator clock cycles memory: 1 program word mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 s l e u n z v c swi software interrupt swi 23 16 15 8 7 0 000000000000000000000110 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 284 instruction set details motorola operation: assembler syntax: if cc, then s1 t d1 tcc s1,d1 if cc, then s1 t d1 and s2 t d2 tcc s1,d1 s2,d2 description: transfer data from the specified source register s1 to the specified desti- nation accumulator d1 if the specified condition is true. if a second source register s2 and a second destination register d2 are also specified, transfer data from address reg- ister s2 to address register d2 if the specified condition is true. if the specified condition is false, a nop is executed. the term cc?? may specify the following conditions: cc?? mnemonic condition cc (hs) ? carry clear (higher or same) c=0 cs (lo) ? carry set (lower) c=1 ec ? extension clear e=0 eq ? equal z=1 es ? extension set e=1 ge ? greater than or equal n ? v=0 gt ? greater than z+(n ? v)=0 lc ? limit clear l=0 le ? less than or equal z+(n ? v)=1 ls ? limit set l=1 lt ? less than n ? v=1 mi ? minus n=1 ne ? not equal z=0 nr ? normalized z+(u e )=1 pl ? plus n=0 nn ? not normalized z+(u e )=0 where u denotes the logical complement of u, + denotes the logical or operator, denotes the logical and operator, and ? denotes the logical exclusive or operator when used after the cmp or cmpm instructions, the tcc instruction can perform many useful functions such as a maximum value, minimum value, maximum absolute value, or minimum absolute value function. the desired value is stored in the destina- tcc transfer conditionally tcc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 285 tion accumulator d1. if address register s2 is used as an address pointer into an array of data, the address of the desired value is stored in the address register d2. the tcc instruction may be used after any instruction and allows efficient searching and sorting algorithms. the tcc instruction uses the internal data alu paths and internal address alu paths. the tcc instruction does not affect the condition code bits. note: this instruction is considered to be a move-type instruction. due to instruction pipelining, if an agu register (mn, nn, or rn) is directly changed with this instruction, the new contents may not be available for use until the second following instruction. see the restrictions discussed in a.9.6 - r, n, and m register restrictions on page a-page 310. example: : cmp x0,a ;compare x0 and a (sort for minimum) tgt x0,a r0,r1 ;transfer x0 t a and r0 t r1 if x0 instruction descriptions a - 286 instruction set details motorola instruction format: tcc s1,d1 opcode: instruction fields: cc=4=bit condition code=cccc s1,d1 j j j d mnemonic c c c c mnemonic c c c c b,a 0 0 0 0 cc (hs) 0 0 0 0 cs (lo) 1 0 0 0 a,b 0 0 0 1 ge 0 0 0 1 lt 1 0 0 1 x0,a 1 0 0 0 ne 0 0 1 0 eq 1 0 1 0 x0,b 1 0 0 1 pl 0 0 1 1 mi 1 0 1 1 x1,a 1 1 0 0 nn 0 1 0 0 nr 1 1 0 0 x1,b 1 1 0 1 ec 0 1 0 1 es 1 1 0 1 y0,a 1 0 1 0 lc 0 1 1 0 ls 1 1 1 0 y0,b 1 0 1 1 gt 0 1 1 1 le 1 1 1 1 y1,a 1 1 1 0 y1,b 1 1 1 1 timing: 2 oscillator clock cycles memory: 1 program word 23 16 15 8 7 0 00000010cccc00000jjjd000 tcc transfer conditionally tcc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 287 instruction format: tcc s1,d1 s2,d2 opcode: instruction fields: cc=4=bit condition code=cccc s1,d1 jjjd s2 t t t mnemonic c c c c mnemonic c c c c b,a 0 0 0 0 rn n n n cc (hs) 0 0 0 0 cs (lo) 1 0 0 0 a,b 0 0 0 1 ge 0 0 0 1 lt 1 0 0 1 x0,a 1 0 0 0 ne 0 0 1 0 eq 1 0 1 0 x0,b 1 0 0 1 pl 0 0 1 1 mi 1 0 1 1 x1,a 1 1 0 0 d2 ttt nn 0 1 0 0 nr 1 1 0 0 x1,b 1 1 0 1 rn n n n ec 0 1 0 1 es 1 1 0 1 y0,a 1 0 1 0 lc 0 1 1 0 ls 1 1 1 0 y0,b 1 0 1 1 gt 0 1 1 1 le 1 1 1 1 y1,a 1 1 1 0 y1,b 1 1 1 1 where nnn??=rn number (r0er7) timing: 2 oscillator clock cycles memory: 1 program word 23 16 15 8 7 0 00000011cccc0tt t 0jjjdttt tcc transfer conditionally tcc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 288 instruction set details motorola operation: assembler syntax: s t d (parallel move) tfr s,d (parallel move) description: transfer data from the specified source data alu register s to the speci- fied destination data alu accumulator d. tfr uses the internal data alu data paths; thus, data does not pass through the data shifter/limiters. this allows the full 56-bit con- tents of one of the accumulators to be transferred into the other accumulator without data shifting and/or limiting. moreover, since tfr uses the internal data alu data paths, parallel moves are possible. the tfr instruction only affects the l condition code bit which can be set by data limiting associated with the instruction?s parallel move opera- tions. example: : tfr a,b a,x1 y:(r4+n4),y0 ;move a to b and x1, update y0 : explanation of example: prior to execution, the 56-bit a accumulator contains the value $01:234567:89abcd, and the 56-bit b accumulator contains the value $ff:ffffff:ffffff. the execution of the tfr a,b instruction moves the 56-bit value in the a accumulator into the 56-bit b accumulator using the internal data alu data paths without any data shifting and/or limiting. the value in the b accumulator would have been limited if a move a,b instruction had been used. note, however, that the parallel move portion of the tfr instruction does use the data shifter/limiters. thus, the value stored in the 24-bit x1 register (not shown) would have been limited in this example. this example illustrates a triple move instruction. tfr transfer data alu register tfr before execution after execution a $01:234567:89abcd b b $ff:ffffff:ffffff $01:234567:89abcd $01:234567:89abcd a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 289 condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move instruction format: tfr s,d opcode: instruction fields: s,d j j j d b,a 0 0 0 0 a,b 0 0 0 1 x0,a 1 0 0 0 x0,b 1 0 0 1 x1,a 1 1 0 0 x1,b 1 1 0 1 y0,a 1 0 1 0 y0,b 1 0 1 1 y1,a 1 1 1 0 y1,b 1 1 1 1 timing: 2+mv oscillator clock cycles memory: 1+mv program words mr ccr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lf dm t ** s1 s0 i1 i0 sl eu n z v c tfr transfer data alu register tfr 23 8 7 4 3 0 data bus move field 0jjj d001 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 290 instruction set details motorola operation: assembler syntax: se0 (parallel move) tst s (parallel move) description: compare the specified source accumulator s with zero and set the condi- tion codes accordingly. no result is stored although the condition codes are updated. example: : tst a #$345678,b ;set ccr bits for value in a, update b : explanation of example: prior to execution, the 56-bit a accumulator contains the value $01:020304:000000, and the 16-bit condition code register contains the value $0300. the execution of the tst a instruction compares the value in the a register with zero and updates the condition code register accordingly. the contents of the a accumu- lator are not affected. condition codes: s ? computed according to the definition in a.5 condition code computation l ? set if data limiting has occurred during parallel move e ? set if the signed integer portion of a or b result is in use u ? set if a or b result is unnormalized n ? set if bit 55 of a or b result is set z ? set if a or b result equals zero v ? always cleared note: the definitions of the e and u bits vary according to the scaling mode being used. refer to section a.5 condition code computation for complete details. tst test accumulator tst before execution after execution a $01:020304:000000 ccr ccr $0300 $0330 $01:020304:000000 a mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 sl eunz v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 291 instruction format: tst s opcode: instruction fields: sd a0 b1 timing: 2+mv oscillator clock cycles memory: 1+mv program words tst test accumulator tst 23 8 7 4 3 0 data bus move field 0000 d011 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions a - 292 instruction set details motorola operation: assembler syntax: disable clocks to the processor core and wait enter the wait processing state. description: enter the wait processing state. the internal clocks to the processor core and memories are gated off, and all activity in the processor is suspended until an unmasked interrupt occurs. the clock oscillator and the internal i/o peripheral clocks remain active. if wait is executed when an interrupt is pending, the interrupt will be pro- cessed; the effect will be the same as if the processor never entered the wait state and three nops followed the wait instruction. when an unmasked interrupt or external (hardware) processor reset occurs, the processor leaves the wait state and begins exception processing of the unmasked interrupt or reset condition. the br/bg circuits remain active during the wait state. the wait state is a low-power standby state. the processor always leaves the wait state in the t2 clock phase (see the dsp56001 advance information data sheet (adi1290)). therefore, multiple processors may be synchronized by having them all enter the wait state and then interrupting them with a common interrupt. restrictions: a wait instruction cannot be used in a fast interrupt routine. a wait instruction cannot be the last instruction in a do loop (at la). a wait instruction cannot be repeated using the rep instruction. example: : wait ;enter low power mode, wait for interrupt : explanation of example: the wait instruction suspends normal instruction execution and waits for an unmasked interrupt or external reset to occur. wait wait for interrupt wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction descriptions motorola instruction set details a - 293 condition codes: the condition codes are not affected by this instruction. instruction format: wait opcode: instruction fields: none timing: the wait instruction takes a minimum of 16 cycles to execute when an internal interrupt is pending during the execution of the wait instruction memory: 1 program word mr ccr 1 514131211109 876 54 32 10 lf dm t ** s1 s0 i1 i0 s l e u n z v c wait wait for interrupt wait 23 16 15 8 7 0 000000000000000010000110 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction timing a - 294 instruction set details motorola a.8 instruction timing this section describes how to calculate dsp56k instruction timing manually using the tables provided. three complete examples illustrate the layered nature of the tables. alternatively, the user can determine the number of instruction program words and the number of oscillator clock cycles required for a given instruction by using the dsp56k simulator. this method of determining instruction timing information is much faster and much simpler than using the tables. this powerful software package is available for the ibm * ? pc and sun workstation. ? table a-6 gives the number of instruction program words and the number of oscillator clock cycles for each instruction mnemonic. ? table a-7 gives the number of additional (if any) instruction words and additional (if any) clock cycles for each type of parallel move operation. ? table a-8 gives the number of additional (if any) clock cycles for each type of movec operation. ? table a-9 gives the number of additional (if any) clock cycles for each type of movep operation. ? table a-10 gives the number of additional (if any) clock cycles for each type of bit manipulation (bchg, bclr, bset, and btst) operation. ? table a-11 gives the number of additional (if any) clock cycles for each type of jump (jcc, jclr, jmp, jscc, jsclr, jset, jsr, and jsset) operation. ? table a-12 gives the number of additional (if any) clock cycles for the rti and rts instructions. ? table a-13 gives the number of additional (if any) instruction words and additional (if any) clock cycles for each effective addressing mode. ? table a-14 gives the number of additional (if any) clock cycles for external data, external program, and external i/o memory accesses. the number of words per instruction is dependent on the addressing mode and the type of parallel data bus move operation specified. the symbols used reference subsequent tables to complete the instruction word count. the number of oscillator clock cycles per instruction is dependent on many factors, *ibm is a trademark of international business machines. sun is a trademark of sun microsystems, inc. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction timing motorola instruction set details a - 295 including the number of words per instruction, the addressing mode, whether the instruc- tion fetch pipe is full or not, the number of external bus accesses, and the number of wait states inserted in each external access. the symbols used reference subsequent tables to complete the execution clock cycle count. all tables are based on the following assumptions: 1. all instruction cycles are counted in oscillator clock cycles . 2. the instruction fetch pipeline is full . 3. there is no contention for instruction fetches. thus, external program instruc- tion fetches are assumed not to have to contend with external data memory accesses. 4. there are no wait states for instruction fetches done sequentially (as for non- change-of-flow instructions), but they are taken into account for change-of-flow instructions which flush the pipeline such as jmp, jcc, rti, etc. to help the user better understand and use the timing tables, the following three exam- ples illustrate the tables layered nature. (remember that it is faster and simpler to use the dsp56k simulator to calculate instruction timing.) example 16: arithmetic instruction with two parallel moves problem: calculate the number of 24-bit instruction program words and the number of oscillator clock cycles required for the instruction macr Cx0,x0,a x1,x:(r6)C y0,y:(r0)+ where operating mode register (omr) = $02 (normal expanded memory map), bus control register (bcr) = $1135, r6 address register = $0052 (internal x memory), and r0 address register = $0523 (external y memory). solution: to determine the number of instruction program words and the number of oscillator clock cycles required for the given instruction, the user should perform the fol- lowing operations: 1. look up the number of instruction program words and the number of oscillator clock cycles required for the opcode-operand portion of the instruction in table a-6. according to table a-6, the macr instruction will require (1+mv) instruction program words and will execute in (2+mv) oscillator clock cycles. the term mv represents the additional (if any) instruction program words and the additional (if any) oscillator clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction timing a - 296 instruction set details motorola cycles that may be required over and above those needed for the basic macr instruc- tion due to the parallel move portion of the instruction. 2. evaluate the mv term using table a-7. the parallel move portion of the macr instruction consists of an xy memory move. according to table a-7, the parallel move portion of the instruction will require mv=0 additional instruction program words and mv=(ea+axy) additional oscillator clock cycles. the term ea represents the number of additional (if any) oscillator clock cycles that are required for the effective addressing move specified in the parallel move portion of the instruction. the term axy represents the number of additional (if any) oscillator clock cycles that are required to access an xy memory operand. 3. evaluate the ea term using table a-13. the parallel move portion of the macr instruction consists of an xy memory move which uses both address register banks (r0Cr3 and r4Cr7) in generating the effective addresses of the xy memory operands. thus, the two effective address operations occur in parallel, and the larger of the two ea terms should be used. the x memory move operation uses the postdecrement by 1 effective addressing mode. according to table a-13, this operation will require ea=0 additional oscillator clock cycles. the y memory move operation uses the postincrement by 1 effective addressing mode. according to table a-13, this operation will also require ea=0 additional oscillator clock cycles. thus, using the maximum value of ea, the effective addressing modes used in the parallel move portion of the macr instruction will require ea=0 additional oscillator clock cycles. 4. evaluate the axy term using table a-14. the parallel move portion of the macr instruction consists of an xy memory move. according to table a-14, the term axy depends upon where the referenced x and y memory locations are located in the dsp56k memory space. external memory accesses require additional oscillator clock cycles according to the number of wait states programmed into the dsp56k bus control register (bcr). thus, assuming that the 16-bit bus control register contains the value $1135, external x memory accesses require wx=1 w ait state of additional oscillator clock cycle while external y memory accesses require wy=1 w ait state or additional oscillator clock cycle. for this example, the x memory refer- ence is assumed to be an internal reference; the y memory reference is assumed to be an external reference. thus, according to table a-14, the xy memory reference in the parallel move portion of the macr instruction will require axy=wy=1 additional oscillator clock cycle. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction timing motorola instruction set details a - 297 5. compute final results. thus, based upon the assumptions given for table a-6 and those listed in the problem statement for example 1, the instruction macr Cx0,x0,a x1,x:(r6)C y0,y:(r0)+ will require (1+mv) = (1+0) = 1 instruction program word and will execute in = (2+mv) = (2+ea+axy) = (2+ea+wy) = (2+0+1) oscillator clock cycles. =3 note that if a similar calculation were to be made for a movec, movem, movep, or one of the bit manipulation (bchg, bclr, bset, or btst) instructions, the use of table a-7 would no longer be appropriate. for one of these cases, the user would refer to table a-8, table a-9, or table a-10, respectively. example 17: jump instruction problem: calculate the number of 24-bit instruction program words and the number of oscillator clock cycles required for the instruction jlc (r2+n2) where operating mode register (omr) = $02 (normal expanded memory map), bus control register (bcr) = $2246, r2 address register = $1000 (external p memory), and n2 address register = $0037. solution: to determine the number of instruction program words and the number of oscillator clock cycles required for the given instruction, the user should perform the fol- lowing operations: 1. look up the number of instruction program words and the number of oscillator clock cycles required for the opcode-operand portion of the instruction in table a-6. according to table a-6, the jcc instruction will require (1+ea) instruction program words and will execute in (4+jx) oscillator clock cycles. the term ea represents the number of f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction timing a - 298 instruction set details motorola additional (if any) instruction program words that are required for the effective address of the jcc instruction. the term jx represents the number of additional (if any) oscillator clock cycles required for a jump-type instruction. 2. evaluate the jx term using table a-11. according to table a-11, the jcc instruction will require jx=ea+(2 * ap) additional oscilla- tor clock cycles. the term ea represents the number of additional (if any) oscillator clock cycles that are required for the e ffective a ddressing mode specified in the jcc instruction. the term ap represents the number of additional (if any) oscillator clock cycles that are required to a ccess a p memory operand. note that the +(2 * ap) term represents the two program memory instruction fetches executed at the end of a one- word jump instruction to refill the instruction pipeline. 3. evaluate the ea term using table a-13. the jlc (r2+n2) instruction uses the indexed by offset nn effective addressing mode. according to table a-13, this operation will require ea=0 additional instruction program words and ea=2 additional oscillator clock cycles. 4. evaluate the ap term using table a-14. according to table a-14, the term ap depends upon where the referenced p memory location is located in the dsp56k memory space. external memory accesses require additional oscillator clock cycles according to the number of wait states programmed into the dsp56k bus control register (bcr). thus, assuming that the 16-bit bus control regis- ter contains the value $2246, external p memory accesses require wp=4 w ait states or additional oscillator clock cycles. for this example, the p memory reference is assumed to be an external reference. thus, according to table a-14, the jcc instruction will use the value ap=wp=4 oscillator clock cycles. 5. compute final results. thus, based upon the assumptions given for table a-6 and those listed in the problem statement for example 2, the instruction f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction timing motorola instruction set details a - 299 jlc (r2+n2) will require = (1+ea) = (1+0) = 1 instruction program word and will execute in = (4+jx) = (4+ea+(2 * ap)) = (4+ea+(2 * wp)) = (4+2+(2 * 4)) oscillator clock cycles. =14 example 18: rti instruction problem: calculate the number of 24-bit instruction program words and the number of oscillator clock cycles required for the instruction rti where operating mode register (omr) = 02 (normal expanded memory map), bus control register (bcr) = $0012, and, return address (on the stack) = $0100 (internal p memory). solution: to determine the number of instruction program words and the number of oscillator clock cycles required for the given instruction, the user should perform the fol- lowing operations: 1. look up the number of instruction program words and the number of oscillator clock cycles required for the opcode-operand portion of the instruction in table a-6. according to table a-6, the rti instruction will require one instruction program word and will execute in (4+rx) oscillator clock cycles. the term rx represents the number of addi- tional (if any) oscillator clock cycles required for an rti or rts instruction. 2. evaluate the rx term using table a-12. according to table a-12, the rti instruction will require rx=(2 * ap) additional oscillator clock cycles. the term ap represents the number of additional (if any) oscillator clock cycles that are required to access a p memory operand. note that the term (2 * ap) rep- resents the two program memory instruction fetches executed at the end of an rti or rts instruction to refill the instruction pipeline. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction timing a - 300 instruction set details motorola 3. evaluate the ap term using table a-14. according to table a-14, the term ap depends upon where the referenced p memory location is located in the dsp56k memory space. external memory accesses require additional oscillator clock cycles according to the number of wait states programmed into the dsp56k bus control register (bcr). thus, assuming that the 16-bit bus control regis- ter contains the value $0012, external p memory accesses require wp=1 w ait state or additional oscillator clock cycles. for this example, the p memory reference is assumed to be an internal reference. this means that the return address ($0100) pulled from the system stack by the rti instruction is in internal p memory. thus, according to table a- 14, the rti instruction will use the value ap=0 additional oscillator clock cycles. 4. compute final results. thus, based upon the assumptions given for table a-6 and those listed in the problem statement for example 3, the instruction rti will require 1 instruction program word and will execute in (4+rx) = (4+(2 * ap)) = (4+(2 * 0)) = 4 oscillator clock cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction timing motorola instruction set details a - 301 note 1: the stop instruction disables the internal clock oscillator. after clock turn on, an internal counter counts 65,536 clock cycles (if bit 6 in the omr is clear) before enabling the clock to the internal dsp circuits. if bit 6 in the omr is set, only six clock cycles are counted before enabling the clock to the external dsp circuits. note 2: the wait instruction takes a minimum of 16 cycles to execute when an internal interrupt is pending during the execution of the wait instruction. note 3: if assumption 4 is not applicable, then to each one-word instruction timing, a +ap term should be added, and, to each two-word instruction, a +(2*ap) term should be added to account for the program memory wait states spent to fetch an instruction word to ?ll the pipeline. mnemonic instruction program words osc. clock cycles notes mnemonic instruction program words osc. clock cycles notes abs 1 + mv 2 + mv lsr 1 + mv 2 + mv adc 1 + mv 2 + mv lua 1 4 add 1 + mv 2 + mv mac 1 + mv 2 + mv addl 1 + mv 2 + mv macr 1 + mv 2 + mv addr 1 + mv 2 + mv move 1 + mv 2 + mv and 1 + mv 2 + mv movec 1 + ea 2 + mvc andi 1 2 movem 1 + ea 6 + ea + ap asl 1 + mv 2 + mv movep 1 + ea 2 + mvp asr 1 + mv 2 + mv mpy 1 + mv 2 + mv bchg 1 + ea 4 + mvb mpyr 1 + mv 2 + mv bclr 1 + ea 4 + mvb neg 1 + mv 2 + mv bset 1 + ea 4 + mvb nop 1 2 btst 1 + ea 4 + mvb norm 1 2 clr 1 + mv 2 + mv not 1 + mv 2 + mv cmp 1 + mv 2 + mv or 1 + mv 2 + mv cmpm 1 + mv 2 + mv ori 1 2 debug 1 4 rep 1 4 + mv debugcc 1 4 reset 1 4 dec 1 2 rnd 1 + mv 2 + mv div 1 2 rol 1 + mv 2 + mv do 2 6 + mv ror 1 + mv 2 + mv enddo 1 2 rti 1 4 + rx eor 1 + mv 2 + mv rts 1 4 + rx inc 1 2 sbc 1 + mv 2 + mv jcc 1 + ea 4 + jx stop 1 n/a 1 jclr 2 6 + jx sub 1 + mv 2 + mv jmp 1 + ea 4 + jx subl 1 + mv 2 + mv jscc 1 + ea 4 + jx subr 1 + mv 2 + mv jsclr 2 6 + jx swi 1 8 jset 2 6 + jx tcc 1 2 jsr 1 + ea 4 + jx tfr 1 + mv 2 + mv jsset 2 6 + jx tst 1 + mv 2 + mv lsl 1 + mv 2 + mv wait 1 n/a 2 table a-6 instruction timing summary (see note 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction timing a - 302 instruction set details motorola parallel move operation + mv words + mv cycles comments no parallel data move 0 0 i immediate short data 0 0 r register to register 0 0 u address register update 0 0 x: x memory move ea ea + ax see note 1 x:r x memory and register ea ea + ax see note 1 y: y memory move ea ea + ay see note 1 r:y y memory and register ea ea + ay see note 1 l: long memory move ea ea + axy x:y: xy memory move 0 ea + axy lms(x) lms x memory moves 0 ea + ax see notes 1,2 lms(y) lms y memory moves 0 ea + ay see notes 1,2 table a-7 parallel data move timing note 1: the ax or ay term does not apply to move immediate data. note 2: the ea term does not apply to absolute address and immediate data. movec operation + mvc cycles comments immediate short ? register 0 register t register 0 x memory t register ea + ax see note 1 y memory t register ea + ay see note 1 p memory t register 4 + ea + ap table a-8 movec timing summary (see note 2) note 1: the ax or ay term does not apply to move immediate data. note 2: if assumption 4 is not applicable, then to each one-word instruction timing, a + ap term should be added, and to each two-word instruction, a + (2 * ap) term should be added to account for the program memory wait states spent to fetch an instruction word to ?ll the pipeline. movep operation + mvp cycles comments register t peripheral aio see note 3 register t peripheral 2+aio see note 4 x memory t peripheral 2 + ea + ax + aio see note 1 y memory t peripheral 2 + ea + ay + aio see note 1 p memory t peripheral 4 + ea + ap + aio note 1: the 2+ax or 2+ay terms do not apply to move immediate data. note 2: if assumption 4 is not applicable, then to each one-word instruction timing,a + ap term should be added, and to each two-word instruction, a + (2 * ap) term should be added to account for the program memory wait states spent to fetch an instruction word to ?ll the pipeline. note 3: register refers to data_alu register note 4: register refers to non data_alu register table a-9 movep timing summary (see note 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction timing motorola instruction set details a - 303 note that the ap term in table a-8 and table a-9 for the p memory move represents the wait states spent when accessing the program memory during data read or write operations and does not refer to instruction fetches. all one-word jump instructions execute two program memory fetches to refill the pipe- line, which is represented by the +(2 * ap) term. all two-word jumps execute three program memory fetches to refill the pipeline, but one of those fetches is sequential (the instruction word located at the jump instruction 2nd word address+1), so it is not counted as per assumption 4. if the jump instruction was fetched from a program memory segment with wait states, another ap should be added to account for that third fetch. note 1: bxxx = bchg, bclr, or bset. note 2: if assumption 4 is not applicable, then to each one-word instruction timing, a + ap term should be added, and to each two-word instruction, a + (2 * ap) term should be added to account for the program memory wait states spent to fetch an instruction word to ?ll the pipeline. bit manipulation operation + mvb cycles comments bxxx periphera l 2 * aio see note 1 bxxx x memory ea + (2 * ax) see note 1 bxxx y memory ea + (2 * ay) see note 1 bxxx register direct 0 see note 1 btst peripheral aio btst x memory ea + ax btst y memory ea + ay table a-10 bit manipulation timing summary (see note 2) note 1: jbit = jclr, jsclr, jset, and jsset note 2: jxxx = jcc, jmp, jscc, and jsr jump instruction operation + jx cycles comments jbit register direct 2 * ap see note 1 jbit peripheral aio + (2 * ap) see note 1 jbit x memory ea + ax + (2 * ap) see note 1 jbit y memory ea + ay + (2 * ap) see note 1 jxxx ea + (2 * ap) see note 2 table a-11 jump instruction timing summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction timing a - 304 instruction set details motorola the term 2 * ap comes from the two instruction fetches done by the rti/rts instruc- tion to refill the pipeline. operation + rx cycles rti 2 * ap rts 2 * ap table a-12 rti/rts timing summary effective addressing mode + ea words + ea cycles address register indirect no update 0 0 postincrement by 1 0 0 postdecrement by 1 0 0 postincrement by offset nn 0 0 postdecrement by offset nn 0 0 indexed by offset nn 0 2 predecrement by 1 0 2 special immediate data 1 2 absolute address 1 2 immediate short data 0 0 short jump address 0 0 absolute sort address 0 0 i/o short address 0 0 implicit 0 0 table a-13 addressing mode timing summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction sequence restrictions motorola instruction set details a - 305 a.9 instruction sequence restrictions due to the pipelined nature of the dsp56k central processor, there are certain instruc- tion sequences that are forbidden and will cause undefined operation. most of these restricted sequences would cause contention for an internal resource, such as the stack register. the dsp assembler will flag these as assembly errors. most of the following restrictions represent very unusual operations which probably would never be used but are listed only for completeness. note: the dsp56k macro assembler is designed to recognize all restrictions and flag them as errors at the source code level. since many of these are instruction sequence restrictions, they cannot be flagged as errors at the object code level such as when using the dsp56k simulators single-line assembler. therefore, if any changes are made at the object code level using the simulator, the user should always re-assemble his pro- gram at the source code level using the dsp56k macro assembler to verify that no restricted instruction sequences have been generated. note 1: wx = external x memory access wait states wy = external y memory access wait states wp = external p memory access wait states wio = external i/o memory access wait states note 2: wx, wy, wp, and wio are programmable from 0 - 15 wait states in the port a bus control register (bcr). access type x mem access y mem access p mem access i/o access + ax cycle + ay cycle + ap cycle + aio cycle + axy cycle x: int 0 x: ext wx y: int 0 y: ext wy p: int 0 p: ext wp i/o: int 0 i/o: ex twio l: xy: int int 0 l: xy: int ext wy l: xy: ext int wx l: xy: ext ext 2 + wx + wy table a-14 memory access timing summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction sequence restrictions a - 306 instruction set details motorola a.9.1 restrictions near the end of do loops proper do loop operation is not guaranteed if an instruction starting at address laC2, laC1, or la specifies one of the program controller registers sr, sp, ssl, la, lc, or (implicitly) pc as a destination register. similarly, the ssh register may not be specified as a source or destination register in an instruction starting at address laC2, laC1, or la . additionally, the ssh register cannot be specified as a source register in the do instruction itself, and la cannot be used as a target for jumps to subroutine (i.e., jsr, jscc, jsset, or jsclr to la). the following instructions cannot begin at the indicated position(s) near the end of a do loop: at laC2, laC1, and la do bchg la, lc, sr, sp, ssh, or ssl bclr la, lc, sr, sp, ssh, or ssl bset la, lc, sr, sp, ssh, or ssl btst ssh jclr/jset/jsclr/jsset ssh movec from ssh movem from ssh movep from ssh movec to la, lc, sr, sp, ssh, or ssl movem to la, lc, sr, sp, ssh, or ssl movep to la, lc, sr, sp, ssh, or ssl andi mr ori mr at la any two-word instruction * jcc jmp jscc jsr rep reset rti rts stop wait *this restriction applies to the situation in which the dsp56k simulators single-line assembler is used to change the last instruction in a do loop from a one-word instruc- tion to a two-word instruction. all changes made using the simulator should be reassem- bled at the source code level using the dsp56k macro assembler to verify that no restricted instruction sequences have been generated. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction sequence restrictions motorola instruction set details a - 307 other restrictions do ssh,xxxx jsr to (la) whenever the loop flag (lf) is set jscc to (la) whenever the loop flag (lf) is set jsclr to (la) whenever the loop flag (lf) is set jsset to (la) whenever the loop flag (lf) is set note: due to pipelining, if an address register (r0Cr7, n0Cn7, or m0Cm7) is changed using a move-type instruction (lua, tcc, move, movec, movem, movep, or parallel move), the new contents of the destination address register will not be available for use during the following instruction (i.e., there is a single instruction cycle pipeline delay). this restriction also applies to the situation in which the last instruction in a do loop changes an address register and the first instruction at the top of the do loop uses that same address register. the top instruction becomes the following instruction because of the loop construct. the assembler will generate a warning if this condition is detected. a.9.2 other do restrictions due to pipelining, the do instruction must not be immediately preceded by any of the following instructions: immediately before do bchg la, lc, ssh, ssl, or sp bclr la, lc, ssh, ssl, or sp bset la, lc, ssh, ssl, or sp movec to la, lc, ssh, ssl, or sp movem to la, lc, ssh, ssl, or sp movep to la, lc, ssh, ssl, or sp movec from ssh movem from ssh movep from ssh a.9.3 enddo restrictions due to pipelining, the enddo instruction must not be immediately preceded by any of the following instructions: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction sequence restrictions a - 308 instruction set details motorola immediately before enddo bchg la, lc, sr, ssh, ssl, or sp bclr la, lc, sr, ssh, ssl, or sp bset la, lc, sr, ssh, ssl, or sp movec to la, lc, sr, ssh, ssl, or sp movem to la, lc, sr, ssh, ssl, or sp movep to la, lc, sr, ssh, ssl, or sp movec from ssh movem from ssh movep from ssh andi mr ori mr rep a.9.4 rti and rts restrictions due to pipelining, the rti and rts instructions must not be immediately preceded by any of the following instructions: immediately before rti bchg sr, ssh, ssl, or sp bclr sr, ssh, ssl, or sp bset sr, ssh, ssl, or sp movec to sr, ssh, ssl, or sp movem to sr, ssh, ssl, or sp movep to sr, ssh, ssl, or sp movec from ssh movem from ssh movep from ssh andi mr or andi ccr ori mr or ori ccr immediately before rts bchg ssh, ssl, or sp bclr ssh, ssl, or sp bset ssh, ssl, or sp movec to ssh, ssl, or sp movem to ssh, ssl, or sp movep to ssh, ssl, or sp movec from ssh movem from ssh movep from ssh a.9.5 sp and ssh/ssl manipulation restrictions in addition to all the above restrictions concerning movec, movem, movep, sp, ssh, and ssl, the following movec, movem, and movep restrictions apply: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction sequence restrictions motorola instruction set details a - 309 immediately before movec from ssh or ssl bchg to sp bclr to sp bset to sp immediately before movem from ssh or ssl bchg to sp bclr to sp bset to sp immediately before movep from ssh or ssl bchg to sp bclr to sp bset to sp immediately before movec from ssh or ssl movec to sp movem to sp movep to sp immediately before movem from ssh or ssl movec to sp movem to sp movep to sp immediately before movep from ssh or ssl movec to sp movem to sp movep to sp immediately before jclr #n,ssh or ssl,xxxx movec to sp movem to sp movep to sp immediately before jset #n,ssh or ssl,xxxx movec to sp movem to sp movep to sp immediately before jsclr #n,ssh or ssl,xxxx movec to sp movem to sp movep to sp immediately before jsset #n,ssh or ssl,xxxx movec to sp movem to sp movep to sp immediately before jclr #n,ssh or ssl,xxxx bchg to sp bclr to sp bset to sp immediately before jset #n,ssh or ssl,xxxx bchg to sp bclr to sp bset to sp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction sequence restrictions a - 310 instruction set details motorola immediately before jsclr from ssh or ssl,xxxx bchg to sp bclr to sp bset to sp immediately before jsset from ssh or ssl,xxxx bchg to sp bclr to sp bset to sp also, the instruction movec ssh,ssh is illegal. a.9.6 r, n, and m register restrictions due to pipelining, if an address register rn is the destination of a move-type instruction except movep (move, movec, movem, lua, tcc), the new contents will not be available for use as an address pointer until the second following instruction cycle . likewise, if an offset register nn or a modifier register mn is the destination of a move- type instruction except movep, the new contents will not be available for use in address calculations until the second following instruction cycle . however, if the processor is in the no update addressing mode (where mn and nn are ignored) and register mn or nn is the destination of a move instruction, the next instruc- tion may use the corresponding rn register as an address pointer. also, if the processor is in the postincrement by 1, postdecrement by 1, or predecrement by 1 addressing mode (where nn is ignored), a move to nn may be immediately followed by an instruc- tion that uses rn as an address pointer. note: this restriction also applies to the situation in which the last instruction in a do loop changes an address register using a move-type instruction and the first instruction at the top of the do loop uses that same address register. the top instruction becomes the following instruction because of the loop construct. the dsp assembler will gener- ate a warning if this condition is detected. a.9.7 fast interrupt routines the following instructions may not be used in a fast interrupt routine: in a fast interrupt routine do movem from ssh stop enddo movep from ssh swi rti ori mr or ori ccr wait rts andi mr or andi ccr movec to la, lc, ssh, ssl, sp, or sr movem to la, lc, ssh, ssl, sp, or sr movep to la, lc, ssh, ssl, sp, or sr movec from ssh f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 311 a.9.8 rep restrictions the rep instruction can repeat any single-word instruction except the rep instruction itself and any instruction that changes program flow. the following instructions are not allowed to follow an rep instruction: immediately after rep do jcc jclr jmp jset jscc jsclr jsr jsset rep rti rts stop swi wait enddo also, an rep instruction cannot be the last instruction in a do loop (at la). a.10 instruction encoding this section summarizes instruction encoding for the dsp56k instruction set. the instruction codes are listed in nominally descending order. the symbols used in decod- ing the various fields of an instruction are identical to those used in the opcode section of the individual instruction descriptions. the user should always refer to the actual instruction description for complete information on the encoding of the various fields of that instruction. section a.10.1 gives the encodings for (1) various groupings of registers used in the instruction encodings, (2) condition code combinations, (3) addressing, and (4) address- ing modes. section a.10.2 gives the encoding for the parallel move portion of an instruction. these 16-bit partial instruction codes may be combined with the 8-bit data alu opcodes listed in section a.10.3 to form a complete 24-bit instruction word. section a.10.3 gives the complete 24-bit instruction encoding for those instructions which do not allow parallel moves. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 312 instruction set details motorola section a.10.4 gives the encoding for the data alu portion of those instructions which allow parallel data moves. these 8-bit partial instruction codes may be combined with the 16-bit parallel move opcodes listed in section a.10.1 to form a complete 24-bit instruction word. a.10.1 partial encodings for use in instruction encoding * for class ii encodings for r:y and x:r, see table a-16 code d* e f where: 0 a x0 y0 d = 2 accumulators in data alu 1 b x1 y1 e = 2 registers in data alu f = 2 registers in data alu table a-15 single-bit register encodings d x:r class ii opcode r:y class ii opcode 0a t x: x0 t a y0 t a a t y: 1b t x: x0 t b y0 t b b t y: table a-16 single-bit special register encodings code dd ee ff 00 x0 x0 y0 01 x1 x1 y1 10 y0 a a 11 y1 b b where: dd = 4 registers in data alu ee = 4 xdb registers in data alu ff = 4 ydb registers in data alu table a-17 double-bit register encodings f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 313 code ddd lll fff nnn ttt ggg 000 a0 a10 m0 n0 r0 * 001 b0 b10 m1 n1 r1 sr 010 a2 x m2 n2 r2 omr 011 b2 y m3 n3 r3 sp 100 a1 a m4 n4 r4 ssh 101 b1 b m5 n5 r5 ssl 110 a ab m6 n6 r6 la 111 b bam7n7r7lc * reserved where: ddd: 8 accumulators in data alu lll: 8 extended-precision registers in data alu; lll ?eld is encoded as l0ll fff: 8 address modi?er registers in address alu nnn: 8 address offset registers in address alu ttt: 8 address registers in address fff: 8 program controller registers table a-18 triple-bit register encodings dddd description 0 0 x x reserved 0 1 d d data alu register 1 d d d data alu register table a-19(a) four-bit register encodings for 12 registers in data alu mnemonic c c c c mnemonic c c c c cc(hs) 0 0 0 0 cs(lo) 1 0 0 0 ge 0001 lt 1001 ne 0 0 1 0 eq 1 0 1 0 pl 0 0 1 1 mi 1 0 1 1 nn 0 1 0 0 nr 1 1 0 0 ec 0 1 0 1 es 1 1 0 1 lc 0 1 1 0 ls 1 1 1 0 gt 0 1 1 1 le 1 1 1 1 table a-19(b) four-bit register encodings for 16 condition codes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 314 instruction set details motorola eeeee or d d d d d description 0000x reserved 0 0 0 1 x reserved 0 0 1 d d data alu register 0 1 d d d data alu register 1 0 t t t address alu register 1 1 n n n address offset register where: eeeee = source ddddd = destination table a-20 five-bit register encodings for 28 registers in data alu and address alu d d d d d d description 000 0 xx reserved 000 1 dd data alu register 001 d dd data alu register 010 t t t address alu register 011 n nn address offset register 100 f f f address modi?er register 101 x xx reserved 110 x xx reserved 111 ggg program controller register table a-21 six-bit register encodings for 43 registers on-chip w operation 0 read register or periphera l 1 write register or peripheral table a-22 write control encoding s operation 0 x memory 1 y memory table a-23 memory space bit encoding f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 315 e e register 0 0 mr mode register 0 1 ccr condition code register 1 0 omr operating mode register 1 1 reserved table a-24 program control unit register encoding code code de?nition c c c c 16 condition code combinations b b b b b 5-bit immediate data i i i i i i i i 8-bit immediate data (int, frac, mask) i i i i i i i i x x x x h h h h 12-bit immediate data (iiii iiii hhhh) a a a a a a 6-bit absolute short (low) address p p p p p p 6-bit absolute i/o (high) address a a a a a a a a a a a a 12-bit fast absolute short (low) address table a-25 condition code and address encoding m2 m1 m0 r2 r1 r0 code de?nition 0 0 0 r r r post - n 0 0 1 r r r post + n 0 1 0 r r r post - 1 0 1 1 r r r post + 1 1 0 0 r r r no update 1 0 1 r r r indexed + n 1 1 1 r r r pre - 1 1 1 0 0 0 0 absolute address 1 1 0 1 0 0 immediate data mmm = three bits m2, m1, m0 determine mode rrr = three bits r2, r1, r0 determine which address register number where rrr refers to the binary representation of the number notes: (1) r2 is 0 for low register bank and 1 for the high register bank. (2) m2 is 0 for all post update modes and 1 otherwise. (3) m1 is 0 for update by register offset and no update and 1 otherwise. (4) m0 is 0 for minus and 1 for plus, except for predecrement which is also 1. (5) for x:y: parallel data moves, bits 14 and 13 of the opcode are a subset of the above rrr and are labelled rr. see the xy parallel data move description for a detailed explanation. (6) for x:y: parallel data moves, bits 21 and 20 of the opcode are a subset of the above mmm and are labelled mm. see the xy parallel data move description for a detailed explanation table a-25 effective addressing mode encoding f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 316 instruction set details motorola a.10.2 instruction encoding for the parallel move portion of an instruction x: y: parallel data move x: parallel data move y: parallel data move l: parallel data move i: immediate short parallel data move 23 16 15 8 7 0 1 w m m e e f f w r r m m r r r instruction opcode 23 16 15 8 7 0 0 1 d d 0 d d d w 1 m m m r r r instruction opcode optional effective address extension 23 16 15 8 7 0 01dd0ddd w0aaaaaa instruction opcode 23 16 15 8 7 0 0 1 d d 1 d d d w 1 m m m r r r instruction opcode optional effective address extension 23 16 15 8 7 0 01dd1ddd w0aaaaaa instruction opcode 23 16 15 8 7 0 0 1 0 0 l 0 l l w 1 m m m r r r instruction opcode optional effective address extension 23 16 15 8 7 0 0100l0ll w0aaaaaa instruction opcode 23 16 15 8 7 0 001ddddd iiiiiiii instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 317 r: register to register parallel data move u: address register update parallel data move parallel data move nop r:y parallel data move (class i) (class ii) x:r parallel data move (class i) (class ii) 23 16 15 8 7 0 001000ee eeeddddd instruction opcode 23 16 15 8 7 0 0 0 1 0 0 0 0 0 0 1 0 m m r r r instruction opcode 23 16 15 8 7 0 00100000 00000000 instruction opcode 23 16 15 8 7 0 0 0 0 1 d e f f w 1 m m m r r r instruction opcode optional effective address extension 23 16 15 8 7 0 optional effective address extension 0 0 0 0 1 0 0 d 1 0 m m m r r r instruction opcode 23 16 15 8 7 0 0 0 0 1 f f d f w 0 m m m r r r instruction opcode optional effective address extension 23 16 15 8 7 0 optional effective address extension 0 0 0 0 1 0 0 d 0 0 m m m r r r instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 318 instruction set details motorola a.10.3 instruction encoding for instructions which do not allow parallel moves note: for following bit class instructions bbbbb = 11bbb is reserved: jsset, jsclr, jset, jclr, btst, bchg, bset, and bclr. jscc xxx jcc xxx jsr xxx jmp xxx jscc ea jsr ea jcc ea jmp ea 23 16 15 8 7 0 00001111 ccccaaaa aaaaaaaa 23 16 15 8 7 0 00001110 ccccaaaa aaaaaaaa 23 16 15 8 7 0 00001101 0000aaaa aaaaaaaa 23 16 15 8 7 0 00001100 0000aaaa aaaaaaaa 23 16 15 8 7 0 00 001011 11mmmrrr 10 1 0cccc optional effective address extension 23 16 15 8 7 0 00001011 11mmmrrr 10000000 optional effective address extension 23 16 15 8 7 0 00 001010 11mmmrrr 10 1 0cccc optional effective address extension 23 16 15 8 7 0 00001010 11mmmrrr 10000000 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 319 jsset #n,x:pp,xxxx jsset #n,y:pp,xxxx jsclr #n,x:pp,xxxx jsclr #n,y:pp,xxxx jset #n,x:pp,xxxx jset #n,y:pp,xxxx jclr #n,x:pp,xxxx jclr #n,y:pp,xxxx jsset #n,x:ea,xxxx jsset #n,y:ea,xxxx jsclr #n,x:ea,xxxx jsclr #n,y:ea,xxxx 23 16 15 8 7 0 00001011 10pppppp 1s1bbbbb absolute address extension 23 16 15 8 7 0 00001011 10pppppp 1s0bbbbb absolute address extension 23 16 15 8 7 0 00001010 10pppppp 1s1bbbbb absolute address extension 23 16 15 8 7 0 00001010 10pppppp 1s0bbbbb absolute address extension 23 16 15 8 7 0 00001011 01mmmrrr 1s1bbbbb absolute address extension 23 16 15 8 7 0 00001011 01mmmrrr 1s0bbbbb absolute address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 320 instruction set details motorola jset #n,x:ea,xxxx jset #n,y:ea,xxxx jclr #n,x:ea,xxxx jclr #n,y:ea,xxxx jsset #n,x:aa,xxxx jsset #n,y:aa,xxxx jsclr #n,x:aa,xxxx jsclr #n,y:aa,xxxx jset #n,x:aa,xxxx jset #n,y:aa,xxxx jclr #n,x:aa,xxxx jclr #n,y:aa,xxxx 23 16 15 8 7 0 00001010 01mmmrrr 1s1bbbbb absolute address extension 23 16 15 8 7 0 00001010 01mmmrrr 1s0bbbbb absolute address extension 23 16 15 8 7 0 00001011 00aaaaaa 1s1bbbbb absolute address extension 23 16 15 8 7 0 00001011 00aaaaaa 1s0bbbbb absolute address extension 23 16 15 8 7 0 00001010 00aaaaaa 1s1bbbbb absolute address extension 23 16 15 8 7 0 00001010 00aaaaaa 1s0bbbbb absolute address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 321 jsset #n,s,xxxx jsclr #n,s,xxxx jset #n,s,xxxx jclr #n,s,xxxx btst #n,x:pp btst #n,y:pp bchg #n,x:pp bchg #n,y:pp bset #n,x:pp bset #n,y:pp 23 16 15 8 7 0 00001011 11dddddd 001bbbbb absolute address extension 23 16 15 8 7 0 00001011 11dddddd 000bbbbb absolute address extension 23 16 15 8 7 0 00001010 11dddddd 001bbbbb absolute address extension 23 16 15 8 7 0 00001010 11dddddd 000bbbbb absolute address extension 23 16 15 8 7 0 00001011 10pppppp 0s1bbbbb 23 16 15 8 7 0 00001011 10pppppp 0s0bbbbb 23 16 15 8 7 0 00001010 10pppppp 0s1bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 322 instruction set details motorola bclr #n,x:pp bclr #n,y:pp btst #n,x:ea btst #n,y:ea bchg #n,x:ea bchg #n,y:ea bset #n,x:ea bset #n,y:ea bclr #n,x:ea bclr #n,y:ea btst #n,x:aa btst #n,y:aa 23 16 15 8 7 0 00001010 10pppppp 0s0bbbbb 23 16 15 8 7 0 00001011 01mmmrrr 0s1bbbbb optional effective address extension 23 16 15 8 7 0 00001011 01mmmrrr 0s0bbbbb optional effective address extension 23 16 15 8 7 0 00001010 01mmmrrr 0s1bbbbb optional effective address extension 23 16 15 8 7 0 00001010 01mmmrrr 0s0bbbbb optional effective address extension 23 16 15 8 7 0 00001011 00aaaaaa 0s1bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 323 bchg #n,x:aa bchg #n,y:aa bset #n,x:aa bset #n,y:aa bclr #n,x:aa bclr #n,y:aa btst #n,d bchg #n,d bset #n,d 23 16 15 8 7 0 00001011 00aaaaaa 0s0bbbbb 23 16 15 8 7 0 00001010 00aaaaaa 0s1bbbbb 23 16 15 8 7 0 00001010 00aaaaaa 0s0bbbbb 23 16 15 8 7 0 00001011 11dddddd 011bbbbb 23 16 15 8 7 0 00001011 11dddddd 010bbbbb 23 16 15 8 7 0 00001010 11dddddd 011bbbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 324 instruction set details motorola bclr #n,d movep x:ea,x:pp movep y:ea,x:pp movep #xxxxxx,x:pp movep x:pp,x:ea movep x:pp,y:ea movep x:ea,y:pp movep y:ea,y:pp movep #xxxxxx,y:pp movep y:pp,x:ea movep y:pp,y:ea movep p:ea,x:pp movep x:pp,p:ea movep p:ea,y:pp movep y:pp,p:ea movep s,x:pp movep x:pp,d movep s,y:pp movep y:pp,d move(m) s,p:ea move(m) p:ea,d 23 16 15 8 7 0 00001010 11dddddd 010bbbbb 23 16 15 8 7 0 0000100s w1mmmrrr 1spppppp optional effective address extension 23 16 15 8 7 0 0000100s w1mmmrrr 01pppppp optional effective address extension 23 16 15 8 7 0 0000100s w1dddddd 00pppppp 23 16 15 8 7 0 00000111 w1mmmrrr 10dddddd optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 325 move(m) s,p:aa move(m) p:aa,d rep #xxx rep s rep x:ea rep y:ea rep x:aa rep y:aa do #xxx,expr do s,expr 23 16 15 8 7 0 00000111 w0aaaaaa 00dddddd 23 16 15 8 7 0 00000110 iiiiiiii 1 010hhhh 23 16 15 8 7 0 00000110 11dddddd 00100000 23 16 15 8 7 0 00000110 01mmmrrr 0s100000 23 16 15 8 7 0 00000110 00aaaaaa 0s100000 23 16 15 8 7 0 00000110 iiiiiiii 1 000hhhh absolute address extension 23 16 15 8 7 0 00 000110 11dddddd 0 0000000 absolute address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 326 instruction set details motorola do x:ea,expr do y:ea,expr do x:aa,expr do y:aa,expr move(c) #xx,d1 move(c) x:ea,d1 move(c) s1,x:ea move(c) y:ea,d1 move(c) s1,y:ea move(c) #xxxx,d1 move(c) x:aa,d1 move(c) s1,x:aa move(c) y:aa,d1 move(c) s1,y:aa move(c) s1,d2 move(c) s2,d1 23 16 15 8 7 0 00000110 01mmmrrr 0s000000 absolute address extension 23 16 15 8 7 0 00000110 00aaaaaa 0s000000 absolute address extension 23 16 15 8 7 0 00000101 iiiiiiii 1 01ddddd 23 16 15 8 7 0 00000101 w1mmmrrr 0s1ddddd optional effective address extension 23 16 15 8 7 0 00000101 w0aaaaaa 0s1ddddd optional effective address extension 23 16 15 8 7 0 00000100 w1eeeeee 101ddddd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 327 lua ea,d tcc s1,d1 s2,d2 tcc s1,d1 norm rn,d div s,d mac ( )s,#n,d macr ( )s,#n,d mpy ( )s,#n,d 23 16 15 8 7 0 00000100 010mmrrr 0001dddd 23 16 15 8 7 0 00 000011 cccc0 t t t 0j j jdttt 23 16 15 8 7 0 00000010 cccc0000 0jjjd000 23 16 15 8 7 0 00000001 11011rrr 0001d101 23 16 15 8 7 0 00000001 10000000 01jjd000 23 16 15 8 7 0 00000001000s ssss 11qqdk10 23 16 15 8 7 0 00000001000s ssss 11qqdk11 23 16 15 8 7 0 00000001000s ssss 11qqdk00 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 328 instruction set details motorola mpyr ( )s,#n,d debugcc debug or(i) #xx,d and(i) #xx,d 23 16 15 8 7 0 00000001000s ssss 11qqdk01 23 16 15 8 7 0 00000000 00000011 0000cccc 23 16 15 8 7 0 00000000 00000010 00000000 23 16 15 8 7 0 00000000 iiiiiiii 1 11110ee 23 16 15 8 7 0 00000000 iiiiiiii 1 01110ee f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 329 enddo stop wait reset rts dec inc swi 23 16 15 8 7 0 00000000 00000000 10001100 23 16 15 8 7 0 00000000 00000000 10000111 23 16 15 8 7 0 00000000 00000000 10000110 23 16 15 8 7 0 00000000 00000000 10000100 23 16 15 8 7 0 00000000 00000000 00001100 23 16 15 8 7 0 00000000 00000000 0000101d 23 16 15 8 7 0 00000000 00000000 0000100d 23 16 15 8 7 0 00000000 00000000 00000110 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 330 instruction set details motorola illegal rti nop a.10.4 parallel instruction encoding of the operation code the operation code encoding for the instructions which allow parallel moves is divided into the multiply and nonmultiply instruction encodings shown in the following subsection. multiply instruction encoding the 8-bit operation code for multiply instructions allowing parallel moves has different fields than the nonmultiply instructions operation code. the 8-bit operation code= 1qqq dkkk where qqq=selects the inputs to the multiplier kkk = three unencoded bits k2, k1, k0 d = destination accumulator d = 0 t a d = 1 t b 23 16 15 8 7 0 00000000 00000000 00000101 23 16 15 8 7 0 00000000 00000000 00000100 23 16 15 8 7 0 00000000 00000000 00000000 code k2 k1 k0 0 positive mpy only dont round 1 negative mpy and acc round table a-26 operation code k0-2 decode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 331 macr ( ) s1,s2,d macr ( ) s2,s1,d mac ( ) s1,s2,d mac ( ) s2,s1,d mpyr ( ) s1,s2,d mpyr ( ) s2,s1,d mpy ( ) s1,s2,d mpy ( ) s2,s1,d qq q s1 s2 00 0 x0 x0 00 1 y0 y0 01 0 x1 x0 01 1 y1 y0 10 0 x0 y1 10 1 y0 x0 11 0 x1 y0 11 1 y1 x1 note: s1 and s2 are the inputs to the multiplier. table a-27 operation code qqq decode 23 87 43 0 data bus move field 1 q q q d k 1 1 optional effective address extension 23 87 43 0 data bus move field 1 q q q d k 1 0 optional effective address extension 23 87 43 0 data bus move field 1 q q q d k 0 1 optional effective address extension 23 87 43 0 data bus move field 1 q q q d k 0 0 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 332 instruction set details motorola nonmultiply instruction encoding the 8-bit operation code for instructions allowing parallel moves contains two 3-bit fields defining which instruction the operation code represents and one bit defining the destina- tion accumulator register. the 8-bit operation code = 0jjj dkkk where jjj=1/2 instruction number kkk=1/2 instruction number d=0 t a d=1 t b jjj d = 0 src oper d = 1 src oper kkk 000 001 010 011 100 101 110 111 000 b a move 1 tfr addr tst * cmp subr cmpm 001 b a add rnd addl clr sub * subl not 010 2 b a asr lsr abs ror 011 2 b a asl lsl neg rol 010 2 x1x0 x1x0 add adc sub sbc 011 2 y1y0 y1y0 add adc sub sbc 100 x0_0 x0_0 add tfr or eor sub cmp and cmpm 101 y0_0 y0_0 add tfr or eor sub cmp and cmpm 110 x1_0 x1_0 add tfr or eor sub cmp and cmpm 111 y1_0 y1_0 add tfr or eor sub cmp and cmpm notes: * = reserved 1 = special case #1 (see table a-29) 2 = special case #2 (see table a-30) table a-28 nonmultiply instruction encoding f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 333 for jjj=010 and 011, k1 qualifies source register selection: cmpm s1,s2 and s,d cmp s1,s2 sub s,d o p e r c o d e operation 000000 00 move 000010 00 reserved table a-29 special case #1 0jjjdk kk operation 0010xx 0x selects x1x0 0011xx 0x selects y1y0 0 0 1 x x x 1 x selects a/b table a-30 special case #2 23 87 43 0 data bus move field 0 j j j d 1 1 1 optional effective address extension 23 87 43 0 data bus move field 0 1 j j d 1 1 0 optional effective address extension 23 87 43 0 data bus move field 0 j j j d 1 0 1 optional effective address extension 23 87 43 0 data bus move field 0 j j j d 1 0 0 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 334 instruction set details motorola eor s,d or s,d tfr s,d add s,d sbc s,d adc s,d rol d 23 87 43 0 data bus move field 0 1 j j d 0 1 1 optional effective address extension 23 87 43 0 data bus move field 0 1 j j d 0 1 0 optional effective address extension 23 87 43 0 data bus move field 0 j j j d 0 0 1 optional effective address extension 23 87 43 0 data bus move field 0 j j j d 0 0 0 optional effective address extension 23 87 43 0 data bus move field 0 0 1 j d 1 0 1 optional effective address extension 23 87 43 0 data bus move field 0 0 1 j d 0 0 1 optional effective address extension 23 87 43 0 data bus move field 0 0 1 1 d 1 1 1 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 335 neg d lsl d asl d ror d abs d lsr d asr d 23 87 43 0 data bus move field 0 0 1 1 d 1 1 0 optional effective address extension 23 87 43 0 data bus move field 0 0 1 1 d 0 1 1 optional effective address extension 23 87 43 0 data bus move field 0 0 1 1 d 0 1 0 optional effective address extension 23 87 43 0 data bus move field 0 0 1 0 d 1 1 1 optional effective address extension 23 87 43 0 data bus move field 0 0 1 0 d 1 1 0 optional effective address extension 23 87 43 0 data bus move field 0 0 1 0 d 0 1 1 optional effective address extension 23 87 43 0 data bus move field 0 0 1 0 d 0 1 0 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 336 instruction set details motorola not d subl s,d clr d addl s,d rnd d subr s,d tst d 23 87 43 0 data bus move field 0 0 0 1 d 1 1 1 optional effective address extension 23 87 43 0 data bus move field 0 0 0 1 d 1 1 0 optional effective address extension 23 87 43 0 data bus move field 0 0 0 1 d 0 1 1 optional effective address extension 23 87 43 0 data bus move field 0 0 0 1 d 0 1 0 optional effective address extension 23 87 43 0 data bus move field 0 0 0 1 d 0 0 1 optional effective address extension 23 87 43 0 data bus move field 0 0 0 0 d 1 1 0 optional effective address extension 23 87 43 0 data bus move field 0 0 0 0 d 0 1 1 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding motorola instruction set details a - 337 addr s,d move s,d 23 87 43 0 data bus move field 0 0 0 0 d 0 1 0 optional effective address extension 23 87 43 0 data bus move field 0 0 0 0 0 0 0 0 optional effective address extension f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction encoding a - 338 instruction set details motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola benchmark programs b - 1 appendix b benchmark programs t t t t t p1 p3 p2 p4 t t t f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section contents b - 2 benchmark programs motorola section b.1 introduction ........................................................................3 section b.2 benchmark programs ......................................................3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction motorola benchmark programs b - 3 b.1 introduction table b-1 provides benchmark numbers for 18 common dsp programs implemented on the 27-mhz dsp56001. the four code examples shown in figures b-1 to b-4 represent the benchmark programs shown in table b-1. b.2 benchmark programs figure b-1 is the code for the 20-tap fir filter shown in table b-1. figure b-2 is the code for an fft using a triple nested do loop. although this code is easier to understand and very compact, it is not as fast as the code used for the benchmarks shown in table b-1, which are highly optimized using the symmetry of the fft and the parallelism of the dsp. figure b-3 is the code for the 8-pole cascaded canonic biquad iir filter, which uses four coefficients (see table b-1). figure b-4 is the code for a 2n delayed least mean square (lms) fir adaptive filter, which is useful for echo cancelation and other adaptive filtering applications.the code example shown in figure b-5 represents the real fft code for the dsp56002, based on the glenn bergland algorithm. the code for these and other programs is free and available through the dr. bub elec- tronic bulletin board. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs b - 4 benchmark programs motorola benchmark program sample rate (hz) or execution time memory size (words) number of clock cycles 20 - tap fir filter 500.0 khz 50 54 64 - tap fir filter 190.1 khz 138 142 67 - tap fir filter 182.4 khz 144 148 8 - pole cascaded canonic biquad iir filter (4x) 540.0 khz 40 50 8 - pole cascaded canonic biquad iir filter (5x) 465.5 khz 45 58 8 - pole cascaded transpose biquad iir filter 385.7 khz 48 70 dot product 444.4 ns 10 12 matrix multiply 2x2 times 2x2 1.556 m s33 42 matrix multiply 3x3 times 3x1 1.259 m s29 34 m-to-m fft 64 point 98.33 m s 489 2655 m-to-m fft 256 point 489.8 m s 1641 13255 m-to-m fft 1024 point 2.453 ms 6793 66240 p-to-m fft 64 point 92.56 m s 704 2499 p-to-m fft 256 point 347.9 m s 2048 9394 p-to-m fft 1024 point 1.489 ms 7424 40144 table b-1 27-mhz benchmark results for the dsp56001r27 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs motorola benchmark programs b - 5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs b - 6 benchmark programs motorola page 132,66,0,6 opt rc ;******************************************************** ;motorola austin dsp operation june 30, 1988 ;******************************************************** ;dsp56000/1 ;20 - tap fir tlter ;file name: 1-56.asm ;********************************************************************************************************************* ; maximum sample rate: 379.6 khz at 20.5 mhz/500.0 khz at 27.0 mhz ; memory size: prog: 4+6 words; data: 2x20 words ; number of clock cycles: 54 (27 instruction cycles) ; clock frequency: 20.5 mhz/27.0 mhz ; instruction cycle time: 97.6 ns/74.1 ns ;********************************************************************************************************************* ; this fir tlter reads the input sample ; from the memory location y:input ; and writes the tltered output sample ; to the memory location y:output ; ; the samples are stored in the x memory ; the coeftcients are stored in the y memory ; ********************************************************************************************************************** ; x memory y memory ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; r0 x(n) x(n-1) t t+t x(n-k+1) x(n+1) t,t+t c(0) c(1) c(k-1) c(0) x x(n) x c(1) x c(2) x c(k-1) fir t t t yn () cp () np () p 0 = k 1 ? = + y(n) figure b-1 20-tap fir filter example (sheet 1 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs motorola benchmark programs b - 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs b - 8 benchmark programs motorola ; ; ; ;********************************************************************************************************************* ; ; initialization ;**************************************** n equ 20 start equ $40 wddr equ $0 cddr equ $0 input equ $ffe0 output equ $ffe1 ; org p:start move #wddr,r0 ;r0 samples move #cddr,r4 ;r1 coeftcients move #n-1,m0 ;set modulo arithmetic move m0,m4 ;for the 2 circular buffers ; opt cc ; tlter loop :8+(n-1) cycles ;********************************************************************************************************************** movep y:input,x: (r0) ;input sample in memory clr a x:(r0)+,x0 y: (r4)+,y0 rep #n-1 mac x0,y0,a x:(r0)+,x0 y:(r4)+,y0 macr x0,x0,a (r0)- movep a,y:output ;output tltered sample ;********************************************************************************************************************* end figure b-1 20-tap fir filter example (sheet 2 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs motorola benchmark programs b - 9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs b - 10 benchmark programs motorola ;this program originally available on the motorola dsp bulletin board. ;it is provided under a disclaimer of warranty available from ;motorola dsp operation, 6501 william cannon drive, austin, tx, 78735 ; ;radix-2, in-place, decimation-in-time fft (smallest code size). ; ;last update 30 sep 86 version 1.1 ; fftr2a macro points,data,coef fftr2a ident 1,1 ; ;radix-2 decimation-in-time in-place fft routine ; ; complex input and output data ; real data in x memory ; imaginary data in y memory ; normally ordered input data ; bit reversed output data ; coeftcient lookup table ; -cosine values in x memory ; -sine values in y memory ; ;macro call ? ffr2a points,data,coef ; ; points number of points (2-32768, power of 2) ; data start of data buffer ; coef start of sine/cosine table ; ;alters data alu registers ;x1x0y1y0 ;a2a1a0a ;b2b1b0b ; ;alters address registers ;r0 n0 m0 ;r1 n1 m1 ;n2 ; ;r4 n4 m4 ;r5 n5 m5 ;r6 n6 m6 ? ?alters program control registers ;pc sr ; ;uses 6 locations on system stack ; figure b-2 radix 2, in-place, decimation-in-time fft (sheet 1 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs motorola benchmark programs b - 11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs b - 12 benchmark programs motorola ;latest revision ? september 30, 1986 ; move #points/2,n0 ;initialize butter?ies per group move #1,n2 ;initialize groups per pass move #points/4,n6 ;initialize c pointer offset move #-1,m0 ;initialize a and b address moditers move m0,m1 ;for linear addressing move m0,m4 move m0,m5 move #0,m6 ;initialize c address moditer for ;reverse carry (bit-reversed) addressing ; ;perform all fft passes with triple nested do loop ; do #@cvi (@log(points)/@log(2)+0.5),_end_pass move #data,r0 ;initialize a input pointer move r0,r4 ;initialize a output pointer lua (r0)+n0,r1 ;initialize b input pointer move #coef,r6 ;initialize c input pointer lua (r1)-,r5 ;initialize b output pointer move n0,n1 ;initialize pointer offsets move n0,n4 move n0,n5 do n2,_end_grp move x:(r1),x1 y:(r6),y0 ;lookup -sine and ; -cosine values move x:(r5),a y:(r0),b ;preload data move x:(r6)+n6,x0 ;update c pointer do n0,_end_bfy mac x1,y0,b y:(r1)+,y1 ;radx 2 dit ;butter?y kernel macr -x0,y1,b a,x:(r5)+ y:(r0),a subl b,a x:(r0),b b,y:(r4) mac -x1,x0,b x:(r0)+,a a,y:(r5) macr -y1,y0,b x:(r1),x1 subl b,a b,x:(r4)+ y:(r0),b _end_bfy move a,x:(r5)+n5 y:(r1)+n1,y1 ;update a and b pointers move x:(r0)+n0,x1 y:(r4)+n4,y1 _end_grp move n0,b1 ;divide butter?ies per group by two isr b n2,a1 ;multiply groups per pass by two isi a b1,n0 move a1,n2 _end_pass endm figure b-2 radix 2, in-place, decimation-in-time fft (sheet 2 of 2) figure b-5 real input fft based on glenn bergland algorithm (sheet 1 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs motorola benchmark programs b - 13 figure b-5 real input fft based on glenn bergland algorithm (sheet 2 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs b - 14 benchmark programs motorola page 132,66,0,6 opt rc ;********************************************************** ;motorola austin dsp operation june 30, 1988 *********************************************************** ;dsp56000/1 ;8-pole 4-multiply cascaded canonic iir tlter ;file name: 4-56.asm ;********************************************************************************************************************** ; maximum sample rate: 410.0 khz at 20.5 mhz/540.0 khz at 27.0 mhz ; memory size: prog: 6+10 words; data: 4(2+4) words ; number of clock cycles: 50 (25 instruction cycles) ; clock frequency: 20.5 mhz/27.0 mhz ; instruction cycle time: 97.5 ns/74.1 ns ;********************************************************************************************************************** ; this iir tlter reads the input sample ; from the memory location y:input ; and writes the tltered output sample ; to the memory location y:output ; ; the samples are stored in the x memory ; the coeftcients are stored in the y memory ; ; ; the equations of the tlter are: ; w(n)= x(n)-ai1 * w(n-1)-ai2 * w(n-2) ; y(n)= w(n)+bi1 * w(n-1)+bi2 * w(n-2) ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ( - ) ( + ) x(n) y(n) w(n) ai1 ai2 bi1 bi2 w(n-1) w(n-2) z -1 z -1 figure b 3 8 pole 4 multiply cascaded canonic iir filter (sheet 1 of 2) figure b-5 real input fft based on glenn bergland algorithm (sheet 3 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs motorola benchmark programs b - 15 figure b-5 real input fft based on glenn bergland algorithm (sheet 4 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs b - 16 benchmark programs motorola ; all coeftcients are divided by 2: ; w(n)/2=x(n)/2-ai1/2*w(n-1)-ai2/2*w(n-2) ; y(n)/2=w(n)/2+bi1/2*w(n-1)+bi2/2*w(n-2) ; ; x memory organization y memory organization ; b1n/2 coef. + 4*nsec - 1 ; b2n/2 ; a1n/2 ; a2n/2 ; wn(n-1) data + 2*nsec - 1 ; wn(n-2) ; b11/2 ; b21/2 ; w1(n-1) a11/2 ; r0 w1(n-2) data r4 a21/2 coef. ; ;********************************************************************************************************************* ; initialization ;************************************* nsec equ 4 start equ $40 data equ 0 coef equ 0 input equ $ffe0 output equ $ffe1 igain equ 0.5 ori #$08,mr ;set scaling mode move #data,r0 ;point to tlter states move #coef,r4 ;point to tlter coeftcients move #2*nsec - 1,m0 move #4*nsec - 1,m4 move #igain,y1 ;y1=initial gain opt cc ; tlter loop: 4*nsec + 9 ;********************************************************************* movep y:input,y0 ;get sample mpy y0,y1,a x:(r0) +,x0 y:(r4)+,y0 ;x0=1st section w(n-2),y0=ai2/2 ; do #nsec,end_cell ;do each section mac -x0,y0,a x:(r0) -,x1 y:(r4) +,y0 ;x1=w(n-1),y0=ai1/2 macr -x1,y0,a x1,x:(r0) + y:(r4) +,y0 ;push w(n-1) to w(n-2),y0=bi2/2 mac x0,y0,a a,x:(r0)+ y:(r4) +,y0 ;push w(n) to w(n-1),y0=bi1/2 mac x1,y0,a x:(r0) +,x0 y:(r4) +,y0 ;next iter:x0=w(n-2),y0=ai2/2 end_cell rnd a ;round result movep a,y:output ;output sample ;**************************************************************************************** end figure b-5 real input fft based on glenn bergland algorithm (sheet 5 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs motorola benchmark programs b - 17 figure b-5 real input fft based on glenn bergland algorithm (sheet 6 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs b - 18 benchmark programs motorola page 132,60,1,1 ;newlms2n.asm ; new implementation of the delayed lms on the dsp56000 revision c ;memory map: ; initial x h ; x(n) x(n-1) x(n-2) x(n-3) x(n-4) hx h0 h1 h2 h3 ;] ] ] ;r0 r5 r4 ;hx is an unused value to make the calculations faster. ; opt cc ntaps equ 4 input equ $ffc0 output equ $ffc1 org x:$0 state ds 5 org y:$0 coef ds 5 ; org p:$40 move #state,r0 ;start of x move #2,n0 move #ntaps,m0 ;mod 5 move #coef +1,r4 ;coeftcients move #ntaps,m4 ;mod 5 move #coef,r5 ;coeftcients move m4,m5 ;mod 5 _smploop ; prog icyc movep y:input,a ;get input sample word move a,x:(r0) ;save input sample 1 1 ;error signal is in y1 ;fir sum in a=a+h(k) old*x(n-k) ;h(k)new in b=h(k)old + error*x(n-k-1) cir a x:(r0)+,x0 ;x0=x(n) 1 1 move x:(r0)+,x1 y:(r4)+,y0 ;x1=x(n-1),y0=h(0) 1 1 do #taps/2,_lms ; 2 3 mac x0,y0,a y0,b b,y:(r5)+ ;a=h(0)*x(n),b=h(0) 1 1 macr x1,y1,b x:(r0)+,x0 y:(r4)+,y0 ;b=h(0)+e*x(n-1)=h(0)new 1 1 ;x0=x(n-2) y0=h(1) mac x1,y0,a y0,b b,y:(r5)+ ;a=a+h(1)*x(n-1) b=h(1) 1 1 macr x0,y1,b x:(r0)+,x1 y:(r4)+,y0 ;b=h(1)+e*x(n-2) 1 1 ; ;x1=x(n-3) y0=h(2) _lms move b,y:(r5)+ ;save last new c( ) 1 1 move (r0) -n0 ;pointer update 1 1 ;(get d(n), subtract tr output (reg a), multiply by u, put ;the result in y1. this section is application dependent.) movep a y:output ;output tr if desired figure b-5 real input fft based on glenn bergland algorithm (sheet 7 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs motorola benchmark programs b - 19 real input fft based on glenn bergland algorithm ; ; normal order input and normal order output. ; ; since 56001 does not support bergland addressing, extra instruction cycles are needed ; for converting bergland order to normal order. it has been done in the last pass by ; looking at the bergtable. ; the micro ?ergsincos generates sin and cos table with size of points/4, cos in y, sin in x ; the micro ?ergorder generates table for address conversion, the size of twiddle factors is half ; of fft outputs. ; the micro ?orm2berg converts normal order data to bergland order. ; the micro ?fft-56b does fft. ; ; real input data are split into two parts, the ?st part is put in x, the second in y. ; real output data are in x, imaginary output data are in y. ; the bergland table for converting berglang order to normal order is stored in output buffer. ; in the last pass the fft output overwrites this table. ; the ?st real output plus the ?st imaginary output is dc value of the spectrum. ; note that only dc to nyquist frequency range is calculated by this algorithm. ; after twiddle factors and bergtable are generated, you may overwrite ?ergorder? ; ?orm2berg by ?fft-56b for saving p memory. ; ; performance ;----------------------------------------------------------------- ; real input data points clock cycle ; 64 1686 ; 128 3846 ; 256 8656 ; 512 19296 ; 1024 49776 ;------------------------------------------------------------------ ; ; memory (word) ;------------------------------------------------------------------ ; p memory x memory y memory ; 87 points/2 (real input) + points/2 (imaginary input) ; points/4 (sin table) + points/4 (cos table) ; points/2 (real output) + points/2 (imaginary output) ; points/2 (bergtable) ;------------------------------------------------------------------- ; ; rfft56bt ident 1,3 page 132,60 opt nomd,nomex,loc,nocex,mu include ?ergsincos include ?ergorder include ?orm2berg include ?fft-56b ; figure b-5 real input fft based on glenn bergland algorithm (sheet 8 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs b - 20 benchmark programs motorola ; main program to call the rfft-56b macro ; argument list ; ; latest modifying date - 4-march-92 reset equ 0 start equ $40 points equ 512 binlogsz equ 9 idata equ $000 odata equ $400 bergtable equ $600 twiddle equ $800 bergsincos points,odata ;generate normal order twiddle factors with size of points/4 opt mex org p:reset jmp start org p:start movep #0,x:$fffe ;0 wait states bergorder points/4,bergtable,odata ;generates bergland table for twiddle factor norm2berg points/4,bergtable,twiddle ;converting twiddle factor from normal order to bergland order bergorder points/2,bergtable,odata ;table for tnal output rifft points,binlogsz,idata,odata,twiddle,bergtable end ; bergsincos macro points,coef bergsincos ident 1,2 ; ; sincos - macro to generate sine and cosine coeftcient ; lookup tables for decimation in time fft ; twiddle factors. ; ; points - number of points (2 - 32768, power of 2) ; coef - base address of sine/cosine table ; negative cosine value in x memory ; negative sine value in y memory ; ; pi equ 3.141592654 freq equ 2.0*pi/@cvf(points) org y:coef f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs motorola benchmark programs b - 21 count set 0 dup points/4 dc @cos(@cvf(count)*freq) ount set count+1 endm org x:coef count set 0 dup points/4 dc @sin(@cvf(count)*freq) count set count+1 endm endm ;end of bergsincos macro bergorder macro points,bergtable,offset bergorder ident 1,3 ;bergorder generates bergland order table move #>4,a move #points,r4 ;points=number of points of bergtable to be generated move #>points/4,b ;nitial pointer move #bergtable,r0 ;table resides in move b,n0 ;init offset move #>0,x0 move x0,x:(r0)+n0 ;seeds move #>2,x0 move x0,x:(r0)+n0 move #>1,x0 move x0,x:(r0)+n0 move #>3,x0 move x0,x:(r0) move #bergtable,n0 ;location of bergtable do #@cvi(@log(points/4)/@log(2)),_endl move b,x0 ;x0=i+i lsr b ;b=i move b,r0 ;r0=i nop move a,x:(r0+n0) ;k-> bergtable lsl a ;k=k*2 move a,y1 ;save a content _star move r4,a ;r4=# of points cmp x0,a ;x0=j, if j< points, cont jle _loop move x0,r0 ;r0=i+i=j,b=i move y1,a ;recover a=k move x:(r0+n0),y0 ;y0=bergtabl[j] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs b - 22 benchmark programs motorola sub y0,a ;k-bergtabl[j] move b,x1 ;save b, x1=i move r0,y0 ;y0=j=i+i add y0,b ;b=j+i move b,r0 ;r0=j+i nop move a,x:(r0+n0) ;store bergtabl[j+i] add x1,b ;b=j+i+i move b,x0 ;save b move x1,b ;recover b=i jmp _star _loop move y1,a ;recover a _endl move #>offset,a ;offset is the location of output data or twiddle move #bergtable,r0 do #points,_add_offset move x:(r0),b add a,b move b,x:(r0)+ _add_offset endm ;end of sincos macro ;convert normal order to berglang order norm2berg macro points,bergtable,twiddle ;points is actual size of table to be converting move #bergtable,r0 ;r0=pointer of bergland table move #twiddle,r2 ;r2=twiddle pointer for x move r2,r6 ;r6=twiddle pointer for y do #points,data_temp move x:(r0)+,r3 ;get index move r3,r7 move x:(r3),a move y:(r7),b ;get value move a,x:(r2)+ b,y:(r6)+ ;write back data_temp endm ; real-valued fft for motorola dsp56000/1/2 ; ; based on glenn bergland?s algorithm ; ; ______________________________ rifft macro points,binlogsz,idata,odata,twiddle,bergtable move #idata,r0 ;r0 = ptr to a move #points/4,n0 ;b?ys in ea group, half at ea pass f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs motorola benchmark programs b - 23 move #twiddle+1,r7 ;r7 always points to start location of twiddle lua (r0)+n0,r1 ;r1 = ptr to b move r0,r4 ;r4 points to c move r1,r5 ;r5 points to d,with predecrement move #1,r3 ;group per pass, double at ea pass move x:(r0),a y:(r4),y0 ;a=a, y0=c do n0,pass1 ;trst pass is trivial, no multiplications ; ------------------------------------------------ ; first pass -- w(n) = 1 ; ; a---\ /---a?= re[ a + jb + (c + jd) ] = a + c ; b----\_|_/----b?= im[ a + jb + (c + jd) ] =j(d + b) ; c----/ | \----c?= re[ a + jb - (c + jd) ] = a - c ; d---/ \---d?= im[-a - jb + (c + jd) ] =j(d - b) ;------------------------------------------------- ; sub y0,a x:(r1),x0 y:(r5),b ;a=a-c=c?,b=d,x0=b, add x0,b a,x:(r1)+ y:(r5),a ;b=d+b=b?, a=d,put c? to x:b sub x0,a x:(r0)+,b b,y:(r4)+ ;a=d-b=d?,b=a,put b? to y:c add y0,b x:(r0)-, a a,y:(r5)+ ;b=a+c=a?, a=next a,put d? move b,x:(r0)+ y:(r4),y0 ;y0=next c, put a? pass1 move #idata,r0 ;r0 = ptr to a do #binlogsz-3,end_pass ;do all passes except trst and last move r7,r2 ;r2 points to real twiddle move r2,r6 ;r6 points to imag twiddle move n0,a ;half b?ys per group lsr a r3,b ;double group per pass lsl a,n0 move b,r3 ;r3 is temp reg. lua (r0)+n0,r1 ;r1 = ptr to b move r0,r4 ;r4 points to c move r1,r5 ;r5 points to d lua (r3)-,n2 ;n2=group per pass -1 move x:(r0),a y:(r4),y0 ;a=a, y0=c do n0,firstgroupinpass ;trst group in a pass sub y0,a x:(r1),x0 y:(r5),b ;a=a-c=c?,b=d,x0=b, add x0,b a,x:(r1)+ y:(r5),a ;b=d+b=b?, a=d,put c? to x:b sub x0,a x:(r0)+,b b,y:(r4)+ ;a=d-b=d?,b=a,put b? to y:c add y0,b x:(r0)-,a a,y:(r5)+ ;b=a+c=a?, a=next a,put d? move b,x:(r0)+ y:(r4),y0 ;y0=next c, put a? firstgroupinpass do n2,end_group ;rest groups in this pass move r5,r0 ;r0 ptr to next group a move r0,r4 ;r4 ptr to next group c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs b - 24 benchmark programs motorola lua (r0)+n0,r1 ;r1 ptr to next group b move r1,r5 ;r5 ptr to next group d ; intermediate passes -- w(n) < 1 ; ; a---\ /---a?= re[ a + jc + (b - jd)w(k) ] = a+bwr+dwi=a+t1 ; b----\_|_/----b?= im[ a + jc - (b - jd)w(k) ] = c+dwr-bwi=t2+c ; c----/ | \----c?= re[ a + jc - (b - jd)w(k) ] = a-(bwr+dwi)=a-t1 ; d---/ \---d?= im[-a - jc - (b - jd)w(k) ] = -c+dwr-bwi=t2-c ; ______________________________ move x:(r2)+,x0 y:(r6)+,y0 ;x0=wi, y0=wr move x:(r1)-,x1 y:(r5),y1 ;x1=b,y1=d move x:(r1),b ;for pointer reason do n0,end_b?y ;n0 b?y in this group mpy -x1,x0,b b,x:(r1) ;b=-bwi, put c? to x:b mac y0,y1,b y:(r4),a ;b=dwr-bwi=t2, a=c sub a,b ;b=t2-c=d? addl b,a x:(r1)+,b b,x:(r5)+ ;a=t2+c=b?, put d? mpy -x1,y0,b x:(r0),a a,y:(r4)+ ;b=-bwr, a=a, put b? to y:c mac -x0,y1,b x:(r1)-,x1 ;b=-bwr-dwi=-t1, x1=next b sub b,a ;a=a+t1=a? addl a,b a,x:(r0)+ y:(r5),y1 ;b=a-t1=c?, y1=next d, put a? end_b?y move b,x:(r1)+ ;put last b? end_group move #idata,r0 ;r0 = ptr to a end_pass ;the last pass converts bergland order to normal order by calling bergtable move r7,r2 ;r2 points to real twiddle move r2,r6 ;r6 points to imag twiddle move r0,r4 r4 points to c move #bergtable,r3 ;r3=pointer of bergland table move #(points/4)-1,n2 ;n2=group per pass -1 move x:(r3)+,r7 ;get trst index move x:(r3)+,r1 ;get second index move #2,n4 ; trst group in the last pass move x:(r0)+,a y:(r4)+,b ;a=a, b=c sub b,a x:(r0)+,x0 y:(r6)+,y0 ;a=a-c=c?,x0=b, y0=wr for next b?y addl a,b a,x:(r1) y:(r4),a ;b=a+c=a?, a=d,put c? to x:b sub x0,a b,x:(r7) ;a=d-b=d?,put a? to x move y:(r4)+,b ;b=d add x0,b a,y:(r1) ;b=d+b=b?, a=next a,put d? move x:(r0)+,a b,y:(r7) ;a=next a, put b? move x:(r2)+,x0 y:(r4)+,b ;x0=wi,b=next c do n2,end_lastg ;rest groups in the last pass f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs motorola benchmark programs b - 25 ; intermediate passes -- w(n) < 1 ; ; a---\ /---a?= re[ a + jc + (b - jd)w(k) ] = a+bwr+dwi=a+t1 ; b----\_|_/----b?= im[ a + jc - (b - jd)w(k) ] = c+dwr-bwi=t2+c ; c----/ | \----c?= re[ a + jc - (b - jd)w(k) ] = a-(bwr+dwi)=a-t1 ; d---/ \---d?= im[-a - jc - (b - jd)w(k) ] = -c+dwr-bwi=t2-c ; ______________________________ move x:(r0)+,x1 y:(r4)-,y1 ;x1=b, y1=d, r4 ptr back to c mpy x1,y0,b x:(r3)+,r7 ;a=bwr, mac x0,y1,b x:(r3)+,r1 ;b=bwr+dwi=t1, get trst index sub b,a ;a=a-t1=c?, get second index addl a,b a,x:(r1) ;b=a+t1=a?, put c? to x:b mpy y1,y0,a b,x:(r7) ;b=dwr, b=c put a? mac -x1,x0,a y:(r4)+n4,b ;a=dwi-bwr=t2, b=c, r4 ptr to next c sub b,a x:(r2)+,x0 y:(r6)+,y0 ;a=t2-c=d?,x0=next wi, y0=next wr addl a,b a,y:(r1) ;b=t2+c=b?, update r4, a=next a, put d? move x:(r0)+,a b,y:(r7) ;put b?, a=next a move y:(r4)+,b ;b=next c end_lastg endm ; real input fft based on glenn bergland algorithm ; ; normal order input and normal order output. ; since 56001 does not support bergland addressing, extra instruction cycles are needed ; for converting bergland order to normal order.it has been done in the last pass by ; looking at the bergtable. ; 'bergsincos' generates sin and cos table with size of points/4,cos in y, sin in x ; 'bergorder' generates table for address conversion, the size of twiddle factors is half ; of fft output's ; 'rfft-56b' does fft ; ; normal order input and normal order output. ; ; real input data are split into two parts, the trst part is put in x, the second in y. ; real output data are in x, imaginary output data are in y. ; the trst real output is dc ; the trst imaginary output is the nyquist frequency. ; note that only dc to nyquist frequency range is calculated by this algorithm ; after twiddle factors and bergtable are generated, you may overwrite 'bergorder', ; 'norm2berg' by 'rfft-56b' for saving p memory. ; ; performance ;---------------------------------------------------------------- ; real input data points clock cycle ; 64 1686 ; 128 3846 ; 256 8656 ; 512 19296 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
benchmark programs b - 26 benchmark programs motorola ; 1024 49776 ;------------------------------------------------------------------ ; ; memory (word) ;---------------------------------------------------------------- ; p memory x memory y memory ; 87 points/2+ (real input) points/2+ (imaginary input ) ; points/4+ (sin table) points/4+ (cos table) ; points/2+ (real output) points/2 (imaginary output) ; points/2 (bergtable) ;---------------------------------------------------------------- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index motorola index - 1 ?a? a accumulator . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 aborted instructions . . . . . . . . . . . . . . . . . . . . 7-25 abs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-22 absolute address . . . . . . . . . . . . . . . . . . . . . . 6-14 absolute short . . . . . . . . . . . . . . . . . . . . . . . . 6-14 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 accumulator shifter . . . . . . . . . . . . . . . . . . . . . 3-9 accumulators, a and b . . . . . . . . . . . . . . . . . . . 3-7 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-24 add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-26 addl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-28 addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-30 address alu . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 address bus signals (a0-a15) . . . . . . . . . 8-3, 8-5 address buses . . . . . . . . . . . . . . . . . . . . . 2-3, 2-4 address generation unit (see agu) . . . . . . . . 4-3 address modifier arithmetic types . . . . . . . . . 4-14 linear modifier . . . . . . . . . . . . . . . . . . . . . 4-16 modulo modifier . . . . . . . . . . . . . . . . . . . . 4-18 reverse-carry modifier . . . . . . . . . . . . . . . 4-22 summary . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 address operands . . . . . . . . . . . . . . . . . . . . . 6-10 table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-6 address register files . . . . . . . . . . . . . . . . . . . 4-7 r, n, and m register restrictions . . . . . . a-310 addressing modes . . . . . . . . . 4-3, 4-8, 6-12, a-10 address register direct . . . . . . . . . . . . . . . 6-13 address register indirect . . . . . . . . . . . . . . 4-9 operators table . . . . . . . . . . . . . . . . . . . . . a-8 register direct . . . . . . . . . . . . . . . . . . . . . 6-13 special . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 timing summary . . . . . . . . . . . . . . . . . . . a-304 agu address alu . . . . . . . . . . . . . . . . . . . . . . . 4-5 address output multiplexers . . . . . . . . . . . 4-6 address register . . . . . . . . . . . . . . . . . 4-3, 4-7 address register restrictions . . . . . . . . . . 7-10 architecture . . . . . . . . . . . . . . . . . . . . . . . . 4-3 modifier register . . . . . . . . . . . . . . . . . 4-5, 4-8 modifier register restrictions . . . . . . . . . . 7-10 offset register . . . . . . . . . . . . . . . . . . . 4-4, 4-7 offset register restrictions . . . . . . . . . . . . 7-10 register restrictions . . . . . . . . . . . . . . . . . 7-10 registers . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 registers operands table . . . . . . . . . . . . . . a-5 and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-32 andi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-34 application development system . . . . . . . . . . 11-6 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 arithmetic instructions . . . . . . . . . . . . . . . . . . .6-22 asl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-36 asr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-38 assembler/simulator . . . . . . . . . . . . . . . . . . . .11-4 assistance . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16 ?b? b accumulator . . . . . . . . . . . . . . . . . . . . . . . . . .3-7 bchg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-40 bclr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-48 benchmark programs . . . . . . . . . . . . . . . . . . . b-3 binary operators . . . . . . . . . . . . . . . . . . . . . . . a-7 bit manipulation instructions . . . . . . . . . . . . . .6-24 bit reverse . . . . . . . . . . . . . . . . . . . . . . . . . . .4-22 bit weighing . . . . . . . . . . . . . . . . . . . . . . . . . .3-12 bset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-56 btst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-64 bus control signals . . . . . . . . . . . . . . . . . . 8-3, 8-5 buses address . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 transfers between . . . . . . . . . . . . . . . . . . . 2-5 byte, length of . . . . . . . . . . . . . . . . . . . . . . . . . .6-5 ?c? carry bit . . . . . . . . . . . . . . . . . . . . . . . . 5-10, a-18 c-compiler features . . . . . . . . . . . . . . . . . . . .11-5 ccr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9 ckout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10 considerations . . . . . . . . . . . . . . . . . . . . . 9-13 synch with extal . . . . . . . . . . . . . . . . . . 9-14 ckp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10 clgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10 clock stabilization delay . . . . . . . . . . . . . . . . .7-38 clr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-70 clvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10 cmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-72 cmpm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-74 condition code computations (table) . . . . . . a-19 condition code register (ccr) . . . . . . . 5-9, a-15 carry (bit 0) . . . . . . . . . . . . . . . . . . 5-10, a-18 extension (bit 5) . . . . . . . . . . . . . . . 5-11, a-16 limit (bit 6) . . . . . . . . . . . . . . . . . . . 5-11, a-16 negative (bit 3) . . . . . . . . . . . . . . . . 5-10, a-17 overflow (bit 1) . . . . . . . . . . . . . . . . 5-10, a-17 scaling (bit 7) . . . . . . . . . . . . . . . . . 5-11, a-16 symbols table . . . . . . . . . . . . . . . . . . . . . . . a-8 unnormalized (bit 4) . . . . . . . . . . . . 5-10, a-17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index (continued) index - 2 motorola zero (bit 2) . . . . . . . . . . . . . . . . . . . .5-10, a-17 condition codes . . . . . . . . . . . . . . . . . . . . . . . .a-3 convergent rounding . . . . . . . . . . . . . . . . . . . . 3-6 ?d? data alu double precision multiply mode . . . . . . . . 3-16 mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 mac and logic unit . . . . . . . . . . . . . . . . . . 3-6 programming model . . . . . . . . . . . . . . . . 3-19 summary . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 data alu accumulator registers . . . . . . . . . . . 3-7 data alu components . . . . . . . . . . . . . . . . . . . 3-3 data alu registers . . . . . . . . . . . . . . . . . 3-3, 6-6 input registers . . . . . . . . . . . . . . . . . . . . . . 3-5 operands table . . . . . . . . . . . . . . . . . . . . . a-5 data arithmetic logic unit (see data alu) . . . 3-3 data bus move field . . . . . . . . . . . . . . . . . . . . 6-5 data bus signals (d0-d15) . . . . . . . . . . . 8-3, 8-5 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 data conversion . . . . . . . . . . . . . . . . . . . . . . . 3-11 data organization . . . . . . . . . . . . . . . . . . . 6-6, 6-9 data shifter/limiter . . . . . . . . . . . . . . . . . . . . . . 3-9 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-76 debug mode entering . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 debug request input (dr) . . . . . . . . . . . . . . . 10-6 debug serial output (dso) . . . . . . . . . . . . . . 10-5 debugcc . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-78 dec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-80 design verification support . . . . . . . . . . . . . . 11-3 dfo-df3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-82 do . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-88 do instruction restrictions . . . . . . . . . . . . . . . . 7-8 do loop control . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 double precision multiply mode . . . . . . . . . . . 3-16 algorithm examples . . . . . . . . . . . . . . . . . 3-16 double precision multiply mode bit . . . . . . . . 5-13 dr. bub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 dsp applications . . . . . . . . . . . . . . . . . . . . . . . 1-7 dsp functions . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 dsp news . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 dsp56k central architecture central components . . . . . . . . . . . . . . . . . . 2-3 address buses . . . . . . . . . . . . . . . . . . 2-4 address generation unit . . . . . . . . . . . 2-5 data alu . . . . . . . . . . . . . . . . . . . . . . . 2-5 data buses . . . . . . . . . . . . . . . . . . . . . 2-3 memory expansion port (port a) . . . . . 2-6 on-chip emulator (once) . . . . . . . . . . 2-6 phase-locked loop (pll) based clocking . . . . . . . . . . . . 2-6 program control unit . . . . . . . . . . . . . . 2-5 ?e? edge sensitive . . . . . . . . . . . . . . . . . . . . . . . .7-16 edge triggered . . . . . . . . . . . . . . . . . . . . . . . . .5-6 electronic bulletin board . . . . . . . . . . . . . . . . .11-7 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . a-311 condition code and address . . . . . . . . . . a-315 double-bit register . . . . . . . . . . . . . . . . . a-312 effective addressing mode . . . . . . . . . . . a-315 five-bit register . . . . . . . . . . . . . . . . . . . . a-314 four-bit register . . . . . . . . . . . . . . . . . . . a-313 memory space bit . . . . . . . . . . . . . . . . . a-314 no parallel move . . . . . . . . . . . . . . . . . . a-318 nonmultiply instruction . . . . . . . . . . . . . . a-332 parallel instruction opcode . . . . . . . . . . . a-330 parallel move . . . . . . . . . . . . . . . . . . . . . a-316 program control unit registers . . . . . . . . a-315 single-bit register . . . . . . . . . . . . . . . . . . a-312 six-bit register . . . . . . . . . . . . . . . . . . . . a-314 triple bit register . . . . . . . . . . . . . . . . . . . a-313 write control . . . . . . . . . . . . . . . . . . . . . . a-314 enddo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-98 enddo instruction restrictions . . . . . . . . . . . .7-9 eor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-100 exception (interrupt) priorities . . . . . . . . . . . . .7-12 exception processing state . . . . . . . . . . . . . .7-10 extal synch w/ckout . . . . . . . . . . . . . . . . . . . 9-14 extension bit . . . . . . . . . . . . . . . . . . . . . 5-11, a-16 external interrupt request pins . . . . . . . . . . . .5-6 ?f? fast interrupt . . . . . . . . . . . . . . . . . . . . . 7-10, 7-12 fast interrupt execution . . . . . . . . . . . . . . . . .7-26 fft code . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 fir filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 frequency multiplication . . . . . . . . . . . . . . . . . .9-3 frequency multiplier . . . . . . . . . . . . . . . . . . . . .9-5 ?g? global data bus (gdb) . . . . . . . . . . . . . . . . . . .2-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index (continued) motorola index - 3 ?h? hardware do loop . . . . . . . . . . . . . . . . 6-24, a-88 hardware interrupt . . . . . . . . . . . . . . . . . . . . . 7-11 hardware interrupt sources . . . . . . . . . . . . . . 7-16 irqa . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 irqb . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 reset . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 hardware reset once pins and . . . . . . . . . . . . . . . . . . . . 10-5 help line . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 ?i? iir filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .b-3 illegal . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-102 illegal instruction interrupt (iii) . . . . . . . . . . . . 7-17 immediate data . . . . . . . . . . . . . . . . . . . . . . . 6-14 immediate short . . . . . . . . . . . . . . . . . . . . . . . 6-14 inc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-104 instruction descriptions . . . . . . . . . . . . . . . . .a-21 instruction encoding . . . . . . . . . . . . . . . . . . .a-311 instruction format . . . . . . . . . . . . . . . . . . . 6-3, a-3 instruction groups . . . . . . . . . . . . . . . . . . . . . 6-20 instruction guide . . . . . . . . . . . . . . . . . . . . . . .a-3 instruction pipeline . . . . . . . . . . . . . . . . . . 5-6, 7-3 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 instruction sequence restrictions . . . . . . . .a-305 instruction syntax . . . . . . . . . . . . . . . . . . . . . . . 6-3 instruction timing . . . . . . . . . . . . . . . . . . . . .a-294 instruction timing summary . . . . . . . . . . . . .a-301 instruction timing symbols . . . . . . . . . . . . . . .a-9 instructions arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 bit manipulation . . . . . . . . . . . . . . . . . . . . 6-24 logical . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 move . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 program control . . . . . . . . . . . . . . . . . . . . 6-27 interrupt fast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 hardware . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 long . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 restrictions . . . . . . . . . . . . . . . . . . . . . . . . 7-10 sources . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 interrupt arbitration . . . . . . . . . . . . . . . . . . . . . 7-24 interrupt control pins . . . . . . . . . . . . . . . . . . . . 2-6 interrupt controller . . . . . . . . . . . . . . . . . . . . . 7-24 interrupt delay possibilities . . . . . . . . . . . . . . 7-25 interrupt execution . . . . . . . . . . . . . . . . . . . . . 7-26 fast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 long . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29 interrupt instruction fetch . . . . . . . . . . . . . . . .7-24 instructions preceding . . . . . . . . . . . . . . . 7-25 interrupt masks . . . . . . . . . . . . . . . . . . . . . . . .5-12 interrupt priority levels (ipl) . . . . . . . . . 5-6, 7-14 interrupt priority register . . . . . . . . . . . . . . . .7-14 interrupt priority structure . . . . . . . . . . . . . . . .7-12 interrupt processing state . . . . . . . . . . . . . . . .7-10 interrupt sources . . . . . . . . . . . . . . . . . . . . . . .7-16 hardware . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 other . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 software . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 interrupt types . . . . . . . . . . . . . . . . . . . . . . . .7-12 ipl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14 irqa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6 irqb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6 ?j? jcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-106 jclr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-110 jmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-116 jscc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-118 jsclr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-122 jset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-130 jsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-136 jsset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-138 ?l? la . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5, 5-17 lc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5, 5-17 level sensitive . . . . . . . . . . . . . . . . . . . . 5-6, 7-16 limit bit . . . . . . . . . . . . . . . . . . . . . . . . . 5-11, a-16 limiting (saturation arithmetic) . . . . . . . . . . . . .3-9 linear arithmetic . . . . . . . . . . . . . . . . . . . . . . .4-14 linear modifier . . . . . . . . . . . . . . . . . . . . . . . .4-16 lock, pll, loss of . . . . . . . . . . . . . . . . . . . . . .9-13 logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 logical instructions . . . . . . . . . . . . . . . . . . . . .6-23 long interrupt . . . . . . . . . . . . . . . . . . . . . . . . .7-12 long interrupt execution . . . . . . . . . . . . . . . . .7-29 long word . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5 loop address (la) register . . . . . . . . . . 5-5, 5-17 loop counter (lc) register . . . . . . . . . . 5-5, 5-17 loop flag bit . . . . . . . . . . . . . . . . . . . . . . . . . .5-13 loop instructions . . . . . . . . . . . . . . . . . . . . . . .6-24 low power divider . . . . . . . . . . . . . . . . . . . . . .9-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index (continued) index - 4 motorola low power divider (lpd) . . . . . . . . . . . . . . . . . 9-5 lsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-144 lsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-146 lua . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-148 ?m? mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 3-13 mac instruction . . . . . . . . . . . . . . . . . . . . . .a-150 macr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-154 memory breakpoint control bits . . . . . . . . . . . 10-9 memory breakpoint occurrence bit . . . . . . . 10-11 memory upper limit register . . . . . . . . . . . . 10-12 mfo-mf11 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 moda/irqa . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 modb/irqb . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 modc/nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 mode control pins . . . . . . . . . . . . . . . . . . . . . . 2-6 mode register (mr) . . . . . . . . . . . . . . . . . . . . . 5-9 double precision multiply mode (bit 14) . . 5-13 interrupt masks (bits 8 and 9) . . . . . . . . . 5-12 loop flag (bit 15) . . . . . . . . . . . . . . . . . . . 5-13 scaling mode (bits 10 and 11) . . . . . . . . . 5-12 symbols table . . . . . . . . . . . . . . . . . . . . . . a-8 trace mode (bit 13) . . . . . . . . . . . . . 5-13, 7-22 modulo arithmetic . . . . . . . . . . . . . . . . . . . . . . 4-14 modulo modifier . . . . . . . . . . . . . . . . . . . . . . . 4-18 linear addressing . . . . . . . . . . . . . . . . . . . 4-18 multiple wrap-around addressing . . . . . . 4-21 move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-158 move instructions . . . . . . . . . . . . . . . . . . . . . . 6-26 move(c) . . . . . . . . . . . . . . . . . . . . . . . . . . .a-206 move(m) . . . . . . . . . . . . . . . . . . . . . . . . . . .a-214 movep . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-220 mpy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-228 mpyr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-232 ?n? neg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-236 negative bit . . . . . . . . . . . . . . . . . . . . . 5-10, a-17 nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6, 7-17 nonmaskable interrupt (nmi) . . . . . . . . . . . . . 7-17 nop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-238 norm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-240 normal processing state . . . . . . . . . . . . . . . . . 7-3 not . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-242 ?o? offset registers . . . . . . . . . . . . . . . . . . . . . . . .4-4 once . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 10-3 using the once . . . . . . . . . . . . . . . . . . . 10-20 once bit counter . . . . . . . . . . . . . . . . . . . . . .10-8 once commands . . . . . . . . . . . . . . . . . . . . .10-19 once controller . . . . . . . . . . . . . . . . . . . . . . .10-6 once decoder . . . . . . . . . . . . . . . . . . . . . . . .10-9 once memory breakpoint . . . . . . . . . . . . . .10-11 once pins . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 once serial interface . . . . . . . . . . . . . . . . . . .10-6 once status and control register . . . . . . . . .10-9 on-chip emulator (once) . . . . . . . . . . . . . . . .2-6 opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 opcode field . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5 operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 accumulator . . . . . . . . . . . . . . . . . . . . . . . . 6-5 byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 long word . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 miscellaneous . . . . . . . . . . . . . . . . . . . . . . a-7 short word . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 symbols for . . . . . . . . . . . . . . . . . . . . . . . . 6-9 word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 operating mode register (omr) . . . . . . 5-5, 5-14 stop delay (sd) bit . . . . . . . . . . . . . . . . . . 7-38 operation word . . . . . . . . . . . . . . . . . . . . . . . . .6-3 operators table, binary . . . . . . . . . . . . . . . . . . . . . . . . a-7 table, unary . . . . . . . . . . . . . . . . . . . . . . . . a-7 optional effective address extension word . . .6-3 or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-244 or(i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-246 overflow bit . . . . . . . . . . . . . . . . . . . . . . 5-10, a-17 overflow protection . . . . . . . . . . . . . . . . . . . . . .3-8 ?p? parallel move descriptions . . . . . . . . .a-20, a-160 address register update . . . . . . . . . . . . . a-172 immediate short data move . . . . . . . . . . a-164 long memory data move . . . . . . . . . . . . a-198 no parallel data move . . . . . . . . . . . . . . a-162 register and y memory data move . . . . a-192 register to register data move . . . . . . . . a-168 x memory and register data move . . . . a-180 x memory data move . . . . . . . . . . . . . . a-174 xy memory data move . . . . . . . . . . . . . a-202 y memory data move . . . . . . . . . . . . . . a-186 pc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5 pcap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index (continued) motorola index - 5 pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 phase detector . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 phase-locked loop (pll) . . . . . . . . . . . . 2-6, 9-3 pinit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 9-3 frequency multiplier . . . . . . . . . . . . . . . . . . 9-5 hardware reset and . . . . . . . . . . . . . . . . . 9-11 introduction . . . . . . . . . . . . . . . . . . . . . . . . 9-3 loss of lock . . . . . . . . . . . . . . . . . . . . . . . 9-13 low power divider . . . . . . . . . . . . . . . . . . . 9-5 operating frequency . . . . . . . . . . . . . . . . 9-11 operation while disabled . . . . . . . . . . . . . 9-12 phase detector . . . . . . . . . . . . . . . . . . . . . 9-4 pll control register . . . . . . . . . . . . . . . . . . 9-5 stop processing state and . . . . . . . . . . . . 9-13 voltage controlled oscillator (vco) . . . . . . 9-5 pll control register . . . . . . . . . . . . . . . . . . . . 9-5 division factor bits . . . . . . . . . . . . . . . . . . 9-12 multiplication factor bits . . . . . . . . . . . . . . 9-12 pll pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 ckout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 ckp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 clgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 clvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 pcap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 pinit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 plock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 pvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 plock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 8-3 port a interface . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 port a signals . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 bus control . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 data bus . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 port a address . . . . . . . . . . . . . . . . . . . . . 8-5 port a wait states . . . . . . . . . . . . . . . . . . . . . . 8-6 power consumption . . . . . . . . . . . . . . . . . . . . 7-37 processing states . . . . . . . . . . . . . . . . . . . . . . . 7-3 interrupt (exception) . . . . . . . . . . . . . . . . 7-10 normal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 program address bus (pab) . . . . . . . . . . . . . . 2-4 program address generator (pag) . . . . . . . . . 5-5 program control instructions . . . . . . . . . . . . . 6-27 program control registers omr and sr . . . . . . . . . . . . . . . . . . . . . . . 6-8 program control unit . . . . . . . . . . . . . . . . . . . . 5-3 loop address (la) . . . . . . . . . . . . . . . . . . . 2-6 loop counter (lc) . . . . . . . . . . . . . . . . . . . 2-6 operating mode register (omr) . . . . . . . . . 2-6 program address generator . . . . . . . . 2-5, 5-5 program counter (pc) . . . . . . . . . . . . . . . . 2-6 program decode controller . . . . . . . . . 2-5, 5-5 program interrupt controller . . . . . . . . 2-5, 5-6 registers operands table . . . . . . . . . . . . . . a-6 stack pointer (sp) . . . . . . . . . . . . . . . . . . . 2-6 status register (sr) . . . . . . . . . . . . . . . . . . 2-6 system stack . . . . . . . . . . . . . . . . . . . 2-5, 5-3 program counter (pc) . . . . . . . . . . . . . . . 5-5, 5-8 program data bus (pdb) . . . . . . . . . . . . . . . . .2-3 program decode controller . . . . . . . . . . . . . . .5-5 program interrupt controller . . . . . . . . . . . . . . .5-6 programming model agu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 data alu . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 program control unit . . . . . . . . . . . . . . . . . . 5-8 summary . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 pvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9 ?r? read/write controls . . . . . . . . . . . . . . . . . . . . .8-5 references memory . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 operand . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 program . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 register direct . . . . . . . . . . . . . . . . . . . . . . . .6-13 register indirect . . . . . . . . . . . . . . . . . . . . . . . .4-8 register references . . . . . . . . . . . . . . . . . . . .6-11 rep instruction . . . . . . . . . . . . . . . . . . . 5-5, a-248 reset instruction . . . . . . . . . . . . . . . . . . . . a-256 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6 reset processing state entering . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 leaving . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 pll and . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 reverse-carry arithmetic . . . . . . . . . . . . . . . .4-14 reverse-carry modifier . . . . . . . . . . . . . . . . . .4-22 rnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-258 rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-262 ror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-264 rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10 rti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-266 rti and rts instruction restrictions . . . . . . . .7-9 rts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-268 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index (continued) index - 6 motorola ?s? saturation arithmetic . . . . . . . . . . . . . . . . . . . . 3-9 sbc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-270 scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 scaling bit . . . . . . . . . . . . . . . . . . . . . . . 5-11, a-16 scaling mode bits . . . . . . . . . . . . . . . . . . . . . . 5-12 sd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 short jump . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 short word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 sign extension . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 simulator features . . . . . . . . . . . . . . . . . . . . . 11-5 software debug occurrence bit . . . . . . . . . . 10-11 software interrupt sources . . . . . . . . . . . . . . . 7-17 illegal instruction (iii) . . . . . . . . . . . . . . . . 7-18 swi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 sp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5, 5-15 ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 stack pointer (sp) register . . . . . . . . . . . . . . 5-15 restrictions . . . . . . . . . . . . . . . . . . . . . . . . 7-10 stack pointer register (sp) . . . . . . . . . . . . . . . 5-5 status register (sr) . . . . . . . . . . . . . . . . . 5-5, 5-9 condition code register . . . . . . . . . . . . . . . 5-9 mode register . . . . . . . . . . . . . . . . . . . . . . 5-9 stop cycles . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 stop delay bit . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 stop instruction . . . . . . . . . . . . . . . . 7-37, a-274 stop processing state . . . . . . . . . . . . . . . . . . 7-37 debug request during . . . . . . . . . . . . . . 10-15 pll and . . . . . . . . . . . . . . . . . . . . . . 7-41, 9-13 sub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-276 subl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-278 subr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-280 support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 swi instruction . . . . . . . . . . . . . . . . . . . . . . .a-282 syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 system stack (ss) . . . . . . . . . . . . . .5-3, 5-5, 5-14 system stack high (ssh) . . . . . . . . . . . . . 5-14 system stack high (ssh) restrictions . . . 7-10 system stack low (ssl) . . . . . . . . . . . . . . 5-14 system stack low (ssl) restrictions . . . . 7-10 ?t? tcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-284 technical assistance . . . . . . . . . . . . . . . . . . 11-16 tfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-288 timing calculations . . . . . . . . . . . . . . . . . . .a-294 timing skew . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 trace mode bit . . . . . . . . . . . . . . . . . . 5-13, 10-10 trace occurrence bit . . . . . . . . . . . . . . . . . . 10-11 tracing once trace logic . . . . . . . . . . . . . . . . . . 10-13 tracing (dsp56000/56001 only) . . . . . . . . . . .7-22 training . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17 tst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-290 ?u? unary operators . . . . . . . . . . . . . . . . . . . . . . . a-7 unnormalized bit . . . . . . . . . . . . . . . . . . 5-10, a-17 user support . . . . . . . . . . . . . . . . . . . . . . . . . .11-3 ?v? v-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-17 voltage controlled oscillator (vco) . . . . . . . . .9-5 ?w? wait instruction . . . . . . . . . . . . . . . . . 7-36, a-292 wait processing state . . . . . . . . . . . . . . . . . . .7-36 debug request during . . . . . . . . . . . . . . . 10-15 pll and . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 word length of . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 optional effective address extension . . . . . 6-3 ?x? x address bus (xab) . . . . . . . . . . . . . . . . . . . .2-4 x data bus (xdb) . . . . . . . . . . . . . . . . . . . . . . .2-3 ?y? y address bus (yab) . . . . . . . . . . . . . . . . . . . .2-4 y data bus (ydb) . . . . . . . . . . . . . . . . . . . . . . .2-3 ?z? zero bit . . . . . . . . . . . . . . . . . . . . . . . . . 5-10, a-17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
order this document by dsp56kfamum/ad motorola reserves the right to make changes without further notice to any products herein to im- prove reliability, function or design. motorola does not assume any liability arising out of the appli- cation or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. buyer agrees to notify motorola of any such intended end use whereupon motorola shall determine availability and suitability of its product or products for the use intended. motorola and m are registered trademarks of motorola, inc. motorola, inc. is an equal employment oppor- tunity /af?mative action employer. once ? is a trade mark of motorola, inc. ? motorola inc., 1994 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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