cy26580 packetclock? network applications clock cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07536 rev. *c revised may 22, 2008 features integrated phase-locked loop (pll) low-jitter, high-accuracy outputs 3.3v operation benefits internal pll with precision operation meets critical timing requirem ents in complex system designs enables application compatibility table 1. frequency table part number outputs input frequency output frequencies cy26580-1 2 125mhz or 25-mhz driven 100 mhz, 133.33 mhz table 2. input select options sel_25 sel_clk input type input frequency clk1 clk2 unit x 0 do not use 0 1 driven 125 133.33 100 mhz 1 1 driven 25 133.33 100 mhz logic block diagram clk output multiplexer and dividers pll osc. 133.33 mhz q p vco vdd gnd gnd 100 mhz vdd sel_25 sel_clk [+] feedback
cy26580 document #: 38-07536 rev. *c page 2 of 6 pin configuration figure 1. cy26580 20-pin ssop (qsop) 1 2 3 4 5 6 7 8 14 15 16 17 18 19 20 100 mhz gnd nc vdd nc sel_clk nc nc vdd 9 10 nc sel_25 12 11 13 nc nc nc nc nc clk nc 133 mhz gnd table 3. pin definition pin name pin number pin description nc 1 no connect nc 2 no connect clk 3 reference input v dd 4 voltage supply nc 5 no connect gnd 6 ground nc 7 no connect nc 8 no connect nc 9 no connect 133 mhz 10 133.33-mhz clock output sel_25 11 reference frequency select input; 0 = 125 mhz, 1 = 25 mhz, weak internal pull up nc 12 no connect nc 13 no connect gnd 14 ground nc 15 no connect v dd 16 voltage supply 100 mhz 17 100-mhz clock output nc 18 no connect sel_clk 19 reference select input; set to 1 = driven, weak internal pull up nc 20 no connect [+] feedback
cy26580 document #: 38-07536 rev. *c page 3 of 6 absolute maximum conditions [1] supply voltage (v dd )........................................ ?0.5 to +7.0v dc input voltage ....................................... ?0.5v to v dd +0.5 storage temperature (non-condensing) .... ?55 c to +125 c junction temperature ................................ ?40 c to +125 c data retention at tj = 125 c ................................> 10 years package power dissipation...................................... 350 mw esd (human body model) mil- std-883......... ........... 2000v figure 2. test and measurement setup notes 1. above which the useful life may be impaired. for user guidelines, not tested. 2. guaranteed by characterization, not 100% tested. recommended oper ating conditions parameter description min typ. max unit v dd supply voltage 3.14 3.3 3.47 v t a , i-grade ambient temperature, industrial ?40 ? 85 c c load max. load capacitance ? ? 15 pf f ref reference frequency ? 125, 25 ? mhz dc electrical specifications parameter [2] description conditions min typ. max unit i oh output high current v oh = v dd ? 0.5, v dd = 3.3v 12 24 ? ma i ol output low current v ol = 0.5, v dd = 3.3v 12 24 ? ma i ih input high current v ih = v dd ?510 a i il input low current v il = 0v ? ? 50 a v ih input high voltage cmos levels, 70% of v dd 0.7 ? ? v dd v il input low voltage cmos levels, 30% of v dd ??0.3v dd i dd supply current v dd current, no load ? 35 50 ma r up pull up resistor on inputs v dd = 3.14 to 3.47v, measured v in = 0v ? 100 150 k ac electrical specifications parameter [2] description conditions min typ. max unit f error frequency error all clocks 0 ppm dc output duty cycle duty cycle is defined in figure 3 , 50% of v dd 45 50 55 % er rising edge rate output clock edge rate, measured from 20% to 80% of v dd , c load = 15 pf. see figure 4 . 0.8 1.4 2 v/ns ef falling edge rate output clock edge rate, measured from 80% to 20% of v dd , c load = 15 pf. see figure 4 . 0.8 1.4 2 v/ns t 9 clock jitter clk1, clk2 peak-peak period jitter ? 100 ? ps t 10 pll lock time ? ? 3 ms 0.1 f v dds outputs c load gnd dut [+] feedback
cy26580 document #: 38-07536 rev. *c page 4 of 6 voltage and timing definitions figure 3. duty cycle definition figure 4. er = (0.6 x v dd ) /t3, ef = (0.6 x v dd ) /t4 clock output v dd 50% of v dd 0v t 1 t 2 clock output t 3 t 4 v dd 80% of v dd 20% of v dd 0v ordering information ordering code [3] package type temperature range operating voltage cy26580oi?2 [4] 20-pin ssop (qsop) industrial 3.3v cy26580oi?2t [4] 20-pin ssop (qsop) ? tape and reel industrial 3.3v cy26580koi?2 20-pin ssop (qsop) industrial 3.3v cy26580koi?2t 20-pin ssop (qsop) ? tape and reel industrial 3.3v pb-free cy26580kqxi?2 20-pin ssop (qsop) industrial 3.3v cy26580kqxi?2t 20-pin ssop (qsop) ? tape and reel industrial 3.3v notes 3. part numbers ending in -1 and -1t have been replaced by part nu mbers ending in -2 and -2t. specifications for -1, -1t, -2 and -2t part numbers are identical. 4. not recommended for new designs. [+] feedback
cy26580 document #: 38-07536 rev. *c page 5 of 6 package drawing and dimensions figure 5. 20-lead qsop o201 and sq201 51-85054-*b [+] feedback
document #: 38-07536 rev. *c revised may 22, 2008 page 6 of 6 packetclock is a trademark of cypress semiconductor. all product and company names mentioned in this document may be the tradem arks of their respective holders. all products and company names mentioned in this document may be the trademarks of their respective holders. cy26580 ? cypress semiconductor corporation, 2008. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy26580 packetcloc k? network applications clock document #: 38-07536 rev. *c rev. ecn no. submission date orig. of change description of change ** 127357 06/17/03 rgl new data sheet *a 128564 09/12/03 ija change pin 1 to nc and pin 3 to clk *b 216828 see ecn rgl removed preliminary *c 2442066 see ecn kvm/aesa updated template. added note ?not recommended for new designs.? added note explaining ?-1? and ?-2? part numbers. removed part numbers cy26580oi-1 and cy26580oi-1t. added part number cy26580oi?2t, cy26580koi?2, cy26580koi?2t, cy26580kqxi?2, and cy26580kqxi?2t in ordering information table. updated figure caption for package drawing. [+] feedback
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