tm 74actq533 quiet series octal transparent latch with 3-state outputs may 2007 ?990 fairchild semiconductor corporation www.fairchildsemi.com 74actq533 rev. 1.3 74actq533 quiet series octal transparent latch with 3-state outputs features i cc and i oz reduced by 50% guaranteed simultaneous switching noise level and dynamic threshold performance guaranteed pin-to-pin skew ac performance improved latch up immunity eight latches in a single package 3-state outputs drive bus lines or buffer memory address registers outputs source/sink 24ma inverted version of the actq373 4kv minimum esd immunity general description the actq533 consists of eight latches with 3-state outputs for bus organized system applications. the flip- flops appear transparent to the data when latch enable (le) is high. when le is low, the data satisfying the input timing requirements is latched. data appears on the bus when the output enable (oe) is low. when oe is high, the bus output is in the high impedance state. the actq533 utilizes fairchild quiet series technol- ogy to guarantee quiet output switching and improve dynamic threshold performance. fact quiet series fea- tures gto output control and undershoot corrector in addition to a split ground bus for superior performance. ordering information device also available in tape and reel. specify by appending suffix letter ??to the ordering number. connection diagram pin description order number package number package description 74actq533sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide body 74actq533mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pin names description d 0 ? 7 data inputs le latch enable input oe output enable input o 0 ? 7 3-state latch outputs fact , fact quiet series , and gto are trademarks of fairchild semiconductor corporation.
74actq533 quiet series octal transparent latch with 3-state outputs ?990 fairchild semiconductor corporation www.fairchildsemi.com 74actq533 rev. 1.3 2 logic symbols ieee/iec truth table h = high voltage level l = low voltage level z = high impedance x = immaterial o 0 = previous o 0 before high-to-low transition of latch enable functional description the actq533 contains eight d-type latches with 3-state standard outputs. when the latch enable (le) input is high, data on the d n inputs enters the latches. in this condition the latches are transparent, i.e., a latch output will change state each time its d input changes. when le is low, the latches store the information that was present on the d inputs at setup time preceding the high-to-low transition of le. the 3-state standard outputs are controlled by the output enable (oe ) input. when oe is low, the standard outputs are in the 2-state mode. when oe is high, the standard outputs are in the high impedance mode but this does not inter- fere with entering new data into the latches. logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. inputs outputs le oe d n o n x h x z h l l h h l h l l l x o 0
74actq533 quiet series octal transparent latch with 3-state outputs ?990 fairchild semiconductor corporation www.fairchildsemi.com 74actq533 rev. 1.3 3 absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter rating v cc supply voltage ?.5v to +7.0v i ik dc input diode current v i = ?.5v v i = v cc + 0.5v ?0ma +20ma v i dc input voltage ?.5v to v cc + 0.5v i ok dc output diode current v o = ?.5v v o = v cc + 0.5v ?0ma +20ma v o dc output voltage ?.5v to v cc + 0.5v i o dc output source or sink current ?0ma i cc or i gnd dc v cc or ground current per output pin ?0ma t stg storage temperature ?5? to +150? dc latch-up source or sink current ?00ma t j j unction temperature 140? symbol parameter rating v cc supply voltage 4.5v to 5.5v v i input voltage 0v to v cc v o output voltage 0v to v cc t a operating temperature ?0? to +85? ? v / ? t minimum input edge rate: v in from 0.8v to 2.0v, v cc @ 4.5v, 5.5v 125mv/ns
74actq533 quiet series octal transparent latch with 3-state outputs ?990 fairchild semiconductor corporation www.fairchildsemi.com 74actq533 rev. 1.3 4 dc electrical characteristics notes: 1. all outputs loaded; thresholds on input associated with output under test. 2. maximum test duration 2.0ms, one output loaded at a time. 3. max number of outputs defined as (n). data inputs are driven 0v to 3v. one output @ gnd. 4. max number of data inputs (n) switching. (n?) inputs switching 0v to 3v input-under-test switching: 3v to threshold (v ild ), 0v to threshold (v ihd ), f = 1 mhz. symbol parameter v cc (v) conditions t a = +25? t a = ?0? to +85? units t yp. guaranteed limits v ih minimum high level input voltage 4.5 v out = 0.1v or v cc ?0.1v 1.5 2.0 2.0 v 5.5 1.5 2.0 2.0 v il maximum low level input voltage 4.5 v out = 0.1v or v cc ?0.1v 1.5 0.8 0.8 v 5.5 1.5 0.8 0.8 v oh minimum high level output voltage 4.5 i out = ?0? 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 v in = v il or v ih : 4.5 i oh = ?4ma 3.86 3.76 5.5 i oh = ?4ma (1) 4.86 4.76 v ol maximum low level output voltage 4.5 i out = 50? 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 v in = v il or v ih : 4.5 i ol = 24ma 0.36 0.44 5.5 i ol = 24ma (1) 0.36 0.44 i in maximum input leakage current 5.5 v i = v cc , gnd ?.1 ?.0 ? i oz maximum 3-state leakage current 5.5 v i = v il , v ih ; v o = v cc , gnd ?.25 ?.5 ? i cct maximum i cc /input 5.5 v i = v cc ?2.1v 0.6 1.5 ma i old minimum dynamic output current (2) 5.5 v old = 1.65v max. 75 ma i ohd 5.5 v ohd = 3.85v min. ?5 ma i cc maximum quiescent supply current 5.5 v in = v cc or gnd 4.0 40.0 ? v olp quiet output maximum dynamic v ol 5.0 figures 1 & 2 (3) 1.1 1.5 v v olv quiet output minimum dynamic v ol 5.0 figures 1 & 2 (3) ?.6 ?.2 v v ihd minimum high level dynamic input voltage 5.0 (4) 1.9 2.2 v v ild maximum low level dynamic input voltage 5.0 (4) 1.2 0.8 v
74actq533 quiet series octal transparent latch with 3-state outputs ?990 fairchild semiconductor corporation www.fairchildsemi.com 74actq533 rev. 1.3 5 ac electrical characteristics notes: 5. voltage range 5.0 is 5.0v ?0.5v. 6. skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). parameter guaranteed by design. ac operating requirements note: 7. voltage range 5.0 is 5.0v ?0.5v. capacitance symbol parameter v cc (v) (5) t a = +25?, c l = 50pf t a = ?0? to +85?, c l = 50pf units min. typ. max. min. max. t phl , t plh propagation delay, d n to o n 5.0 2.0 6.0 8.0 2.0 8.5 ns t phl , t plh propagation delay, le to o n 5.0 2.5 7.0 9.0 2.5 9.5 ns t pzl , t pzh output enable time 5.0 2.0 7.0 9.0 2.0 9.5 ns t phz , t plz output disable time 5.0 1.0 8.0 10.0 1.0 10.5 ns t oshl , t oslh output to output skew, d n to o n (6) 5.0 0.5 1.0 1.0 ns symbol parameter v cc (v) (7) t a = +25?, c l = 50pf t a = ?0? to +85?, c l = 50pf units t yp. guaranteed minimum t s setup time, high or low, d n to le 5.0 0 3.0 3.0 ns t h hold time, high or low, d n to le 5.0 0 1.5 1.5 ns t w le pulse width, high 5.0 2.0 4.0 4.0 ns symbol parameter conditions typ. units c in input capacitance v cc = open 4.5 pf c pd power dissipation capacitance v cc = 5.0v 40 pf
74actq533 quiet series octal transparent latch with 3-state outputs ?990 fairchild semiconductor corporation www.fairchildsemi.com 74actq533 rev. 1.3 6 fa ct noise characteristics the setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. the following is a brief description of the setup used to measure the noise characteristics of fact. equipment: hewlett packard model 8180a word generator pc-163a test fixture tektronics model 7854 oscilloscope procedure: 1. verify test fixture loading: standard load 50pf, 500 ? . 2. deskew the hfs generator so that no two channels have greater than 150ps skew between them. this requires that the oscilloscope be deskewed ?st. it is important to deskew the hfs generator channels before testing. this will ensure that the outputs switch simultaneously. 3. terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. set the hfs generator to toggle all but one output at a frequency of 1mhz. greater frequencies will increase dut heating and effect the results of the measurement. 5. set the hfs generator input levels at 0v low and 3v high for act devices and 0v low and 5v high f or ac devices. verify levels with a digital volt meter. notes: 8. v ohv and v olp are measured with respect to ground reference. 9. input pulses have the following characteristics: f = 1mhz, t r = 3ns, t f = 3ns, skew < 150ps. figure 1. quiet output noise voltage waveforms v olp /v olv and v ohp /v ohv : determine the quiet output pin that demonstrates the greatest noise levels. the worst case pin will usually be the furthest from the ground pin. monitor the output voltages using a 50 ? coaxial cable plugged into a standard smb type connector on the test fixture. do not use an active fet probe. measure v olp and v olv on the quiet output during the worst case transition for active and enable. measure v ohp and v ohv on the quiet output during the worst case active and enable transition. verify that the gnd reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. v ild and v ihd : monitor one of the switching outputs using a 50 ? coaxial cable plugged into a standard smb type connector on the test fixture. do not use an active fet probe. first increase the input low voltage level, v il , until the output begins to oscillate or steps out a min of 2ns. oscillation is defined as noise on the output low level that exceeds v il limits, or on output high levels that exceed v ih limits. the input low voltage level at which oscillation occurs is defined as v ild . next decrease the input high voltage level on the v ih until the output begins to oscillate or steps out a min of 2ns. oscillation is defined as noise on the output low level that exceeds v il limits, or on output high levels that exceed v ih limits. the input high voltage level at which oscillation occurs is defined as v ihd . verify that the gnd reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. figure 2. simultaneous switching test circuit
74actq533 quiet series octal transparent latch with 3-state outputs ?990 fairchild semiconductor corporation www.fairchildsemi.com 74actq533 rev. 1.3 7 physical dimensions dimensions are in inches (millimeters) unless otherwise noted. figure 3. 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide pa ck ag e number m20b
74actq533 quiet series octal transparent latch with 3-state outputs ?990 fairchild semiconductor corporation www.fairchildsemi.com 74actq533 rev. 1.3 8 physical dimensions (continued) dimensions are in millimeters unless otherwise noted. figure 4. 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pa ck ag e number mtc20
74actq533 quiet series octal transparent latch with 3-state outputs ?990 fairchild semiconductor corporation www.fairchildsemi.com 74actq533 rev. 1.3 9 trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. acex across the board. around the world. activearray bottomless build it now coolfet crossvolt ctl current transfer logic dome e 2 cmos ecospark ensigna fact quiet series fact fast fastr fps frfet globaloptoisolator gto hisec i-lo implieddisconnect intellimax isoplanar microcoupler micropak microwire motion-spm msx msxpro ocx ocxpro optologic optoplanar pacman pdp-spm pop power220 power247 poweredge powersaver power-spm powertrench programmable active droop qfet qs qt optoelectronics quiet series rapidconfigure rapidconnect scalarpump smart start spm stealth superfet supersot -3 supersot -6 supersot -8 syncfet tcm the power franchise tinyboost tinybuck tinylogic tinyopto tinypower tinywire trutranslation serdes uhc unifet vcx wire disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild? worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems wh ich, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform w hen properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary this datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production first production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. rev. i26
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