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dram module KMM5322104CKU/ckug KMM5322104CKU/ckug fast page mode with extended data out 2m x 32 dram simm using 2mx8 , 2k refresh, 5v the samsung KMM5322104CKU is a 2mx32bits dynamic ram high density memory module. the samsung KMM5322104CKU consists of four cmos 2mx8bits drams in 28-pin soj package mounted on a 72-pin glass-epoxy sub- strate. a 0.1 or 0.22uf decoupling capacitor is mounted on the printed circuit board for each dram. the KMM5322104CKU is a single in-line memory module with edge connections and is intended for mounting into 72 pin edge connector sockets. ? part identification - KMM5322104CKU(2048 cycles/32ms ref, soj, solder) - KMM5322104CKUg(2048 cycles/32ms ref, soj, gold) ? fast page mode with extended data out ? cas -before- ras refresh capability ? ras -only and hidden refresh capability ? ttl compatible inputs and outputs ? single +5v 10% power supply ? jedec standard pdpin & pinout ? pcb : height(1000mil), single sided component general description features performance range speed t rac t cac t rc t hpc -5 50ns 13ns 90ns 25ns -6 60ns 15ns 110ns 30ns pin names pin name function a0 - a10 address inputs dq0 - dq31 data in/out w read/write enable ras0 row address strobe cas0 - cas3 column address strobe pd1 -pd4 presence detect vcc power(+5v) vss ground nc no connection res reserved pin presence detect pins (optional) * pin connection changing available pin 50ns 60ns pd1 pd2 pd3 pd4 nc nc vss vss nc nc nc nc pin configurations pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 symbol v ss dq0 dq18 dq1 dq19 dq2 dq20 dq3 dq21 vcc nc a0 a1 a2 a3 a4 a5 a6 a10 dq4 dq22 dq5 dq23 dq6 dq24 dq7 dq25 a7 res(a11) vcc a8 a9 res( ras1 ) ras0 nc nc pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 symbol nc nc vss cas0 cas2 cas3 cas1 ras0 res( ras1 ) nc w nc dq9 dq27 dq10 dq28 dq11 dq29 dq12 dq30 dq13 dq31 vcc dq32 dq14 dq33 dq15 dq34 dq16 nc pd1 pd2 pd3 pd4 nc vss samsung electronics co., ltd. reserves the right to change products and specifications without notice.
dram module KMM5322104CKU/ckug functional block diagram dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 w a0-a10 vcc vss .1 or .22uf capacitor for each dram to all drams dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 a0-a10 w u0 u1 u2 u3 w a0-a10 w a0-a10 w a0-a10 dq24-dq31 dq16-dq23 dq8-dq15 dq0-dq7 ras0 cas0 cas1 cas2 cas3 ras cas oe ras cas oe ras cas oe ras cas oe
dram module KMM5322104CKU/ckug i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one edo mode cycle, t hpc . * note : absolute maximum ratings * * permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for in tended periods may affect device reliability. item symbol rating unit voltage on any pin relative to v ss voltage on v cc supply relative to v ss storage temperature power dissipation short circuit output current v in , v out v cc t stg p d i os -1 to +7.0 -1 to +7.0 -55 to +150 4 50 v v c w ma recommended operating conditions (voltage referenced to v ss , t a = 0 to 70 c) *1 : v cc +2.0v/ 20ns, pulse width is measured at v cc . *2 : -2.0v/ 20ns, pulse width is measured at v ss . item symbol min typ max unit supply voltage ground input high voltage input low voltage v cc v ss v ih v il 4.5 0 2.4 -1.0 *2 5.0 0 - - 5.5 0 v cc +1 *1 0.8 v v v v dc and operating characteristics (recommended operating conditions unless otherwise noted) i cc1 i cc2 i cc3 i cc4 i cc5 i cc6 i i(l) i o(l) v oh v ol symbol speed KMM5322104CKU/ckug unit min max i cc1 -5 -6 - - 440 400 ma ma i cc2 don t care - 8 ma i cc3 -5 -6 - - 440 400 ma ma i cc4 -5 -6 - - 360 320 ma ma i cc5 don t care - 4 ma i cc6 -5 -6 - - 440 400 ma ma i i(l) i o(l) don t care -20 -5 20 5 ua ua v oh v ol don t care 2.4 - - 0.4 v v : operating current * ( ras , cas , address cycling @ t rc =min) : standby current ( ras = cas = w =v ih ) : ras only refresh current * ( cas =v ih , ras cycling @ t rc =min) : edo mode current * ( ras =v il , cas cycling : t hpc =min) : standby current ( ras = cas = w =vcc-0.2v) : cas -before- ras refresh current * ( ras and cas cycling @ t rc =min) : input leakage current (any input 0 v in vcc+0.5v, all other pins not under test=0 v) : output leakage current(data out is disabled, 0v v out vcc) : output high voltage level (i oh = -5ma) : output low voltage level (i ol = 4.2ma)
dram module KMM5322104CKU/ckug capacitance (t a = 25 c, v cc =5v, f = 1mhz) item symbol min max unit input capacitance[a0-a10] input capacitance[ w ] input capacitance[ ras0 ] input capacitance[ cas0 - cas3 ] input/output capacitance[dq0-31] c in1 c in2 c in3 c in4 c dq - - - - - 35 40 40 20 20 pf pf pf pf pf test condition : v ih /v il =2.4/0.8v, v oh /v ol =2.0/0.8v, output loading cl=100pf parameter symbol -5 -6 unit note min max min max random read or write cycle time t rc 90 110 ns access time from ras t rac 50 60 ns 3,4,10 access time from cas t cac 13 15 ns 3,4,5 access time from column address t aa 25 30 ns 3,10 cas to output in low-z t clz 3 3 ns 3 output buffer turn-off delay from cas t cez 3 13 3 15 ns 6,11,12 transition time(rise and fall) t t 2 50 2 50 ns 2 ras precharge time t rp 30 40 ns ras pulse width t ras 50 10k 60 10k ns ras hold time t rsh 13 15 ns cas hold time t csh 40 50 ns cas pulse width t cas 8 10k 10 10k ns 13 ras to cas delay time t rcd 20 37 20 45 ns 4 ras to column address delay time t rad 15 25 15 30 ns 10 cas to ras precharge time t crp 5 5 ns row address set-up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set-up time t asc 0 0 ns column address hold time t cah 8 10 ns column address to ras lead time t ral 25 30 ns read command set-up time t rcs 0 0 ns read command hold time referenced to cas t rch 0 0 ns 8 read command hold time referenced to ras t rrh 0 0 ns 8 write command hold time t wch 10 10 ns write command pulse width t wp 10 10 ns write command to ras lead time t rwl 13 15 ns write command to cas lead time t cwl 8 10 ns data-in set-up time t ds 0 0 ns 9 data-in hold time t dh 8 10 ns 9 refresh period t ref 32 32 ms write command set-up time t wcs 0 0 ns 7 cas setup time( cas -before- ras refresh) t csr 5 5 ns cas hold time( cas -before- ras refresh) t chr 10 10 ns ras precharge to cas hold time t rpc 5 5 ns cas precharge time ( c -b- r counter test) t cpt 20 20 ns ac characteristics (0 c t a 70 c, v cc =5.0v 10%. see notes 1,2.)
dram module KMM5322104CKU/ckug notes an initial pause of 200us is required after power-up followed by any 8 ras -only or cas -before- ras refresh cycles before proper device operation is achieved. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) and are assumed to be 5ns for all inputs. measured with a load equivalent to 2 ttl loads and 100pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes that t rcd 3 t rcd (max). this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . t wcs is non-restrictive operating parameter. it is included in the data sheet as electrical characteristic s only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. either t rch or t rrh must be satisfied for a read cycle. these parameters are referenced to the cas leading edge in early write cycles and to the w leading edge in read-write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . t cez (max), t rez (max), t wez (max) and t oez (max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage level. if ras goes to high before cas high going, the open circuit condtion of the output is achieved by cas high going. if cas goes to high before ras high going, the open circuit condtion of the output is achieved by ras high going. t asc 3 t cp min 1. 2. 3. 4. 5. 8. 9. 10. test condition : v ih /v il =2.4/0.8v, v oh /v ol =2.0/0.8v, output loading cl=100pf parameter symbol -5 -6 unit note min max min max access time from cas precharge t cpa 30 35 ns 3 hyper page mode cycle time t hpc 25 30 ns 13 cas precharge time from (hyper page cycle) t cp 8 10 ns ras pulse width (hyper page cycle) t rasp 50 200k 60 200k ns ras hold time from cas precharge t rhcp 30 35 ns w to ras precharge time ( c -b- r refresh) t wrp 10 10 ns w to ras hold time ( c -b- r refresh) t wrh 10 10 ns output data hold time t doh 5 5 ns output buffer turn off delay from ras t rez 3 13 3 15 ns 6,11,12 output buffer turn off delay from w t wez 3 13 3 15 ns 6,11 w to data delay t wed 15 15 ns w pulse width (hyper page cycle) t wpe 5 5 ns ac characteristics (0 c t a 70 c, v cc =5.0v 10%. see notes 1,2.) 11. 12. 13. 6. 7.
dram module KMM5322104CKU/ckug ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - v oh - v ol - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t asr t rah t asc t cah t crp t aa t clz t rac open t rch don t care undefined t rad t rrh data-out t rez t rcs read cycle t cez t wez dq t cac
dram module KMM5322104CKU/ckug t wcs note : d out = open write cycle ( early write ) ras v ih - v il - v ih - v il - a v ih - v il - w v ih - v il - v ih - v il - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp don t care undefined t wch t wp cas t rwl t cwl t ds t dh data-in dq
dram module KMM5322104CKU/ckug t doh hyper page read cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - column address row addr t rasp t rp t rcd t asr t crp don t care undefined v oh - v ol - dq column address t cas t cas t cas t cas t cp t cp t cp t hpc t hpc t hpc t rhcp t csh t rad t rah t asc t cah t cah t cah t asc t cah t rcs t aa t rch t asc column address column addr valid data-out t aa t cac t aa t cpa t cpa valid data-out valid data-out t clz t rac t cac t rrh t rez t cac t cpa t cac ? t asc t aa t doh valid data-out t doh
dram module KMM5322104CKU/ckug ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - column address row addr. t rasp t rp t rcd t asr t crp don t care hyper page write cycle ( early write ) undefined v ih - v il - dq t rhcp t rad t rah t cah t cah t asc t cah t asc valid data-in t ds ? column address column address t cas t cp t cas t cp t cas t rsh ? t csh t asc ? ? t wp t wcs t wch t wp t wcs t wch t wp t wcs t wch ? valid data-in valid data-in ? ? t dh t ds t dh t ds t dh t cwl t cwl t cwl t rwl note : d out = open t hpc t hpc
dram module KMM5322104CKU/ckug don t care ras - only refresh cycle* note : w , oe , d in = don t care undefined d out = open ras v ih - v il - cas v ih - v il - a v ih - v il - row addr t rc t rp t asr t crp t ras t rah t rpc t crp open cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rc t rp t ras t rpc t cp t rpc t csr t chr t cez v oh - v ol - dq t wrp t wrh w v ih - v il - t rp * in ras -only refresh cycle of 64mb a-dile & b-die, when cas signal transits from low to high, the valid data may be cut off.
dram module KMM5322104CKU/ckug hidden refresh cycle ( read ) data-out t rp ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - row address t ras t rc t chr t rcd t rsh t rad t asr t rah t asc t crp don t care undefined v oh - v ol - dq t wrh t rrh column address t ras t rc t cah t rcs t aa t rac t clz t cac t cez open t rp t wez t rez t wrp
dram module KMM5322104CKU/ckug t crp t wcs t rp ras v ih - v il - a v ih - v il - w v ih - v il - row address t ras t rc t rad t asr t rah t asc don t care hidden refresh cycle ( write ) undefined cas v ih - v il - v ih - v il - dq t rsh t rcd t wrh column address t ras t rc t chr t cah t wrp t ds note : d out = open t wp t wch data-in t dh t rp
dram module KMM5322104CKU/ckug cas -before- ras refresh counter test cycle ras v ih - v il - cas v ih - v il - a v ih - v il - column address t ras t rsh t chr t ral t csr t cpt t rp t cas t asc t cah read cycle v oh - v ol - data-out dq t rez t clz write cycle v ih - v il - data-in dq t dh t ds don t care undefined t wrp t wrh t rrh t rch t rcs t cac t aa v ih - v il - w t wrp t wrh t wcs t wch t cwl v ih - v il - w t wp t rwl note : this timing diagram is applied to all devices besides 64m dram based modules. t cez t wez
dram module KMM5322104CKU/ckug open cas - before - ras self refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rps t rass t rpc t cp t rpc t csr t cez v oh - v ol - dq t rp don t care undefined t chs t wrp t wrh w v ih - v il - open test mode in cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rp t rc t rpc t cp t rpc t csr t cez v oh - v ol - dq t wts t wth w v ih - v il - t chr t rp t ras
dram module KMM5322104CKU/ckug package dimensions .133(3.38) 4.250(107.95) 3.984(101.19) .125(3.17) r.062 .004(r1.57 .10) .250 (6.35) 3.750(95.25) .250(6.35) units : inches (millimeters) gold & solder plating lead .010(.25)max .050(1.27) .041 .004(1.04 .10) .100(2.54) min .200(5.08) max .054 (1.37) tolerances : .005(.13) unless otherwise specified note : the used device is 2mx8 dram dram part no. : KMM5322104CKU/ckug -- km48c2104ck (300mil) 1.00(24.50) min .400(10.16) .125 dia .002(3.18 .051) r.062(1.57) .250(6.35) .080(2.03) .047(1.19) ( back view ) ( front view ) revision history rev 0.0 : aug. 1997 .

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