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TC59LM818DMB-30,-33,-40 2003-02-28 1/55 tentative toshiba mos digital integrated circuit silicon monolithic 4,194,304-words 4 banks 18-bits network fcram tm description network fcram tm is double data rate fast cycle random access memory. TC59LM818DMB is network fcram tm containing 301,989,888 memory cells. TC59LM818DMB is organized as 4,194,304-words 4 banks 18 bits. TC59LM818DMB feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM818DMB can operate fast core cycl e compared with regular ddr sdram. TC59LM818DMB is suitable for network, server and other applications where large memory density and low power consumption are required. the output driver for network fcram tm is capable of high quality fast data transfer under light loading condition. features TC59LM818DMB parameter -30 -33 -40 cl = 4 4.0 ns 4.5 ns 5.0 ns cl = 5 3.33 ns 3.75 ns 4.5 ns t ck clock cycle time (min) cl = 6 3.0 ns 3.33 ns 4.0 ns t rc random read/write cycle time (min) 20.0 ns 22.5 ns 25 ns t rac random access time (max) 20.0 ns 22.5 ns 25 ns i dd1s operating current (single bank) (max) 250 ma 235 ma 210 ma l dd2p power down current (max) 60ma 55 ma 50 ma l dd6 self-refresh current (max) 10 ma 10 ma 10 ma ? fully synchronous operation ? double data rate (ddr) data input/output are synchronized with both edges of ds / qs. ? differential clock (clk and clk ) inputs cs , fn and all address input signals are sampled on the positive edge of clk. output data (dqs and qs) is aligned to the crossings of clk and clk . ? fast clock cycle time of 3.0 ns minimum clock: 333 mhz maximum data: 666 mbps/pin maximum ? quad independent banks operation ? fast cycle and short latency ? selectable data strobe ? distributed auto-refresh cycle in 3.9 s ? self-refresh ? power down mode ? variable write length control ? write latency = cas latency-1 ? programable cas latency and burst length cas latency = 4, 5, 6 burst length = 2, 4 ? organization: 4,194,304 words 4 banks 18 bits ? power supply voltage v dd : 2.5 v 0.125v v ddq : 1.4 v ~ 1.9 v ? low voltage cmos i/o covered with sstl-18 (half strength driver) and hstl ? package: 60ball bga, 1mm 1mm ball pitch (p-bga60-0917-1.00az) notice: fcram is trademark of fujitsu limited, japan. ( datasheet : )
TC59LM818DMB-30,-33,-40 2003-02-28 2/55 pin names pin assignment (top view) pin name a0~a14 address input ba0, ba1 bank address dq0~dq17 data input/output cs chip select fn function control pd power down control clk, clk clock input ds / qs write/read data strobe v dd power ( + 2.5 v) v ss ground v ddq power ( + 1.5 v, +1.8 v) (for dq buffer) v ssq ground (for dq buffer) v ref reference voltage nc not connected 5 a b c d e f g h j k 1 3 6 4 2 x18 inde x l m n p r v ss dq17 dq0 v dd dq16 v ss q v dd q dq1 dq15 v dd q v ss q dq2 dq14 dq13 dq4 dq3 dq12 v ss q v dd q dq5 dq11 v dd q v ss q dq6 dq10 v ss q v dd q dq7 dq9 ds qs dq8 vref v ss v dd a14 clk clk fn a13 nc a12 pd cs ba0 a11 a9 ba1 a10 a8 a7 a0 a1 a5 a6 a2 v dd v ss a4 a3 ball pitch=1.0 x 1.0mm : depopulated ball
TC59LM818DMB-30,-33,-40 2003-02-28 3/55 block diagram note: the TC59LM818DMB configuration is 4 bank of 32768 128 18 of cell array with the dq pins numbered dq0~dq17. dq0~dq17 bank #1 dll clock buffer clk clk pd to each block command decoder cs fn address buffer control signal generator mode register refresh counter a0~a14 ba0, ba1 bank #0 memory cell array column decoder row decoder burst counter write address latch/ address comparator data control and latch circuit upper address latch read data buffer dq buffer ds lower address latch bank #2 bank #3 write data buffer qs
TC59LM818DMB-30,-33,-40 2003-02-28 4/55 absolute maximum ratings symbol parameter rating unit notes v dd power supply voltage ? 0.3~ 3.3 v v ddq power supply voltage (for dq buffer) ? 0.3~v dd + 0.3 v v in input voltage ? 0.3~v dd + 0.3 v v out output and dq pin voltage ? 0.3~v ddq + 0.3 v v ref input reference voltage ? 0.3~v dd + 0.3 v t opr operating temperature (ambient) 0~70 c t stg storage temperature ? 55~150 c t solder soldering temperature (10 s) 260 c p d power dissipation 2 w i out short circuit output current 50 ma caution: conditions outside the limits listed under ?absolute maximum ratings? ma y cause permanent damage to the device. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to ?absolute maximum ratings? conditions for extended periods may affect device reliability. recommended dc, ac operating conditions (notes: 1) (t case = 0 ~ 85c) symbol parameter min typ. max unit notes v dd power supply voltage 2.375 2.5 2.625 v v ddq power supply voltage (for dq buffer) 1.4 ? 1.9 v v ref reference voltage v ddq /2 95% v ddq /2 v ddq /2 105% v 2 v ih (dc) input dc high voltage v ref + 0.125 ? v ddq + 0.2 v 5 v il (dc) input dc low voltage ? 0.1 ? v ref ? 0.125 v 5 v ick (dc) differential clock dc input voltage ? 0.1 ? v ddq + 0.1 v 10 v id (dc) differential input voltage. clk and clk inputs (dc) 0.4 ? v ddq + 0.2 v 7, 10 v ih (ac) input ac high voltage v ref + 0.2 ? v ddq + 0.2 v 3, 6 v il (ac) input ac low voltage ? 0.1 ? v ref ? 0.2 v 4, 6 v id (ac) differential inputvoltage. clk and clk inputs (ac) 0.55 ? v ddq + 0.2 v 7, 10 v x (ac) differential ac input cross point voltage v ddq /2 ? 0.125 ? v ddq /2 + 0.125 v 8, 10 v iso (ac) differential clock ac middle level v ddq /2 ? 0.125 ? v ddq /2 + 0.125 v 9, 10
TC59LM818DMB-30,-33,-40 2003-02-28 5/55 note: (1) all voltages referenced to v ss , v ssq . (2) v ref is expected to track variations in v ddq dc level of the transmitting device. peak to peak ac noise on v ref may not exceed 2% v ref (dc). (3) overshoot limit: v ih (max) = v ddq + 0.7 v with a pulse width 5 ns. (4) undershoot limit: v il (min) = ? 0.7 v with a pulse width 5 ns. (5) v ih (dc) and v il (dc) are levels to maintain the current logic state. (6) v ih (ac) and v il (ac) are levels to change to the new logic state. (7) v id is differential voltage of clk input level and clk input level. (8) the value of v x (ac) is expected to equal v ddq /2 of the transmitting device. (9) v iso means {v ick (clk) + v ick ( clk )} /2 (10) refer to the figure below. (11) in the case of external termination, vtt (termination voltage) should be gone in the range of v ref (dc) 0.04 v. capacitance (v dd = 2.5v , v ddq = 1.8 v, f = 1 mhz, ta = 25c) symbol parameter min max delta unit c in input pin capacitance 1.5 2.5 0.25 pf c inc clock pin (clk, clk ) capacitance 1.5 2.5 0.25 pf c i/o dq, ds, qs capacitance 2.5 3.5 0.5 pf c nc nc pin capacitance ? 1.5 ? pf note: these parameters are periodically sampled and not 100% tested. v iso ( min ) v iso ( max ) v ick v ick v x v x v x v x v x v ick v ick clk clk v ss |v id (ac)| 0 v differential v iso v ss v id (ac)
TC59LM818DMB-30,-33,-40 2003-02-28 6/55 recommended dc operating conditions (v dd = 2.5 v 0.125 v, v ddq = 1.4 v ~ 1.9 v, t case = 0 ~ 85c) max symbol parameter -30 -33 -40 unit notes i dd1s operating current t ck = min; i rc = min, read/write command cycling, 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq , 1 bank operation, burst length = 4, address change up to 2 times during minimum i rc . 250 235 210 1, 2 i dd2n standby current t ck = min, cs = v ih , pd = v ih , 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq , all banks: inactive state, other input signals are changed one time during 4 t ck . 100 95 90 1 i dd2p standby (power down) current t ck = min, cs = v ih , pd = v il (power down), 0 v v in v ddq , all banks: inactive state 60 55 50 1 i dd5 auto-refresh current t ck = min; i refc = min, t refi = min, auto-refresh command cycling, 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq , address change up to 2 times during minimum i refc . 100 90 80 1 i dd6 self-refresh current self-refresh mode pd = 0.2 v, 0 v v in v ddq 10 10 10 ma symbol parameter min max unit notes i li input leakage current ( 0 v v in v ddq , all other pins not under test = 0 v) ? 5 5 a i lo output leakage current (output disabled, 0 v v out v ddq ) ? 5 5 a i ref v ref current ? 5 5 a i oh (dc) v oh = 1.420 v ? 5.6 ? 3 i ol (dc) normal output driver v ol = 0.280 v 5.6 ? 3 i oh (dc) v oh = 1.420 v ? 9.8 ? 3 i ol (dc) strong output driver v ol = 0.280 v 9.8 ? 3 i oh (dc) v oh = 1.420 v ? 2.8 ? 3 i ol (dc) weak output driver output dc current (v ddq = 1.7v~1.9v) v ol = 0.280 v 2.8 ma i oh (dc) v oh = v ddq ? 0.4v ? 4 ? 3 i ol (dc) normal output driver v ol = 0.4v 4 ? 3 i oh (dc) v oh = v ddq ? 0.4v ? 8 ? 3 i ol (dc) strong output driver v ol = 0.4v 8 ? 3 i oh (dc) not defined ? ? i ol (dc) weak output driver output dc current (v ddq = 1.4v~1.6v) not defined ? ? ma notes: 1. these parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t ck , t rc and i rc . 2. these parameters depend on the output loading. the specified values are obtained with the output open. 3. refer to output driver characteristics for the detail. output driver strength is selected by extended mode register.
TC59LM818DMB-30,-33,-40 2003-02-28 7/55 ac characteristics and operating conditions (notes: 1, 2) (v dd = 2.5 v 0.125v, v ddq = 1.4v ~ 1.9v, t case = 0 ~ 85c) -30 -33 -40 symbol parameter min max min max min max unit notes t rc random cycle time 20.0 ? 22.5 ? 25 ? 3 c l = 4 4.0 7.5 4.5 7.5 5.0 7.5 3 c l = 5 3.33 7.5 3.75 7.5 4.5 7.5 3 t ck clock cycle time c l = 6 3.0 7.5 3.33 7.5 4.0 7.5 3 t rac random access time ? 20.0 ? 22.5 ? 25 3 t ch clock high time 0.45 t ck ? 0.45 t ck ? 0.45 t ck ? 3 t cl clock low time 0.45 t ck ? 0.45 t ck ? 0.45 t ck ? 3 t ckqs qs access time from clk ? 0.45 0.45 ? 0.45 0.45 ? 0.5 0.5 3, 8 t qsq data output skew from qs ? 0.2 ? 0.25 ? 0.3 4 t ac data access time from clk ? 0.5 0.5 ? 0.5 0. 5 ? 0.6 0.6 3, 8 t oh data output hold time from clk ? 0.5 0.5 ? 0.5 0.5 ? 0.6 0.6 3, 8 t hp clk half period (minimum of actual t ch , t cl ) min(t ch , t cl ) ? min(t ch , t cl ) ? min(t ch , t cl ) ? 3 t qsp qs (read) pulse width t hp ? t qhs ? t hp ? t qhs ? t hp ? t qhs ? 4, 8 t qsqv data output valid time from qs t hp ? t qhs ? t hp ? t qhs ? t hp ? t qhs ? 4, 8 t qhs dq, qs hold skew factor ? 0.055 t ck + 0.17 ? 0.055 t ck + 0.17 ? 0.055 t ck + 0.17 t dqss ds (write) low to high setup time 0.8 t ck 1.2 t ck 0.8 t ck 1.2 t ck 0.8 t ck 1.2 t ck 3 t dspre ds (write) preamble pulse width 0.4 t ck ? 0.4 t ck ? 0.4 t ck ? 4 t dspres ds first input setup time 0 ? 0 ? 0 ? 3 t dspreh ds first low input hold time 0.3 t ck ? 0.3 t ck ? 0.3 t ck ? 3 t dsp ds high or low input pulse width 0.45 t ck 0.55 t ck 0.45 t ck 0.55 t ck 0.45 t ck 0.55 t ck 4 c l = 4 0.75 ? 0.8 ? 1.0 ? 3, 4 c l = 5 0.75 ? 0.8 ? 1.0 ? 3, 4 t dss ds input falling edge to clock setup time c l = 6 0.75 ? 0.8 ? 1.0 ? 3, 4 t dspst ds (write) postamble pulse width 0.45 t ck ? 0.45 t ck ? 0.45 t ck ? 4 c l = 4 0.75 ? 0.8 ? 1.0 ? 3, 4 c l = 5 0.75 ? 0.8 ? 1.0 ? 3, 4 t dspsth ds (write) postamble hold time c l = 6 0.75 ? 0.8 ? 1.0 ? 3, 4 t ds data input setup time from ds 0.3 ? 0.35 ? 0.4 ? 4 t dh data input hold time from ds 0.3 ? 0.35 ? 0.4 ? 4 t is command/address input setup time 0.6 ? 0.6 ? 0.7 ? 3 t ih command/address input hold time 0.6 ? 0.6 ? 0.7 ? ns 3
TC59LM818DMB-30,-33,-40 2003-02-28 8/55 ac characteristics and operating conditions (notes: 1, 2) (continued) -30 -33 -40 symbol parameter min max min max min max unit notes t lz data-out low impedance time from clk ? 0.5 ? ? 0.5 ? ? 0.6 ? 3,6,8 t hz data-out high impedance time from clk ? 0.5 ? 0.5 ? 0.6 3,7,8 t qpdh last output to pd high hold time 0 ? 0 ? 0 ? t pdex power down exit time 0.6 ? 0.6 ? 0.7 ? 3 t t input transition time 0.1 1 0.1 1 0.1 1 t fpdl pd low input window for self-refresh entry ? 0.5 t ck 5 ? 0.5 t ck 5 ? 0.5 t ck 5 ns 3 t refi auto-refresh average interval 0.4 3.9 0.4 3.9 0.4 3.9 5 t pause pause time after power-up 200 ? 200 ? 200 ? s c l = 4 5 ? 5 ? 5 ? c l = 5 6 ? 6 ? 6 ? i rc random read/write cycle time (applicable to same bank) c l = 6 7 ? 7 ? 7 ? i rcd rda/wra to lal command input delay (applicable to same bank) 1 1 1 1 1 1 c l = 4 4 ? 4 ? 4 ? c l = 5 5 ? 5 ? 5 ? i ras lal to rda/wra command input delay (applicable to same bank) c l = 6 6 ? 6 ? 6 ? i rbd random bank access delay (applicable to other bank) 2 ? 2 ? 2 ? b l = 2 2 ? 2 ? 2 ? i rwd lal following rda to wra delay (applicable to other bank) b l = 4 3 ? 3 ? 3 ? i wrd lal following wra to rda delay (applicable to other bank) 1 ? 1 ? 1 ? c l = 4 7 ? 7 ? 7 ? c l = 5 7 ? 7 ? 7 ? i rsc mode register set cycle time c l = 6 7 ? 7 ? 7 ? i pd pd low to inactive state of input buffer ? 2 ? 2 ? 2 i pda pd high to active state of input buffer 1 ? 1 ? 1 ? c l = 4 19 ? 19 ? 19 ? c l = 5 23 ? 23 ? 23 ? i pdv power down mode valid from ref command c l = 6 25 ? 25 ? 25 ? c l = 4 19 ? 19 ? 19 ? c l = 5 23 ? 23 ? 23 ? i refc auto-refresh cycle time c l = 6 25 ? 25 ? 25 ? i ckd ref command to clock input disable at self-refresh entry i refc ? i refc ? i refc ? i lock dll lock-on time (applicable to rda command) 200 ? 200 ? 200 ? cycle
TC59LM818DMB-30,-33,-40 2003-02-28 9/55 ac test conditions symbol parameter value unit notes v ih (min) input high voltage (minimum) v ref + 0.2 v v il (max) input low voltage (maximum) v ref ? 0.2 v v ref input reference voltage v ddq /2 v v tt termination voltage v ref v v swing input signal peak to peak swing 0.7 v vr differential clock input reference level v x (ac) v v id (ac) input differential voltage 1.0 v slew input signal minimum slew rate 2.5 v/ns v otr output timing measurement reference voltage v ddq /2 v 9 note: (1) transition times are measured between v ih min (dc) and v il max (dc). transition (rise and fall) of input signals have a fixed slope. (2) if the result of nominal calculation with regard to t ck contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., t dqss = 0.8 t ck , t ck = 3.3 ns, 0.8 3.3 ns = 2.64 ns is rounded up to 2.7 ns.) (3) there parameters are measured from the differential clock (clk and clk ) ac cross point. (4) these parameters are measured from signal transition point of ds crossing v ref level. (5) the t refi (max) applies to equally distributed refresh method. the t refi (min) applies to both burst refresh method and distributed refresh method. in such case, the average interval of eight consecutive auto-refresh commands has to be more than 400 ns always. in other words, the number of auto-refresh cycles which can be performed within 3.2 s (8 400 ns) is to 8 times in the maximum. (6) low impedance state is specified at v ddq /2 0.2 v from steady state. (7) high impedance state is specified where output buffer is no longer driven. (8) these parameters depend on the clock jitter. these parameters are measured at stable clock. (9) output timing is measured by using normal driver strength at v ddq = 1.7 1.9v. output timing is measured by using strong driver strength at v ddq = 1.4 1.6v. slew = (v ih min (ac) ? v il max (ac))/ ? t v ih min (ac) ? t v ref v il max (ac) v swing ? t v ss v ddq z = 50 ? ac test load output v tt 50 ? z = 50 ? 25 ? v tt 50 ?
TC59LM818DMB-30,-33,-40 2003-02-28 10/55 power up sequence (1) as for pd , being maintained by the low state ( 0.2 v) is desirable before a power-supply injection. (2) apply v dd before or at the same time as v ddq . (3) apply v ddq before or at the same time as v ref . (4) start clock (clk, clk ) and maintain stable condition for 200 s (min). (5) after stable power and clock, apply desl and take pd =h. (6) issue emrs to enable dll and to define driv er strength and data strobe type. (note: 1) (7) issue mrs for set cas latency (cl), burst type (bt), and burst length (bl). (note: 1) (8) issue two or more auto-refresh commands (note: 1). (9) ready for normal operation after 200 clocks from extended mode register programming. notes: (1) sequence 6, 7 and 8 can be issued in random order. (2) l = logic low, h = logic high (3) dq output is hi-z state during power upsequence. command cl k address v dd v ddq v ref ds qs (free running mode) clk pd 2.5v ( typ ) 1.5v or 1.8v ( typ ) 1/2 v ddq (typ) 200us ( min ) t pde x l pd a l rsc l rsc l refc l refc l lock = 200clock cycle(min) desl rda mrs desl rda mrs desl wra ref desl wra ref desl op-code emrs op-code mrs qs (uni-qs mode) emrs mrs auto refresh cycle normal operation low dq (input)
TC59LM818DMB-30,-33,-40 2003-02-28 11/55 timing diagrams input timing timing of the clk, t t t ck clk v ih v il v ih v il t cl t ch t t v ih (ac) v il (ac) cl k clk cl k v x v x v x v id (ac) cl k t ih t is t ih t ck t cl t ch cs clk clk refer to the command truth table. t ck 1st 2nd t is t ih t is t ih 1st 2nd t ih t is t ih ua, ba la t is t is fn a0~a14 ba0, ba1 ds command and address data dqn (input) t ds t dh t ds t dh t ds t dh t ds t dh dqm (input)
TC59LM818DMB-30,-33,-40 2003-02-28 12/55 read timing (burst length = 4) unidirectional ds/qs mode t oh clk clk input (control & addresses) qs (output) dq (output) cas latency = 4 qs (output) dq (output) cas latency = 5 ds (input) qs (output) dq (output) cas latency = 6 note: dq0 to dq17 are aligned with qs. low lal (after rda) t is t ih hi-z t ch t cl t ck low low t qsq hi-z low t ckqs t ckqs t qsp t qsp t ckqs t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac t ckqs t ckqs t qsp t qsp t ckqs q0 q1 q2 q3 t qsq t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 t ckqs t ckqs t qsp t qsp t ckqs t qs t qsq t qsqv t qsqv t qsq t hz t lz t ac t ac t ac q0 q1 q2 q3 low hi-z desl low
TC59LM818DMB-30,-33,-40 2003-02-28 13/55 read timing (burst length = 4) unidirectional ds/free running qs mode clk clk input (control & addresses) qs (output) dq (output) cas latency = 4 qs (output) dq (output) cas latency = 5 note: dq0 to dq17 are aligned with qs. qs is always asserted in free running qs mode. hi-z hi-z t qsq t ckqs t ckqs t qsp t qsp t ckqs t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac t ckqs t ck q s t qsp t qsp t ckqs q0 q1 q2 q3 t qsq t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 ds (input) lal (after rda) t is t ih t ch t cl t ck qs (output) dq (output) cas latency = 6 hi-z t ckqs t qsp t qsp t qsq t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 t ck q s t ckqs desl
TC59LM818DMB-30,-33,-40 2003-02-28 14/55 write timing (burst length = 4) unidirectional ds/qs mode, unidirectional ds/free running qs mode note: dq0 to dq17 are sampled at both edges of ds. dq (input) ds (input) dq (input) cas latency = 5 ds (input) cas latency = 4 t dspre t ds t dh d0 d1 t ds t dh d3 t ds t dh t dss t dqss t dspreh t dsp t dsp t ds preamble postamble t dsp t dqss t dspres t dspst t dspsth t dh d1 t ds t dh d3 t ds t dh t dss t dqss t dspreh t dsp t dsp preamble postamble t dsp t dss t dspres t dspst t dss t dspsth t dqss clk clk input (control & addresses) lal (after wra) t is t ih t ch t cl t ck t dspre ds (input) dq (input) cas latency = 6 t dspre t dss t dspreh t dsp t dsp t ds preamble postamble t dsp t dqss t dspres t dspst t dspsth t dh d1 t ds t dh d3 t ds t dh t dss t dqss qs (uni-qs) qs (free runninig) low desl d2 d2 d0 d0 d2
TC59LM818DMB-30,-33,-40 2003-02-28 15/55 t refi , t pause , i xxxx timing clk clk inpu t (control & addresses) command t is t ih note: ?i xxxx ? means ?i rc ?, ?i rcd ?, ?i ras ?, etc. t refi , t pause , i xxxx command t is t ih
TC59LM818DMB-30,-33,-40 2003-02-28 16/55 function truth table (notes: 1, 2, 3) command truth table (notes: 4) ? the first command symbol function cs fn ba1~ba0 a14~a9 a8 a7 a6~a0 desl device deselect h rda read with auto-close l h ba ua ua ua ua wra write with auto-close l l ba ua ua ua ua ? the second command (the next clock of rda or wra command) symbol function cs fn ba1~ ba0 a14~ a13 a12~ a11 a10~a9 a8 a7 a6~a0 lal lower address latch h v la ref auto-refresh l mrs mode register set l v l l l l v v notes: 1. l = logic low, h = logic high, = either l or h, v = valid (specified value), ba = bank address, ua = upper address, la = lower address 2. all commands are assumed to issue at a valid state. 3. all inputs for command (excluding selfx and pdex) are latched on the crossing point of differential clock input where clk goes to high. 4. operation mode is decided by the combination of 1st command and 2nd command. refer to ?state diagram? and the command table below. read command table command (symbol) cs fn ba1~ba0 a14~a9 a8 a7 a6~a0 notes rda (1st) l h ba ua ua ua ua lal (2nd) h la write command table command(symbol) cs fn ba1~ ba0 a14 a13 a12 a11 a10~ a9 a8 a7 a6~a0 wra (1st) l l ba ua ua ua ua ua ua ua ua lal (2nd) h vw0 vw1 la notes: 5. a14~ a13 are used for variable write length (vw) control at write operation. vw truth table burst length function vw0 vw1 write all words l bl=2 write first one word h reserved l l write all words h l write first two words l h bl=4 write first one word h h
TC59LM818DMB-30,-33,-40 2003-02-28 17/55 function truth table (continued) mode register set command table command (symbol) cs fn ba1~ba0 a14~a9 a8 a7 a6~a0 notes rda (1st) l h mrs (2nd) l v l l v v 6 notes: 6. refer to ?mode register table?. auto-refresh command table pd function command (symbol) current state n ? 1n cs fn ba1~ba0 a14~a9 a8 a7 a6~a0 notes active wra (1st) standby h h l l auto-refresh ref (2nd) active h h l self-refresh command table pd function command (symbol) current state n ? 1n cs fn ba1~ba0 a14~a9 a8 a7 a6~a0 notes active wra (1st) standby h h l l self-refresh entry ref (2nd) active h l l 7, 8 self-refresh continue ? self-refresh l l self-refresh exit selfx self-refresh l h h 9 power down table pd function command (symbol) current state n ? 1n cs fn ba1~ba0 a14~a9 a8 a7 a6~a0 notes power down entry pden standby h l h 8 power down continue ? power down l l power down exit pdex power down l h h 9 notes: 7. pd has to be brought to low within t fpdl from ref command. 8. pd should be brought to low after dq?s state turned high impedance. 9. when pd is brought to high from low, this function is executed asynchronously.
TC59LM818DMB-30,-33,-40 2003-02-28 18/55 function truth table (continued) pd current state n ? 1 n cs fn address command action notes h h h desl nop h h l h ba, ua rda row activate for read h h l l ba, ua wra row activate for write h l h pden power down entry 10 h l l ? illegal idle l ? refer to power down state h h h la lal begin read h h l op-code mrs/emrs access to mode register h l h pden illegal h l l mrs/emrs illegal row active for read l ? invalid h h h la lal begin write h h l ref auto-refresh h l h pden illegal h l l ref (self) self-refresh entry row active for write l ? invalid h h h desl continue burst read to end h h l h ba, ua rda illegal 11 h h l l ba, ua wra illegal 11 h l h pden illegal h l l ? illegal read l ? invalid h h h desl data write&continue burst write to end h h l h ba, ua rda illegal 11 h h l l ba, ua wra illegal 11 h l h pden illegal h l l ? illegal write l ? invalid h h h desl nop idle after i refc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h pden self-refresh entry 12 h l l ? illegal auto-refreshing l ? refer to self-refreshing state h h h desl nop idle after i rsc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h pden illegal h l l ? illegal mode register accessing l ? invalid h ? invalid l l ? maintain power down mode l h h pdex exit power down mode idle after t pdex power down l h l ? illegal h ? invalid l l ? maintain self-refresh l h h selfx exit self-refresh idle after i refc self-refreshing l h l ? illegal notes: 10. illegal if any bank is not idle. 11. illegal to bank in specified states; function may be legal in the bank inidicated by bank address (ba). 12. illegal if t fpdl is not satisfied.
TC59LM818DMB-30,-33,-40 2003-02-28 19/55 mode register table regular mode register (notes: 1) address ba1 * 1 ba0 * 1 a14~a8 a7 * 3 a6~a4 a3 a2~a0 register 0 0 0 te cl bt bl a7 test mode (te) a3 burst type (bt) 0 regular (default) 0 sequential 1 test mode entry 1 interleave a6 a5 a4 cas latency (cl) a2 a1 a0 burst length (bl) 0 0 reserved * 2 0 0 0 reserved * 2 0 1 0 reserved * 2 0 0 1 2 0 1 1 reserved * 2 0 1 0 4 1 0 0 4 0 1 1 1 0 1 5 1 reserved * 2 1 1 0 6 1 1 1 reserved * 2 extended mode register (notes: 4) address ba1 * 4 ba0 * 4 a14~a7 a6~a5 a4~a3 a2~a1 a0 * 5 register 0 1 0 ss dic (qs) dic (dq) ds qs dq a6 a5 strobe select a4 a3 a2 a1 output drive impedance control (dic) 0 0 reserved * 2 0 0 0 0 normal output driver 0 1 reserved * 2 0 1 0 1 strong output driver 1 0 unidirectional ds/qs 1 0 1 0 weak output driver 1 1 unidirectional ds/free running qs 1 1 1 1 reserved a0 dll switch (ds) 0 dll enable 1 dll disable notes: 1. regular mode register is chosen using the combination of ba0 = 0 and ba1 = 0. 2. ?reserved? places in regular mode register should not be set. 3. a7 in regular mode register must be set to ?0? (low state). because test mode is specific mode for supplier. 4. extended mode register is chosen using the combination of ba0 = 1 and ba1 = 0. 5. a0 in extended mode register must be set to "0" to enable dll for normal operation.
TC59LM818DMB-30,-33,-40 2003-02-28 20/55 state diagram standby (idle) self- refresh power down pden ( pd = l) pdex ( pd = h) selfx ( pd = h) mode register auto- refresh active active (restore) read write (buffer) pd = l pd = h wra rda mrs ref command input lal a utomatic return the second command at active state must be issued 1 clock after rda or wra command input. lal
TC59LM818DMB-30,-33,-40 2003-02-28 21/55 timing diagrams single bank read timing (cl = 4) cl k clk low ds (input) dq (output) bl = 2 i rc = 5 cycles hi-z q0 q1 cl = 4 command i rc = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda lal desl rda lal rda lal desl desl i rc = 5 cycles address ua la ua la ua la i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rcd = 1 cycle i ras = 4 cycles bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) cl = 4 q0 q1 q0 cl = 4 low ds (input) dq (output) bl = 4 hi-z q0 q1 cl = 4 qs (output) cl = 4 q0 q1 q0 cl = 4 q2 q3 q2 q3 ds (input) dq (output) bl = 2 hi-z q0 q1 cl = 4 unidirectional ds/free running qs mode qs (output) cl = 4 q0 q1 q0 cl = 4 ds (input) dq (output) bl = 4 hi-z q0 q1 cl = 4 qs (output) cl = 4 q0 q1 q0 cl = 4 q2 q3 q2 q3 rda ua #0
TC59LM818DMB-30,-33,-40 2003-02-28 22/55 single bank read timing (cl = 5) i rc = 6 cycles clk clk low ds (input) dq (output) bl = 2 hi-z q0 q1 cl = 5 command i rc = 6 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda lal desl rda lal rda lal desl address ua la ua la ua la i ras = 5 cycles i rcd = 1 cycle i ras = 5 cycles i rcd = 1 cycle i rcd = 1 cycle bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) cl = 5 q0 q1 low ds (input) dq (output) bl = 4 hi-z q0 q1 cl = 5 qs (output) cl = 5 q0 q1 q2 q3 q2 q3 ds (input) dq (output) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (output) bl = 4 qs (output) desl hi-z q0 q1 cl = 5 cl = 5 q0 q1 hi-z q0 q1 cl = 5 cl = 5 q0 q1 q2 q3 q2 q3
TC59LM818DMB-30,-33,-40 2003-02-28 23/55 single bank read timing (cl = 6) i rc = 7 cycles clk clk low ds (input) dq (output) bl = 2 hi-z q0 q1 cl = 6 command i rc = 7 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda rda lal rda lal desl address ua la ua la ua la i ras = 6 cycles i rcd = 1 cycle i ras = 6 cycles i rcd = 1 cycle i rcd = 1 cycle bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) cl = 6 q0 q1 low ds (input) dq (output) bl = 4 hi-z q0 q1 cl = 6 qs (output) cl = 6 q0 q1 q2 q3 q2 ds (input) dq (output) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (output) bl = 4 qs (output) desl hi-z q0 q1 cl = 6 cl = 6 q0 q1 hi-z q0 q1 cl = 6 cl = 6 q0 q1 q2 q3 q2 lal
TC59LM818DMB-30,-33,-40 2003-02-28 24/55 single bank write timing (cl = 4) clk clk low ds (input) dq (input) bl = 2 i rc = 5 cycles wl = 3 command i rc = 5 cycles 0 1 23 4 56789101112 13 1415 wra lal desl wra lal wra lal desl desl i rc = 5 cycles address ua la ua la ua la i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rcd = 1 cycle i ras = 4 cycles bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) wl = 3 d0 d1 wl = 3 low ds (input) dq (input) bl = 4 d0 d1 wl = 3 qs (output) wl = 3 wl = 3 d2 d3 ds (input) dq (input) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (input) qs (output) d0 d1 d0 d1 d0 d1 d2 d3 d0 d1 d2 wl = 3 wl = 3 wl = 3 d0 d1 d0 d1 d0 d1 wl = 3 wl = 3 wl = 3 d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 bl = 4 wra ua #0 d3 d3
TC59LM818DMB-30,-33,-40 2003-02-28 25/55 single bank write timing (cl = 5) i rc = 6 cycles clk clk low ds (input) dq (input) bl = 2 wl = 4 command i rc = 6 cycles 0 1 23 4 56789101112 13 1415 wra lal desl wra lal wra lal desl address ua la ua la ua la i ras = 5 cycles i rcd = 1 cycle i ras = 5 cycles i rcd = 1 cycle i rcd = 1 cycle bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) wl = 4 low ds (input) dq (input) bl = 4 qs (output) ds (input) dq (input) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (input) bl = 4 qs (output) desl d0 d1 d0 d1 wl = 4 wl = 4 d0 d1 d0 d1 d2 d3 d2 d3 wl = 4 wl = 4 d0 d1 d0 d1 d0 d1 d0 d1 d2 d3 d2 d3 wl = 4 wl = 4
TC59LM818DMB-30,-33,-40 2003-02-28 26/55 single bank write timing (cl = 6) i rc = 7 cycles clk clk low ds (input) dq (input) bl = 2 wl = 5 command i rc = 7 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wra wra lal wra lal desl address ua la ua la ua la i ras = 6 cycles i rcd = 1 cycle i ras = 6 cycles i rcd = 1 cycle i rcd = 1 cycle bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) wl = 5 low ds (input) dq (input) bl = 4 qs (output) ds (input) dq (input) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (input) bl = 4 qs (output) desl lal d0 d1 wl = 5 wl = 5 wl = 5 wl = 5 wl = 5 wl = 5 d0 d1 d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d0 d1 d0 d1 d2 d3 d0 d1 d2 d3
TC59LM818DMB-30,-33,-40 2003-02-28 27/55 single bank read-write timing (cl = 4) cl k clk low ds (input) dq bl = 2 i rc = 5 cycles hi-z cl = 4 command i rc = 5 cycles 0 1 23 4 56789101112 13 1415 rda lal desl rda lal wra lal desl desl i rc = 5 cycles address ua la ua la ua la bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) wl = 3 q0 cl = 4 low ds (input) dq bl = 4 hi-z cl = 4 qs (output) wl = 3 cl = 4 ds (input) dq bl = 2 hi-z cl = 4 unidirectional ds/free running qs mode qs (output) wl = 3 cl = 4 ds (input) dq bl = 4 hi-z cl = 4 qs (output) wl = 3 cl = 4 read data write data wra ua #0 q0 q1 d0 d1 q0 q1 d0 d1 q0 q2 q3 d2 d3 q0 q1 d0 d1 q0 q0 q1 q0 q2 q3 d0 d1 d2 d3
TC59LM818DMB-30,-33,-40 2003-02-28 28/55 single bank read-write timing (cl = 5) clk clk ds (input) dq bl = 2 command 0 1 23 4 56789101112 13 1415 desl address bank add. unidirectional ds/qs mode qs (output) ds (input) dq bl = 4 qs (output) ds (input) dq bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq bl = 4 qs (output) i rc = 6 cycles low hi-z cl = 5 i rc = 6 cycles rda lal rda lal wra lal desl ua la ua la ua la #0 #0 #0 wl = 4 low hi-z cl = 5 desl hi-z cl = 5 hi-z cl = 5 wl = 4 wl = 4 wl = 4 read data write data q0 q1 q2 q3 d0 d1 d2 d3 q0 q1 d0 d1 q0 q1 q2 q3 d0 d1 d2 d3 q0 q1 d0 d1
TC59LM818DMB-30,-33,-40 2003-02-28 29/55 single bank read-write timing (cl = 6) i rc = 7 cycles clk clk low ds (input) dq bl = 2 hi-z cl = 6 command i rc = 7 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda rda lal wra lal desl address ua la ua la ua la bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) wl = 5 low ds (input) dq bl = 4 hi-z cl = 6 qs (output) ds (input) dq bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (output) bl = 4 qs (output) desl hi-z cl = 6 hi-z cl = 6 lal wl = 5 wl = 5 wl = 5 read data write data q0 q1 q2 q3 d0 d1 d2 d3 q0 q1 d0 d1 q0 q1 d0 d1 q0 q1 q2 q3 d0 d1 d2 d3
TC59LM818DMB-30,-33,-40 2003-02-28 30/55 multiple bank read timing (cl = 4) rda ua bank "b" clk clk low ds (input) dq (output) bl = 2 i rbd = 2 cycles hi-z qa0 qa1 cl = 4 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lal rda rda lal rda lal address ua la ua la ua la bank add. bank "a" unidirectional ds/qs mode qs (output) cl = 4 ds (input) bl = 4 rda lal desl i rbd = 2 cycles rda lal rda i rbd = 2 cycles i rbd = 2 cycles lal rda lal ua la ua la ua la ua bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 5 cycles i rc (bank"b") = 5 cycles qb0 qb1 qa0 qa1 qb0 qb1 qc0 qc1 i rbd = 2 cycles dq (output) hi-z qs (output) ds (input) dq (output) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (output) bl = 4 qs (output) low cl = 4 cl = 4 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 cl = 4 cl = 4 cl = 4 cl = 4 note: l rc to the same bank must be satisfied. hi-z qa0 qa1 qb0 qb1 qa0 qa1 qb0 qb1 qc0 qc1 hi-z qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 la
TC59LM818DMB-30,-33,-40 2003-02-28 31/55 multiple bank read timing (cl = 5) cl k clk ds (input) dq (output) bl = 2 hi-z cl = 5 command 0 1 2 3 4 56789101112 13 14 15 rda lal rda lal rda address ua la ua la ua bank add. bank "a" unidirectional ds/qs mode qs (output) cl = 5 ds (input) dq (output) bl = 4 hi-z qs (output) ds (input) dq (output) bl = 2 hi-z unidirectional ds/free running qs mode qs (output) ds (input) dq (output) bl = 4 hi-z qs (output) rda lal lal rda lal rda lal rda ua la la ua la ua la ua bank "b" bank "a" bank "b" bank "c" bank "d" i rc (bank"a") = 6 cycles i rc (bank"b") = 6 cycles low low cl = 5 cl = 5 cl = 5 cl = 5 cl = 5 cl = 5 note: l rc to the same bank must be satisfied. desl bank "a" i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles lal la qa0qa1qa2qa3qb0qb1qb2qb3 qa0 qa1 qa2 qa3 qb0qb1qb2 qa0qa1 qb0qb1 qa0 qa1 qb0qb1 qa0qa1qa2qa3qb0qb1qb2qb3 qa0 qa1 qa2 qa3 qb0qb1qb2 qa0qa1 qb0qb1 qa0 qa1 qb0qb1
TC59LM818DMB-30,-33,-40 2003-02-28 32/55 multiple bank read timing (cl = 6) cl k clk low ds (input) dq (output) bl = 2 hi-z cl = 6 command 0 1 2 3 4 56789101112 13 14 15 rda lal rda lal address ua la ua la ua bank add. bank "a" unidirectional ds/qs mode qs (output) cl = 6 ds (input) dq (output) bl = 4 hi-z qs (output) ds (input) dq (output) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (output) bl = 4 qs (output) rda lal lal rda lal rda lal ua la la ua la ua la bank "b" bank "b" bank "c" bank "d" i rc (bank"a") = 7 cycles i rc (bank"b") = 7 cycles low cl = 6 cl = 6 cl = 6 cl = 6 cl = 6 cl = 6 bank "a" desl i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles rda ua bank "a" hi-z hi-z rda qa0 qa1 qb0 qa0 qa1 qb1 qa0qa1qa2 qa0qa1qa2qa3qb0qb1qb2qb3 qa0qa1 qb0qb1 qa0qa1 qa0qa1qa2qa3qb0qb1qb2qb3 qa0qa1qa2
TC59LM818DMB-30,-33,-40 2003-02-28 33/55 multiple bank write timing (cl = 4) cl k clk low ds (input) dq (input) bl = 2 wl = 3 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lal wra wra lal wra lal address ua la ua la ua la bank add. bank "a" unidirectional ds/qs mode qs (output) wl = 3 ds (input) dq (input) bl = 4 qs (output) unidirectional ds/free running qs mode wra lal desl wra lal wra lal wra lal ua la ua la ua la ua la bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 5 cycles i rc (bank"b") = 5 cycles db0 db1 da0 da1 db0 db1 dc0 dc1 low da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 dc2 dc3 note: l rc to the same bank must be satisfied. i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles da0 da1 dd0 dd1 wl = 3 wl = 3 dd0 dd1 ds (input) dq (input) bl = 2 wl = 3 qs (output) wl = 3 ds (input) dq (input) bl = 4 qs (output) db0 db1 da0 da1 db0 db1 dc0 dc1 da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 dc2 dc3 da0 da1 dd0 dd1 wl = 3 wl = 3 dd0 dd1 wra ua bank "b"
TC59LM818DMB-30,-33,-40 2003-02-28 34/55 multiple bank write timing (cl = 5) cl k clk low ds (input) dq (input) bl = 2 wl = 4 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wra lal wra lal wra address ua la ua la ua la bank add. unidirectional ds/qs mode qs (output) wl = 4 ds (input) dq (input) bl = 4 qs (output) unidirectional ds/free running qs mode wra lal lal wra lal wra lal wra ua la ua la ua la ua bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 6 cycles i rc (bank"b") = 6 cycles db0 db1 da0 da1 db0 db1 dc0 dc1 low da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 note: l rc to the same bank must be satisfied. i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles da0 da1 desl wl = 4 wl = 4 ds (input) dq (input) bl = 2 wl = 4 qs (output) wl = 4 ds (input) dq (input) bl = 4 qs (output) db0 db1 da0 da1 db0 db1 dc0 dc1 da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 da0 da1 wl = 4 wl = 4 lal la bank "a" bank "b" bank "a"
TC59LM818DMB-30,-33,-40 2003-02-28 35/55 multiple bank write timing (cl = 6) note: l rc to the same bank must be satisfied. clk clk low ds (input) dq (input) bl = 2 wl = 5 command 0 1 2 3 4 56789101112 13 14 15 wra lal wra lal wra address ua la ua la ua la bank add. bank "a" unidirectional ds/qs mode qs (output) wl = 5 ds (input) dq (input) bl = 4 qs (output) unidirectional ds/free running qs mode wra lal lal wra lal wra lal wra ua la ua la ua la ua bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 7 cycles i rc (bank"b") = 7 cycles db0 db1 da0 da1 db0 db1 low da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles da0 da1 desl wl = 5 wl = 5 ds (input) dq (input) bl = 2 wl = 5 qs (output) wl = 5 ds (input) dq (input) bl = 4 qs (output) db0 db1 da0 da1 db0 db1 da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 da0 da1 wl = 5 wl = 5
TC59LM818DMB-30,-33,-40 2003-02-28 36/55 multiple bank read-write timing (bl = 2) cl k clk ds (input) cl = 4 i rbd = 2 cycles wl = 3 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 address bank add. unidirectional ds/qs mode cl = 4 unidirectional ds/free running qs mode i rc (bank"a") i rc (bank"b") i wrd = 1 cycle i rwd = 2 cycles i wrd = 1 cycle i rwd = 2 cycles qs (output) low dq da0 da1 qb0 qb1 dc0 dc1 qd0 qd1 da0 da1 hi - z ds (input) cl = 5 wl = 4 qs (output) cl = 5 low ds (input) cl = 6 wl = 5 cl = 6 qs (output) low wra desl wra wra wra rda lal lal desl desl rda lal lal rda lal lal ua la ua la ua la ua la ua la ua la ua b an k "a" b an k "b" b an k "c" b an k "d" b an k "a" b an k "b" b an k "c" dq hi-z da0 da1 qb0 qb1 dc0 dc1 qd0 qd1 da0 da1 dq hi-z da0 da1 qb0 qb1 dc0 dc1 qd0 qd1 ds (input) cl = 4 wl = 3 cl = 4 qs (output) dq da0 da1 qb0 qb1 dc0 dc1 qd0 qd1 da0 da1 hi - z ds (input) cl = 5 wl = 4 qs (output) cl = 5 ds (input) cl = 6 wl = 5 cl = 6 qs (output) dq hi - z da0 da1 qb0 qb1 dc0 dc1 qd0 qd1 da0 da1 dq hi-z da0 da1 qb0 qb1 dc0 dc1 qd0 qd1 note: l rc to the same bank must be satisfied.
TC59LM818DMB-30,-33,-40 2003-02-28 37/55 multiple bank read-write timing (bl = 4) cl k clk ds (input) cl = 4 i rbd = 2 cycles wl = 3 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 address bank add. unidirectional ds/qs mode cl = 4 unidirectional ds/free running qs mode i rc (bank"a") i rc (bank"b") i wrd = 1 cycle i rwd = 3 cycles i wrd = 1 cycle i rwd = 3 cycles qs (output) dq hi-z ds (input) cl = 5 wl = 4 qs (output) cl = 5 low ds (input) cl = 6 wl = 5 cl = 6 qs (output) low dq hi-z dq hi - z ds (input) cl = 4 wl = 3 cl = 4 qs (output) dq hi - z ds (input) cl = 5 wl = 4 qs (output) cl = 5 ds (input) cl = 6 wl = 5 cl = 6 qs (output) dq hi-z dq hi-z note: l rc to the same bank must be satisfied. lal rda wra rda lal lal lal lal wra rda wra lal desl desl ua la ua la ua la ua ua la la ua la b an k "a" b an k "b" b an k "c" b an k "d" b an k "a" b an k "b" low qb0 qb1 da0 da1 da2 da3 qb2 qb3 dc0 dc1 dc2 dc3 qd0 qd1 qd2 qd3 qb0 qb1 da0 da1 da2 da3 qb2 qb3 dc0 dc1 dc2 dc3 qd0 qd1 qd2 qd3 qb0 qb1 da0 da1 da2 da3 qb2 qb3 dc0 dc1 dc2 dc3 qd0 qd1 qd2 qd3 qb0 qb1 da0 da1 da2 da3 qb2 qb3 dc0 dc1 dc2 dc3 qd0 qd1 qd2 qd3 qb0 qb1 da0 da1 da2 da3 qb2 qb3 dc0 dc1 dc2 dc3 qd0 qd1 qb0 qb1 da0 da1 da2 da3 qb2 qb3 dc0 dc1 dc2 dc3 qd0 qd1 i wrd = 1 cycle
TC59LM818DMB-30,-33,-40 2003-02-28 38/55 write with variable write length (vw) control (cl = 4) cl k clk ds (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wra lal wra lal desl address ua la=#3 vw=all ua bank add. bank "a" bank "a" bl = 2, sequential mode desl la=#1 vw=1 vw0 = low vw1 = don't care vw0 = high vw1 = don't care dq (input) d0 d0 d1 lower address #3 #2 #1 ( #0 ) last one data is masked. ds (input) command wra lal wra lal desl address ua la=#3 vw=all ua bank add. bank "a" bank "a" bl = 4, sequential mode desl la=#1 vw=1 dq (input) d0 d0 d1 lower address #3 #0 #1 ( #2 )( #3 )( #0 ) last three data are masked. desl wra lal vw0 = high vw1 = low vw0 = high vw1 = high ua la=#2 vw=2 vw0 = low vw1 = high bank "a" d2 d3 d0 d1 #1 #2 last two data are masked. ( #0 )( #1 ) #2 #3 note: ds input must be continued till end of burst count even if some of laster data is masked.
TC59LM818DMB-30,-33,-40 2003-02-28 39/55 power down timing (cl = 4, bl = 4) read cycle to power down mode cl k clk 0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3 i pda t ih t is i pd = 2 cycle t pdex power down entry power down exit note: pd must be kept "high" level until end of burst data output. pd should be brought to "high" within t refi (max.) to maintain the data written into cell. in power down mode, pd "low" and a stable clock signal must be maintained. when pd is brought to "high", a valid executable command may be applied l pda cycles later. qs (output) command rda lal desl address ua ua desl rd a or wr a la l rc(min) , t refi(max) t qpdh ds (input) low hi-z q0 q1 cl = 4 q2 q3 hi-z dq (output) unidirectional ds/qs mode qs (output) ds (input) hi-z q0 q1 cl = 4 q2 q3 hi-z dq (output) unidirectional ds/free running qs mode pd
TC59LM818DMB-30,-33,-40 2003-02-28 40/55 power down timing (cl = 4, bl = 4) write cycle to power down mode cl k clk 0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3 i pda t ih t is i pd = 2 cycle t pdex note: pd must be kept "high" level until wl+2 clock cycles from lal command. pd should be brought to "high" within t refi (max.) to maintain the data written into cell. in power down mode, pd "low" and a stable clock signal must be maintained. when pd is brought to "high", a valid executable command may be applied l pda cycles later. qs (output) command wra lal address ua ua desl rd a or wr a la l rc(min) , t refi(max) ds (input) low wl = 3 d0 d1 d2 d3 dq (input) unidirectional ds/qs mode qs (output) ds (input) dq (input) unidirectional ds/free running qs mode pd 2 clock cycles wl = 3 wl = 3 d0 d1 d2 d3 desl
TC59LM818DMB-30,-33,-40 2003-02-28 41/55 mode register set timing (cl = 4, bl = 2) from read operation to mode register set operation. cl k clk ds (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rda lal rda mrs desl a14~a0 ua val id (opcode) qs (output) i rsc = 7 cycles desl rda or wra la ua ba0, ba1 ba ba0="0" ba1="0" ba unidirectional ds/qs mode unidirectional ds/free running qs mode lal dq (output) ds (input) qs (output) dq (output) cl + bl/2 low q0 q1 q0 q1 note: minimum delay from lal following rda to rda of mrs operation is cl+bl/2. 15 la
TC59LM818DMB-30,-33,-40 2003-02-28 42/55 mode register set timing (cl = 4, bl = 4) from write operation to mode register set operation. cl k clk ds (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 wra lal rda mrs desl a14~a0 ua val id (opcode) qs (output) i rsc = 7 cycles desl rda or wra la ua ba0, ba1 ba ba0="0" ba1="0" ba unidirectional ds/qs mode unidirectional ds/free running qs mode low d0 d1 d2 d3 dq (input) ds (input) qs (output) d0 d1 d2 d3 dq (input) 15 wl+bl/2 la lal note: minimum delay from lal following wra to rda of mrs operation is wl+bl/2.
TC59LM818DMB-30,-33,-40 2003-02-28 43/55 extended mode register set timing (cl = 4, bl = 2) from read operation to extended mode register set operation. cl k clk ds (input) command 0 1 23 4 56789101112 13 14 rda lal rda mrs desl a14~a0 ua val id (opcode) qs (output) i rsc = 7 cycles desl rda or wra la ua ba0, ba1 ba ba0="1" ba1="0" ba unidirectional ds/qs mode unidirectional ds/free running qs mode dq (output) ds (input) qs (output) dq (output) cl + bl/2 low q0 q1 q0 q1 note: minimum delay from lal following rda to rda of emrs operation is cl+bl/2. when dq strobe mode is changed by emrs, qs output is invalid for l rsc period. dll switch in extended mode register must be set to enable mode for normal operation. dll lock-on time is needed after initial emrs operation. see power up sequence. 15 la lal
TC59LM818DMB-30,-33,-40 2003-02-28 44/55 extended mode register set timing (cl = 4, bl = 4) from write operation to extended mode register set operation. cl k clk ds (input) command 0 1 23 4 56789101112 13 14 wra lal rda mrs desl a14~a0 ua val id (opcode) qs (output) wl+bl/2 i rsc = 7 cycles desl rda or wra la ua ba0, ba1 ba ba0="1" ba1="0" ba unidirectional ds/qs mode unidirectional ds/free running qs mode low d0 d1 d2 d3 dq (input) ds (input) qs (output) d0 d1 d2 d3 dq (input) note: when dq strobe mode is changed by emrs, qs output is invalid for l rsc period. dll switch in extended mode register must be set to enable mode for normal operation. dll lock-on time is needed after initial emrs operation. see power up sequence. minimum delay from lal following wra to rda of emrs operation is wl+bl/2. 15 lal la
TC59LM818DMB-30,-33,-40 2003-02-28 45/55 auto-refresh timing (cl = 4, bl = 4) clk wra ref wra ref wra ref wra ref wra ref t 1 t 2 t 3 t 7 t 8 8 refresh cycle t refi = total time of 8 refresh cycle 8 t 1 + t 2 + t 3 + t 4 + t 5 + t 6 + t 7 + t 8 8 = t refi is specified to avoid partly concentrated current of refresh operation that is activated larger area than read / write operation. cl k clk qs (output) dq (output) 0 1 2 3 4 5 6 7 n ? 1n n + 1 n + 2 rda lal hi-z hi-z cl = 4 command i rc = 5 cycles desl rda or wra lal o r mrs or ref i rcd = 1 cycle note: in case of cl = 4, i refc must be meet 19 clock cycles. when the auto-refresh operation is performed, the synthetic average interval of auto-refresh command specified by t refi must be satisfied. t refi is average interval time in 8 refresh cycles that is sampled randomly. wra ref i refc = 19 cycles low i ras = 4 cycles i rcd = 1 cycle desl clk clk qs (output) dq (output) rda lal hi-z hi-z cl = 4 command i rc = 5 cycles desl rda or wra lal o r mrs or ref i rcd = 1 cycle wra ref i refc = 19 cycles i ras = 4 cycles i rcd = 1 cycle desl unidirectional ds/qs mode unidirectional ds/free running qs mode bank, ua la bank, address bank, ua la bank, address q0 q1 q2 q3 low q0 q1 q2 q3
TC59LM818DMB-30,-33,-40 2003-02-28 46/55 self-refresh entry timing self-refresh exit timing notes: 1. is don?t care. 2. pd must be brought to "low" within the timing between t fpdl (min) and t fpdl (max) to self refresh mode.when pd is brought to "low" after l pdv , TC59LM818DMB perform auto refresh and enter power down mode. in case of pd fall between t fpdl (max) and l pdv , TC59LM818DMB will either entry self-refresh mode or power dow n mode after auto-refresh operation. it can?t be specified which mode TC59LM818DMB operates. 3. it is desirable that clock input is continued at least l ckd from ref command even though pd is brought to ?low? for self-refresh entry. 4. in case of self-refresh entry after write operation, from the lal command following wra to the ref command delay time is write latency(wl)+2 clock cycles minimum. clk clk low qs (output) dq (output) 0 12 345m ? 1mm + 1 wra ref qx hi-z command i rcd = 1 cycle i refc desl t fpdl (min) t fpdl (max) i pdv * 2 pd unidirectional ds/qs mode i ckd t qpdh auto refresh self refresh entry hi-z notes: 1. is don?t care. 2. clock should be stable prior to pd = ?high? if clock input is suspended in self-refresh mode. 3. desl command must be asserted during i refc after pd is brought to ?high?. 4. i pda is defined from the first clock rising edge after pd is brought to ?high?. 5. it is desirable that one auto-refresh command is issued just after self-refresh exit before any other operation. 6. any command (except read command) can be issued after i refc . 7. read command (rda + lal) can be issued after i lock . clk clk hi-z qs (output) dq (output) 0 1 3 m ? 1mm + 1m + 2 hi-z command i lock t pde x i pda = 2 cycles * 4 pd desl * 3 lal * 7 wra * 5 ref * 5 desl rda * 7 n ? 1nn + 1 p ? 1 p command (1st) * 6 command (2nd) * 6 i rcd = 1 cycle self-refresh exit * 2 unidirectional ds/qs mode i refc i refc i rcd = 1 cycle low
TC59LM818DMB-30,-33,-40 2003-02-28 47/55 self-refresh entry timing self-refresh exit timing notes: 1. is don?t care. 2. clock should be stable prior to pd = ?high? if clock input is suspended in self-refresh mode. 3. desl command must be asserted during i refc after pd is brought to ?high?. 4. i pda is defined from the first clock rising edge after pd is brought to ?high?. 5. it is desirable that one auto-refresh command is issued just after self-refresh exit before any other operation. 6. any command (except read command) can be issued after i refc . 7. read command (rda + lal) can be issued after i lock . 8. qs output is invalid until dll lock from self-refresh exit. clk clk qs (output) dq (output) 0 1 3 m ? 1mm + 1m + 2 hi-z command i lock t pde x i pda = 2 cycles * 4 pd desl * 3 lal * 7 wra * 5 ref * 5 desl rda * 7 n ? 1nn + 1 p ? 1 p command ( 1st ) * 6 command ( 2nd ) * 6 i rcd = 1 cycle self-refresh exit * 2 unidirectional ds/free running qs mode i refc i refc i rcd = 1 cycle notes: 1. is don?t care. 2. pd must be brought to "low" within the timing between t fpdl (min) and t fpdl (max) to self refresh mode. when pd is brought to "low" after l pdv , TC59LM818DMB perform auto refresh and enter power down mode. in case of pd fall between t fpdl (max) and l pdv , TC59LM818DMB will either entry self-refresh mode or power dow n mode after auto-refresh operation. it can?t be specified which mode TC59LM818DMB operates. 3. it is desirable that clock input is continued at least l ckd from ref command even though pd is brought to ?low? for self-refresh entry. 4. in case of self-refresh entry after write operation, from the lal command following wra to the ref command delay time is write latency(wl)+2 clock cycles minimum. clk clk hi-z qs (output) dq (output) 0 1 2 3 4 5 m ? 1mm + 1 wra ref qx hi-z command i rcd = 1 cycle i refc desl t fpdl (min) t fpdl (max) i pdv * 2 pd unidirectional ds/free running qs mode i ckd t qpdh auto refresh self refresh entry
TC59LM818DMB-30,-33,-40 2003-02-28 48/55 functional description network fcram tm the fcram tm is an acronym of fast cycle random access memory. the network fcram tm is competent to perform fast random core access, low latency and high-speed data transfer. pin functions clock inputs: clk & the clk and clk inputs are used as the reference for synchronous operation. clk is master clock input. the cs , fn and all address input signals are sampled on the crossing of the positive edge of clk and the negative edge of clk . the qs and dq output data are aligned to the crossing point of clk and clk . the timing reference point for the differential clock is when the clk and clk signals cross during a transition. power down: the pd input controls the entry to the power down or self-refresh modes. the pd input does not have a clock suspend function like a cke input of a standard sdrams, therefore it is illegal to bring pd pin into low state if any read or write operation is being performed. chip select & function control: & fn the cs and fn inputs are a control signal for forming the operation commands on fcram tm . each operation mode is decided by the combination of the two consecutive operation commands using the cs and fn inputs. bank addresses: ba0 & ba1 the ba0 and ba1 inputs are latched at the time of assertion of the rda or wra command and are selected the bank to be used for the operation. ba0 and ba1 also define which mode register is loaded during the mode register set command (mrs or emrs). ba0 ba1 bank #0 0 0 bank #1 1 0 bank #2 0 1 bank #3 1 1 address inputs: a0~a14 address inputs are used to access the arbitrary address of the memory cell array within each bank. the upper addresses with bank addresses are latched at the rda or wra command and the lower addresses are latched at the lal command. the a0 to a14 inputs are also used fo r setting the data in the regular or extended mode register set cycle. upper address lower address TC59LM818DMB a0~a14 a0~a6 cl k pd cs
TC59LM818DMB-30,-33,-40 2003-02-28 49/55 data input/output: dq0~dq17 the input data of dq0 to dq17 are taken in synchronizing with the both edges of ds input signal. the output data of dq0 to dq17 are outputted synchronizing with the both edges of qs output signal. data strobe: ds, qs method of data strobe is chosen by extended mode register. (1) unidirectional ds / qs mode ds is input signal and qs is output signal. both edge s of ds are used to sample all dqs at write operation. both edges of qs are used for trigger signal of all dqs at read operation. during write, auto-refresh and nop cycle, qs assert always ?low? level. qs is hi-z in self-refresh mode. (2) unidirectional ds / free running qs mode ds is input signal and qs is output signal. both edge of ds are used to sample all dqs at write operation. both edges of qs are used for trigger signal of all dqs at read operation. qs assert always toggle signal except self-refresh mode. this strobe type is easy to use for pin to pin connect application. power supply: v dd , v ddq , v ss , v ssq v dd and v ss are power supply pins for memory core and peripheral circuits. v ddq and v ssq are power supply pins for the output buffer. reference voltage: v ref v ref is reference voltage for all input signals.
TC59LM818DMB-30,-33,-40 2003-02-28 50/55 command functions and operations TC59LM818DMB are introduced the two consecutive command input method. therefore, except for power down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed. read operation (1st command + 2nd command = rda + lal) issuing the rda command with bank addresses and upper addresses to the idle bank puts the bank designated by bank address in a read mode. when the lal command wi th lower addresses is issued at the next clock of the rda command, the data is read out sequentially synchronizing with the both edges of qs output signal (burst read operation). the initial valid read data appears after cas latency from the issuing of the lal command. the valid data is outputted for a burst length. the cas latency, the burst length of read data and the burst type must be set in the mode register beforehand. the read operated bank goes back automatically to the idle state after l rc . write operation (1st command + 2nd command = wra + lal) issuing the wra command with bank addresses and upper addresses to the idle bank puts the bank designated by bank address in a write mode. when the lal command with lower addresses is issued at the next clock of the wra command, the input data is latched sequentially synchr onizing with the both edges of ds input signal (burst write operation). the data and ds inputs have to be asserted in keeping with clock input after cas latency-1 from the issuing of the lal command. the ds has to be provided for a burst length. the cas latency and the burst type must be set in the mode register beforehand . the write operated bank goes back automatically to the idle state after l rc . write burst length is controlled by vw0 and vw1 inputs with lal command. see vw truth table. auto-refresh operation (1st command + 2nd command = wra + ref) TC59LM818DMB are required to refresh like a standard sdram. the auto-refresh operation is begun with the ref command following to the wra command. the auto-refresh mode can be effective only when all banks are in the idle state and all dq are in hi-z states. in a point to notice, the write mode started with the wra command is canceled by the ref command having gone into the next clock of the wra command instead of the lal command. the minimum period between the auto-refresh command and the next command is specified by l refc . however, about a synthetic average interval of auto-refresh command, it must be careful. in case of equally distributed refresh, auto-refresh command has to be issued within once for every 3.9 s by the maximum. in case of burst refresh or random distributed refresh, the average interval of eight consecutive auto-refresh commands has to be more than 400 ns always. in other words, the number of auto-refresh cycles that can be performed within 3.2 s (8 400 ns) is to 8 times in the maximum. self-refresh operation (1st command + 2nd command = wra + ref with = ?l?) in case of self-refresh operation, refresh operation can be performed automatically by using an internal timer. when all banks are in the idle state and all outputs are in hi-z states, the TC59LM818DMB become self-refresh mode by issuing the self-refresh command. pd has to be brought to ?low? within t fpdl from the ref command following to the wra command for a self-refresh mode entry. in order to satisfy the refresh period, the self-refresh entry command should be asserted within 3.9 s after the latest auto-refresh command. once the device enters self-refresh mode, the desl command must be continued for l refc period. in addition, it is desirable that clock input is kept in l ckd period. the device is in self-refresh mode as long as pd held ?low?. during self-refresh mode, all input and output buffers are disabled except for pd , therefore the power dissipation lowers. regarding a self-refresh mode exit, pd has to be changed over from ?low? to ?high? along with the desl command, and the desl command has to be continuously issued in the number of clocks specified by l refc . the self-refresh exit function is asynchronous operation. it is required that one auto-refresh command is issued to avoid the violation of the refresh period just after l refc from self-refresh exit. power down mode ( = ?l?) when all banks are in the idle state and dq outputs are in hi-z states, the TC59LM818DMB become power down mode by asserting pd is ?low?. when the device enters the power down mode, all input and output buffers are disabled after specified time except for pd , clk, clk and qs. therefore, the power dissipation lowers. to exit the power down mode, pd has to be brought to ?high? and the desl command has to be issued for l pda cycle after pd goes high. the power down exit function is asynchronous operation. pd pd
TC59LM818DMB-30,-33,-40 2003-02-28 51/55 mode register set (1st command + 2nd command = rda + mrs) when all banks are in the idle state, issuing the mrs command following to the rda command can program the mode register. in a point to notice, the read mode started with the rda command is canceled by the mrs command having gone into the next clock of the rda command instead of the lal command. the data to be set in the mode register is transferred using a0 to a14, ba0 and ba1 address inputs. the TC59LM818DMB have two mode registers. these are regular and extended mode register. the regular or extended mode register is chosen by ba0 and ba1 in the mrs command. the regular mode register designates the operation mode for a read or write cycle. the regular mode register has four function fields. the four fields are as follows: (r-1) burst length field to set the length of burst data (r-2) burst type field to designate the lower address access sequence in a burst cycle (r-3) cas latency field to set the access time in clock cycle (r-4) test mode field to use for supplier only. the extended mode register has three function fields. the three fields are as follows: (e-1) dll switch field to choose either dll enable or dll disable (e-2) output driver impedance control field. (e-3) data strobe select once those fields in the mode register are set up, the register contents are maintained until the mode register is set up again by another mrs command or power supply is lost. the initial value of the regular or extended mode register after power-up is undefined, therefore the mode register set command must be issued before proper operation. ? regular mode register/extended mode register change bits (ba0, ba1) these bits are used to choose either regular mrs or extended mrs ba1 ba0 a14~a0 0 0 regular mrs cycle 0 1 extended mrs cycle 1 reserved regular mode register fields (r-1) burst length field (a2 to a0) this field specifies the data length for column access us ing the a2 to a0 pins and sets the burst length to be 2 or 4 words. a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 reserved 1 reserved (r-2) burst type field (a3) the burst type can be chosen interleave mode or sequen tial mode. when the a3 bit is ?0?, sequential mode is selected. when the a3 bit is ?1?, interleave mode is selected. both burst types support burst length of 2 and 4 words. a3 burst type 0 sequential 1 interleave
TC59LM818DMB-30,-33,-40 2003-02-28 52/55 ? addressing sequence of sequential mode (a3) a column access is started from the inputted lower address and is performed by incrementing the lower address input to the device. addressing sequence for sequential mode data access address burst length data 0 n data 1 n + 1 data 2 n + 2 data 3 n + 3 2 words (address bits is la0) not carried from la0~la1 4 words (address bits is la1, la0) not carried from la1~la2 ? addressing sequence of interleave mode a column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following. addressing sequence for interleave mode data access address burst length data 0 ??? a8 a7 a6 a5 a4 a3 a2 a1 a0 data 1 ??? a8 a7 a6 a5 a4 a3 a2 a1 0 a data 2 ??? a8 a7 a6 a5 a4 a3 a2 1 a a0 data 3 ??? a8 a7 a6 a5 a4 a3 a2 1 a 0 a 2 words 4 words (r-3) cas latency field (a6 to a4) this field specifies the number of clock cycles from the assertion of the lal command following the rda command to the first data read. the minimum value of cas latency depends on the frequency of clk. in a write mode, the place of clock that should input write data is cas latency cycles ? 1. a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 reserved 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 reserved (r-4) test mode field (a7) this bit is used to enter test mode for supplier on ly and must be set to ?0? for normal operation. (r-5) reserved field in the regular mode register ? reserved bits (a8 to a14) these bits are reserved for future operations. they must be set to ?0? for normal operation. clk clk command qs dq data 0 data 1 data 2 data 3 rda lal cas latency = 4 (free running qs mode)
TC59LM818DMB-30,-33,-40 2003-02-28 53/55 extended mode register fields (e-1) dll switch field (a0) this bit is used to enable dll. when the a0 bit is set ?0?, dll is enabled. this bit must be set to ?0? for normal operation. (e-2) output driver impedanc e control field (a1 to a4) this field is used to choose output driver strength. three types of driver strength are supported. qs and dq driver strength can be chosen separately. a2-a1 specified the dq driver strength. a4-a3 specified the qs driver strength. qs dq a4 a3 a2 a1 output driver impedance control 0 0 0 0 normal output driver 0 1 0 1 strong output driver 1 0 1 0 weak output driver 1 1 1 1 reserved (e-3) strobe select (a6 / a5) two types of data strobe are supported. this field is used to choose the type of data strobe. (1) unidirectional ds/qs mode data strobe is separated ds for write strobe and qs for read strobe. ds is used to sample write data at write operation. qs is aligned with read data at read operation. (2) unidirectional ds/free running qs mode data strobe is separated ds for write strobe and qs for read strobe. ds is used to sample write data at write operation. qs is aligned with read data and always clocking. a6 a5 strobe select 0 0 reserved 0 1 reserved 1 0 unidirectional ds/qs mode 1 1 unidirectional ds/free running qs mode (e-4) reserved field (a7 to a14) these bits are reserved for future operations and must be set to ?0? for normal operation.
TC59LM818DMB-30,-33,-40 2003-02-28 54/55 package dimensions p-bga60-0917-1.00az 0.2 s b 0.2 s a 0.08 s ab 12.518 0 -0.15 16.5 6.218 0 -0.15 9.0 1 0.15 4 0.1 s 0.2 s 0.15min 1.2max 0.4 0.05 1.5 1.5 123 456 index r p n m l k j h g f e d c b a 1.0 1.25 2.0 2.0 1.0 1 1 1 b a s 0.5 0.05 weight: 0.15 g (typ.)
TC59LM818DMB-30,-33,-40 2003-02-28 55/55 ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their in herent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctio n or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traf fic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. ? the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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