rt9005a/b preliminary 1 ds9005a/b-01 september 2007 www.richtek.com pin configurations ddr vddq and termination voltage regulator ordering information note : richtek pb-free and green products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ` 100% matte tin (sn) plating. (top view) sop-8 (exposed pad) general description the rt9005a/b is a dual-output linear regulator for ddr- sdram vddq supply and termination voltage vtt supply. the regulator is capable of actively sinking or sourcing up to 2a. the output termination voltage can be tightly regulated to track 1/2 vddq by two external voltage divider resistors. features z z z z z ideal for ddr-i and ddr-ii vddq, vtt applications z z z z z integrated power mosfets z z z z z generates termination voltage for sstl_2, sstl _18, hstl, scsi-2 and scsi-3 interfaces z z z z z high accuracy output voltage at full-load z z z z z vout2 sink and source 2a continuous current z z z z z vout2 adjustment by two external resistors z z z z z shutdown for suspend to ram (str) functionality with high-impedance output z z z z z current limiting protection z z z z z on-chip thermal protection z z z z z available in sop-8 (exposed pad) packages z z z z z rohs compliant and 100% lead (pb)-free applications z desktop pcs, notebooks, and workstations z graphics card memory termination z set top boxes, digital tvs, printers z embedded systems z active termination buses z ddr-i and ddr-ii memory systems package type sp : sop-8 (exposed pad-option 2) operating temperature range p : pb free with commercial standard g : green (halogen free with commer- cial standard) rt9005 vout1 output voltage a : 2.5v b : 1.8v bp vin1 vin2 vcntl vout1 gnd vrefen gnd 2 3 4 5 6 7 8 vout2 9
rt9005a/b preliminary 2 ds9005a/b-01 september 2007 www.richtek.com typical application circuit functional pin description pin no. pin name pin function 1 bp noise reduction. connecting a 10nf capacitor to gnd to reduce output noise. 7, exposed pad (9) gnd common ground (t he exposed pad must be soldered to a large pc b and connected to gnd for maximum power dissipation). the gnd pad are a should be as large as possible and using many vias to conduct the heat into the buried gnd plate of pcb layer. 2 vin1 linear regulator power input voltage. 3 vin2 input voltage which supplies current to the output pin. connect this pin to a well-decoupled supply voltage. to prevent the input rail from dropping during large load transient, a large, low esr capacitor is recommended to use. the capacitor should be placed as close as possible to the vin2 pin. 4 vcntl vcntl supplies the internal control circuitr y and provides the drive voltage. the driving capability of output current is proportioned to the vcntl. connect this pin to 3.3v bias supply to handle large output current with at least 10uf capacitor from this pin to gnd . 5 vrefen reference voltage input and active low vout2 shutdown control pin. two resistors dividing down the vin voltage on the pin to create the regulated output voltage. pulling the pin to ground turns off the device by an open-drain, such as 2n7002, signal n-mosfet. 6 vout2 regulator output. vout2 is regulated to refen voltage that is used to terminate the bus resistors. it is capable of sinking and sourcing current while regulating the output rail. to maintain adequate large signal transient response, typical value of 1000 f al electrolytic capacitor with 10 f ceramic capacitors are recommended to reduce the effects of current transients on v out . 8 vout1 regulator 2.5v/1.8/1.5v output. note : if there is any application need to use 10 f ceramic capacitor in front of r tt , please shut one 1000 f (aluminum eletrolytic capacitor). vin1 vrefen gnd vout2 rt9005a/b en 2n7002 r1 r2 c ss v in1 c vcntl c in2 r tt c out2 gnd vout1 c out1 v out1 7, exposed pad(9) 3 5 8 6 bp 1 vin2 vcntl c in1 c bp v in2 v ctnl = 3.3v 2 4 2.2uf 10nf 2.2uf 1uf 470uf 47uf 470uf
rt9005a/b preliminary 3 ds9005a/b-01 september 2007 www.richtek.com function block diagram thermal shutdown vout1 gnd vin1 0.8v reference current limit sensor vcntl vrefen current limit thermal protection vout2 vin2 + - + - + - error amplifier bp vcntl
rt9005a/b preliminary 4 ds9005a/b-01 september 2007 www.richtek.com absolute maximum ratings (note 1) z supply input voltage, v in -------------------------------------------------------------------------------------------- 6v z power dissipation, p d @ t a = 25 c sop-8 (exposed) ----------------------------------------------------------------------------------------------------- 1.33w z package thermal resistance (note 4) sop-8 (exposed), ja ------------------------------------------------------------------------------------------------ 75 c/w sop-8 (exposed), jc ----------------------------------------------------------------------------------------------- 28 c/w z junction temperature ------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10se c.) ---------------------------------------------------------------------------- 260 c z storage temperature range ---------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 2) hbm (human body mode) ------------------------------------------------------------------------------------------ 2kv mm (ma chine mode) -------------------------------------------------------------------------------------------------- 200v electrical characteristics parameter symbol test conditions min typ max units input operation current i vcntl i out = 0a -- 1.5 3.0 ma standby current (note 5) i stby2 v refen < 0.2v (shutdown), r load = 180 -- 50 90 a vout1 (vddq) vout1 accuracy v out i out = 10ma ? 2 -- +2 v vout1 current limit i lim1 r load = 0.5 , v in1 = 3.3v 2 2.8 3 a i out = 0.5a -- 120 180 vout1 dropout voltage (note 6) v drop i out = 1.0a -- 240 360 mv line regulation v line v in1 = (v out1 + 0.5v) to 5.5v i out1 = 1ma -- -- 0.3 % load regulation (note 7) v load v in1 = (v out1 + 0.5v) 10ma < i out1 < 1a -- 0.4 -- %/a vout2 (vtt) output offset voltage (note 8) v os i out = 0a ? 20 -- +20 mv recommended operating conditions (note 3) z supply input voltage, v in1 ------------------------------------------------------------------------------------------ 5v to 2.5v z supply input voltage, v in2 ------------------------------------------------------------------------------------------ 3.6v to 1.5v z control voltage, v cntl ----------------------------------------------------------------------------------------------- 5v to 3.1v z junction temperature range ---------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------------------------------------------------------------------- ? 40 c to 85 c to be continued (v in1 =3.3v , v in1 = v out + 1v, c in1 = c out1 = 2.2 f (ceramic) & c bp = 10nf; v in2 = 2.5v/1.8/1.5v, v cntl = 3.3v, v refen = 1.25v/ 0.9/0.75v, c in2 = 470 f, c vcntl = 47 f, c out2 = 1000 f(electrolytic), t a = 25 c , unless otherwise specified)
rt9005a/b preliminary 5 ds9005a/b-01 september 2007 www.richtek.com parameter symbol test conditions min typ max units i out = +2a load regulation (note 7) v load i out = ? 2a ? 20 -- +20 mv vout2 current limit i lim2 2.2 -- -- a protection thermal shutdown temperature t sd -- 170 -- c thermal shutdown hysteresis t sd -- 35 -- c refen shutdown v ih enable 0.6 -- -- shutdown threshold v il shutdown -- -- 0.2 v note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. the device is not guaranteed to function outside its operating conditions. note 4. ja is measured in the natural convection at t a = 25 c on a high effective thermal conductivity test board (4 layers, 2s2p) of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for sop-8 (exposed pad) package. note 5. v out2 standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on refen pin (v il < 0.2v). it is measured with v in2 = v cntl = 5 v. note 6. the dropout voltage is defined as v in -v out , which is measured when v out is v out(normal) ? 100mv. note 7. regulation is measured at constant junction temperature by using a 5ms current pulse. devices are tested for load regulation in the load range from 0a to 2a. note 8. v os offset is the voltage measurement defined as v out subtracted from v refen .
rt9005a/b preliminary 6 ds9005a/b-01 september 2007 www.richtek.com typical operating characteristics v cntl current vs. temperature 0.3 0.35 0.4 0.45 0.5 0.55 0.6 -50 -25 0 25 50 75 100 125 temperature v cntl current (ma) ( c) v in2 = 2.5v, v cntl = 5v v in2 = 2.5v, v cntl = 3.3v v in2 = 1.8v, v cntl = 3.3v v in2 = 1.8v, v cntl = 5v v in2 = 1.5v, v cntl = 5v v in2 = 1.5v, v cntl = 3.3v v in2 current vs. temperature 2 2.5 3 3.5 4 4.5 5 -50 -25 0 25 50 75 100 125 temperature v in2 current (ma) v in2 = 2.5v, v cntl = 5v v in2 = 2.5v, v cntl = 3.3v v in2 = 1.8v, v cntl = 3.3v v in2 = 1.8v, v cntl = 5v v in2 = 1.5v, v cntl = 5v v in2 = 1.5v, v cntl = 3.3v ( c) output voltage vs. temperature 1.0 1.5 2.0 2.5 3.0 -50 -25 0 25 50 75 100 125 temperature output voltage (v) v in1 = v in2 = v cntl = 3.3v ( c) v out1 = 2.5v v out1 = 1.25v v out1 short circuit v out1 (1v/div) v in1 = v in2 = v cntl = 3.3v time (1ms/div) i out1 (1a/div) refen threshold vs. temperature 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 -50 -25 0 25 50 75 100 125 temperature refen threshold (v) ( c) v cntl = 3.3v, turn on v cntl = 5v, turn off v cntl = 5v, turn on v cntl = 3.3v, turn off v out2 short circuit v out2 (1v/div) v in1 = v in2 = v cntl = 3.3v time (1ms/div) i out2 (2a/div)
rt9005a/b preliminary 7 ds9005a/b-01 september 2007 www.richtek.com v in1 = v in2 = v cntl = 3.3v, i out2 = 50ma to 2a v out2 @ 2a load transient response time (500 s/div) v out1 (20mv/div) v out2 (20mv/div) i out2 (2a/div) source v in1 = v in2 = v cntl = 3.3v, i out2 = 50ma to 2a v out2 @ 2a load transient response time (500 s/div) v out1 (20mv/div) v out2 (20mv/div) i out2 (2a/div) sink v in1 = v in2 = v cntl = 3.3v, i out1 = 50ma to 1.5a v out1 @ 1.5a load transient response time (500 s/div) v out1 (100mv/div) v out2 (100mv/div) i out1 (1a/div) v in2 = v cntl = 3.3v, i load = 1a line transient response v in1 (v) time (500 s/div) v out1 (100mv/div) 4.3 3.3 v out2 (100mv/div) v in1 = v in2 = v cntl = 3.3v, i out1 = 50ma to 1a v out1 @ 1a load transient response time (500 s/div) v out1 (50mv/div) v out2 (50mv/div) i out1 (1a/div)
rt9005a/b preliminary 8 ds9005a/b-01 september 2007 www.richtek.com application information thermal consideration rt9005a/b regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. for continued operation, do not exceed maximum operation junction temperature 125 c. the power dissipation definition in device is : p d = (v in - v out ) x i out + v in x i q the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) -t a ) / ja where t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. the junction to ambient thermal resistance ( ja is layout dependent) for sop-8 package (exposed pad) is 75 c/ w on standard jedec 51-7 (4 layers, 2s2p) thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c - 25 c) / 75 c/w = 1.33w figure 2 show the package sectional drawing of sop-8 (exposed pad). every package has several thermal dissipation paths. as show in figure 2, the thermal resistance equivalent circuit of sop-8 (exposed pad). the path 2 is the main path due to these materials thermal conductivity. we define the exposed pad is the case point of the path 2. ambient molding compound gold line lead frame die pad case (exposed pad) figure 1. sop-8 (exposed pad) package sectional drawing figure 2. thermal resistance equivalent circuit junction r die r die-attach r die-pad r gold-line r lead frame case (exposed pad) r pcb r pcb ambient r molding-compound path 1 path 2 path 3 the thermal resistance ja of sop-8 (exposed pad) is determined by the package design and the pcb design. however, the package design has been decided. if possible, it's useful to increase thermal performance by the pcb design. the thermal resistance can be decreased by adding copper under the expose pad of sop-8 package. about pcb layout , the figure 3 show the relation between thermal resistance ja and copper area on a standard jedec 51-7 (4 layers, 2s2p) thermal test board at t a = 25 c.we have to consider the copper couldn't stretch infinitely and avoid the tin overflow. we use the ? dog-bone ? copper patterns on the top layer as figure 4. as shown in figure 5, the amount of copper area to which the sop-8 (exposed pad) is mounted affects thermal performance. when mounted to the standard sop-8 (exposed pad) pad of 2 oz. copper (figure 5.a), ja is 75 c/w. adding copper area of pad under the sop-8 (exposed pad) (figure 5.b) reduces the ja to 64 c/w. even further, increasing the copper area of pad to 70mm 2 (figure 5.e) reduces the ja to 49 c/w.
rt9005a/b preliminary 9 ds9005a/b-01 september 2007 www.richtek.com ja vs. copper area 30 40 50 60 70 80 90 100 0 10203040506070 copper area (mm 2 ) ja (c/w) figure 3 figure 4. dog-bone layout figure 5 (a). minimum footprint, ja = 75 c/w exposed pad w Q 2.28mm figure 5. thermal resistance vs. different cooper area layout design figure 5 (b). copper area = 10mm 2 , ja = 64 c/w figure 5 (c). copper area = 30mm 2 , ja = 54 c/w figure 5 (d). copper area = 50mm 2 , ja = 51 c/w figure 5 (e). copper area = 70mm 2 , ja = 49 c/w
rt9005a/b preliminary 10 ds9005a/b-01 september 2007 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 8f, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com outline dimension a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package symbol dimensions in millimeters dimensions in inches min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 option 1 x 2.000 2.300 0.079 0.091 y 2.000 2.300 0.079 0.091 option 2 x 2.100 2.500 0.083 0.098 y 3.000 3.500 0.118 0.138
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