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19-3886; rev 1; 8/06 general description the max8809a/max8810a synchronous, 2-/3-/4- phase, step-down, current-mode controllers with inte- grated dual-phase mosfet drivers provide flexible solutions that fully comply with intel vrd11/vrd10 and amd k8 rev f cpu core supplies. the flexible design supplies load currents up to 150a for low-volt- age cpu core power requirements. a tri-state sel input is available to configure the vid logic for either the intel vrd11/vrd10 or amd k8 rev f applications. an enable input (en) is available to dis- able the ic. true-differential remote output-voltage sensing enables precise regulation at the load by elimi- nating the effects of trace impedance in the output and return paths. a high-accuracy dac combined with pre- cision current-sense amplifiers and droop control enable the max8809a/max8810a to meet the most stringent tolerance requirements of new-generation high-current cpus. these ics use either integral or volt- age-positioning feedback control to achieve high out- put-voltage accuracy. the comp input allows for either positive or negative voltage offsets from the vid code voltage. a power- good signal (vrready) is provided for startup sequencing and fault annunciation. the ss/ovp pin enables the programming of the soft-start period, and provides an indication of an overvoltage condition. a soft-stop feature prevents negative voltage spikes on the output at turn-off, eliminating the need for an exter- nal schottky clamp diode. the max8809a/max8810a incorporate a proprietary ?apid active average?current-mode control scheme for fast and accurate transient-response performance, as well as precise load current sharing. either the inductor dcr or a resistive current-sensing element is used for current sensing. when used with dcr sensing, rapid active current averaging (ra 2 ) eliminates the tolerance effects of the inductance and associated current-sens- ing components, providing superior phase current matching, accurate current limit, and precise load-line. the max8809a operates as a single-chip, 2-phase solution with integrated drivers. it also provides a 3rd- phase pwm output and easily supports 3-phase design by adding the max8552 high-performance driver. the max8810a enables up to 4-phase designs by adding the max8523 high-performance dual driver for a com- pact 2-chip solution. features ? vrd11/vrd10 and k8 rev f compliant ? ?.35% initial output voltage accuracy ? dual integrated drivers with integrated bootstrap diodes ? up to 26v input voltage ? adaptive shoot-through protection ? soft-start, soft-stop, vrready output ? fast load transient response ? individual phase, fully temperature- compensated cycle-by-cycle average current limit ? current foldback at short circuit ? voltage positioning or integral feedback ? differential remote voltage sensing ? programmable positive and negative offset voltages ? 150khz to 1.2mhz switching frequency per phase ? ntc-based, temperature-independent load line ? precise phase current sharing ? programmable thermal-monitoring output (vrhot) ? 6a peak mosfet drivers ? 0.3 /0.85 low-side, 0.8 /1.1 high-side drivers (typ) ? 40-pin and 48-pin thin qfn packages applications desktop pcs servers, workstations desknote and lcd pcs voltage-regulator modules max8809a/max8810a vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers ________________________________________________________________ maxim integrated products 1 for pricing delivery, and ordering information please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information + denotes lead-free package. note: all parts are specified in the -40c to +85? extended temperature range. evaluation kit available part pin- package pkg code function max8809a etl+ 40 thin qfn 5mm x 5mm t4055-1 2-/3-phase max8810a etm+ 48 thin qfn 6mm x 6mm t4866-1 2-/3-/4-phase pin configurations appear at end of data sheet. intel is a registered trademark of intel corp.
max8809a/max8810a 2 _______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers absolute maximum ratings electrical characteristics (v vl_ = v bst_ = 6.5v, v cc = v en = 5v, v ilim = 1.5v, vid_ = sel = ref = buf = unconnected, v comp = v rs+ = 1.0v, r vrready = 5k pullup to 5v, r ss/ovp = 12k to gnd, r ntc = 10k to gnd, f sw = 300khz, r vrtset = 118k to gnd, v cs_+ = v cs_- = 1v, pwm_ = unconnected, r vrhot = 249 pullup to 1.05v, v gnd = v pgnd_ = v lx_ = v rs- = 0v, dl_ = dh_ = unconnected, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ref, comp, ss/ovp, osc, ntc, vrtset, rs+, rs-, pwm_ to gnd.......................-0.3v to (v cc + 0.3v) cs_+, cs_-, vid_, buf, en, ilim, sel, vrready, vrhot, v cc to gnd ............................................-0.3v to +6v bst_ to pgnd_ ......................................................-0.3v to +35v lx_ to pgnd_............................................................-1v to +28v bst_ to vl_ ...............................................................-1v to +30v dh_ to pgnd_ .........................................-0.3v to (v bst_ + 0.3v) dh_, bst_ to lx_ .....................................................-0.3v to +7v vl_ to pgnd_ ..........................................................-0.3v to +7v dl_ to pgnd_ ..........................................-0.3v to (v vl_ + 0.3v) pgnd_ to gnd......................................................-0.3v to +0.3v cs_+ to cs_-.........................................................-0.3v to +0.3v dh_, dl_ current ....................................................?00ma rms vl_ to bst_ diode current...........................................50ma rms continuous power dissipation (t a = +70 c) 40-pin thin qfn 5mm x 5mm (derate 35.7mw/ c above +70 c) ..........................2857.1mw 48-pin thin qfn 6mm x 6mm (derate 37mw/ c above +70 c) ................................2963mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter conditions min typ max units v cc operating range 4.5 5.5 v rising 4.0 4.25 4.5 v cc uvlo trip level falling 3.7 4.0 4.3 v v cc shutdown supply current v cc < 3.75v 0.35 ma v cc standby supply current v en = 0v 0.5 ma v cc operating supply current v rs+ - v rs- = 1.0v, no switching, v dac = 1.0v (note 1) 13 ma thermal shutdown temperature rising, hyster esi s = 25 c ( typ ) +160 c internal reference (ref) output voltage i ref = -100? 1.992 2.000 2.008 v output regulation (sourcing) v cc = 4.5v at i ref = -500? to v cc = 5.5v at i ref = -100? -0.05 +0.05 % output regulation (sinking) v cc = 4.5v at i ref = +100? to v cc = 5.5v at i ref = +500? -0.2 +0.2 % reference uvlo trip level rising (100mv typ hysteresis) 1.84 v buf reference buf regulation voltage i buf = 0a 0.99 1.0 1.01 v buf output regulation v cc = 4.5v at i buf = +100? to v cc = 5.5v at i buf = +500? -0.25 +0.25 % soft-start en startup delay (td1) from en rising to v out rising 1.6 2.2 2.8 ms soft-start period range (td2) 12k < r ss/ovp < 90.9k 0.5 6.5 ms soft-start tolerance r ss/ovp = 56k () = =
max8809a/max8810a _______________________________________________________________________________________ 3 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers electrical characteristics (continued) (v vl_ = v bst_ = 6.5v, v cc = v en = 5v, v ilim = 1.5v, vid_ = sel = ref = buf = unconnected, v comp = v rs+ = 1.0v, r vrready = 5k pullup to 5v, r ss/ovp = 12k to gnd, r ntc = 10k to gnd, f sw = 300khz, r vrtset = 118k to gnd, v cs_+ = v cs_- = 1v, pwm_ = unconnected, r vrhot = 249 pullup to 1.05v, v gnd = v pgnd_ = v lx_ = v rs- = 0v, dl_ = dh_ = unconnected, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units voltage regulation rs+ input bias current v rs+ = 1v 0.1 1 a rs- input bias current v rs- = 0.2v 0.1 1 a output voltage initial accuracy v dac = 1v (note 1) -0.35 +0.35 % t a = +25? to +85? -3.5 +3.5 droop accuracy v dac = 1v (note 1), r ntc = 10k t a = -5? to +85? -5.5 +5.5 % g mv amplifier transconductance 1.94 2.00 2.06 ms g mv gain bandwidth product 5 mhz comp output current v dac - v rs+ = 200mv (note 1) 385 ? current limit average current-limit trip level accuracy v ilim = 1.5v -6 +6 % ilim input bias current 0.01 1a ilim default program level v ilim > v cc - 0.2v 1.197 1.330 1.463 v enable input (en) turn-on threshold (rising) v cc = 4.5v to 5.5v, 100mv typ hysteresis 0.8 0.85 0.9 v logic inputs (vid0?id7) intel (sel = high or low) input low level v cc = 4.5v to 5.5v 0.4 v input high level v cc = 4.5v to 5.5v 0.8 v input pulldown resistance 100 270 k amd (sel = unconnected) input low level v cc = 4.5v to 5.5v 0.6 v input high level v cc = 4.5v to 5.5v 1.4 v input pulldown resistance 100 270 k logic input (sel) internal bias resistance 50 100 200 k internal bias voltage v cc = 4.5v to 5.5v v cc / 2 v input low level v cc = 4.5v to 5.5v 0.5 v input high level v cc = 4.5v to 5.5v v cc - 0.5 v vrready output output low level i vrready = +4ma 0.4 v output high leakage v vrready = 5.5v 1 a vrready blanking time fr om e n r i si ng to v rre ad y r isi ng, r s s /ov p = 12k 3.0 5.5 ms
max8809a/max8810a 4 _______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers electrical characteristics (continued) (v vl_ = v bst_ = 6.5v, v cc = v en = 5v, v ilim = 1.5v, vid_ = sel = ref = buf = unconnected, v comp = v rs+ = 1.0v, r vrready = 5k pullup to 5v, r ss/ovp = 12k to gnd, r ntc = 10k to gnd, f sw = 300khz, r vrtset = 118k to gnd, v cs_+ = v cs_- = 1v, pwm_ = unconnected, r vrhot = 249 pullup to 1.05v, v gnd = v pgnd_ = v lx_ = v rs- = 0v, dl_ = dh_ = unconnected, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units (v rs+ - v rs-) rising v dac + 0.150 v dac + 0.200 vrready upper threshold (note 1) (v rs+ - v rs-) falling v dac + 0.075 v dac + 0.125 v (v rs+ - v rs-) falling v dac - 0.250 v dac - 0.200 vrready lower threshold (note 1) (v rs+ - v rs-) rising v dac - 0.175 v dac - 0.125 v overvoltage protection intel (sel = high or low) (v rs+ - v rs-) rising (note 1) v dac + 0.150 v dac + 0.175 v dac + 0.200 v amd (sel = unconnected) (v rs+ - v rs-) rising 1.750 1.775 1.800 v ss/ovp high level i ss/ovp = -10ma v cc - 0.450 v oscillator oscillator frequency accuracy (per phase) frequency per phase = 300khz -10 +10 % switching frequency range (per phase) 150 1200 khz current-sense amplifiers current-sense amplifier gain (g ca )r ntc = 10k , t a = +25? to +85? 28.8 30.0 31.2 v/v cs_+ input bias current v cs_+ = v cs _- = 2v 0.3 3.0 ? cs_- input bias current v cs_+ = v cs _- = 2v 0.6 5.5 ? cs to pwm_ delay v comp falling 20 ns gain temperature compensation (ntc) compensation accuracy r ntc temperature = 0 c to +125 c (10k ntc panasonic ertj1vr103) -6 +6 % vrhot temperature monitoring vrhot output low voltage i vrhot = +4ma 0.4 v vrhot output high leakage current v vrhot = 5.5v 5 a vrtset temperature range +60 +125 c vrtset accuracy r n tc tem p er atur e = + 60 c to + 125 c , 15 c hyster esi s ( typ ) ( 10k n tc p anasoni c e rtj1v r103) -5 +5 c
max8809a/max8810a _______________________________________________________________________________________ 5 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers electrical characteristics (continued) (v vl_ = v bst_ = 6.5v, v cc = v en = 5v, v ilim = 1.5v, vid_ = sel = ref = buf = unconnected, v comp = v rs+ = 1.0v, r vrready = 5k pullup to 5v, r ss/ovp = 12k to gnd, r ntc = 10k to gnd, f sw = 300khz, r vrtset = 118k to gnd, v cs_+ = v cs_- = 1v, pwm_ = unconnected, r vrhot = 249 pullup to 1.05v, v gnd = v pgnd_ = v lx_ = v rs- = 0v, dl_ = dh_ = unconnected, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units pwm driver output low level i pwm_ = +5ma 0.1 0.4 v output high level i pwm_ = -5ma 4.5 4.9 v source current v pwm_ = v cc - 2v 52 ma sink current v pwm_ = 2v 65 ma rise/fall times 10 ns pwm disable program threshold 4v < v cc < 5.5v 3.0 v cc - 0.7 v gate-driver specifications v l_, bs t_ to lx _ inp ut v ol tag e rang e 4.5 6.5 v lx operating range 26 v vl_ uvlo threshold (vl12, max8809a; vl1, max8810a) v vl_ rising, 250mv hysteresis (typ) 3.25 3.55 3.80 v dh_ = bst_ 1 1.6 driver static supply current, i vl_ (per channel) dh_ = lx_ 1.1 1.8 ma boost static supply current, i bst_ (per channel) dh_ = bst_ 0.6 1 ma sourcing current, v vl _ = 6.5v 1.1 2.0 dh driver resistance sinking current, v vl _ = 6.5v 0.8 1.2 sourcing current, v vl _ = 6.5v 0.85 1.7 dl driver resistance sinking current, v vl _ = 6.5v 0.3 0.6 dh_ rise time (t rdh )c dh_ = 3000pf 14 ns dh_ fall time (t fdh )c dh_ = 3000pf 9 ns dl_ rise time (t rdl )c dl_ = 3000pf 10 ns dl_ fall time (t fdl )c dl_ = 3000pf 7 ns dh_ propagation delay (t pdhf ) cs+ rising to dh falling 32 ns dead time (t pdlr ) lx_ falling to dl_ rising 18 ns dead time (t dead ) dl_ falling to dh_ rising 35 ns internal boost-diode specifications on-resistance i bst_ = 2ma 6
max8809a/max8810a 6 _______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers parameter conditions min typ max units v cc operating range 4.5 5.5 v rising 4.0 4.5 v cc uvlo trip level falling 3.7 4.3 v internal reference (ref) output voltage i ref = -100? 1.99 2.01 v output regulation (sourcing) v cc = 4.5v at i ref = -500? to v cc = 5.5v at i ref = -100? -0.065 +0.065 % output regulation (sinking) v cc = 4.5v at i ref = +100? to v cc = 5.5v at i ref = +500? -0.2 +0.2 % buf reference buf regulation voltage i buf = 0a 0.99 1.01 v buf output regulation v cc = 4.5v at i buf = +100? to v cc = 5.5v at i ref = +500? -0.4 +0.4 % soft-start en startup delay (td1) from en rising to v out rising 1.6 2.8 ms soft-start period range (td2) 12k < r ss/ovp < 90.9k 0.5 6.5 ms soft-start tolerance r ss/ovp = 56k () = = voltage regulation rs+ input bias current v rs+ = 1.0v 1 a rs- input bias current v rs- = 0.2v 1 a output-voltage initial accuracy v dac_ = 1v (note 1) -0.35 +0.35 % g mv amplifier transconductance 1.91 2.06 ms current limit average current-limit trip-level accuracy v ilim = 1.5v -11 +11 % ilim input bias current 1a ilim default program level v ilim > v cc - 0.2v 1.197 1.463 v enable input (en) turn-on threshold (rising) v cc = 4.5v to 5.5v, 100mv typ hysteresis 0.8 0.9 v logic inputs (vid0?id7) intel (sel = high or low) input low level v cc = 4.5v to 5.5v 0.4 v input high level v cc = 4.5v to 5.5v 0.8 v input pulldown resistance 100 270 k electrical characteristics (v vl_ = v bst_ = 6.5v, v cc = v en = 5v, v ilim = 1.5v, vid_ = sel = ref = buf = unconnected, v comp = v rs+ = 1.0v, r vrready = 5k pullup to 5v, r ss/ovp = 12k = r ntc = 10k to gnd, f sw = 300khz, r vrtset = 50k to gnd, v cs_+ = v cs_- = 1v, pwm_ = unconnected, r vrhot = 249 pullup to 1.05v, v gnd = v pgnd_ = v lx_ = v rs- = 0v, dl_ = dh_ = unconnected, t a = -40 c to +85 c .) (note 2)
max8809a/max8810a _______________________________________________________________________________________ 7 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers parameter conditions min typ max units amd (sel = unconnected) input low level v cc = 4.5v to 5.5v 0.6 v input high level v cc = 4.5v to 5.5v 1.4 v input pulldown resistance 100 270 k logic input (sel) internal bias resistance 50 200 k input low level v cc = 4.5v to 5.5v 0.5 v input high level v cc = 4.5v to 5.5v v cc - 0.5 v vrready output output low level i vrready = +4ma 0.4 v output high leakage v vrready = 5.5v 1 a vrready blanking time fr om e n r i si ng to v rre ad y r i si ng , r s s / ov p = 12k 3.0 5.5 ms (v rs+ - v rs-) rising v d ac + 0.150 v d ac + 0.200 vrready upper threshold (note 1) (v rs+ - v rs-) falling v d ac + 0.075 v d ac + 0.125 v (v rs+ - v rs-) falling v dac - 0.250 v dac - 0.200 vrready lower threshold (note 1) (v rs+ - v rs-) rising v dac - 0.175 v dac - 0.125 v overvoltage protection intel (sel = high or low) (v rs+ - v rs-) rising (note 1) v d ac + 0.150 v d ac + 0.200 v amd (sel = unconnected) (v rs+ - v rs-) rising 1.75 1.80 v ss/ovp high level i ss/ovp = 10ma v cc - 0.450 v oscillator oscillator frequency accuracy (per phase) frequency per phase = 300khz -20 +20 % switching frequency range (per phase) 150 1200 khz electrical characteristics (continued) (v vl_ = v bst_ = 6.5v, v cc = v en = 5v, v ilim = 1.5v, vid_ = sel = ref = buf = unconnected, v comp = v rs+ = 1.0v, r vrready = 5k pullup to 5v, r ss/ovp = 12k = r ntc = 10k to gnd, f sw = 300khz, r vrtset = 50k to gnd, v cs_+ = v cs_- = 1v, pwm_ = unconnected, r vrhot = 249 pullup to 1.05v, v gnd = v pgnd_ = v lx_ = v rs- = 0v, dl_ = dh_ = unconnected, t a = -40 c to +85 c .) (note 2)
max8809a/max8810a 8 _______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers parameter conditions min typ max units current-sense amplifiers current-sense amplifier gain (g ca )r ntc = 10k 27 33 v/v cs_+ input bias current v cs _+ = v cs _- = 2v 4.5 ? cs_- input bias current v cs _+ = v cs _- = 2v 7 a gain temperature compensation (ntc) tem p er atur e c om p ensati on accur acy r ntc temperature = 0 c to +125 c (10k ntc panasonic ertj1vr103) -7.5 +7.5 % vrhot temperature monitoring vrhot output low voltage 4ma sink current 0.4 v vrhot output high leakage current v vrhot = 5.5v 5 a vrtset temperature range +60 +125 c vrtset accuracy r ntc temperature = +60 c to +125 c (10k ntc panasonic ertj1vr103) -5 +5 c pwm driver output low level i pwm_ = +5ma 0.4 v output high level i pwm_ = -5ma 4.5 v pwm disable program threshold 4v < v cc < 5.5v 3 v gate-driver specifications vl_, bst_ to lx_ input voltage range 4.5 6.5 v lx_ operating range 26 v vl_ uvlo threshold (max8809a, vl12; max8810a, vl1) v vl_ rising, 250mv hysteresis (typ) 3.25 3.80 v dh_ = bst_ 1.6 driver static supply current, i vl_ (per channel) dh_ = lx_ 1.8 ma boost static supply current, i bst_ (per channel) dh_ = bst_ 1 ma sourcing current, v vl _ = 6.5v 2.0 dh_ driver resistance sinking current, v vl _ = 6.5v 1.2 sourcing current, v vl _ = 6.5v 1.7 dl_ driver resistance sinking current, v vl _ = 6.5v 0.6 electrical characteristics (continued) (v vl_ = v bst_ = 6.5v, v cc = v en = 5v, v ilim = 1.5v, vid_ = sel = ref = buf = unconnected, v comp = v rs+ = 1.0v, r vrready = 5k pullup to 5v, r ss/ovp = 12k = r ntc = 10k to gnd, f sw = 300khz, r vrtset = 50k to gnd, v cs_+ = v cs_- = 1v, pwm_ = unconnected, r vrhot = 249 pullup to 1.05v, v gnd = v pgnd_ = v lx_ = v rs- = 0v, dl_ = dh_ = unconnected, t a = -40 c to +85 c .) (note 2) note 1: v dac refers to the internal voltage set by the vid code. note 2: specifications to -40 c are guaranteed by design and characterization.
typical operating characteristics (circuit of figure 14, v in = 12v, v out = 1.35v, i out_max = 115a, r o = 1m , f sw = 200khz, v cc = 5v, v vl_ = 6.5v, t a = +25?, unless otherwise noted.) max8809a/max8810a _______________________________________________________________________________________ 9 efficiency vs. load current r osc = 130k load current (a) efficiency (%) max8809a toc01 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 v in = 12v v in = 20v v in = 7v output voltage vs. load current load current (a) output voltage (v) max8809a toc02 0 20 40 60 80 100 120 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 output voltage vs. inductor temperature max8809a toc03 inductor temperature ( c) output voltage (v) 100 75 50 25 1.20 1.25 1.30 1.35 1.40 1.15 0 125 i load = 50a i load = 0a output load transient max8809a toc04 i out v out 50mv/div 60a/div 20 s/div active current sharing vs. load current load current (a) v dc (mv) max8809a toc05 0 50 100 0 5 10 15 20 25 measured across c19, c20, c26, c27 average dcr is 0.86m (+25 c) dynamic vid response max8809a toc06 vrready i out v out vrready 500mv/div 60a/div 1v/div 200 s/div soft-start waveforms (intel) max8809a toc07 en v out i in vrready 500ma/div 1v/div 1v/div 1v/div 1ms/div vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers
typical operating characteristics (continued) (circuit of figure 14, v in = 12v, v out = 1.35v, i out_max = 115a, r o = 1m , f sw = 200khz, v cc = 5v, v vl_ = 6.5v, t a = +25?, unless otherwise noted.) max8809a/max8810a 10 ______________________________________________________________________________________ soft-start waveforms (amd) max8809a toc08 i in v out ven vrready 500ma/div 1v/div 1v/div 1v/div 1ms/div shutdown waveforms at no load max8809a toc09 en v out i in vrready 500ma/div 1v/div 1v/div 1v/div 400 s/div shutdown waveforms at full load max8809a toc10 en v out i in vrready 500mv/div 2v/div 1v/div 5a/div 500 s/div short-circuit and recovery waveforms max8809a toc11 vrready i out i in v out 500mv/div 50a/div 5a/div 2v/div 40 s/div current threshold vs. inductor case temperature inductor temperature ( c) rms current limit (a) max8809a toc12 90 80 60 70 10 20 30 40 50 0 20 40 60 80 100 120 140 160 i lim = 155a i lim = 100a 180 0 -10 100 reference voltage vs. ambient temperature ambient temperature ( c) reference voltage (v) max8809a toc13 -40-200 20406080 1.90 1.95 2.00 2.05 2.10 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers
typical operating characteristics (continued) (circuit of figure 14, v in = 12v, v out = 1.35v, i out_max = 115a, r o = 1m , f sw = 200khz, v cc = 5v, v vl_ = 6.5v, t a = +25?, unless otherwise noted.) max8809a/max8810a ______________________________________________________________________________________ 11 buf voltage vs. ambient temperature ambient temperature ( c) buf voltage (v) max8809a toc14 -40-200 20406080 0.90 0.95 1.00 1.05 1.10 per-phase frequency vs. r osc r osc (k ) per-phase frequency (khz) max8809a toc15 0 100 200 100 300 500 700 900 1100 1300 2/4 phase 3 phase clock frequency vs. temperature temperature ( c) frequency (khz) max8809a toc16 -40 -15 10 35 60 85 500 550 600 650 700 750 800 850 900 950 1000 output voltage offset vs. r os max8809a toc17 r os (k ) output voltage (mv) 50 40 30 5 15 10 20 25 30 35 0 20 60 soft-start duration vs. r ss/ovp r ss/ovp (k ) soft-start duration (ms) max8809a toc18 0 20406080100 0 1 2 3 4 5 6 vrhot setpoint vs. r vrtset r vrtset (k ) vrhot setpoint ( c) max8809a toc19 0 50 100 150 200 250 300 50 60 70 80 90 100 110 120 130 output overvoltage protection waveform max8809a toc20 v out ss/ovp vrready 500mv/div 1v/div 5v/div 2 s/div vl_ power dissipation vs. per-phase switching frequency f s (khz) vl_ power dissipation (mw) max8809a toc21 0 200 400 600 800 1000 0 200 400 600 800 1000 c dl_ = c dh_ = 3300pf 1200 1400 1600 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers
max8809a/max8810a 12 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 14, v in = 12v, v out = 1.35v, i out_max = 115a, r o = 1m , f sw = 200khz, v cc = 5v, v vl_ = 6.5v, t a = +25?, unless otherwise noted.) vl_ power dissipation vs. load capacitance dh_/dl_ load capacitance (pf) vl_ power dissipation (mw) max8809a toc22 1000 2000 3000 4000 5000 6000 7000 0 50 100 150 200 250 300 350 400 dl_ rise/fall time vs. load capacitance load capacitance (pf) rise/fall time (ns) max8809a toc23 1000 3000 5000 7000 0 5 10 15 20 25 30 dl_ rise dl_ fall dh_ rise/fall time vs. load capacitance load capacitance (pf) rise/fall time (ns) max8809a toc24 0 2000 4000 6000 8000 0 5 10 15 20 25 30 dh_ rise dh_ fall dh_/dl_ rise/fall time vs. ambient temperature ambient temperature ( c) rise/fall time (ns) max8809a toc25 -40 -20 0 20 40 60 80 0 5 10 15 20 25 dl_ rise dh_ rise dh_ fall dl_ fall c dh_ = c dl_ = 3300pf vl_ supply current vs. per-phase switching freqency f s (khz) vl_ supply current (ma) max8809a toc26 0 200 400 600 800 1000 0 50 100 150 200 250 c dh_ = c dl_ = 3300pf switching waveforms max8809a t0c27 dl_ dh_ lx_ 10v/div 10v/div 20v/div 200ns/div vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers
max8809a/max8810a ______________________________________________________________________________________ 13 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers bst_ and vl_ waveforms v in = 8v max8809a toc28 vl_ lx_ bst_ 500mv/div (ac-coupled) 200mv/div (ac-coupled) 5v/div 500ns/div typical operating characteristics (continued) (circuit of figure 14, v in = 12v, v out = 1.35v, i out_max = 115a, r o = 1m , f sw = 200khz, v cc = 5v, v vl_ = 6.5v, t a = +25?, unless otherwise noted.) dh_ falling propagation delay vs. temperature ambient temperature ( c) propagation delay (ns) max8809a toc29 -40-200 20406080 20 25 30 35 40 45 50 pin description pin max8809a max8810a name function 148 vrready o p en- d r ai n, p ow er - o kay ind i cator . v rre ad y i s an op en- d r ai n outp ut that g oes hi g h i m p ed ance w hen the outp ut i s i n r eg ul ati on. v rre ad y p ul l s l ow w hen the outp ut i s out of r eg ul ati on, the ic i s i n shutd ow n, or v c c i s b el ow the u v lo thr eshol d . 2 1 ilim current-limit set input. connect to the center tap of an external resistor-divider from ref to gnd to set the cycle-by-cycle average current-limit threshold. connect ilim to v cc to select the default current-limit threshold. 3 2 ref inter nal refer ence o utp ut. re f r eg ul ates to 2v . byp ass re f to g n d w i th a 0.1f to 1f cer am i c cap aci tor . d o not use a cap aci tor g r eater than 1f. re f sour ces up to 500? for exter nal l oad s. re f i s enab l ed w hen v c c i s ab ove u v lo r eg ar d l ess of the state of e n . 4 3 comp error-amplifier output. connect comp to the compensation network to implement either voltage positioning or integral feedback-control. connect a resistor from comp to gnd to set the offset voltage. see the loop-compensation design section for details on determining the compensation network. 5 5 gnd analog ground. connect gnd to the analog ground plane. 66v cc ic supply input. connect v cc to a 4.5v to 5.5v power supply. bypass v cc to gnd with a 1? or larger ceramic capacitor. 7 8 rs- output-voltage remote-sense negative input. connect rs- to the v ss_sen remote- sense point at the load when using the remote sense. otherwise, connect rs- to gnd at the load. 8 9 rs+ output-voltage remote-sense positive input. connect rs+ to the v cc_sen remote- sense point at the load when using remote sense. otherwise, connect rs+ to the output at the load.
max8809a/max8810a 14 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers pin description (continued) pin max8809a max8810a name function 9 11 osc internal clock oscillator frequency set input. connect a resistor from osc to gnd to set the internal oscillator frequency. see the setting the switching frequency section for determining the resistor value. 10 12 ss/ovp s oft- s tar t p r og r am inp ut and over vol tag e- p r otecti on faul t fl ag . c onnect a r esi stor fr om s s /ov p to gn d to set the soft- star t p er i od . s s /o v p p ul l s to v c c d ur i ng an o v p event to si g nal the faul t cond i ti on. s ee the s oft- s tar t secti on for d eter m i ni ng the r esi stor val ue. 11 13 vrtset temperature comparator program input. connect a resistor from vrtset to gnd to set the vrhot temperature threshold. connect vrtset to v cc to disable the vrhot monitoring feature. see the temperature monitoring (vrtset, vrhot) section for resistor selection. 12 14 ntc temperature-sensing input. connect a 10k ntc thermistor between ntc and gnd for load-line independent temperature compensation. connect ntc to v cc to disable the temperature compensation and vrhot monitoring features. see the temperature monitoring (vrtset, vrhot) section for more details on selection of the ntc device. 13 cs3- phase 3 current-sense negative input. connect to the load side of the output current- sensing element. 14 17 cs3+ phase 3 current-sense positive input. connect cs3+ to the positive side of the output current-sense resistor, or the positive side of the filtering capacitor if inductor dcr current sensing is used. 15 18 cs2+ phase 2 current-sense positive input. connect cs2+ to the positive side of the output current-sense resistor, or the positive side of the filtering capacitor if inductor dcr current sensing is used. 16 19 cs12- phases 1 and 2 current-sense common negative input. connect to the load side of the output current-sensing elements. 17 20 cs1+ phase 1 current-sense positive input. connect cs1+ to the positive side of the output current-sense resistor, or the positive side of the filtering capacitor if inductor dcr current sensing is used. 18 21 en enable input. drive en high to enable the ic. drive en low to place the ic in shutdown mode. if v cc is greater than the uvlo threshold, en is internally pulled to v cc with a 100k resistor. if v cc is less than the uvlo threshold, en is internally pulled to gnd with a 2k resistor. 19 23 pwm3 pwm signal output for phase 3. pwm3 is low during shutdown, uvlo, and ovp faults. connect pwm3 to v cc to enable 2-phase operation. 20 24 vrhot temperature fault flag. vrhot is an active-high, open-drain output that goes high impedance when the temperature sensed by the thermistor at ntc exceeds the temperature threshold programmed at vrtset. 21 25 dh1 phase 1 high-side mosfet gate-drive output. connect to the gate of the high-side mosfet for phase 1. dh1 is pulled low during shutdown, uvlo, and ovp faults. 22 26 lx1 phase 1 inductor sense point. connect lx1 to the switched side of the inductor for phase 1.
max8809a/max8810a ______________________________________________________________________________________ 15 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers pin description (continued) pin max8809a max8810a name function 23 27 bst1 p hase 1 h i g h- s i d e m o s fe t gate- d r i ve s up p l y. c onnect a 0.22f or l ar g er cer am i c cap aci tor fr om bs t1 to lx 1 to sup p l y g ate d r i ve for the hi g h- si d e m o s fe t. s ee the boost c ap aci tor s el ecti on secti on for d etai l s on cal cul ati ng the bs t1 cap aci tor val ue. 24 28 dl1 p hase 1 low - s i d e m os fe t gate- d r i ve outp ut. c onnect to the g ate of the l ow - si d e m o s fe t for p hase 1. d l1 i s p ul l ed l ow d ur i ng und er vol tag e l ockout and p ul l ed hi g h d ur i ng an ov p faul t. d l1 i s hi g h i n shutd ow n i f v c c i s g r eater than the u v lo thr eshol d . 25 29 pgnd1 power ground for the phase 1 driver. connect pgnd1 to the source of the phase 1 low-side mosfet. pgnd1 must be connected to pgnd2 and gnd externally. see the pc board layout guidelines section for more details. 26 vl12 phase 1 and 2 low-side mosfet gate-drive supply. connect vl12 to a 4.5v to 6.5v supply. bypass vl12 with a 2.2? or larger ceramic capacitor to the power ground plane. 27 32 pgnd2 power ground for the phase 2 driver. connect pgnd2 to the source of the phase 2 low-side mosfet. pgnd2 must be connected to pgnd1 and gnd externally. see the pc board layout guidelines section for more details. 28 33 dl2 p hase 2 low - s i d e m os fe t gate- d r i ve outp ut. c onnect to the g ate of the l ow - si d e m os fe t for p hase 2. d l2 i s p ul l ed l ow d ur i ng und er vol tag e l ockout and p ul l ed hi g h d ur i ng an ov p faul t. d l2 i s hi g h i n shutd ow n i f v c c i s g r eater than the u v lo thr eshol d . 29 34 bst2 p hase 2 h i g h- s i d e m o s fe t gate- d r i ve s up p l y. c onnect a 0.22f or l ar g er cer am i c cap aci tor fr om bs t2 to lx 2 to sup p l y g ate d r i ve for the hi g h- si d e m o s fe t. s ee the boost c ap aci tor s el ecti on secti on for d etai l s on cal cul ati ng the bs t2 cap aci tor val ue. 30 35 lx2 phase 2 inductor sense point. connect lx2 to the switched side of the inductor for phase 2. 31 36 dh2 phase 2 high-side mosfet gate-drive output. connect to the gate of the high-side mosfet for phase 2. dh2 is pulled low during shutdown, uvlo, and ovp faults. 32 38 sel vid table selection input. connect sel to gnd to select the vrd10 vid code (table 5). connect sel to v cc to select the vrd11 8-bit vid code (table 6). leave sel unconnected to select the k8 rev f vid code (table 4). 33?0 39?6 vid7?id0 voltage identification code inputs. use vid_ to set the output voltage. sel selects the vrd10, vrd11, or k8 rev f vid logic codes. connect vid_ to the system v tt with a 680 resistor for logic-high for intel vr solutions. connect vid_ to the system v ddq with a 1k resistor for logic-high for amd vr solutions.
max8809a/max8810a 16 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers pin description (continued) pin max8809a max8810a name function 4 buf 1v reference output. bypass buf to gnd with a 1? or larger ceramic capacitor. connect a resistor from comp to buf to set the load-line. see the loop-compensation design section for more details. 7, 10, 37, 47 n.c. no internal connection 15 cs4+ phase 4 current-sense positive input. connect cs4+ to the positive side of the output current-sense resistor, or the positive side of the filtering capacitor if inductor dcr current sensing is used. 16 cs34- phases 3 and 4 current-sense common negative input. connect to the load side of the output current-sensing elements. 22 pwm4 pwm signal output for phase 4. pwm4 is low during shutdown, uvlo, and ovp faults. connect pwm4 to v cc to enable 3-phase operation. connect pwm3 and pwm4 to v cc to enable 2-phase operation. 30 vl1 phase 1 low-side mosfet gate-drive supply. connect vl1 to a 4.5v to 6.5v supply. vl1 must be connected to vl2 externally. bypass the vl1/vl2 connection with a 2.2? or larger ceramic capacitor to the power ground plane. 31 vl2 phase 2 low-side mosfet gate-drive supply. connect vl2 to a 4.5v to 6.5v supply. vl2 must be connected to vl1 externally. bypass the vl1/vl2 connection with a 2.2? or larger ceramic capacitor to the power ground plane. ep exposed paddle. connect to the analog gnd plane for enhanced thermal power dissipation.
max8809a/max8810a ______________________________________________________________________________________ 17 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers vl1 en v cc max8809a max8810a 1v ref g mb temperature compensation temperature compensation ntc thermistor linearization circuit max8810a only ovp comparator s/r s/r s/r pwm3 bst1 dh1 lx1 dl1 pgnd1 vl1 (max8810a) vl12 (max8809a) (max8809a) bst2 dh2 lx2 dl2 pgnd2 vl2 (max8810a) pwm1 pwm2 v dac dhout lx sense dlout dl sense dhout lx sense dlout dl sense pwm4 (max8810a) s/r 2-/3-/4- phase control osc power-good circuitry soft-start soft-stop vid decode logic driver control logic 2v reference ovp threshold uvlo bias clamp vrhot ntc vrtset ref / 2 rsda current foldback + - cs1+ cs2+ cs3- (max8809a) cs3+ cs34- (max8810a) cs4+ (max8810a) buf (max8810a) comp ss/ovp ref vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 sel rs+ rs- ilim vrready cs12- oscillator operation mode detect g mv + figure 1. block diagram
max8809a/max8810a 18 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers t rdl t pdlr t fdl t dead t rdh t fdh dl lx dh figure 2. driver timing diagram detailed description the max8809a/max8810a synchronous, 2-/3-/4- phase, step-down, current-mode controllers with inte- grated dual-phase mosfet drivers provide flexible solutions that fully comply with intel vrd11/vrd10 and amd k8 rev f cpu core supplies. the flexible design supplies load currents of up to 150a for low-voltage cpu core power supplies. the max8809a is suitable for 2- or 3-phase core sup- ply applications. with an integrated dual-mosfet dri- ver, the max8809a offers a single-chip ic solution for dual-phase core supplies. together with the max8552, a high-performance single-phase mosfet driver, the max8809a also supports 3-phase core supplies. similarly, the max8810a features a single ic solution for dual-phase core supplies. it also features two-ic solutions for 3- or 4-phase core supplies by adding a single mosfet driver (max8552) or a dual-mosfet driver (max8523). both the max8809a and max8810a fully comply with intel vrd11, extended vrd10, and the amd k8 rev f vid codes. the sel input allows the user to select the architecture specifications. clock frequency (osc) an external resistor, r osc , from osc to gnd sets the internal clock frequency of the max8809a/max8810a. a 1% resistor is recommended to maintain good fre- quency accuracy. the internal clock frequency sets the per-phase switching frequency. the selection of switch- ing frequency per phase is influenced by factors such as the switching speed of the mosfets, the inductor? core material, different types of input and output capac- itors, and the available board space. once the per- phase switching frequency is selected, the internal clock frequency is determined using the procedure in the setting the switching frequency section.
max8809a/max8810a ______________________________________________________________________________________ 19 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers voltage reference (ref) a precision 2v reference is provided by the max8809a/ max8810a at the ref output. ref is capable of sinking and sourcing up to 500? for external loads. connect a 0.1? to 1? ceramic capacitor from ref to gnd. internal refok circuitry monitors the reference voltage. the reference voltage must be above the refok thresh- old of 1.84v to activate the controller. the controller is disabled if the reference voltage falls below 1.74v. output current sensing (cs_+, cs_-) the output current of each phase is sensed differentially. a low-offset-voltage, differential-current amplifier (30v/v) at each phase allows low-resistance current- sense resistors to be used to minimize power dissipa- tion. sensing the current at the output of each phase offers advantages including less noise sensitivity, more accurate current sharing between phases, and the flex- ibility of using either a current-sense resistor or the dc resistance of the output inductor. using the dc resistance, r dc , of the output inductor (figure 3) allows higher efficiency. in this configuration, the initial tolerance and temperature coefficient of r dc must be accounted for in the output-voltage droop-error budget. the temperature coefficient can be compensat- ed; see the load-line independent inductor dc resistance temperature compensation section for more details. an rc-filtering network is needed to extract the current information from the output inductor. the time constant of the rc network is calculated as follows: where l is the inductance of the output inductor. for 20a or higher current-per-phase applications, the dc resistance of commercially available inductors is approximately 1m . to minimize current-sense error due to the bias current at the current-sense inputs, choose r1 less than 2k . determine the value for c1 as: select a 1% resistor for r1. for mainstream pcs 20% tolerance is recommended for c1, and for performance pcs 10% tolerance should be considered. if using an inductor with r dc greater than 1m , a resistor (r2) may be necessary to divide down the voltage across cs_+ and cs_-. the maximum average signal present at the input of the current-sense amplifier should not exceed 85mv. when a current-sense resistor is used for more accu- rate current sharing and load-line, a similar rc-filtering circuit is recommended to cancel the equivalent series inductance of the current-sense resistor, as shown in figure 4. again, select r2 less than 2k , and c2 is determined by the following equation: where esl is the equivalent series inductance of the current-sense resistor and r s is the value of the cur- rent-sense resistor. for example, a 1m , 2025 pack- age sense resistor has an esl of 1.6nh. if using an r s greater than 1m , a resistor (r2) may be necessary to divide down the voltage across cs_+ and cs_-. the maximum average signal present at the input of the current-sense amplifier should not exceed 85mv. output current limit and short-circuit protection (ilim) the max8809a/max8810a feature a precise average output current limit on a cycle-by-cycle basis using maxim? proprietary ra 2 technology. the current-limit scheme is insensitive to input-voltage variation, the inductor tolerance, and the tolerance of the current- sense capacitor, permitting the use of low-cost compo- nents to reduce total bom cost. furthermore, the current limit is fully temperature compensated resulting c esl rr s 2 2 = () c l rr dc 1 1 = () rc l r dc 11 = r dc i out r1 r2 optional v rdc = r dc x i out r dc is the inductor dc resistance l c1 cs_+ cs_- figure 3. inductor r dc current sense r s i out r2 v s = r s x i out esl is the parasitic inductance of the current-sense resistor esl l c2 cs_+ cs_- r2 optional figure 4. resistor current sense
max8809a/max8810a 20 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers in a constant output current limit over the entire opera- tional temperature range. this eliminates the need to oversize mosfets and inductors to compensate for thermal effects. connecting ilim to v cc programs the default current-limit threshold. to select a different cur- rent-limit threshold, connect a resistor-divider from ref to gnd with ilim connected to the center tap. the volt- age at ilim is proportional to the current-limit threshold. see the setting the current-limit section for more details. the current-limit circuitry terminates the dh_ on-time immediately when the current-sense voltage (v cs_+ - v cs_- ) exceeds the current-limit threshold, allowing the output inductor current to ramp down. at the next switching cycle, the pwm pulse is skipped if the output inductor current is still above the current-limit threshold. otherwise, the new cycle initiates as normal. the max8809a/max8810a offer foldback-current pro- tection under soft-start and overload conditions. this feature allows the vrm to safely operate under short- circuit conditions and to automatically recover once the short-circuit condition is removed. if the output voltage falls below the vrready threshold during an overcur- rent event, the foldback current-limit circuitry sets the current-limit threshold to half the user-selected value. output differential sensing (rs+, rs-) the max8809a/max8810a feature differential output- voltage sensing to achieve the highest possible output accuracy. this allows the controllers to sense the actu- al voltage at the load, so the controller can compensate for losses in the power output and ground lines. traces from the load point back to rs+ and rs- should be routed close to each other and as far away as possible from noise sources (such as inductors and high di/dt traces). use a ground plane to shield the remote-sense traces from noise sources. to filter out common-mode noise, rc filtering is recommended for these inputs as shown in figure 5. for vrd applications, a 100 resis- tor with a 1nf capacitor should be used. for vrm applications, additional 50 resistors should be con- nected from these inputs to the local outputs of the converter before the vrm connector. this avoids excessive voltage at the cpu in case the remote-sense connections get disconnected. programming the output-voltage droop both the max8809a and max8810a employ peak-cur- rent-mode control with finite gain to actively set the out- put-voltage droop. figure 6 shows the simplified control block diagram. the relationship between the output inductor current in an n-phase dc-dc converter and the output voltage of the voltage-error amplifier is: where g ca (30v/v typ) is the gain of the differential cur- rent amplifier and n is the number of phases. i out is the total output current. therefore, when the output current increases, v c increases. on the other hand, v c is relat- ed to the output voltage of the converter by the following equation: where g mv is the transconductance of the voltage-error amplifier (2ms typ) and v dac is the vid-generated voltage. vg r v v c mv comp dac out = ? () v i n rg c out sense ca = max8809a/ max8810a rs+ r1 50 r2 50 r3 100 r4 100 c2 1nf c1 1nf rs- to remote sense location to positive output of vrm to power ground of vrm figure 5. recommended filtering for output-voltage remote sensing pwm comparator voltage- error amplifier r comp v c g mv v i v dac v out i l_peak g ca r sense figure 6. simplified peak current-mode control ic with active output-voltage positioning
max8809a/max8810a ______________________________________________________________________________________ 21 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers the dc gain of the voltage-error amplifier is equal to g mv x r comp . from the previous equations it is clear that the output-voltage droop can be accurately pro- grammed if the dc gain of the voltage-error amplifier is set to be a finite value. as the output current increases, v c increases and, consequently, v out decreases. define the output-droop resistance, r droop , as: then r droop can be expressed as: since g ca and g mv are constants, r droop is solely determined by r comp when r sense and n are chosen. peak current-mode control with finite gain is the sim- plest way to achieve the output-voltage droop without introducing a separate current loop, which is the case for voltage-mode control. therefore, the response time of the output-voltage droop is the same as the voltage- feedback loop, resulting in fast output-voltage-droop transient response and less output capacitance than solutions using voltage-mode control. other features offered by peak-current-mode control are excellent line regulation and inherent current shar- ing between phases. standard peak-current-mode con- trol does have one disadvantage in that current matching between phases is impacted by the inductor mismatch (tolerance) between phases. because only the current peak is controlled, any mismatch in the inductor value between two phases creates an inductor ripple current mismatch, which, in turn, creates a dc current mismatch between those two phases. tolerance mismatch between the current-sense capac- itors used in dcr current sensing creates the exact same dc current mismatch as an inductor mismatch. maxim? proprietary ra 2 technology addresses this issue by averaging out the inductor ripple current indi- vidually at each phase, as shown in figure 7. the rapid active average circuitry learns the peak-to-peak ripple current of each phase in 5 to 10 switching cycles and then biases the peak current signal down by half of the peak-to-peak ripple current, consequently eliminating the impact of both output inductance and dcr current- sense capacitance variations. since the rapid active average circuitry is not part of the current-loop path, it does not slow down the transient response. programming the output offset voltage according to the intel vrd specifications, the output voltage at no load cannot exceed the voltage specified by the vid code, including the initial set tolerance, rip- ple voltage, and other errors. therefore, the actual out- put voltage should be biased lower to compensate for these errors. for the max8809a, the output-voltage off- set is created through a resistor-divider that is connect- ed between ref and gnd, with the center tap connected to comp as shown in figure 8. this resistor- divider also sets the output load-line. the max8810a contains a buf output that makes the output-voltage offset setting independent of the output load-line. to program the output-voltage offset, connect a resistor between comp and gnd. a resistor between buf and comp sets the output load-line. see the loop compensation design section for details on setting the output-voltage offset. r rg ng r droop sense ca mv comp = r vv i droop dac out out = ? () 1/s pwm comparator voltage- error amplifier r comp v c v dac v out g ma g ca r sense x (i out / n) r sense x (i out / n) ra 2 algorithm v c g mb g mv figure 7. implementation of the rapid active averaging (ra 2 ) algorithm
max8809a/max8810a 22 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers load-line independent inductor dc resistance temperature compensation changes in inductor resistance due to temperature cause a change in the output-droop characteristic. this is compensated by changing the gain of the current- sense amplifier as a function of temperature. in doing so, the voltage at comp is independent of temperature, resulting in a temperature-independent load-line setting. additionally, the output short-circuit protection is also temperature independent because current limit is imple- mented by clamping the voltage at comp. this technol- ogy uses an ntc thermistor solely for temperature compensation, freeing it from being one of the compo- nents that determines the output load-line. therefore, only one ntc thermistor is needed to enable any output load-line. the same ntc thermistor is used for tempera- ture sense for the vrhot output. the max8809a/ max8810a temperature-compensation scheme is opti- mized for use with a panasonic ertj1vr103 10k ntc thermistor. other thermistors may be used. contact your local maxim representative for more details. loop compensation during a load transient, the output voltage instantly changes due to the esr of the output capacitors by an amount equal to their esr times the change in load cur- rent ( v out = r esr x i load ). the output voltage then deviates further based on the speed at which the loop compensates for the load transient. the voltage-posi- tioning method allows better utilization of the output reg- ulation window, resulting in less required output capacitors. the ra 2 architecture adjusts the output cur- rent based on the instantaneous output voltage, result- ing in fast voltage positioning. the voltage-error amplifier consists of a high-bandwidth, high-accuracy transconductance amplifier ( g mv in figure 7 ) . the nega- tive input of the transconductance amplifier is connected to the output of the remote-voltage differential amplifier, and the positive input is connected to the output of an internal dac controlled by the vid inputs. the dc gain of the transconductance amplifier is set to a finite value to achieve fast output-voltage positioning by connecting an rc circuit (r comp and c comp ) from comp to gnd. see the loop-compensation design section for details on selecting the required components. vr ready output (vrready) vrready is an open-drain output that turns high impedance when the output voltage reaches regula- tion. vrready goes low if v out is less than (v dac - 225mv) or greater than (v dac + 175mv), signaling an out-of-regulation fault. vrready is held low in shut- down, if v cc is less than the uvlo threshold, or during soft-start. for logic-level output voltages, connect an external pullup resistor between vrready and the logic power supply. a 100k resistor works well in most applications. dynamic vid change the max8809a/max8810a provide the ability for the cpu to dynamically change the vid inputs while the controller is operating (on-the-fly or otf). the output voltage changes in 6.25mv steps (intel) or 12.5mv/25mv steps (amd) when a vid change is detected. the controller provides a 400ns logic-skew window to prevent false code changes. the controller accepts both step-by-step changes of vid inputs or all-at-once vid input changes. for all-at-once vid input changes, the output-voltage slew rate is the same, 1 lsb per step and 2? duration. vrready is blanked during dynamic vid changes. multiphase operation selection the max8809a operates in either a 2- or 3-phase config- uration. connect pwm3 to v cc for 2-phase operation. the max8810a operates in 2-, 3- or 4-phase configura- tion. connect pwm4 to v cc for 3-phase operation. connect pwm4 and pwm3 to v cc for 2-phase operation. all active pwm outputs are held low during shutdown. uvlo and output enable when the ic supply voltage (v cc ) is less than the uvlo threshold (4.25v typ), all active pwm outputs are internally pulled low and most internal circuitry is shut down to reduce the quiescent current. when en is released and v cc > uvlo, the internal 100k resistor pulls en to v cc and soft-start is initiated (after a typical 2.2ms delay). r os r ll ref comp r os r ll buf comp max8810a max8809a figure 8. programming the output offset voltage
max8809a/max8810a ______________________________________________________________________________________ 23 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers when the driver supply voltage (v vl_ ) is less than its uvlo threshold (3.55v typ), dh_ and dl_ are held low. if v vl_ is above the uvlo threshold and while en is low, dl_ is driven high and dh_ is held low. this prevents the output of the converter from rising before a valid en high signal is present. soft-start the max8809a/max8810a soft-start with 6.25mv steps, regardless of processor architecture. connect a resistor between ss/ovp and gnd to program the soft- start time. when the device is enabled, ss/ovp is dri- ven to 2v and the current drawn by the set resistor is measured. this current sets the internal delay time between the dac voltage steps. select a resistor between 12k and 90.9k for a corresponding soft- start time of 500? to 6.5ms. for intel designs, the resistor value is calculated as: where t ss is the desired soft-start time (in ms) to the 1.1v v boot level. figure 9 shows the intel startup sequence, and table 1 shows the values of the time delays. for amd applications, the controllers soft-start up to the voltage set by the vid inputs. the soft-start time is set by the following equation: where v dac is the output voltage set by the vid inputs. figure 10 shows the amd startup sequence, and table 2 shows the values of the time delays. soft-stop when en goes low, the output of the converter ramps down to 0v in 6.25mv dac steps in the time set by the ss/ovp input. once the output reaches 0v, dl is held high and dh is held low to maintain the 0v output. this rk t v v ss ovp ss dac / () . . . = ? 0 0183 0 0532 11 rk t ss ovp ss / () . . = ? 0 0183 0 0532 vid input read (ss time) no. of steps x 2 s td5 td4 td3 td2 td1 soft-start rate set by r ss/ovp soft-stop rate set by r ss/ovp v boot 6.25mv/step 6.25mv/step out vrready en vid code change step to vid code 6.25mv/2 s normal operation 6.25mv/2 s figure 9. intel vrd11/vrd10 startup sequence table 1. intel startup sequence specifications parameter min max td1 1ms 5ms td2 50? 5ms td3 50? 3ms td4 2.5ms td5 50? 3ms
approach prevents large negative voltages on the out- put during shutdown and therefore eliminates the need for a schottky clamp diode on the output. output overvoltage protection (ovp) when the output voltage exceeds the regulation voltage by 200mv (intel) or exceeds 1.8v (amd), all active pwm outputs are pulled low and the controller is latched off. ss/ovp is internally pulled to v cc to signal an overvolt- age fault. all dh_ outputs are held low and all dl_ out- puts are held high to discharge the output. the latch condition can only be cleared by cycling the input volt- age (v cc ). integrated dual-mosfet driver the max8809a/max8810a contain a dual-phase gate driver capable of driving 3000pf capacitive loads with only 32ns propagation delay and 11ns typical rise and fall times, allowing operation up to 1.2mhz per phase. adaptive dead time controls low-side mosfet turn-on and high-side mosfet turn-on. this maximizes converter efficiency, while allowing operation with a variety of mosfets. a uvlo circuit ensures proper power-on sequencing. adaptive shoot-through protection adaptive shoot-through protection is incorporated for the switching transition after the high-side mosfet is turned off and before the low-side mosfet is turned on. the low-side driver is turned on only when the lx_ voltage falls below 2.5v typical. in addition, a fixed 35ns delay time between the low-side mosfet turn-off and high-side mosfet turn-on adds further protection from ?hoot-through.?the 35ns time begins after dl_ has fallen through 1.5v typical. mosfet driver uvlo when v vl12 (max8809a) or v vl1 (max8810a) is below the uvlo threshold (3.55 typ), dh_ and dl_ are held max8809a/max8810a 24 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers ss time td2 td3 td1 2ms td4 1.1ms soft-start rate set by r ss/ovp above 0.775v 25mv/4 s soft-stop rate set by r ss/ovp vid code level 6.25mv/step 6.25mv/step below 0.775v 12.5mv/2 s out vrready en vid input change figure 10. k8 rev f startup sequencing and timing table 2. amd startup sequence specifications parameter m in im u m t im e ( ? s ) m a xim u m t im e ( m s ) td1 1 td2* 500 6.5 td3 20 td4 500 * user programmable.
max8809a/max8810a ______________________________________________________________________________________ 25 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers low. once v vl_ is above the uvlo threshold and en is low, dl_ is kept high and dh_ is kept low. this pre- vents the output from rising before a valid en signal is given. boost circuit for high-side mosfet driver the gate-drive voltage for the high-side mosfet dri- vers is generated by a flying-capacitor boost circuit. the capacitor between bst_ and lx_ is charged from the vl_ supply through an internal switch while the low- side mosfet is on. when the low-side mosfet is switched off, the stored voltage on the capacitor is stacked above lx_ to provide the necessary turn-on voltage for the high-side mosfet(s). no external boost diode is needed. see the boost capacitor selection section for details on selecting the correct capacitor. thermal protection the max8809a/max8810a feature a thermal-fault-pro- tection circuit. when the junction temperature rises above +160 c typical, an internal thermal sensor acti- vates the shutdown circuit to hold all mosfet drivers and active pwm outputs low to disable switching. the thermal sensor reactivates the controller after the junc- tion temperature cools by 25 c typical. temperature monitoring (vrtset, vrhot) the max8809a/max8810a contain temperature-moni- toring circuitry that allows the user to program a tem- perature trip point between +60 c and +125 c, and monitor an active-high, open-drain vrhot output. connect a resistor from vrtset to gnd to set the tem- perature-monitoring threshold. the resistor is calculat- ed as follows: where k t is a temperature scale factor specifically for the panasonic ertj1vr103 ntc thermistor. table 3 provides values of k t and the closest standard 1% r vrtset values needed to program the vrhot thresh- old over a +60 c to +125 c range. r vrtset must be greater than 20k . contact your local maxim represen- tative for information on using other thermistors. architecture selection and timing amd k8 rev f the amd k8 rev f processor uses a 6-bit vid code that specifies a 0.375v to 1.55v output voltage range (see table 4). leave sel unconnected to select the amd k8 rev f architecture. the startup sequencing and timing specifications are shown in figure 10. note that the vid input defines the amd processor boot level, and there is no internal default. the boot level is not latched; therefore, if the codes change during soft- start, the boot level also changes. extended intel vrd10 the intel vrd10 processor uses a 7-bit vid code that specifies a 0.83125v to 1.6v output voltage range (see table 5). connect sel to gnd to select the vrd10 architecture. the startup sequencing and timing speci- fications are shown in figure 9. the intel boot level is internally set to 1.1v; therefore, the vid inputs are ignored during soft-start. in compliance with the intel vrd specifications, there is a typical 2.2ms delay after en is asserted before soft-start begins. this delay is not included in the soft-start time set by ss/ovp. intel vrd11 the intel vrd11 processor uses an 8-bit vid code that specifies a 0.3125v to 1.6v output voltage range (see table 6). connect sel to v cc to select the vrd11 architecture. the startup sequencing and timing speci- fications are shown in figure 9. the intel boot level is internally set to 1.1v; therefore, the vid inputs are ignored during soft-start. in compliance with the intel vrd specifications, there is a typical 2.2ms delay after en is asserted before soft-start begins. this delay is not included in the soft-start time set by ss/ovp. r k in k vrtset t . = 800 06 table 3. temperature scale factor temperature ( c) k t r vrtset (k ) +60 4.497 294 +65 5.453 243 +70 6.580 200 +75 7.903 169 +80 9.447 140 +85 11.244 118 +90 13.325 100 +95 15.725 84.5 +100 18.484 71.5 +105 21.643 61.9 +110 25.247 52.3 +115 29.345 45.3 +120 33.988 39.2 +125 39.231 34
max8809a/max8810a 26 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers table 4. amd k8 rev f vid code, sel = unconnected vid5 vid4 vid3 vid2 vid1 vid0 v out (v) 111111 0.3750 111110 0.3875 111101 0.4000 111100 0.4125 111011 0.4250 111010 0.4375 111001 0.4500 111000 0.4625 110111 0.4750 110110 0.4875 110101 0.5000 110100 0.5125 110011 0.5250 110010 0.5375 110001 0.5500 110000 0.5625 101111 0.5750 101110 0.5875 101101 0.6000 101100 0.6125 101011 0.6250 101010 0.6375 101001 0.6500 101000 0.6625 100111 0.6750 100110 0.6875 100101 0.7000 100100 0.7125 100011 0.7250 100010 0.7375 100001 0.7500 100000 0.7625 vid5 vid4 vid3 vid2 vid1 vid0 v out (v) 0 1 1 1 1 1 0.7750 0 1 1 1 1 0 0.8000 0 1 1 1 0 1 0.8250 0 1 1 1 0 0 0.8500 0 1 1 0 1 1 0.8750 0 1 1 0 1 0 0.9000 0 1 1 0 0 1 0.9250 0 1 1 0 0 0 0.9500 0 1 0 1 1 1 0.9750 0 1 0 1 1 0 1.0000 0 1 0 1 0 1 1.0250 0 1 0 1 0 0 1.0500 0 1 0 0 1 1 1.0750 0 1 0 0 1 0 1.1000 0 1 0 0 0 1 1.1250 0 1 0 0 0 0 1.1500 0 0 1 1 1 1 1.1750 0 0 1 1 1 0 1.2000 0 0 1 1 0 1 1.2250 0 0 1 1 0 0 1.2500 0 0 1 0 1 1 1.2750 0 0 1 0 1 0 1.3000 0 0 1 0 0 1 1.3250 0 0 1 0 0 0 1.3500 0 0 0 1 1 1 1.3750 0 0 0 1 1 0 1.4000 0 0 0 1 0 1 1.4250 0 0 0 1 0 0 1.4500 0 0 0 0 1 1 1.4750 0 0 0 0 1 0 1.5000 0 0 0 0 0 1 1.5250 0 0 0 0 0 0 1.5500 note: vid voltage increment is 12.5mv from 0.3875 to 0.775 and 25mv from 0.775 to 1.550.
max8809a/max8810a ______________________________________________________________________________________ 27 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers table 5. extended intel vrd10 vid code, sel = gnd vid6 vid5 vid4 vid3 vid2 vid1 vid0 v out (v) 1101010 1.60000 0101010 1.59375 1001011 1.58750 0001011 1.58125 1101011 1.57500 0101011 1.56875 1001100 1.56250 0001100 1.55625 1101100 1.55000 0101100 1.54375 1001101 1.53750 0001101 1.53125 1101101 1.52500 0101101 1.51875 1001110 1.51250 0001110 1.50625 1101110 1.50000 0101110 1.49375 1001111 1.48750 0001111 1.48125 1101111 1.47500 0101111 1.46875 1010000 1.46250 0010000 1.45625 1110000 1.45000 0110000 1.44375 1010001 1.43750 0010001 1.43125 1110001 1.42500 0110001 1.41875 1010010 1.41250 0010010 1.40625 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v out (v) 1110010 1.40000 0110010 1.39375 1010011 1.38750 0010011 1.38125 1110011 1.37500 0110011 1.36875 1010100 1.36250 0010100 1.35625 1110100 1.35000 0110100 1.34375 1010101 1.33750 0010101 1.33125 1110101 1.32500 0110101 1.31875 1010110 1.31250 0010110 1.30625 1110110 1.30000 0110110 1.29375 1010111 1.28750 0010111 1.28125 1110111 1.27500 0110111 1.26875 1011000 1.26250 0011000 1.25625 1111000 1.25000 0111000 1.24375 1011001 1.23750 0011001 1.23125 1111001 1.22500 0111001 1.21875 1011010 1.21250 0011010 1.20625
max8809a/max8810a 28 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers vid6 vid5 vid4 vid3 vid2 vid1 vid0 v out (v) 1111010 1.20000 0111010 1.19375 1011011 1.18750 0011011 1.18125 1111011 1.17500 0111011 1.16875 1011100 1.16250 0011100 1.15625 1111100 1.15000 0111100 1.14375 1011101 1.13750 0011101 1.13125 1111101 1.12500 0111101 1.11875 1011110 1.11250 0011110 1.10625 1111110 1.10000 0111110 1.09375 1011111 off 0011111 off 1111111 off 0111111 off 1000000 1.08750 0000000 1.08125 1100000 1.07500 0100000 1.06875 1000001 1.06250 0000001 1.05625 1100001 1.05000 0100001 1.04375 1000010 1.03750 0000010 1.03125 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v out (v) 1100010 1.02500 0100010 1.01875 1000011 1.01250 0000011 1.00625 1100011 1.00000 0100011 0.99375 1000100 0.98750 0000100 0.98125 1100100 0.97500 0100100 0.96875 1000101 0.96250 0000101 0.95625 1100101 0.95000 0100101 0.94375 1000110 0.93750 0000110 0.93125 1100110 0.92500 0100110 0.91875 1000111 0.91250 0000111 0.90625 1100111 0.90000 0100111 0.89375 1001000 0.88750 0001000 0.88125 1101000 0.87500 0101000 0.86875 1001001 0.86250 0001001 0.85625 1101001 0.85000 0101001 0.84375 1001010 0.83750 0001010 0.83125 table 5. extended intel vrd10 vid code, sel = gnd (continued)
max8809a/max8810a ______________________________________________________________________________________ 29 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers table 6. intel vrd11 vid code, sel = v cc vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v out (v) 00000000off 00000001off 0 0 0 0 0 0 1 0 1.60000 0 0 0 0 0 0 1 1 1.59375 0 0 0 0 0 1 0 0 1.58750 0 0 0 0 0 1 0 1 1.58125 0 0 0 0 0 1 1 0 1.57500 0 0 0 0 0 1 1 1 1.56875 0 0 0 0 1 0 0 0 1.56250 0 0 0 0 1 0 0 1 1.55625 0 0 0 0 1 0 1 0 1.55000 0 0 0 0 1 0 1 1 1.54375 0 0 0 0 1 1 0 0 1.53750 0 0 0 0 1 1 0 1 1.53125 0 0 0 0 1 1 1 0 1.52500 0 0 0 0 1 1 1 1 1.51875 0 0 0 1 0 0 0 0 1.51250 0 0 0 1 0 0 0 1 1.50625 0 0 0 1 0 0 1 0 1.50000 0 0 0 1 0 0 1 1 1.49375 0 0 0 1 0 1 0 0 1.48750 0 0 0 1 0 1 0 1 1.48125 0 0 0 1 0 1 1 0 1.47500 0 0 0 1 0 1 1 1 1.46875 0 0 0 1 1 0 0 0 1.46250 0 0 0 1 1 0 0 1 1.45625 0 0 0 1 1 0 1 0 1.45000 0 0 0 1 1 0 1 1 1.44375 0 0 0 1 1 1 0 0 1.43750 0 0 0 1 1 1 0 1 1.43125 0 0 0 1 1 1 1 0 1.42500 0 0 0 1 1 1 1 1 1.41875 0 0 1 0 0 0 0 0 1.41250 0 0 1 0 0 0 0 1 1.40625 0 0 1 0 0 0 1 0 1.40000 0 0 1 0 0 0 1 1 1.39375 0 0 1 0 0 1 0 0 1.38750 0 0 1 0 0 1 0 1 1.38125 0 0 1 0 0 1 1 0 1.37500 0 0 1 0 0 1 1 1 1.36875
max8809a/max8810a 30 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers table 6. intel vrd11 vid code, sel = v cc (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v out (v) 0 0 1 0 1 0 0 0 1.36250 0 0 1 0 1 0 0 1 1.35625 0 0 1 0 1 0 1 0 1.35000 0 0 1 0 1 0 1 1 1.34375 0 0 1 0 1 1 0 0 1.33750 0 0 1 0 1 1 0 1 1.33125 0 0 1 0 1 1 1 0 1.32500 0 0 1 0 1 1 1 1 1.31875 0 0 1 1 0 0 0 0 1.31250 0 0 1 1 0 0 0 1 1.30625 0 0 1 1 0 0 1 0 1.30000 0 0 1 1 0 0 1 1 1.29375 0 0 1 1 0 1 0 0 1.28750 0 0 1 1 0 1 0 1 1.28125 0 0 1 1 0 1 1 0 1.27500 0 0 1 1 0 1 1 1 1.26875 0 0 1 1 1 0 0 0 1.26250 0 0 1 1 1 0 0 1 1.25625 0 0 1 1 1 0 1 0 1.25000 0 0 1 1 1 0 1 1 1.24375 0 0 1 1 1 1 0 0 1.23750 0 0 1 1 1 1 0 1 1.23125 0 0 1 1 1 1 1 0 1.22500 0 0 1 1 1 1 1 1 1.21875 0 1 0 0 0 0 0 0 1.21250 0 1 0 0 0 0 0 1 1.20625 0 1 0 0 0 0 1 0 1.20000 0 1 0 0 0 0 1 1 1.19375 0 1 0 0 0 1 0 0 1.18750 0 1 0 0 0 1 0 1 1.18125 0 1 0 0 0 1 1 0 1.17500 0 1 0 0 0 1 1 1 1.16875 0 1 0 0 1 0 0 0 1.16250 0 1 0 0 1 0 0 1 1.15625 0 1 0 0 1 0 1 0 1.15000 0 1 0 0 1 0 1 1 1.14375 0 1 0 0 1 1 0 0 1.13750 0 1 0 0 1 1 0 1 1.13125 0 1 0 0 1 1 1 0 1.12500 0 1 0 0 1 1 1 1 1.11875
max8809a/max8810a ______________________________________________________________________________________ 31 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers table 6. intel vrd11 vid code, sel = v cc (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v out (v) 0 1 0 1 0 0 0 0 1.11250 0 1 0 1 0 0 0 1 1.10625 0 1 0 1 0 0 1 0 1.10000 0 1 0 1 0 0 1 1 1.09375 0 1 0 1 0 1 0 0 1.08750 0 1 0 1 0 1 0 1 1.08125 0 1 0 1 0 1 1 0 1.07500 0 1 0 1 0 1 1 1 1.06875 0 1 0 1 1 0 0 0 1.06250 0 1 0 1 1 0 0 1 1.05625 0 1 0 1 1 0 1 0 1.05000 0 1 0 1 1 0 1 1 1.04375 0 1 0 1 1 1 0 0 1.03750 0 1 0 1 1 1 0 1 1.03125 0 1 0 1 1 1 1 0 1.02500 0 1 0 1 1 1 1 1 1.01875 0 1 1 0 0 0 0 0 1.01250 0 1 1 0 0 0 0 1 1.00625 0 1 1 0 0 0 1 0 1.00000 0 1 1 0 0 0 1 1 0.99375 0 1 1 0 0 1 0 0 0.98750 0 1 1 0 0 1 0 1 0.98125 0 1 1 0 0 1 1 0 0.97500 0 1 1 0 0 1 1 1 0.96875 0 1 1 0 1 0 0 0 0.96250 0 1 1 0 1 0 0 1 0.95625 0 1 1 0 1 0 1 0 0.95000 0 1 1 0 1 0 1 1 0.94375 0 1 1 0 1 1 0 0 0.93750 01101101 0.93125 01101110 0.92500 01101111 0.91875 01110000 0.91250 01110001 0.90625 01110010 0.90000 01110011 0.89375 01110100 0.88750 01110101 0.88125 01110110 0.87500 01110111 0.86875
max8809a/max8810a 32 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers table 6. intel vrd11 vid code, sel = v cc (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v out (v) 01111000 0.86250 01111001 0.85625 01111010 0.85000 01111011 0.84375 01111100 0.83750 01111101 0.83125 01111110 0.82500 01111111 0.81875 10000000 0.81250 10000001 0.80625 10000010 0.80000 10000011 0.79375 10000100 0.78750 10000101 0.78125 10000110 0.77500 10000111 0.76875 10001000 0.76250 10001001 0.75625 10001010 0.75000 10001011 0.74375 10001100 0.73750 10001101 0.73125 10001110 0.72500 10001111 0.71875 10010000 0.71250 10010001 0.70625 10010010 0.70000 10010011 0.69375 10010100 0.68750 10010101 0.68125 10010110 0.67500 10010111 0.66875 10011000 0.66250 10011001 0.65625 10011010 0.65000 10011011 0.64375 10011100 0.63750 10011101 0.63125 10011110 0.62500 10011111 0.61875
max8809a/max8810a ______________________________________________________________________________________ 33 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers table 6. intel vrd11 vid code, sel = v cc (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v out (v) 1 0 1 0 0 0 0 0 0.61250 1 0 1 0 0 0 0 1 0.60625 1 0 1 0 0 0 1 0 0.60000 1 0 1 0 0 0 1 1 0.59375 1 0 1 0 0 1 0 0 0.58750 1 0 1 0 0 1 0 1 0.58125 1 0 1 0 0 1 1 0 0.57500 1 0 1 0 0 1 1 1 0.56875 1 0 1 0 1 0 0 0 0.56250 1 0 1 0 1 0 0 1 0.55625 1 0 1 0 1 0 1 0 0.55000 1 0 1 0 1 0 1 1 0.54375 1 0 1 0 1 1 0 0 0.53750 1 0 1 0 1 1 0 1 0.53125 1 0 1 0 1 1 1 0 0.52500 1 0 1 0 1 1 1 1 0.51875 1 0 1 1 0 0 0 0 0.51250 1 0 1 1 0 0 0 1 0.50625 1 0 1 1 0 0 1 0 0.50000 11111110off 11111111off design procedure the following sections detail the selection process for the external components used with the max8809a/ max8810a. contact your local maxim representative to obtain a spreadsheet-based tool to facilitate your design. setting the switching frequency the switching frequency influences the switching loss, the size of the power mosfets, and the size of power components such as output inductors and capacitors. higher switching frequencies result in smaller external components and more compact designs. however, power-mosfet switching losses and magnetic core losses in the output inductor increase with switching frequency, reducing efficiency. select a switching fre- quency as a tradeoff between size and efficiency. once the per-phase switching frequency is selected, the internal oscillator frequency (f osc ) must be set. determine the required oscillator frequency based on the desired per-phase switching frequency (f sw ) from table 7. for 2- or 4-phase designs, the internal clock frequency should be set at four times the desired per-phase switching frequency. in 3-phase designs, the internal clock frequency should be set at three times the desired per-phase switching frequency. set the internal clock frequency with a resistor from osc to gnd (r osc ). the value of r osc for a given internal clock frequency is approximated from the following equation: rf osc osc . . = ? 161 88 1 2074 table 7. required clock frequency for per-phase switching frequency no. of phases configuration f osc 2 pwm3 = v cc (max8809a); pwm3 = pwm4 = v cc (max8810a) 4 x f sw 3 pwm4 = v cc (max8810a) 3 x f sw 4 max8810a only 4 x f sw
max8809a/max8810a 34 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers where f osc is given in mhz and r osc is in k . also see the per-phase frequency vs. r osc graph in the typical operating characteristics for the relationship between the clock frequency and the value of the fre- quency-setting resistor. output inductor selection the output inductor is selected based on the desired amount of inductor ripple current. a larger inductance value minimizes output ripple current and increases efficiency but slows down the output-inductor-current slew rate during a load transient. lir is the ratio of rip- ple current to the total current per phase. for the best tradeoff of size, cost, and efficiency, an lir of 30% to 60% is recommended (lir = 0.3 to 0.6). choose a higher lir when more phases are used to take advan- tage of ripple-current cancellation. the inductor value is determined from: where f sw is the per-phase switching frequency, i out_max is the maximum-rated output current, d is the duty ratio, n is the number of phases, and v out is the output voltage at a given vid code. the output-inductor ripple current produces a ripple voltage across the out- put-capacitor esr that usually is the dominant compo- nent of the output voltage ripple. for an n-phase buck converter with a d x n factor of less than 1, the output ripple voltage, v ripple , can be calculated using: this equation takes into account the voltage ripple can- cellation from multiphase designs. optimum voltage positioning (droop) requires the effective output-capac- itor esr to match the load resistance, r o . for initial rip- ple-voltage estimates, replace r esr_co with r o . if the output-ripple-voltage specification is not satisfied, a larger value of output inductance should be chosen. the selected inductor should have the lowest possible dc resistance, and the saturation current should be greater than the peak inductor current, i peak . i peak is found from: when the dc resistance (r dc ) of the output inductor is used for current sensing, the dc resistance should be a minimum of 0.5m . it is also important that the peak-to-peak ripple voltage at the input of the current-sense amplifier not exceed 23mv: (v cs+ - v cs- ) = i ripple x r sense where r sense is the sense resistance value at the highest operating temperature. if this condition is not met, then the lir must be adjusted or the input signal to the current-sense amplifier must be scaled down with a resistor-divider. output capacitor selection in most cases, selection of the output capacitor is dic- tated by the target esr requirement, r esr_co = r o (load resistance), to meet the core-supply transient response. however, the minimum output capacitance, c o(min) , required to meet load-dump requirements, is estimated based on energy balance from: where i init and i fin are the initial and final values of the inductor current during a load dump, v init is the volt- age prior to the load dump, v fin is the voltage after, and v ov is the allowed overshoot above v fin . the above equation is an approximation, and the output- capacitance value obtained serves as a good starting point. the final value should be obtained from actual measurements. there is also an upper limit on the amount of output capacitance to meet the otf vid change requirement. too much output capacitance can prevent the output voltage from reaching the new vid output voltage with- in the otf time window: where t otf is the time window to achieve v otf (change in output voltage). if c o(max) is less than c o(min) , the system does not meet the vid otf specifi- cation. i lim is usually set at 110% to 120% of i out_max . rms ripple current rating is an additional requirement for the output capacitors. for a multiphase buck con- verter, the rms ripple current in the output capacitors is given by: for (n x d) 1, where d is the duty cycle and is com- puted from the following equation: d nv i r r nv i r r out out max dson ls dc in out max dson hs ds lo = + + ? ? __ ___ () () i vnd lf co rms out sw _ () = ? 1 23 c ii t v o max lim out max otf otf () _ ? () c li i nv v v v omin init fin fin init ov init () ? ? ? ? ? ? ?+ () 1 2 22 i i n lir peak out max _ =+ ? ? ? ? ? ? 1 2 v vr dn fl ripple out esr co sw = ? _ (( )) 1 l vdn lir f i out sw out max ? () _ 1
max8809a/max8810a ______________________________________________________________________________________ 35 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers use the maximum input voltage for calculating the duty cycle to obtain the worst-case rms ripple current. r dson_ls and r dson_hs are the on-state resistances of the low-side and high-side mosfets, respectively, and r dc is the dc resistance of the output inductor. input capacitor selection the input capacitor reduces the peak current drawn from the power source and reduces the noise and volt- age ripple on the input dc voltage bus caused by the circuit? switching. the input capacitors must meet the ripple-current requirement (i rms ) imposed by the switching currents as defined by the following equation: for (d x n) 1 use the minimum input voltage for calculating the duty cycle to obtain the worst-case input-capacitor rms rip- ple current. low-esr aluminum electrolytic, polymer, or ceramic capacitors should be used to avoid large volt- age transients at the input during a large step load change at the output. the ripple-current specifications provided by the manufacturer should be carefully reviewed for temperature derating. additional small- value, low-esl ceramic capacitors (1? to 10? with proper voltage rating) can be used in parallel to reduce any high-frequency ringing. boost capacitor selection the max8809a/max8810a use a bootstrap circuit to generate the floating supply voltages for the high-side drivers. the selected high-side mosfet determines the appropriate boost capacitance values according to the following equation: where m hs is the total number of high-side mosfets handled by each bst_ capacitor, q gate_hs is the total gate charge of each high-side mosfet, and v bst is the voltage variation allowed on the high-side mosfet drive. choose v bst = 0.1v to 0.2v when determining the c bst_ value. use low-esr ceramic capacitors for c bst_ . note that q gate_hs is a function of gate-drive voltage v vl_ and should be obtained from the mosfet data sheet v gs vs. q gate curve. vl_ bypass capacitor selection vl _ provides the supply voltages for the low-side dri- vers. the decoupling capacitor at vl_ also charges the high-side driver? bst capacitor during the time period when the low-side mosfet is turned on. therefore, the decoupling capacitor for vl_ should be large enough to minimize the ripple voltage during switching transi- tions. choose c vl_ according to the following equation: power-mosfet selection mosfet power dissipation depends on the gate-drive voltage (v d ), the on-resistance (r dson ), the total gate charge (q gate ), and the gate threshold voltage (v th ). the supply voltage (vl_) range for the mosfet drivers is from 4.5v to 7v. with v gate < 10v, logic-level threshold mosfets are recommended. power dissipation in the high-side mosfet consists of two parts: the conduction loss and the switching loss. the per phase conduction loss for the high side can be calculated from: where n is the number of phases and m hs is the num- ber of mosfets in parallel for each phase. total high- side conduction loss equals the number of phases times p cond_hs . switching loss is the major contributor to the high-side mosfet power dissipation due to the hard switching transition every time it turns on. the switching loss is found from the following: where v d is the gate-drive voltage and r gate is the total gate resistance including the driver? on-resistance (see the electrical characteristics table) and the mosfet gate resistance. for a logic-level power mosfet, the gate resistance is approximately 2 . q miller is the mosfet miller charge found in the mosfet data sheet. note that adding more mosfets in parallel on the high side increases the switching loss. smaller miller gate charge and lower gate resistance usually result in lower switching loss. the low-side mosfet power dissipation is mostly attributed to the conduction loss. switching loss is neg- ligible due to the zero-voltage switching at turn-on and body-diode clamp at turn-off. power dissipation in the low-side mosfets of each phase can be calculated from the following equation: pd i n lir r m cond ls out max dson ls ls _ __ () =? + ? ? ? ? ? ? 11 12 2 2 2 p vi n rq vv fm sw hs in out max gate miller dth sw hs _ _ = ? 2 pd i n lir r m cond hs out max dson hs hs _ __ () = + 2 2 2 1 12 cc vl bst __ = 10 c qm v bst gate hs hs bst _ = idi nd rms out max _ = ? 1 1
max8809a/max8810a 36 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers where m ls is the number of mosfets in parallel per phase on the low side. total power dissipation for the low side equals the number of phases times the low- side conduction loss of each phase. even though the switching loss is insignificant in the low-side mosfets, r dson is not the only parameter that should be considered in selecting the low-side mosfets. large miller capacitance (c rss ) could turn on the low-side mosfets momentarily when the drain- to-source voltage goes high at fast slew rates, if the dri- ver cannot hold the gate low. the ratio of c rss /c iss should be less than 1/10th for the low-side mosfets to avoid shoot-through current due to momentary turn-on of the low-side switch. adding a resistor between bst_ and c bst_ can slow the high-side mosfet turn-on. similarly, adding a capacitor from the gate to the source of the high-side mosfet has the same effect. however, both methods are at the expense of increas- ing the high-side switching losses. loop-compensation design loop compensation with voltage positioning processor power-supply specifications often require the output voltage to ?roop?from its no-load value at a fixed slope with increasing load current. this slope is termed the load-line resistance (r o ). once the current- sense resistance (r sense ), the required load-line resis- tance, and the output offset voltage (v os ) are determined, the values of r ll and r os (see figure 8) are calculated from the following equations: for the max8809a: for the max8810a: the 1v buf output simplifies the r os calculation con- siderably. r os and r ll are calculated as: the pole due to the load (r out ) and output capaci- tance produces a -20db/decade slope up to the output- capacitor esr zero frequency. to continue to roll off the gain out to high frequencies at -20db/decade, the com- pensation places a pole at the esr zero frequency. an rc circuit, r comp and c comp , must be connected from comp to ground. calculate r comp as the parallel combination of r ll and r os . the capacitor value can be found from the following equation once the output capacitor esr is known: where r esr_co is the total equivalent series resistance and c o is the total capacitance of the output capacitors. loop compensation with integral feedback for applications that do not implement droop, it is nec- essary to compensate the loop using integral feedback. looking at the transfer function from inductor current i l (t) to output: the dc gain is the output impedance r out : r out = v out / i out_max a pole and zero are present due to the output capaci- tance (c o ), output-capacitor esr (r esr_co ), and the load impedance (r out ), as follows: the transfer function from control voltage v c (t) to induc- tor current i l (t) is: where r sense is the resistance of the current-sense element, and g ca is the current-sense amplifier gain. the simplified control-to-output transfer function is then: gggn contr output pwm vi _ ? () = () g it vt rg pwm l c sense ca = () () = 1 : _ _ _ = + () = () + () pole out esr co o zero out esr co out esr co o rr c and rr rr c 1 1 gr vi out zero pole ? ? () = + + 1 1 c rc r comp esr co o comp = _ r gv r rr rr r rg ng r os mv os ll os comp os comp comp sense ca mv o = = ? = 1 r gnr rg v r gnr rg v ll mv o sense ca os os mv o sense ca os = ? ? ? ? ? ? ? = + ? ? ? ? ? ? ? 1 2 1 2 1 20 10 6 where:
max8809a/max8810a ______________________________________________________________________________________ 37 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers this simplified transfer function ignores a double pole due to the current-mode sampling effect, which can be approximately placed at 1/2 the per-phase switching frequency. as a rule-of-thumb, the loop should be designed to close between 1/5th and 1/10th of the per-phase switching frequency. at this point, a determination should be made as to which of the following cases applies to the desired crossover frequency: case 1: pole < 2 x f crossover < zero this case is likely to exist in situations where the zero frequency ( zero ) is relatively high due to use of low- value output capacitors with low esr (e.g., 560?/7m or all-ceramic designs). analysis of the control-to-output transfer function for this case shows that 1) the slope is -1 at the crossover frequency due to the low-frequency pole ( pole ), and 2) the compensation must provide gain boost at the crossover frequency to bring the loop gain to zero at crossover. because of item 1), the compensator gain must be flat at crossover so that the closed-loop gain rolls off with -1 slope at crossover. for this case, it is recommended to design the com- pensator with type ii compensation. the zero is placed to ensure flat gain at crossover, and the 2nd pole pro- vides phase shift above crossover. the compensator consists of a series resistor (r comp ) and capacitor (c comp1 ) from comp to gnd, and a second capacitor (c comp2 ) placed from comp to gnd, in parallel to r comp and c comp1 (see figure 11). the first step in the compensator design is to choose the desired phase margin at crossover and solve for the error-amplifier phase shift: error_amplifier = margin - contr_output where margin is the desired phase margin at cross- over, and contr_output is the phase shift from control- to-output (at crossover). the next step is to determine the constant k value in the equation below, which provides the desired error-ampli- fier phase shift determined above. the value of k deter- mines the locations of the error-amplifier zero and high-frequency pole relative to the crossover frequency: the simplified compensator transfer function can be modeled at low frequencies as: where g mv is the transconductance of the error amplifi- er. at crossover, c comp1 is essentially a short and can be ignored. the compensator must provide gain boost to bring the loop gain to zero at crossover. applying these criteria and solving for r comp : solving for c comp1 and c comp2 is now relatively straightforward: case 2: zero < 2 x f crossover < pole-cm where pole-cm is the frequency of the double pole created by the sampling effect. this case is likely to exist in situations where high-capacitance, high-esr output capacitors (e.g., low-cost aluminum electrolytic such as 2800?/12m ) are used. analysis of the control-to-output transfer function for this case shows that 1) the slope is zero at crossover so the compensation must roll off with a -1 slope, and 2) the compensation must provide gain boost at the crossover frequency to bring the loop gain to zero at crossover. both of these conditions are satisfied with the following relationship: g fc gf mv crossover comp contr output crossover || _ = () 1 2 1 c r c r comp zero error amplifier comp comp pole error amplifier comp 1 2 1 1 __ __ = = r gg f comp mv contr output crossover || _ = () 1 gr c mv comp comp + ? ? ? ? ? ? 1 1 error amplifier zero error amplifier crossover pole error amplifier crossover k k f k fk _ __ __ arctan arctan = () ? ? ? ? ? ? ? ? ? ? ? ? ? + = = 1 180 90 2 2 max8809a/ max8810a comp r comp c comp2 c comp1 figure 11. type ii compensation scheme
max8809a/max8810a 38 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers where g mv is the transconductance of the error amplifi- er and c comp is a capacitor placed from the output of the error amplifier (comp) to gnd. solving for c comp : multiload-line programming (max8810a) in some applications, it may be desired to implement multiple load-lines. this is easily accomplished by switching resistors in parallel with r ll (figure 12). paralleling resistors with r ll causes the load-line resis- tance to increase. with this scheme implemented for the max8810a, the offset voltage is not affected by the new load-line setting. it is also not necessary to change the temperature compensation based on the new load- line setting. switches s1 and s2 can be implemented with small-signal n-channel mosfets. r ll1 and r os are designed using methods described in the loop-compensation design section. r o1 , r o2 , and r o3 are the required load-line resistances. r ll2 and r ll3 are calculated as follows: setting the current limit the current-limit threshold sets the maximum available output dc current. the output current limit should be selected to meet the otf requirement as described in the output capacitor selection section. the voltage at ilim and the value of the current-sense resistor or the dc resistance of the output inductor sets the current- limit threshold: where r sense is the resistance of the current-sensing element. the value of r sense at room temperature must be used because the max8809a and max8810a provide temperature-compensated current limit. v ilim is set by connecting ilim to the center tap of a resistor- divider from ref to gnd. select r1 and r3 (figure 13) so the current through the divider is at least 10?: r1 + r3 < 200k a typical value for r1 is 10k ; then solve for r3 using: rr v v lim lim 31 2 = ? vgr i n ilim ca sense lim = rrr r rr rr r r r r r rr rr r rr rr r r r comp ll os ll comp comp comp comp comp o o comp comp ll os ll os ll comp comp comp comp comp o o 1 2 12 12 2 1 2 1 1 1 1 3 23 23 3 2 3 || = = ? = = + = ? = r comp2 cgx gf f comp mv contr output crossover crossover || _ = () 2 max8810a comp buf r ll1 r os r ll2 r ll3 figure 12. load-line switching circuit where: and: where:
max8809a/max8810a ______________________________________________________________________________________ 39 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers applications information pc board layout guidelines a properly designed pc board layout is important in any switching dc-dc converter circuit. mount the mosfets, inductors, input/output capacitors, and cur- rent-sense resistor on the top side of the pc board. a single large ground plane is preferred; however it is very important to partition the ?nalog?portion of this ground plane from the ?ower?portion of the ground plane. ensure that all analog ground connections are made to the ground plane away from any areas of power ground switching currents. do not connect the analog returns at a single point to the ground plane; use as many direct connections as possible. connect the gnd of the ic to the thermal pad of the ic on the top layer. connect the thermal pad to the ground plane through at least nine 10-mil drill size vias. to help dissipate heat, place high-power components (mosfets and inductors) on a large copper area, or use a heat sink. keep high-current traces short, wide, and tightly coupled to reduce trace inductances and resistances. gate-drive traces should be at least 20 mils wide, kept as short as possible, and tightly cou- pled to reduce emi and ringing induced by high-fre- quency gate currents. adjacent dh_ and lx_ traces should be tightly coupled. connect the pgnd_ pins to the ground plane near the controller through two vias (each). a clean current-sense signal is critical to a successful layout. always place the current-sense traces on the bottom layer. make sure all adjacent traces (for exam- ple cs1+, cs2+, and cs12-) are tightly coupled. kelvin connections to the current-sense element are essential. for inductor dcr current-sensing, place all current- sense components near the inductor, except for the fil- tering capacitors, which should be placed next to the controller ic. this ensures that noise generated by large di/dt on the lx node is kept away from both cur- rent-sense signals and the controller ic. to ensure the integrity of the current-sense signal, the inner layer above the bottom layer must be a solid ground plane. place the vl_ decoupling capacitor on the top layer and near the vl_ pins. the negative terminal of the vl_ decoupling capacitor should be connected to pgnd_ on the top layer. also place the bst capacitors on the top layer near the controller. when needed always use double vias on the driver traces to reduce inductance. do not connect the pgnd_ pins to the thermal pad on the top layer. the ntc thermistor should be placed near the ?ottest inductor. use two traces, tightly coupled, to return to the controller. to ensure temperature compensation accuracy, make sure that the gnd trace of the ntc is not ?ccidentally?connected to any other gnd trace or ground plane on the way back to the controller. place the buf capacitor, ref capacitor, vcc capaci- tor, the current-sense decoupling capacitors, and the remote-sense decoupling capacitors as close to the max8809a/max8810a as possible. all decoupling capacitors must make a direct connection to the corre- sponding pin. making the connection using vias to transition between layers creates parasitic inductance, which negates the benefit of the decoupling capacitor. if this cannot be avoided, use double vias to minimize the parasitic inductance. a sample layout is available in the evaluation kit to speed designs. chip information process: bicmos
max8809a/max8810a 40 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers r5 r4 c10 cs1+ v in + v out vtt vrhot vrready v cc _sen v ss _sen outen ref ref system 5v c12 r7 r6 c21 system 5v c26 c25 r17 r13 r12 r16 r23 r24 vout v in + n1 n3 n2 1 2 3 1 2 3 2 3 1 2 3 1 1 2 3 1 2 3 2 3 1 2 3 1 c5 c6 c7 c1 c2 l1 l2 c3 c4 c27 c28 c29 c30 c31 c32 c33 c17 c15 c11 c9 c8 6 32 20 1 18 3 10 4 12 11 5 26 8 7 c18 c19 c22 c23 c24 n4 v in + max8809a c14 r11 r10 c13 cs2+ r15 c16 n5 n7 n6 n8 r20 r19 c20 cs3+ n9 n11 n10 1 1 2 9 3 3 1 2 3 2 3 1 2 3 1 10 1 4 bst dh1 bst1 ilim ilim lx1 lx2 dl1 pgnd1 dh2 dl2 bst2 pgnd2 vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 cs3+ cs3- cs2+ cs1+ cs12- pwm3 osc dh lx cs3- cs3+ cs2+ cs1+ cs12- dl 5 6 7 vl 9 v cc gnd pgnd v cc sel vrhot vrready en ref ss/ovp comp vrtset ntc gnd vl12 vl ep rs+ rs- v cc vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 dly pwm max8552 en 8 21 u1 2 23 22 24 25 31 29 30 28 27 33 34 35 36 37 38 39 40 13 14 15 17 16 19 2 3 l3 r21 r9 n12 vl r14 r22 r1 r3 r2 r18 d1 u2 r25 cs12- cs3- figure 13. intel vrd11 desktop application circuit using the max8809a?-phase, 85a
max8809a/max8810a ______________________________________________________________________________________ 41 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers components description part number c1?4 1500?, 16v aluminum electrolytic capacitors rubycom 16vmbz1500 c5, c6, c7 10?, 16v x5r ceramic capacitors (1206) taiyo yuden emk316bj106ml c8, c15, c21 2.2?, 10v x5r ceramic capacitors (0603) taiyo yuden lmk107bj225ma c9, c11, c12, c16, c17 0.22?, 16v x5r ceramic capacitors (0603) taiyo yuden emk107bj224ka c10, c13, c20 2200pf, 50v x7r ceramic capacitors (0603) tdk c1608x7r1h222k c14 68pf, 50v c0g ceramic capacitor (0603) kemet c0603c101j5gactu c18, c22, c23 0.22?, 10v x5r ceramic capacitors (0603) tdk c1608x5r1a224k c19, c24, c25, c26 1000pf, 50v x7r ceramic capacitors (0603) kemet c0603c102j5ractu c27?33 560?, 4v, 7m esr os-con capacitors sanyo 4r5sep560m d1 30v, 200ma schottky diode (sot23) central semiconductor cmpsh-3 l1, l2, l3 0.20?, 30a toroid cores falco t50069 n1, n2, n5, n6, n9, n10 30v, 12m n-channel logic mosfets (dpak) international rectifier irlr7821 n3, n4, n7, n8, n11, n12 30v, 4.5m n-channel logic mosfets (dpak) international rectifier irlr7843 r1 10k 1% resistor (0603) r2 10 5% resistor (0603) r15 5.62k 1% resistor (0603) r4, r9, r10, r19, r21 2.2 5% resistors (0603) r5, r11, r20 1.62k 1% resistors (0603) r6, r7 680 1% resistors (0603) r3, r12 8.06k 1% resistors (0603) r13 22k 5% resistor (0603) r14 0 5% resistor (0603) r16 10k ntc thermistor panasonic ertj1vr103 r17 61.9k 1% resistor (0603) r18 7.1k 1% resistor (0603) r22 not installed r23, r24 100 1% resistors (0603) r25 220k 1% resistor (0603) u1 vrd11, vrd10, and k8 rev f 3-phase controller maxim max8809a u2 high-speed, single-phase mosfet driver maxim max8552 table 8. bill of materials for intel vrd11 3-phase desktop application circuit (figure 13)
max8809a/max8810a 42 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers r4 c11 v in + v out vtt vrhot vrready v cc _sen v ss _sen outen ref ref system 5v c13 r7 r6 c17 c25 c31 c30 r12 ntc r16 r22 r23 c14 r13 v out v in + n1 n3 n2 c5 1 2 3 1 2 3 2 3 1 2 3 1 1 2 3 1 2 3 2 3 1 2 3 1 c6 c7 c8 c1 c2 l1 l2 c3 c4 c33 c34 c35 c36 c37 c38 c22 c18 c23 c19 c12 c10 c9 6 38 24 48 21 2 12 3 4 14 13 5 30 31 9 8 c20 c21 c26 c27 c28 c29 n4 v in + max8810a r10 c15 c39 c40 n5 n7 n6 n8 r17 c24 v in + n9 n11 n10 1 1 2 2 11 3 3 1 2 3 2 3 1 2 3 1 1 16 15 14 12 1 4 13 bst1 dh1 bst1 ilim lx1 dl1 pgnd1 dh2 bst2 lx2 dl2 pgnd2 vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 cs34- cs4+ cs3+ cs2+ cs1+ cs12- pwm3 pwm4 osc dh1 lx1 cs34- cs4+ cs3+ cs2+ cs1+ cs12- pgnd1 dl1 pgnd2 bst2 dh2 lx2 dl2 7 8 9 10 2 pv1 pv2 v cc sel vrhot vrready en ref ss/ovp comp buf ntc vrtset gnd vl1 vl system 5v vl2 ep rs+ rs- v cc n.c. n.c. vid5 vid4 vid3 vid2 vid1 vid0 v cc dly pwm1 max8523 pwm2 3 25 u1 1 27 26 28 29 36 34 35 33 32 39 40 41 42 43 44 45 46 16 15 17 18 20 19 23 22 5 6 11 2 3 1 2 3 2 3 1 2 3 1 l3 l4 r19 r9 n12 vl r25 r24 r21 r14 r15 r1 r3 r2 r20 d1 u2 r26 c32 cs4+ cs12- cs34- n13 n15 n14 n16 r27 r5 cs1+ r27 c41 r11 cs2+ r28 c42 r18 cs3+ r29 c43 r30 c44 figure 14. intel vrd11 desktop application circuit using the max8810a?-phase, 115a
max8809a/max8810a ______________________________________________________________________________________ 43 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers table 9. bill of materials for intel vrd11 4-phase desktop application circuit (figure 14) components description part number c1?4 1500?, 16v aluminum electrolytic capacitors rubycom 16vmbz1500 c5?8 10?, 16v x5r ceramic capacitors (1206) taiyo yuden emk316bj106ml c9, c17, c18, c25 2.2?, 10v x5r ceramic capacitors (0603) taiyo yuden lmk107bj225ma c10, c12, c13, c22, c29 0.22?, 16v x5r ceramic capacitors (0603) taiyo yuden emk107bj224ka c11, c15, c24, c32 2200pf, 50v x7r ceramic capacitors (0603) tdk c1608x7r1h222k c14 68pf, 50v c0g ceramic capacitor (0603) kemet c0603c101j5gactu c19, c20, c26, c27 0.22?, 10v x5r ceramic capacitors (0603) tdk c1608x5r1a224k c21, c28, c30, c31 1000pf, 50v x7r ceramic capacitors (0603) murata c0603c102j5ractu c33?40 560?, 4v, 7m esr os-con capacitors sanyo 4r5sep560m d1 30v, 200ma schottky diode (sot23) central semiconductor cmpsh-3a l1?4 0.20?, 30a toroid cores falco t50069 n 1, n 2, n 5, n 6, n 9, n 10, n 13, n 14 30v, 12m n-channel logic mosfets (dpak) international rectifier irlr7821 n 3, n 4, n 7, n 8, n 11, n 12, n 15, n 16 30v, 4.5m n-channel logic mosfets (dpak) international rectifier irlr7843 r1 10k 1% resistor (0603) r2, r15 10 5% resistors (0603) r3 7.15 1% resistor (0603) r4, r9, r10, r17, r19, r24 2.2 5% resistors (0603) r5, r11, r18, r25 1.62k 1% resistors (0603) r6, r7 680 1% resistors (0603) r12 22.0k 1% resistor (0603) r13 26.1k 1% resistor (0603) r14, r21 0 5% resistors (0603) r16 61.9k , ?% resistor (0603) r20 7.17 1% resistor (0603) r22, r23 100 1% resistors (0603) r26 160k 1% resistor (0603) r27 2.87k 1% resistor (0603) ntc 10k ntc thermistor panasonic ertj1vr103 u1 vrd11, vrd10, and k8 rev f 4-phase controller maxim max8810a u2 high-speed, dual-phase mosfet driver maxim max8523
max8809a/max8810a 44 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers r5 r27 r4 c11 cs1+ c41 v in + v out vtt vrhot vrready vcc_sen vss_sen outen ref ref system 5v c13 r7 r6 c17 c25 c31 c30 r12 ntc r16 r22 r23 c14 c16 r13 v out v in + n1 n3 n2 c5 1 2 3 1 2 3 2 3 1 2 3 1 1 2 3 1 2 3 2 3 1 2 3 1 c6 c7 c8 c1 c2 l1 l2 c3 c4 c33 c34 c35 c36 c37 c38 c22 c18 c23 c19 c12 c10 c9 6 38 24 48 21 2 12 3 4 14 13 5 30 31 9 8 c20 c21 c26 c27 c28 c29 n4 v in + max8810a r28 c42 r29 c43 r30 c44 r11 r10 c15 cs2+ c39 c40 n5 n7 n6 n8 r18 r17 c24 cs3+ v in + n9 n11 n10 1 1 2 2 11 3 3 1 2 3 2 3 1 2 3 1 1 16 15 14 12 1 4 13 bst1 dh1 bst1 ilim lx1 dl1 pgnd1 dh2 bst2 lx2 dl2 pgnd2 vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 cs34- cs4+ cs3+ cs2+ cs1+ cs12- pwm3 pwm4 osc dh1 lx1 dl1 cs34- cs4+ cs3+ cs2+ cs1+ cs12- pgnd1 pgnd2 bst2 dh2 lx2 dl2 7 8 9 10 2 pv1 pv2 v cc sel vrhot vrready en ref ss/ovp comp buf ntc vrtset gnd vl1 vl system 5v vl2 ep rs+ rs- v cc n.c. n.c. vid5 vid4 vid3 vid2 vid1 vid0 v cc dly pwm1 max8523 pwm2 3 25 u1 1 27 26 28 29 36 34 35 33 32 39 40 41 42 43 44 45 46 16 15 17 18 20 19 23 22 5 6 11 2 3 1 2 3 2 3 1 2 3 1 l3 l4 r19 r9 n12 vl r25 r24 r21 r14 r15 r1 r3 r2 r20 d1 u2 r26 c32 cs4+ cs12- cs34- n13 n15 n14 n16 figure 15. amd k8 rev f desktop application circuit using the max8810a?-phase, 115a
max8809a/max8810a ______________________________________________________________________________________ 45 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers table 10. bill of materials for amd k8 rev f desktop application circuit (figure 15) components description part number c1?4 1500?, 16v aluminum electrolytic capacitors rubycom 16vmbz1500 c5?8 10?, 16v x5r ceramic capacitors (1206) taiyo yuden emk316bj106ml c9, c17, c18, c25 2.2?, 10v x5r ceramic capacitors (0603) taiyo yuden lmk225bj225ml c10, c12, c13, c22, c29 0.22?, 10v x5r ceramic capacitors (0603) taiyo yuden emk107bj224ka c11, c15, c24, c32 2200pf, 50v x7r ceramic capacitors (0603) tdk c1608x7r1h222k c14 not installed (0603) c16 0.015?, 50v c0g ceramic capacitor (0603) murata grm39x7r153k50 c19, c20, c23, c26, c27 0.22?, 10v x5r ceramic capacitors (0603) tdk c1608x5r1a224k c21, c28, c30, c31 1000pf, 50v x7r ceramic capacitors (0603) kemet c0603c102j5ractu c33?40 2200?, 6.3v, 12m esr aluminum electrolytic capacitors rubycon 6.3vmbz2200 c41?44 not installed (0603) d1 30v, 200ma schottky diode (sot23) central semiconductor cmpsh-3a l1?4 0.28?, 30a toroid cores falco t50183 n 1, n 2, n 5, n 6, n 9, n 10, n 13, n 14 30v, 12m n-channel logic mosfets (dpak) international rectifier irlr7821 n 3, n 4, n 7, n 8, n 11, n 12, n 15, n 16 30v, 4.5m n-channel logic mosfets (dpak) international rectifier irlr7843 r1 10k 1% resistor (0603) r2, r15 10 5% resistors (0603) r3 7.15k 1% resistor (0603) r4, r9, r10, r17, r19, r24 2.2 5% resistors (0603) r5, r11, r18, r25 1.62k 1% resistors (0603) r6, r7 680 1% resistors (0603) r12 22.0k 1% resistor (0603) r13 4.32k 1% resistor (0603) r14, r21 0 5% resistors (0603) r16 61.9k 1% resistor (0603) r20 7.10k 1% resistor (0603) r22, r23 100 11% resistors (0603) r26 160k 1% resistor (0603) r27?30 not installed (0603) ntc 10k ntc thermistor panasonic ertj1vr103 u1 vrd11, vrd10, and k8 rev f 4-phase maxim max8810a u2 high-speed, dual-phase mosfet driver maxim max8523
max8809a/max8810a 46 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers table 11. suggested component suppliers component supplier phone fax website bi technologies 714-447-2300 714-388-0046 www.bitechnologies.com falco 305-662-7276 928-752-3256 www.falco.com international rectifier 310-252-7105 310-252-7903 www.irf.com kemet 864-963-6300 408-986-1442 www.kemet.com murata 770-436-1300 770-436-3030 www.murata.com pulse 215-781-6400 215-781-6403 www.pulseeng.com panasonic 800-344-2112 www.panasonic.com sanyo 619-661-6835 619-661-1055 www.sanyo.com taiyo yuden 81-3-3833-5441 81-3-3835-4754 www.t-yuden.com tdk 408-437-9585 408-437-9591 www.component.tdk.com pin configurations top view max8810a thin qfn 13 14 15 16 17 18 19 20 21 22 23 24 vrtset ntc cs4+ cs34- cs3+ cs2+ cs12- cs1+ en pwm4 pwm3 vrhot 48 47 46 45 44 43 42 41 40 39 38 37 1 2 345678910 11 12 vrready n.c. vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 sel n.c. ss/ovp osc n.c. rs+ rs- n.c. v cc gnd buf comp ref ilim 36 35 34 33 32 31 30 29 28 27 26 25 dh1 lx1 bst1 dl1 pgnd1 vl1 vl2 pgnd2 dl2 bst2 lx2 dh2 max8809a thin qfn top view 35 36 34 33 12 11 13 ilim comp gnd v cc rs- 14 vrready pgnd2 pgnd1 dl1 dl2 bst2 lx2 bst1 lx1 12 vid6 4567 27 28 29 30 26 24 23 22 vid5 vid4 en cs1+ cs12- cs2+ ref vl12 3 25 37 vid3 cs3+ 38 39 40 vid2 vid1 vid0 + cs3- ntc vrtset vid7 32 15 pwm3 sel 31 16 17 18 19 20 vrhot rs+ osc ss/ovp dh1 8910 21 dh2 +
max8809a/max8810a ______________________________________________________________________________________ 47 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps
max8809a/max8810a 48 ______________________________________________________________________________________ vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max8809a/max8810a ______________________________________________________________________________________ 49 vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps
max8809a/max8810a maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 50 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. vrd11/vrd10, k8 rev f 2/3/4-phase pwm controllers with integrated dual mosfet drivers package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) cardenas - 80% freed - 20% revision history pages changed at rev 1: 1?, 8, 13?6, 19, 20, 22, 30-37, 40, 43.

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