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publication number 23569 revision a amendment 5 issue date december 4, 2006 the following document contains information on spansion memory products. although the document is marked with the name of the company that orig inally developed the specification, spansion will continue to offer these products to existing customers. continuity of specifications there is no change to this data sheet as a result of offering the device as a spansion product. any changes that have been made are the result of no rmal data sheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers spansion continues to support existing part number s beginning with ?am? and ?mbm?. to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local sales office for additi onal information about spansion memory solutions. am29pds322d data sheet
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data sheet this data sheet states amd?s current technical specificat ions regarding the products described herein. this data sheet may be revised by subsequent versions or modifications due to changes in technical specifications. publication# 23569 rev: a amendment/ 5 issue date: december 4, 2006 am29pds322d 32 megabit (2 m x 16-bit) cmos 1.8 volt-only (1.8 v to 2.2 v) simultaneous read/write page-m ode boot sector flash memory distinctive characteristics architectural advantages simultaneous read/write operations ? data can be continuously read from one bank while executing erase/program functions in other bank. ? zero latency between read and write operations page mode operation ? 4 word page allows fast asynchronous reads dual bank architecture ? one 4 mbit bank and one 28 mbit bank secsi (secured silicon) sector: extra 64 kbyte sector ? factory locked and identifiable: 16 byte electronic serial number available for factory secure, random id; verifiable as factory locked through autoselect function. expressflash option allows entire sector to be available for factory-secured data ? customer lockable: can be read, programmed, or erased just like other sect ors. once locked, data cannot be changed zero power operation ? sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. package options ? 48-ball fbga top or bottom boot block manufactured on 0.23 m process technology compatible with jedec standards ? pinout and software compatible with single-power-supply flash standard performance characteristics high performance ? access time as fast 40 ns (100 ns random access time) at 1.8 v to 2.2 v v cc ? random access time of 100 ns at 1.8 v to 2.2 v v cc will be required as customers migrate downward in voltage ultra low power consumption (typical values) ? 2.5 ma active read current at 1 mhz for initial page read ? 24 ma active read current at 10 mhz for initial page read ? 0.5 ma active read current at 10 mhz for intra-page read ? 1 ma active read current at 20 mhz for intra-page read ? 200 na in standby or automatic sleep mode minimum 1 million write cycles guaranteed per sector 20 year data retention at 125 c ? reliable operation for the life of the system software features data management software (dms) ? amd-supplied software manages data programming, enabling eeprom emulation ? eases historical sector erase flash limitations erase suspend/erase resume ? suspends erase operations to allow programming in same bank data# polling and toggle bits ? provides a software method of detecting the status of program or erase cycles unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features any combination of sectors can be erased ready/busy# output (ry/by#) ? hardware method for detecting program or erase cycle completion hardware reset pin (reset#) ? hardware method of resetting the internal state machine to the read mode wp#/acc input pin ? write protect (wp#) function allows protection of two outermost boot sectors, regardless of sector protect status ? acceleration (acc) function accelerates program timing ? acc voltage is 8.5 v to 12.5 v sector protection ? hardware method of locking a sector, either in-system or using prog ramming equipment, to prevent any program or erase operation within that sector ? temporary sector unprotect allows changing data in protected sectors in-system
2 am29pds322d 23569a5 december 4, 2006 data sheet general description the am29pds322d is a 32 mbit, 1.8 v-only flash memory organized as 2,097,152 words of 16 bits each. this device is offered in a 48-ball fbga pack- age. the device is designed to be programmed in sys- tem with standard system 1.8 v v cc supply. this device can also be reprogrammed in standard eprom programmers. the am29pds322d offers fast page access time of 40 ns with random access time of 100 ns (at 1.8 v to 2.2 v v cc ), allowing operation of high-speed micropro- cessors without wait states. to eliminate bus conten- tion the device has separate chip enable (ce), write enable (we), and output enable (oe) controls. the page size is 4 words. the device requires only a single 1.8 volt power sup- ply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. simultaneous read/write operations with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into two banks. the device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and si- multaneously read from the other bank, with zero latency. this releases the system from waiting for the completion of program or erase operations. the device is divided as shown in the following table: am29pds322d features the secsi (secured silicon) sector is an extra 64 kbyte sector capable of being permanently locked by amd or customers. the secsi indicator bit (dq7) is permanently set to a 1 if the part is factory locked , and set to a 0 if customer lockable . this way, cus- tomer lockable parts can never be used to replace a factory locked part. factory locked parts provide several options. the secsi sector may store a secure, random 16 byte esn (electronic serial number), customer code (pro- grammed through amd?s expressflash service), or both. customer lockable parts may utilize the secsi sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. dms (data management software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of eeprom devices. dms will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. to write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. this is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the flash memory device (or memory de- vices), and more. using dms, user-written software does not need to interface with the flash memory di- rectly. instead, the user's software accesses the flash memory by calling one of only six functions. amd pro- vides this software to simplify system design and soft- ware integration efforts. the device offers complete compatibility with the jedec single-power-supply flash command set standard . commands are written to the command register using standard microprocessor write timings. reading data out of the device is similar to reading from other flash or eprom devices. the host system can detect whether a program or erase operation is complete by using the device sta- tus bits: ry/by# pin, dq7 (data# polling) and dq6/dq2 (toggle bits). after a program or erase cycle has been completed, the device automatically returns to the read mode. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. this can be achieved in-system or via program- ming equipment. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly re- duced in both modes. bank 1 sectors bank 2 sectors quantity size quantity size 84 kwords 56 32 kwords 7 32 kwords 4 mbits total 28 mbits total
december 4, 2006 23569a5 am29pds322d 3 data sheet table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 special handling instructions for fbga package .................... 5 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . 7 device bus operations . . . . . . . . . . . . . . . . . . . . . 8 table 1. am29pds322d device bus operations .............................8 requirements for reading array data ..................................... 8 read mode ............................................................................... 8 random read (non-page mode read) ............................................8 page mode read ...................................................................... 9 table 2. page word mode ................................................................9 writing commands/command sequences .............................. 9 accelerated program operation ........................................................9 autoselect functions .........................................................................9 simultaneous read/write operations with zero latency ......... 9 standby mode .......................................................................... 9 automatic sleep mode ........................................................... 10 reset#: hardware reset pin ............................................... 10 output disable mode .............................................................. 10 table 3. am29pds322dt top boot sector addresses ..................11 table 4. am29pds322dt top boot secsi sector address ...........12 table 5. am29pds322db bottom boot sector addresses ............12 table 6. am29pds322db bottom boot secsi sector address . . .14 autoselect mode..................................................................... 15 table 7. autoselect codes (high voltage method) ........................15 sector/sector block protection and unprotection .................. 16 table 8. top boot sector/sector block addresses for protection/unprotection ...................................................................16 table 9. bottom boot sector/sector block addresses for protection/unprotection ...................................................................16 write protect (wp#) ................................................................ 17 temporary sector/sector block unprotect ............................. 17 figure 1. temporary sector unprotect operation........................... 17 figure 2. temporary sector group unprotect operation................ 18 figure 3. in-system sector group protect/unprotect algorithms ... 19 secsi (secured silicon) sector flash memory region .......... 20 factory locked: secsi sector programmed and protected at the factory ..................................................................................20 hardware data protection ...................................................... 20 low v cc write inhibit .......................................................................20 write pulse ?glitch? protection ........................................................21 logical inhibit ..................................................................................21 power-up write inhibit ....................................................................21 command definitions . . . . . . . . . . . . . . . . . . . . . 21 reading array data ................................................................ 21 reset command ..................................................................... 21 autoselect command sequence ............................................ 21 enter secsi sector/exit secsi sector command sequence .. 22 word program command sequence ..................................... 22 unlock bypass command sequence ..............................................22 chip erase command sequence ........................................... 22 figure 4. unlock bypass algorithm................................................. 23 figure 5. program operation .......................................................... 23 sector erase command sequence ........................................ 24 erase suspend/erase resume commands ........................... 24 figure 6. erase operation.............................................................. 25 am29pds322d command definitions . . . . . . . . 26 write operation status . . . . . . . . . . . . . . . . . . . . . 27 dq7: data# polling ................................................................. 27 figure 7. data# polling algorithm .................................................. 27 ry/by#: ready/busy#............................................................ 28 dq6: toggle bit i .................................................................... 28 figure 8. toggle bit algorithm........................................................ 28 dq2: toggle bit ii ................................................................... 29 reading toggle bits dq6/dq2 ............................................... 29 dq5: exceeded timing limits ................................................ 29 dq3: sector erase timer ....................................................... 29 table 11. write operation status ................................................... 30 absolute maximum ratings. . . . . . . . . . . . . . . . . 31 figure 9. maximum negative overshoot waveform ...................... 31 figure 10. maximum positive overshoot waveform...................... 31 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 31 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11. i cc1 current vs. time (showing active and automatic sleep currents) .............................................................................. 33 figure 12. typical i cc1 vs. frequency ............................................ 33 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13. test setup.................................................................... 34 table 12. test specifications ......................................................... 34 key to switching waveforms. . . . . . . . . . . . . . . . 34 figure 14. input waveforms and measurement levels ................. 34 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 15. conventional read operation timings ......................... 35 figure 16. page mode read timings ............................................ 36 hardware reset (reset#) .................................................... 37 figure 17. reset timings ............................................................... 37 erase and program operations .............................................. 38 figure 18. program operation timings.......................................... 39 figure 19. accelerated program timing diagram.......................... 39 figure 20. chip/sector erase operation timings .......................... 40 figure 21. back-to-back read/write cycle timings ...................... 41 figure 22. data# polling timings (during embedded algorithms). 41 figure 23. toggle bit timings (during embedded algorithms)...... 42 figure 24. dq2 vs. dq6................................................................. 42 temporary sector unprotect .................................................. 43 figure 25. temporary sector group unprotect timing diagram ... 43 figure 26. sector group protect and unprotect timing diagram .. 44 alternate ce# controlled erase and program operations ..... 45 figure 27. alternate ce# controlled write (erase/program) operation timings.......................................................................... 46 erase and programming performance. . . . . . . . 47 latchup characteristics . . . . . . . . . . . . . . . . . . . . 47 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 48 fbd048?48-ball fine-pitch ball grid array (fbga) 6 x 12 mm package ................................................................ 48 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 49
4 am29pds322d 23569a5 december 4, 2006 data sheet product selector guide note: see ?ac characteristics? for full specifications. block diagram part number am29pds322d speed options standard voltage range: v cc = 1.8?2.2 v 10 12 max random address access time (ns) 100 120 max page address access time (ns) 40 45 ce# access time (ns) 100 120 oe# access time (ns) 35 40 v cc v ss upper bank address a0?a20 reset# we# ce# dq0?dq15 wp#/acc state control & command register ry/by# upper bank x-decoder y-decoder latches and control logic oe# dq0?dq15 lower bank y-decoder x-decoder latches and control logic lower bank address status control a0?a20 a0?a20 a0?a20 a0?a20 dq0?dq15 dq0?dq15 mux mux mux
december 4, 2006 23569a5 am29pds322d 5 data sheet connection diagrams special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq15 v ss nc a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 nc reset# we# dq11 dq3 dq10 dq2 a20 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 48-ball fbga top view, balls facing down
6 am29pds322d 23569a5 december 4, 2006 data sheet pin description a0?a20 = 21 addresses inputs dq0?dq15 = 16 data inputs/outputs ce# = chip enable input oe# = output enable input we# = write enable input wp#/acc = hardware write protect/ acceleration input reset# = hardware reset pin input ry/by# = ready/busy output v cc = 1.8 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 21 16 dq0?dq15 a0?a20 ce# oe# we# ry/by# reset# wp#/acc
december 4, 2006 23569a5 am29pds322d 7 data sheet ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. am29pds322d b 10 wm i n optional processing blank = standard processing n = 16-byte esn devices (contact an amd representative for more information) temperature range i = industrial (?40 c to +85 c) package type wm = 48-ball fine-pitch ball grid array (fbga) 0.80 mm pitch, 6 x 12 mm package (fbd048) speed option see product selector guide and valid combinations boot code sector architecture t = top sector b = bottom sector device number/description am29pds322d 32 megabit (2 m x 16-bit) cmos boot sector page mode flash memory 1.8 volt-only read, program, and erase valid combinations for fbga package order number package marking am29pds322dt10, am29pds322db10 wmi p322dt10u, p322db10u i am29pds322dt12, am29pds322db12 wmi p322dt12u, p322db12u i
8 am29pds322d 23569a5 december 4, 2006 data sheet device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. am29pds322d device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 9.0?11.0 v, v hh = 9.0 0.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. the sector protect and sector unprotect functions may also be implemented vi a programming equipment. see the ?sector/sector block protection and unprotection? section. 2. if wp#/acc = v il , the two outermost boot sectors re main protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotect ed using the method described in ?sector/sector block protection and unprotecti on?. if wp#/acc = v hh, all sectors will be unprotected. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?requirements for reading array data? for more information. refer to the ac read-only operations table for timing specifications and to figure 15 for the timing diagram. i cc1 in the dc characteristics table represents the active current specification for reading array data. read mode random read (non-page mode read) the device has two control functions which must be satisfied in order to obtain data at the outputs. ce# is the power control and should be used for device selec- tion. oe# is the output control and should be used to gate data to the output pins if the device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ad- dresses and stable ce# to valid data at the output pins. the output enable access time is the delay from the falling edge of oe# to valid data at the output pins (assuming the addresses have been stable for at least t acc ?t oe time). operation ce# oe# we# reset# wp#/acc addresses (note 1) dq0?dq15 read l l h h l/h a in d out write l h l h (note 2) a in d in standby v cc 0.3 v x x v cc 0.3 v h x high-z output disable l h h h l/h x high-z reset x x x l l/h x high-z sector protect (note 1) l h l v id l/h sa, a6 = l, a1 = h, a0 = l d in sector unprotect (note 1) l h l v id (note 2) sa, a6 = h, a1 = h, a0 = l d in temporary sector unprotect x x x v id (note 2) a in d in
december 4, 2006 23569a5 am29pds322d 9 data sheet page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read oper- ation. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words. the appropriate page is selected by the higher address bits a20?a2 and the lsb bits a1?a0 determine the specific word within that page. this is an asynchronous operation with the micropro- cessor supplying the spec ific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) are equivalent to t pac c . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . here again, ce# selects the device and oe# is the output control and should be used to gate data to the output pins if the device is se- lected. fast page mode accesses are obtained by keeping a2?a20 constant and changing a0 to a1 to select the specific word within that page. see figure 16 for timing specifications. the following table determines the specific word within the selected page: table 2. page word mode writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word, instead of four. the ?word program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 2 indicates the address space that each sector occupies. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the ac characteristics section cont ains timing specification tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is prima- rily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the acc pin returns the device to normal op- eration. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autose lect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autose- lect command sequence sections for more informa- tion. simultaneous read/writ e operations with zero latency this device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. an erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. i cc6 and i cc7 in the dc characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. standby mode when the system is not read ing or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device re- quires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. word a1 a0 word 0 0 0 word 1 0 1 word 2 1 0 word 3 1 1
10 am29pds322d 23569a5 december 4, 2006 data sheet if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad- dress access timings provide new data when ad- dresses are changed. while in sleep mode, output data is latched and always available to the system. automatic sleep mode current is drawn when ce# = v ss 0.3 v and all inputs are held at v cc 0.3 v. if ce# and reset# voltages are not held within these tolerances, the automatic sleep mode current will be greater. i cc5 in the dc characteristics table represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for th e duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc3 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. if reset# is asserted during a program or erase op- eration, the ry/by# pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the sys- tem can thus monitor ry/by# to determine whether the reset operation is comp lete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algo- rithms). the system can read data t rh after the re- set# pin returns to v ih . refer to the ac characteristics tables for reset# pa- rameters and to figure 17 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
december 4, 2006 23569a5 am29pds322d 11 data sheet table 3. am29pds322dt top boot sector addresses bank sector sector address a20?a12 sector size (kwords) (x16) address range bank 2 sa0 000000xxx 32 000000h?07fffh sa1 000001xxx 32 008000h?0ffffh sa2 000010xxx 32 010000h?17fffh sa3 000011xxx 32 018000h?01ffffh sa4 000100xxx 32 020000h?027fffh sa5 000101xxx 32 028000h?02ffffh sa6 000110xxx 32 030000h?037fffh sa7 000111xxx 32 038000h?03ffffh sa8 001000xxx 32 040000h?047fffh sa9 001001xxx 32 048000h?04ffffh sa10 001010xxx 32 050000h?057fffh sa11 001011xxx 32 058000h?05ffffh sa12 001100xxx 32 060000h?067fffh sa13 001101xxx 32 068000h?06ffffh sa14 001110xxx 32 070000h?077fffh sa15 001111xxx 32 078000h?07ffffh sa16 010000xxx 32 080000h?087fffh sa17 010001xxx 32 088000h?08ffffh sa18 010010xxx 32 090000h?097fffh sa19 010011xxx 32 098000h?09ffffh sa20 010100xxx 32 0a0000h?0a7fffh sa21 010101xxx 32 0a8000h?0affffh sa22 010110xxx 32 0b0000h?0b7fffh sa23 010111xxx 32 0b8000h?0bffffh sa24 011000xxx 32 0c0000h?0c7fffh sa25 011001xxx 32 0c8000h?0cffffh sa26 011010xxx 32 0d0000h?0d7fffh sa27 011011xxx 32 0d8000h?0dffffh sa28 011100xxx 32 0e0000h?0e7fffh sa29 011101xxx 32 0e8000h?0effffh sa30 011110xxx 32 0f0000h?0f7fffh sa31 011111xxx 32 0f8000h?0fffffh sa32 100000xxx 32 100000h?107fffh sa33 100001xxx 32 108000h?10ffffh sa34 100010xxx 32 110000h?117fffh sa35 100011xxx 32 118000h?11ffffh sa36 100100xxx 32 120000h?127fffh sa37 100101xxx 32 128000h?12ffffh sa38 100110xxx 32 130000h?137fffh sa39 100111xxx 32 138000h?13ffffh sa40 101000xxx 32 140000h?147fffh sa41 101001xxx 32 148000h?14ffffh sa42 101010xxx 32 150000h?157fffh sa43 101011xxx 32 158000h?15ffffh
12 am29pds322d 23569a5 december 4, 2006 data sheet table 4. am29pds322dt top boot secsi sector address bank 2 sa44 101100xxx 32 160000h?167fffh sa45 101101xxx 32 168000h?16ffffh sa46 101110xxx 32 170000h?177fffh sa47 101111xxx 32 178000h?17ffffh sa48 110000xxx 32 180000h?187fffh sa49 110001xxx 32 188000h?18ffffh sa50 110010xxx 32 190000h?197fffh sa51 110011xxx 32 198000h?19ffffh sa52 110100xxx 32 1a0000h?1a7fffh sa53 110101xxx 32 1a8000h?1affffh sa54 110110xxx 32 1b0000h?1b7fffh sa55 110111xxx 32 1b8000h?1bffffh bank 1 sa56 111000xxx 32 1c0000h?1c7fffh sa57 111001xxx 32 1c8000h?1cffffh sa58 111010xxx 32 1d0000h?1d7fffh sa59 111011xxx 32 1d8000h?1dffffh sa60 111100xxx 32 1e0000h?1e7fffh sa61 111101xxx 32 1e8000h?1effffh sa62 111110xxx 32 1f0000h?1f7fffh sa63 111111000 4 1f8000h?1f8fffh sa64 111111001 4 1f9000h?1f9fffh sa65 111111010 4 1fa000h?1fafffh sa66 111111011 4 1fb000h?1fbfffh sa67 111111100 4 1fc000h?1fcfffh sa68 111111101 4 1fd000h?1fdfffh sa69 111111110 4 1fe000h?1fefffh sa70 111111111 4 1ff000h?1fffffh table 3. am29pds322dt top boot sector addresses (continued) bank sector sector address a20?a12 sector size (kwords) (x16) address range sector address a20?a12 sector size (x16) address range 111111xxx 32 1f8000h?1ffffh table 5. am29pds322db bottom boot sector addresses bank sector sector address a20?a12 sector size (kwords) (x16) address range bank 1 sa0 000000000 4 000000h?000fffh sa1 000000001 4 001000h?001fffh sa2 000000010 4 002000h?002fffh sa3 000000011 4 003000h?003fffh sa4 000000100 4 004000h?004fffh sa5 000000101 4 005000h?005fffh sa6 000000110 4 006000h?006fffh sa7 000000111 4 007000h?007fffh sa8 000001xxx 32 008000h?00ffffh sa9 000010xxx 32 010000h?017fffh sa10 000011xxx 32 018000h?01ffffh sa11 000100xxx 32 020000h?027fffh sa12 000101xxx 32 028000h?02ffffh sa13 000110xxx 32 030000h?037fffh sa14 000111xxx 32 038000h?03ffffh
december 4, 2006 23569a5 am29pds322d 13 data sheet bank 2 sa15 001000xxx 32 040000h?047fffh sa16 001001xxx 32 048000h?04ffffh sa17 001010xxx 32 050000h?057fffh sa18 001011xxx 32 058000h?05ffffh sa19 001100xxx 32 060000h?067fffh sa20 001101xxx 32 068000h?06ffffh sa21 001110xxx 32 070000h?077fffh sa22 001111xxx 32 078000h?07ffffh sa23 010000xxx 32 080000h?087fffh sa24 010001xxx 32 088000h?08ffffh sa25 010010xxx 32 090000h?097fffh sa26 010011xxx 32 098000h?09ffffh sa27 010100xxx 32 0a0000h?0a7fffh sa28 010101xxx 32 0a8000h?0affffh sa29 010110xxx 32 0b0000h?0b7fffh sa30 010111xxx 32 0b8000h?0bffffh sa31 011000xxx 32 0c0000h?0c7fffh sa32 011001xxx 32 0c8000h?0cffffh sa33 011010xxx 32 0d0000h?0d7fffh sa34 011011xxx 32 0d8000h?0dffffh sa35 011100xxx 32 0e0000h?0e7fffh sa36 011101xxx 32 0e8000h?0effffh sa37 011110xxx 32 0f0000h?0f7fffh sa38 011111xxx 32 0f8000h?0fffffh sa39 100000xxx 32 100000h?107fffh sa40 100001xxx 32 108000h?10ffffh sa41 100010xxx 32 110000h?117fffh sa42 100011xxx 32 118000h?11ffffh sa43 100100xxx 32 120000h?127fffh sa44 100101xxx 32 128000h?12ffffh sa45 100110xxx 32 130000h?137fffh sa46 100111xxx 32 138000h?13ffffh sa47 101000xxx 32 140000h?147fffh sa48 101001xxx 32 148000h?14ffffh sa49 101010xxx 32 150000h?157fffh sa50 101011xxx 32 158000h?15ffffh sa51 101100xxx 32 160000h?167fffh sa52 101101xxx 32 168000h?16ffffh sa53 101110xxx 32 170000h?177fffh sa54 101111xxx 32 178000h?17ffffh sa55 111000xxx 32 180000h?187fffh sa56 110001xxx 32 188000h?18ffffh sa57 110010xxx 32 190000h?197fffh sa58 110011xxx 32 198000h?19ffffh sa59 110100xxx 32 1a0000h?1a7fffh sa60 110101xxx 32 1a8000h?1affffh sa61 110110xxx 32 1b0000h?1b7fffh sa62 110111xxx 32 1b8000h?1bffffh table 5. am29pds322db bottom boot sector addresses (continued) bank sector sector address a20?a12 sector size (kwords) (x16) address range
14 am29pds322d 23569a5 december 4, 2006 data sheet table 6. am29pds322db bottom boot secsi sector address . bank 2 sa63 111000xxx 32 1c0000h?1c7fffh sa64 111001xxx 32 1c8000h?1cffffh sa65 111010xxx 32 1d0000h?1d7fffh sa66 111011xxx 32 1d8000h?1dffffh sa67 111100xxx 32 1e0000h?1e7fffh sa68 111101xxx 32 1e8000h?1effffh sa69 111110xxx 32 1f0000h?1f7fffh sa70 111111xxx 32 1f8000h?1fffffh sector address a20?a12 sector size (x16) address range 000000xxx 32 00000h-07fffh table 5. am29pds322db bottom boot sector addresses (continued) bank sector sector address a20?a12 sector size (kwords) (x16) address range
december 4, 2006 23569a5 am29pds322d 15 data sheet autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq15?dq0. this mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-syste m through the command register. when using programming equipment, the autoselect mode requires v id (8.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in table 7. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see tables 3 through 6). table 7 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15?dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 10. this method does not require v id . refer to the autoselect com- mand sequence section for more information. table 7. autoselect codes (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. description ce# oe# we# a20 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq0 manufacturer id : amd llh x xv id xlxxxll 0001h device id word 1 l l h x x v id xlxlllh 227eh device id word 2 l l h x x v id x l xhhhl 2206h device id word 3: top or bottom boot llh x xv id x l xhhhh 2201h (top boot), 2200h (bottom boot) sector protection verification llhsaxv id xlxxxhl xx01h (protected), xx00h (unprotected) secsi indicator bit (dq7), wp# protects highest address sector llh x xv id xlxxxhh 80h (factory locked), 00h (not factory locked)
16 am29pds322d 23569a5 december 4, 2006 data sheet sector/sector bl ock protection and unprotection (note: for the following discussion, the term ?sector? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see tables 8 and 9). table 8. top boot sector/sector block addresses for protection/unprotection table 9. bottom boot sector/sector block addresses for protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hard- ware sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector protection and unprotection can be im- plemented via two methods. the primary method requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 3 shows the algo- rithms and figure 26 shows the timing diagram. this method uses standard microprocessor bus cycle tim- ing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. sector group sectors a20?a12 sector/ sector block size sga0 sa0 000000xxx 64 (1x64) kbytes sga1 sa1?sa3 00001xxxx 192 (3x64) kbytes sga2 sa4?sa7 0001xxxxx 256 (4x64) kbytes sga3 sa8?sa11 0010xxxxx 256 (4x64) kbytes sga4 sa12?sa15 0011xxxxx 256 (4x64) kbytes sga5 sa16?sa19 0100xxxxx 256 (4x64) kbytes sga6 sa20?sa23 0101xxxxx 256 (4x64) kbytes sga7 sa24?sa27 0110xxxxx 256 (4x64) kbytes sga8 sa28?sa31 0111xxxxx 256 (4x64) kbytes sga9 sa32?sa35 1000xxxxx 256 (4x64) kbytes sga10 sa36?sa39 1001xxxxx 256 (4x64) kbytes sga11 sa40?sa43 1010xxxxx 256 (4x64) kbytes sga12 sa44?sa47 1011xxxxx 256 (4x64) kbytes sga13 sa48?sa51 1100xxxxx 256 (4x64) kbytes sga14 sa52?sa55 1101xxxxx 256 (4x64) kbytes sga15 sa56?sa59 1110xxxxx 256 (4x64) kbytes sga16 sa60?sa62 111100xxx 192 (3x64) kbytes sga17 sa63 111111000 8 kbytes sga18 sa64 111111001 8 kbytes sga19 sa65 111111010 8 kbytes sga20 sa66 111111011 8 kbytes sga21 sa67 111111100 8 kbytes sga22 sa68 111111101 8 kbytes sga23 sa69 111111110 8 kbytes sga24 sa70 111111111 8 kbytes sector group sectors a20?a12 sector/sector block size sga0 sa70 111111xxx 64 (1x64) kbytes sga1 sa69?sa67 11110xxxx 192 (3x64) kbytes sga2 sa66?sa63 1110xxxxx 256 (4x64) kbytes sga3 sa62?sa59 1101xxxxx 256 (4x64) kbytes sga4 sa58?sa55 1100xxxxx 256 (4x64) kbytes sga5 sa54?sa51 1011xxxxx 256 (4x64) kbytes sga6 sa50?sa47 1010xxxxx 256 (4x64) kbytes sga7 sa46?sa43 1001xxxxx 256 (4x64) kbytes sga8 sa42?sa39 1000xxxxx 256 (4x64) kbytes sga9 sa38?sa35 0111xxxxx 256 (4x64) kbytes sga10 sa34?sa31 0110xxxxx 256 (4x64) kbytes sga11 sa30?sa27 0101xxxxx 256 (4x64) kbytes sga12 sa26?sa23 0100xxxxx 256 (4x64) kbytes sga13 sa22?sa19 0011xxxxx 256 (4x64) kbytes sga14 sa18?sa15 0010xxxxx 256 (4x64) kbytes sga15 sa14?sa11 0001xxxxx 256 (4x64) kbytes sga16 sa10?sa8 000011xxx 192 (3x64) kbytes sga17 sa7 000000111 8 kbytes sga18 sa6 000000110 8 kbytes sga19 sa5 000000101 8 kbytes sga20 sa4 000000100 8 kbytes sga21 sa3 000000011 8 kbytes sga22 sa2 000000010 8 kbytes sga23 sa1 000000001 8 kbytes sga24 sa0 000000000 8 kbytes
december 4, 2006 23569a5 am29pds322d 17 data sheet the alternate method intended only for programming equipment requires v id on address pin a9 and oe#. this method is compatible with programmer routines written for earlier amd flash devices. contact an amd representative for further details. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is pro- tected or unprotected. see the autoselect mode section for details. write protect (wp#) the write protect function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp#/acc pin. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in the two ?outermost? 8 kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in ?sector/sector block protection and unprotection?. the two outermost 8 kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether the two outermost 8 kbyte boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in ?sec- tor/sector block protection and unprotection?. note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. temporary sector/sector block unprotect (note: for the following discussion, the term ?sector? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see tables 8 and 9). this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the re- set# pin to v id (9.0 v ? 11.0 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously pro- tected sectors are protected again. figure 1 shows the algorithm, and figure 25 shows the timing diagrams, for this feature. figure 1. temporary sector unprotect operation start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected (if wp#/acc = v il , outermost boot sectors will remain protected). 2. all previously protected sectors are protected once again.
18 am29pds322d 23569a5 december 4, 2006 data sheet start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sector groups unprotected (if wp# = v il , the first or last sector will remain protected). 2. all previously protected sector groups are protected once again. figure 2. temporary sector group unprotect operation
december 4, 2006 23569a5 am29pds322d 19 data sheet figure 3. in-system sector group protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
20 am29pds322d 23569a5 december 4, 2006 data sheet secsi (secured sili con) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 64 kbytes in length, and uses a secsi sector indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the secu- rity of the esn once the product is shipped to the field. amd offers the device with the secsi sector either factory locked or customer lockable. the fac- tory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bit permanently set to a ?1.? the cus- tomer-lockable version is shipped with the secsi sec- tor unprotected, allowing customers to utilize that sector in any manner they choose. the customer-lock- able version also has the secsi sector indicator bit permanently set to a ?0.? thus, the secsi sector indi- cator bit prevents customer-lockable devices from being used to replace devices that are factory locked. the system accesses the secsi sector through a command sequence (see ?enter secsi sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the ad- dresses normally occupied by the first sector (sa0). this mode of operation continues until the system is- sues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors instead of the secsi sector factory locked: secsi sector programmed and protected at the factory in a factory locked device, the secsi sector is pro- tected when the device is shipped from the factory. the secsi sector cannot be modified in any way. the device is available preprogrammed with one of the following: a random, secure esn only customer code through th e expressflash service both a random, secure esn and customer code through the expressflash service. in devices that have an esn, a bottom boot device will have the 16-byte esn in the lowest addressable mem- ory area at addresses 000000h?000007h. in the top boot device the starting address of the esn will be at the bottom of the lowest 8 kbyte boot sector at ad- dresses 1f8000h?1f8007h. customers may opt to have their code programmed by amd through the amd expressflash service. amd programs the customer?s code, with or without the ran- dom esn. the devices are then shipped from amd?s factory with the permanently locked. contact an amd representative for details on using amd?s express- flash service. customer lockable: secsi sector not programmed or protected at the factory if the security feature is not required, the secsi sector can be treated as an additional flash memory space, expanding the size of the available flash array by 64 kbytes. the secsi sector can be read, programmed, and erased as often as required. the secsi sector area can be protected using one of the following procedures: write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 3, ex- cept that reset# may be at either v ih or v id . this allows in-system protection of the secsi sector without raising any device pin to a high voltage. note that this method is on ly applicable to the secsi sector. write the three-cycle enter secsi sector region command sequence, and then use the alternate method of sector protection described in the ?sec- tor/sector block protection and unprotection? sec- tion. once the secsi sector is locked and verified, the sys- tem must write the exit secsi sector region command sequence to return to reading and writing the remainder of the array. the secsi sector protection must be used with cau- tion since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 10 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent
december 4, 2006 23569a5 am29pds322d 21 data sheet writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 10 defines the valid register command sequences. writing incorrect address and data val- ues or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens la ter. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. after completing a pro- gramming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section fo r more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. see the next section, reset co mmand, for more informa- tion. see also requirements for reading array data in the device bus operations section for more information. the read-only operations table provides the read pa- rameters, and figure 15 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a pr ogram command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an aut oselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the de- vice entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. table 10 shows the address and data requirements. this method is an alternative to that shown in table 7, which is intended for prom programmers and re- quires v id on address pin a9. the autoselect com- mand sequence may be written to an address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the de- vice is actively programming or erasing. the autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode,
22 am29pds322d 23569a5 december 4, 2006 data sheet and the system may read any number of autoselect codes without reinitiating the command sequence. table 10 shows the address and data requirements for the command sequence. to determine sector protec- tion information, the system must write to the appropri- ate sector group address (sga). tables 3 and 5 show the address range associated with each sector. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in erase suspend). enter secsi sector/e xit secsi sector command sequence the secsi sector region provides a secured data area containing an 16-byte random electronic serial num- ber (esn). the system can access the secsi sector region by issuing the thr ee-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector command sequence returns the de- vice to normal operation. table 10 shows the address and data requirements for both command sequences. see also ?secsi (secured silicon) sector flash mem- ory region? for further information. note that a hard- ware reset (reset#=v il ) will reset the device to reading array data. word program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 10 shows the address and data requirements for the program command se- quence. when the embedded program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7, dq6, or ry/by#. refe r to the write operation status section for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. the unlock bypass command sequence is initiated by first writing two un- lock cycles. this is followed by a third write cycle con- taining the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle un- lock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program com- mand, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. table 10 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h. the second cycle must contain the data 00h. the device then returns to reading array data. see figure 4 for the unlock bypass algorithm. the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh any operation other than accelerated programming, or device dam- age may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. figure 5 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 18 for timing diagrams. chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock
december 4, 2006 23569a5 am29pds322d 23 data sheet cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 10 shows the address and data requirements for the chip erase command sequence. start 555h/aah 2aah/55h xxxh/a0h 555h/20h verify byte? no program address/program data data# polling device last address ? programming completed (ba) xxxh/90h xxxh/f0h increment address no yes yes set unlock bypass mode in unlock bypass program reset unlock bypass mode figure 4. unlock bypass algorithm start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 10 for program command sequence. figure 5. program operation
24 am29pds322d 23569a5 december 4, 2006 data sheet when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write operation status section for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that oc- curs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 6 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characterist ics section for parameters, and figure 20 section for timing diagrams. sector erase co mmand sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 10 shows the ad- dress and data requirements for the sector erase com- mand sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. the system must re- write the command sequence and any additional ad- dresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing sector. the system can de- termine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing sector. refer to the write operation status section for infor- mation on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 6 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 20 section for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sec- tor erase operation, including the 50 s time-out pe- riod during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a max- imum of 20 s to suspend the erase operation. how- ever, when the erase suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) note that un- lock bypass programming is not allowed when the device is erase-suspended. reading at any address within erase-suspended sec- tors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. after an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read
december 4, 2006 23569a5 am29pds322d 25 data sheet mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspended sector is required when writ- ing this command. further writes of the resume com- mand are ignored. another erase suspend command can be written after the chip has resumed erasing. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 10 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer. figure 6. erase operation
26 am29pds322d 23569a5 december 4, 2006 data sheet table 10. am29pds322d command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sga = address of the sector group to be verified (in autoselect mode) or erased. address bits a20?a12 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth and fifth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a20?a12 are don?t cares in unlock sequence. 6. no unlock or command cycles required when device is in read mode. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 goes high (while the device is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address to obtain the manufacturer id, device id, or secsi sector factory protect information. data bits dq15?dq8 are don?t care. see the autoselect command sequence section for more information. 9. the device id must be read across the fourth, fifth and sixth cycles. the sixth cycle specifies 2201h for top boot or 2200h for bottom boot. 10. the data is 80h for factory locked and 00h for not factory locked. 11. the data is 00h for an unprotected sector group and 01h for a protected sector group. 12. the unlock bypass command is required prior to the unlock bypass program command. 13. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id (note 9) 6 555 aa 2aa 55 555 90 x01 227e x0e 2206 x0f 2201/ 2200 secsi sector factory protect (note 10) 4 555 aa 2aa 55 555 90 x03 80/00 sector group protect verify (note 11) 4 555 aa 2aa 55 555 90 (sga) x02 xx00/ xx01 enter secsi sector region 3 555 aa 2aa 55 555 88 exit secsi sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 12) 2 xxx a0 pa pd unlock bypass reset (note 13) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 14) 1 ba b0 erase resume (note 15) 1 ba 30
december 4, 2006 23569a5 am29pds322d 27 data sheet write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 11 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is com- plete or in progress. the device also provides a hard- ware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is ac- tive for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on suc- cessive read cycles. table 11 shows the outputs for data# polling on dq7. figure 7 shows the data# po lling algorithm. figure 22 in the ac characteristics section shows the data# polling timing diagram. figure 7. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being eras ed. during chip erase, a valid address is any non- protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
28 am29pds322d 23569a5 december 4, 2006 data sheet ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or the device is in the erase-suspend-read mode. table 11 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read c ycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approxi- mately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the de- vice enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alterna- tively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 11 shows the outputs for toggle bit i on dq6. figure 8 shows the toggle bit algorithm. figure 23 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 24 shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. figure 8. toggle bit algorithm start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
december 4, 2006 23569a5 am29pds322d 29 data sheet dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to con- trol the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 11 to compare out- puts for dq2 and dq6. figure 8 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the dq 6: toggle bit i subsection. figure 23 shows the toggle bit timing diagram. figure 24 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 8 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is th at the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 8). dq5: exceeded ti ming limits dq5 indicates whether the program or erase time has exceeded a specified internal pul se count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions , the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previ- ously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to det ermine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between addi- tional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 11 shows the status of dq3 relative to the other status bits.
30 am29pds322d 23569a5 december 4, 2006 data sheet table 11. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedde d erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status inform ation. refer to the appropriate subsection for further details. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
december 4, 2006 23569a5 am29pds322d 31 data sheet absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v a9 , oe# , and reset# (note 2) . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +11 v wp#/acc . . . . . . . . . . . . . . . . . . ?0.5 v to +12.6 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 100 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 9. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 10. 2. minimum dc input voltage on pins a9, oe#, reset#, and wp#/acc is ?0.5 v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 9. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +12.6 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functi onal operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 9. maximum negative overshoot waveform figure 10. maximum positive overshoot waveform operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c v cc supply voltages v cc for standard voltage range . . . . . . . 1.8 v to 2.2 v operating ranges define those li mits between which the func- tionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
32 am29pds322d 23569a5 december 4, 2006 data sheet dc characteristics cmos compatible notes: 1. the i cc current listed is ty pically less than 2 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for 150 ns. 5. embedded algorithm (program or erase) is in progress (at 8 mhz). parameter symbol parameter description te st conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9, oe#, reset# = 11 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active inter-page read current (notes 1, 2) ce# = v il , oe# = v ih , 1 mhz 2.5 3 ma 10 mhz 24 28 i cc2 v cc active write current (notes 2, 3) ce# = v il, oe# = v ih 15 30 ma i cc3 v cc standby current (note 2) ce#, reset# = v cc 0.3 v 0.2 5 a i cc4 v cc reset current (note 2) wp#/acc = v cc 0.3 v, reset# = v ss 0.3 v 0.1 5 a i cc5 v cc automatic sleep mode current (notes 2, 4) ce# = v ss 0.3 v; reset# = v cc 0.3 v, v in = v cc 0.3 v or v ss 0.3 v 0.2 5 a i cc6 v cc active read-while-program current (notes 1, 2, 5) ce# = v il , oe# = v ih 30 55 ma i cc7 v cc active read-while-erase current (notes 1, 2, 5) ce# = v il , oe# = v ih 30 55 ma i cc8 v cc active program-while-erase-suspended current (note 2) ce# = v il , oe# = v ih 17 35 ma i cc9 v cc active intra-page read current ce# = v il , oe# = v ih 10 mhz 0.5 1 ma 20 mhz 1 2 i acc wp#/acc accelerated program current v cc = v ccmax , wp#/acc = v accmax 12 20 ma v il input low voltage ?0.5 v cc x 0.2 v v ih input high voltage 0.8 x v cc v cc + 0.3 v v acc voltage for wp#/acc sector protect/unprotect and program acceleration v cc = 1.8?2.2 v 8.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 1.8?2.2 v 9 11 v v ol output low voltage i ol = 100 a, v cc = v cc min 0.1 v v oh output high voltage i oh = ?100 a v cc ? 0.1 v v lko low v cc lock-out voltage 1.2 1.5 v
december 4, 2006 23569a5 am29pds322d 33 data sheet dc characteristics zero-power flash note: addresses are switching at 1 mhz figure 11. i cc1 current vs. time (showing active and automatic sleep currents) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 15 12 3 0 13578 frequency in mhz supply current in ma note: t = 25 c figure 12. typical i cc1 vs. frequency 2.0 v 6 9 18 246
34 am29pds322d 23569a5 december 4, 2006 data sheet test conditions table 12. test specifications key to switching waveforms c l device under te s t note: diodes are in3064 or equivalent figure 13. test setup test condition 10 12 unit output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0?2.0 v v input timing measurement reference levels 1.0 v output timing measurement reference levels 1.0 v ks000010-pal waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v cc 0.0 v 1.0 v output measurement level input 0.5 v cc figure 14. input waveforms and measurement levels
december 4, 2006 23569a5 am29pds322d 35 data sheet ac characteristics read-only operations notes: 1. not 100% tested. 2. see figure 13 and table 12 for test specifications. 3. measurements performed by placing a 50 termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . parameter description test setup speed option jedec std 10 12 unit t avav t rc read cycle time (note 1) min 100 120 ns t avqv t acc address to output delay ce#, oe# = v il max 100 120 ns t prc page read cycle min 40 50 ns t pac c page address to output delay ce#, oe# = v il max 40 50 ns t elqv t ce chip enable to ou tput delay oe# = v il max 100 120 ns t glqv t oe output enable to output delay max 35 50 ns t ehqz t df chip enable to output high z (notes 1, 3) max 16 ns t ghqz t df output enable to output high z (notes 1, 3) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df figure 15. conventional read operation timings
36 am29pds322d 23569a5 december 4, 2006 data sheet ac characteristics figure 16. page mode read timings same page addresses we# oe# ce# a20 to a2 a1 to a0 output aa ab ac ad high-z da db dc dd t rc t ce t oe t acc t prc t prc t prc t pacc t pacc t pacc t oh t oh t oh t oh t df t oeh
december 4, 2006 23569a5 am29pds322d 37 data sheet ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 200 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb figure 17. reset timings
38 am29pds322d 23569a5 december 4, 2006 data sheet ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter speed option jedec std description 10 12 unit t avav t wc write cycle time (note 1) min 100 120 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 60 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 60 ns t whdx t dh data hold time min 0 ns t ceph chip enable high during toggle bit polling min 20 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 60 ns t whdl t wph write pulse width high min 60 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) typ 11 s t whwh1 t whwh1 accelerated programming operation (note 2) typ 5 s t whwh2 t whwh2 sector erase operation (note 2) typ 1 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns
december 4, 2006 23569a5 am29pds322d 39 data sheet ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n ote: pa = program address, pd = program data, d out is the true data at the program address. figure 18. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 19. accelerated program timing diagram
40 am29pds322d 23569a5 december 4, 2006 data sheet ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?). figure 20. chip/sector erase operation timings
december 4, 2006 23569a5 am29pds322d 41 data sheet ac characteristics figure 21. back-to-back read/write cycle timings oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle af ter command sequence, last stat us read cycle, and array data read cycle. figure 22. data# polling timings (during embedded algorithms)
42 am29pds322d 23569a5 december 4, 2006 data sheet ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# note: va = valid address; not requir ed for dq6. illust ration shows first two status cycle af ter command sequence, last status read cycle, and array data read cycle figure 23. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase- suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 24. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
december 4, 2006 23569a5 am29pds322d 43 data sheet ac characteristics temporary sector unprotect note: not 100% tested. parameter description all speed options unit jedec std t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector/sector block unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector/sector block unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb figure 25. temporary sector group unprotect timing diagram
44 am29pds322d 23569a5 december 4, 2006 data sheet ac characteristics sector/sector block protect: 150 s, sector/sector block unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector/sector block protect or unprotect verify v id v ih * for sector group protect, a6 = 0, a1 = 1, a0 = 0. for sector group unprotect, a6 = 1, a1 = 1, a0 = 0. figure 26. sector group protect and unprotect timing diagram
december 4, 2006 23569a5 am29pds322d 45 data sheet ac characteristics alternate ce# cont rolled erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter speed option jedec std description 10 12 unit t avav t wc write cycle time (note 1) min 100 120 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 60 ns t dveh t ds data setup time min 60 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 60 ns t ehel t cph ce# pulse width high min 60 ns t whwh1 t whwh1 programming operation (note 2) typ 16 s t whwh1 t whwh1 accelerated programming operation (note 2) typ 5 5 s t whwh2 t whwh2 sector erase operation (note 2) typ 1 sec
46 am29pds322d 23569a5 december 4, 2006 data sheet ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 27. alternate ce# controlled write (erase/program) operation timings
december 4, 2006 23569a5 am29pds322d 47 data sheet erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 2.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90 c, v cc = 1.8 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maxi mum program times listed. 4. in the pre-programming step of the embedded erase al gorithm, all bits are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the tw o- or four-bus-cycle sequence for the program command. see table 10 for further information on command definitions. 6. the device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 1.8 v, one pin at a time. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 1 10 sec excludes 00h programming prior to erasure (note 4) chip erase time 93 sec word program time 16 360 s excludes system level overhead (note 5) accelerated word program time 5 s chip program time (note 3) 20 100 sec description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter description t est conditions min unit minimum pattern data retention time 150 c10years 125 c20years
48 am29pds322d 23569a5 december 4, 2006 data sheet physical dimensions fbd048?48-ball fine-pitch ball gr id array (fbga) 6 x 12 mm package * for reference only. bsc is an ansi standard for basic space centering. dwg rev af; 1/2000 xfbd 048 6.00 mm x 12.00 mm package 1.20 0.20 0.84 0.94 12.00 bsc 6.00 bsc 5.60 bsc 4.00 bsc 8 6 48 0.25 0.30 0.35 0.80 bsc 0.40 bsc
december 4, 2006 23569a5 am29pds322d 49 data sheet revision summary revision a (december 4, 2000) initial release. revision a+1 ( february 16, 2001) ordering information added ?u? designator to package marking. deleted burn-in option. revision a+2 (a ugust 31, 2001) autoselect command sequence modified section to point to appropriate tables for au- toselect functions. revision a+3 ( february 18, 2002) global removed ?advance information? designation from data sheet. erase suspend/erase resume commands noted in the third paragraph that unlock bypass pro- gramming is not allowed when the device is erase sus- pended. revision a+4 (august 7, 2002) distinctive characteristics removed ?supports common flash memory interface (cfi)) table 10. am29pds322d command definitions changed the command cycle device id cycle from 6 to 4. revision a5 (december 4, 2006) global removed advance information designation from docu- ment (inadvertently restored in revision a+4). ac characteristics erase and program operations table: changed t busy to a maximum specification. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita- tion, ordinary industrial use, general o ffice use, personal use, and household use, but are not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers th at, unless extremely high safety is secured, could have a seri ous effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolera ble (i.e., submersible repeater and artifici al satellite). please note that spansion inc. will not be liable to you and/or any third party for any claims or damages arisi ng in connection with above-mentioned uses of the products. any se miconductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and pr evention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on expor t under the foreign exchange and foreign trade law of japan, the us export administra tion regulations or the applicable laws of any other country, the prior au- thorization by the respective government entit y will be required for export of those products. trademarks copyright ? 2000?2005 advanced micro devices, inc. all rights reserv ed. amd, the amd logo, and combinations thereof are registe red trade- marks of advanced micro devices, inc. expressflash is a trademar k of advanced micro devices, inc. product names used in this pu blication are for identification purposes only and may be tr ademarks of their respective companies. copyright ? 2006 spansion inc. all rights reserved. spansion, t he spansion logo, mirrorbit, orna nd, hd-sim, and combinations th ereof are trademarks of spansion inc. other names are for informational purposes only and may be trademarks of their respective owners.

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