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ltc3589/ltc3589-1/ ltc3589-2 1 3589fe typical application features description applications the ltc ? 3589 is a complete power management solu- tion for arm and arm-based processors and advanced portable microprocessor systems. the device contains three step-down dc/dc converters for core, memory and soc rails, a buck-boost regulator for i/o at 1.8v to 5v and three 250ma ldo regulators for low noise analog sup- plies. an i 2 c serial port is used to control enables, output voltage levels, dynamic voltage scaling, operating modes and status reporting. differences between the ltc3589, ltc3589-1, and ltc3589-2 are summarized in table 1. regulator start-up is sequenced by connecting outputs to enable pins in the desired order or programmed via the i 2 c port. system power-on, power-off, and reset functions are controlled by pushbutton interface, pin inputs, or i 2 c interface. the ltc3589 supports i.mx53/51, pxa and omap pro- cessors with eight independent rails at appropriate power levels. other features include interface signals such as the vstb pin that simultaneously toggle up to four rails between programmed run and standby output voltages. the device is available in a low profile 40-pin 6mm 6mm exposed pad qfn package. start-up sequence n triple i 2 c adjustable high efficiency step-down dc/ dc converters: 1.6a, 1a/1.2a, 1a/1.2a n high efficiency 1.2a buck-boost dc/dc converter n triple 250ma ldo regulators n pushbutton on/off control with system reset n flexible pin-strap sequencing operation n i 2 c and independent enable control pins n power good and reset outputs n dynamic voltage scaling and slew rate control n selectable 2.25mhz or 1.12mhz switching frequency n always-alive 25ma ldo regulator n 8a standby current n 40-pin 6mm 6mm 0.75mm qfn n handheld instruments and scanners n portable industrial devices n automotive infotainment n medical devices n high end consumer devices n multirail systems n supports freescale i.mx53/51, marvell pxa and other application processors l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 8-output regulator with sequencing and i 2 c 500s/div 0.5v/div 3589 ta01b bb_out wake (1v/div) ldo2 sw3 sw1 sw2 ldo3 ldo1_stdby v in 2.7v to 5.5v 1h 1f 1f 1f 1f 1.5h 1.5h 2.7h sw1 sw2 sw3 sw4cd bb_out sw4ab ltc3589 0.8v to v in at 25ma 0.5v to v in at 1.6a 22f 22f 22f 22f 0.5v to v in at 1a 0.5v to v in at 1a 0.36v to v in at 250ma 1.8v at 250ma 2.8v at 250ma 3589 ta01a v in ldo2 ldo3 ldo4 gnd i 2 c enables pwr_on on 3 4 7 status wake 1.8v to 5v
ltc3589/ltc3589-1/ ltc3589-2 2 3589fe table of contents features ...................................................................................................................... ...... 1 applications .................................................................................................................. ..... 1 typical application .......................................................................................................... ..... 1 description.................................................................................................................... ..... 1 absolute maximum ratings ..................................................................................................... 3 pin configuration ............................................................................................................. .... 3 order information ............................................................................................................. .... 3 electrical characteristics .................................................................................................... .... 4 typical performance characteristics .......................................................................................... 9 pin functions ................................................................................................................. ....13 block diagram ................................................................................................................. ...15 operation...................................................................................................................... ....16 introduction .................................................................................................................. ........................................ 16 ltc3589, ltc3589-1, and ltc3589-2 functional comparison ....................................................................... ...... 17 always-on ldo ................................................................................................................. .................................... 17 step-down switching regulators ................................................................................................ ......................... 20 buck-boost switching regulator ................................................................................................ .......................... 24 slewing dac reference operation ............................................................................................... ......................... 28 pushbutton operation .......................................................................................................... ................................. 29 enable and power-on sequencing ................................................................................................ ........................ 31 fault detection, shutdown, and reporting ...................................................................................... ...................... 32 i 2 c operation ................................................................................................................... ..................................... 36 thermal considerations and board layout ....................................................................................... .................... 42 typical application ........................................................................................................... ...46 package description ........................................................................................................... .48 revision history .............................................................................................................. ...49 typical application ........................................................................................................... ...50 related parts ................................................................................................................. ....50
ltc3589/ltc3589-1/ ltc3589-2 3 3589fe absolute maximum ratings (notes 1, 3) order information pin configuration sw1, sw2, sw3, sw4ab, sw4cd (transients < 1ms, duty cycle < 1%) ........... C0.3v to 7v pv in1 , pv in2 , pv in3 , pv in4 ............... C0.3v to v in + 0.3v v in_ldo2 , v in_ldo34 ......................... C0.3v to v in + 0.3v v in , dv dd ..................................................... C0.3v to 6v ldo1_stby, ldo1_fb, buck1_fb, buck2_fb, buck3_fb, bb_fb, bb_out, ldo2, ldo2_fb, ldo3, lead free finish tape and reel part marking* package description temperature range ltc3589euj#pbf ltc3589euj#trpbf ltc3589uj 40-lead (6mm 6mm) plastic qfn C40c to 125c ltc3589iuj#pbf ltc3589iuj#trpbf ltc3589uj 40-lead (6mm 6mm) plastic qfn C40c to 125c ltc3589huj#pbf ltc3589huj#trpbf ltc3589uj 40-lead (6mm 6mm) plastic qfn C40c to 150c ltc3589euj-1#pbf ltc3589euj-1#trpbf ltc3589uj-1 40-lead (6mm 6mm) plastic qfn C40c to 125c ltc3589iuj-1#pbf ltc3589iuj-1#trpbf ltc3589uj-1 40-lead (6mm 6mm) plastic qfn C40c to 125c ltc3589huj-1#pbf ltc3589huj-1#trpbf ltc3589uj-1 40-lead (6mm 6mm) plastic qfn C40c to 150c ltc3589euj-2#pbf ltc3589euj-2#trpbf ltc3589uj-2 40-lead (6mm 6mm) plastic qfn C40c to 125c ltc3589iuj-2#pbf ltc3589iuj-2#trpbf ltc3589uj-2 40-lead (6mm 6mm) plastic qfn C40c to 125c ltc3589huj-2#pbf ltc3589huj-2#trpbf ltc3589uj-2 40-lead (6mm 6mm) plastic qfn C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ldo4, pgood, vstb, en1, en2, en3, en4, en_ldo2, en_ldo34, en_ldo3, on , pbstat, wake, rsto , pwr_on, irq, ............................................ C0.3v to 6v sda, scl ......................................C0.3v to dv dd + 0.3v operating junction temperature range (note 2) .................................................. C40c to 150c storage temperature range .................. C65c to 150c ltc3589 ltc3589-1/ltc3589-2 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 top view 41 gnd uj package 40-lead (6mm 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 v in_ldo2 ldo2 ldo3 ldo4 v in_ld34 pv in1 sw1 rsto en_ldo2 en1 scl pgood vstb pv in3 sw3 sw2 pv in2 wake pbstat on bb_fb buck1_fb ldo2_fb v in ldo1_stby ldo1_fb buck3_fb buck2_fb dv dd sda en2 sw4ab en3 en4 pv in4 bb_out irq en_ldo34 sw4cd pwr_on 21 30 10 1 t jmax = 125c, ja = 33c/w exposed pad (pin 41) is gnd, must be soldered to pcb 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 top view 41 gnd uj package 40-lead (6mm w 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 v in_ldo2 ldo2 ldo3 ldo4 v in_ld34 pv in1 sw1 rsto en_ldo2 en1 scl pgood vstb pv in3 sw3 sw2 pv in2 wake pbstat on bb_fb buck1_fb ldo2_fb v in ldo1_stby ldo1_fb buck3_fb buck2_fb dv dd sda en2 sw4ab en3 en4 pv in4 bb_out irq en_ldo3 sw4cd pwr_on 21 30 10 1 t jmax = 125c, ja = 33c/w exposed pad (pin 41) is gnd, must be soldered to pcb
ltc3589/ltc3589-1/ ltc3589-2 4 3589fe electrical characteristics symbol parameter conditions min typ max units v in operating input supply voltage, v in l 2.7 5.5 v i standby v in standby current all enables = 0v, pwr_on = 0, i ldo1 = 0 l 818a f osc oscillator frequency l 1.8 2.25 2.6 mhz step-down switching regulators 1, 2, and 3 i vin pulse-skipping mode v in quiescent current per buck burst mode ? v in quiescent current per buck v fb = 0.85v (note 5) l l 120 23 200 40 a a i fb feedback pin input current v fb = 0.8v C50 50 na d x maximum duty cycle v fb = 0v 100 % r sw sw pull-down resistance regulators disabled 2.5 k t ss soft-start rate (note 6) 0.8 v/ms v fb(max) maximum feedback voltage bxdt v1 = bxdt v2 = 11111, v in = 2.7v to 5.5v l 0.735 0.75 0.765 v v fb(lsb) feedback lsb step size 12.5 mv v fb(min) minimum feedback voltage bxdtv1 = bxdtv2 = 00000, v in = 2.7v to 5.5v l 0.351 0.3625 0.374 v 1.6a step-down switching regulator 1 i lim1 peak pmos current limit sw1 l 2.0 2.7 a rp1 r ds(on) of pmos1 i sw1 = 100ma 180 m rn1 r ds(on) of nmos1 i sw1 = 100ma 110 m 1.0a/1.2a step-down switching regulators 2 and 3 i lim2, 3 peak pmos current limit sw2 and sw3 (ltc3589) peak pmos current limit sw2 and sw3 (ltc3589-1/ ltc3589-2) l l 1.5 1.8 1.9 2.3 a a rp2, 3 r ds(on) of pmos2 and pmos3 250 m rn2, 3 r ds(on) of nmos2 and nmos3 130 m 1.2a buck-boost switching regulator 4 (buck-boost) i vin pwm mode v in quiescent current burst mode v in quiescent current v bb_fb = 0.85v (note 5) l l 115 19 170 35 a a v bb_fb feedback voltage v in = 2.7v to 5.5v, v out = 5.5v l 0.776 0.8 0.824 v v outbb output voltage range 1.8 5.0 v i lim4 peak pmos current limit sw4ab l 2.3 2.9 a i peak4 forward burst current limit (switch a) burst mode operation 600 ma i limr4 reverse current limit (switch d) 1a i zero4 reverse burst current limit (switch d) burst mode operation 0 ma rp4 r ds(on) of switch a and switch d i sw4ab = i sw4cd = 100ma 160 m rn4 r ds(on) of switch b and switch c i sw4ab = i sw4cd = C100ma 110 m r out4 bb_out pull-down resistance regulator disabled 2.5 k t ss soft-start rate (note 6) 2 v/ms i fb feedback pin input current v fb = 0.85v C50 50 na the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = pv in1 = pv in2 = pv in3 = pv in4 = v in_ldo2 = v in_ldo34 = dv dd = 3.8v. all regulators disabled unless otherwise noted.
ltc3589/ltc3589-1/ ltc3589-2 5 3589fe symbol parameter conditions min typ max units ldo regulators t ldo_ss soft-start time ldo2, ldo3, ldo4 100 s r ldo_pd output pull-down resistance ldo2, ldo3, ldo4 ldo disabled 2.5 k always-on regulator (ldo1_stdby) v ldo1_fb ldo1 feedback voltage l 0.76 0.8 0.84 v v ldo1 ldo1 line regulation i ldo1_stby = 1ma, ldo1_stby = 1.2v, v in = 2.7v to 5.5v 0.15 %/v ldo1 load regulation i ldo1 = 0.1ma to 25ma, ldo1_stby = 1.2v 0.1 % i ldo1 available output current l 25 ma i ldo1_sc short-circuit output current limit 65 100 ma v drop1 dropout voltage (note 4) i ldo1 = 25ma, ldo1_stby = 3.3v 200 mv i ldo1_fb ldo1_fb input current v ldo1_fb = 0.85v C50 50 na ldo regulator 2 (ldo2) v in_ldo2 v in_ldo2 input voltage range l 1.7 v in v i vin_ldo2 v in_ldo2 quiescent current v in_ldo2 shutdown current regulator enabled regulator disabled l l 12 0 20 1 a a i vin v in quiescent current en_ldo2 = high l 50 85 a v fb2(max) ldo2 maximum feedback voltage l2dt v1 = l2dt v2 = 11111 l 0.735 0.75 0.765 v v fb2(lsb) ldo2 feedback lsb step size 12.5 mv v fb2(min) ldo2 minimum feedback voltage l2dtv1 = l2dtv2 = 00000 v in_ldo2 = v in = 2.7v to 5.5v, i ldo2 = 1ma l 0.351 0.3625 0.374 v ldo2 line regulation i ldo2 =1ma, v inldo2 = 2.7v to 5.5v 0.01 %/v ldo2 load regulation i ldo2 = 1ma to 250ma 0.01 % i out2 ldo2 available output current l 250 ma i sc2 ldo2 short-circuit current limit 300 450 600 ma v drop2 dropout voltage (note 4) i ldo2 = 200ma, v ldo2 = 2.5v i ldo2 = 200ma, v ldo2 = 1.2v 140 350 180 500 mv mv i ldo2_fb ldo2_fb input current v ldo2_fb = 0.8v C50 50 na ldo regulator 3 (ldo3) v in_ldo34 v in_ldo34 input range (ltc3589) v in_ldo34 input range (ltc3589-1/ltc3589-2) l l 2.35 3.0 v in v in v v i vin_ldo34 v in_ldo34 quiescent current v in_ldo34 shutdown current regulator enabled regulator disabled l l 15 0 29 1 a a i vin v in quiescent current l 50 85 a v ldo3 ldo3 output voltage (ltc3589) ldo3 output voltage (ltc3589-1/ltc3589-2) v in_ldo34 = v in = 2.7v to 5v, i ldo3 = 1ma l l 1.746 2.716 1.8 2.8 1.854 2.884 v v ld03 line regulation i ldo3 =1ma, v inldo34 = 2.7v to 5.5v 0.01 %/v ldo3 load regulation i ldo3 = 1ma to 250ma 0.05 % i ldo3 ldo3 available output current l 250 ma i ldo3_sc ldo3 short-circuit current limit 300 450 600 ma v drop3 ldo3 dropout voltage (ltc3589) (note 4) ldo3 dropout voltage (ltc3589-1/ltc3589-2) (note 4) i ldo3 = 200ma, v ldo3 = 1.8v i ldo3 = 200ma, v ldo3 = 2.8v 190 140 250 180 mv mv electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = pv in1 = pv in2 = pv in3 = pv in4 = v in_ldo2 = v in_ldo34 = dv dd = 3.8v. all regulators disabled unless otherwise noted.
ltc3589/ltc3589-1/ ltc3589-2 6 3589fe symbol parameter conditions min typ max units ldo regulator 4 (ldo4) v in_ldo34 v in_ldo34 input range (ltc3589) v in_ldo34 input range (ltc3589-1/ltc3589-2) l l 2.35 1.7 v in v in v v i vin_ldo34 v in_ldo34 quiescent current v in_ldo34 shutdown current regulator enabled regulator disabled l l 14 0 24 1 a a i vin enabled v in quiescent current l 50 85 a v ldo4 (ltc3589) ldo 4 output voltage i ldo4 = 1ma, l2dtv2[6:5] = 00 l2dtv2[6:5] = 01 l2dtv2[6:5] = 10 l2dtv2[6:5] = 11 l l l l 2.716 2.425 1.746 3.201 2.8 2.5 1.8 3.3 2.884 2.575 1.854 3.399 v v v v v ldo4 (ltc3589-1) (ltc3589-2) ldo 4 output voltage i ldo4 = 1ma, l2dtv2[6:5] = 00 l2dtv2[6:5] = 01 l2dtv2[6:5] = 10 l2dtv2[6:5] = 11 l l l l 1.164 1.746 2.425 3.104 1.2 1.8 2.5 3.2 1.236 1.854 2.575 3.296 v v v v ld04 line regulation i ldo4 =1ma, v inldo4 = 2.7v to 5.5v, v out = 1.8v 0.01 %/v ldo4 load regulation i ldo4 = 1ma to 250ma 0.05 % i ldo4 ldo4 available output current l 250 ma i ldo4_sc ldo4 short-circuit current limit 300 450 600 ma v drop4 ldo4 dropout voltage (note 4) i ldo4 = 200ma, v ldo4 = 3.3v i ldo4 = 200ma, v ldo4 = 1.8v i ldo4 = 200ma, v ldo4 = 3.2v (ltc3589-1/ ltc3589-2) 120 190 120 160 250 160 mv mv mv enable inputs v enx_thr threshold rising, all enables low l 0.8 1.2 v v enx_thr2 v enx_thf2 threshold rising, any enable high threshold falling, any enable high l l 0.420 0.5 0.45 0.530 v v r enx input pull-down resistance 4.5 m vstb, pwr_on inputs v vstb_thr v vstb_thf vstb pin threshold rising vstb pin threshold falling l l 0.4 0.8 0.7 1.2 v v r vstb pull-down resistance 4.5 m v pwr_onthr v pwr_onthf pwr_on pin threshold rising pwr_on pin threshold falling l l 0.4 0.8 0.7 1.2 v v r pwr_on pull-down resistance 4.5 m i 2 c port dv dd dv dd input supply voltage l 1.6 5.5 v i dvdd dv dd quiescent current scl/sda = 0khz 0.5 a v dvdd_uvlo dv dd uvlo level 0.8 v address device address C write device address C read 01101000 01101001 v ih sda, scl v il sda, scl sda and scl input threshold rising sda and scl input threshold falling 70 30 %dv dd %dv dd i ihscx i ilscx sda and scl input current sda = scl = 0v to 5.5v C250 250 na v ol sda sda output low voltage i sda = 3ma l 0.4 v f scl scl clock operating frequency 400 khz electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = pv in1 = pv in2 = pv in3 = pv in4 = v in_ldo2 = v in_ldo34 = dv dd = 3.8v. all regulators disabled unless otherwise noted.
ltc3589/ltc3589-1/ ltc3589-2 7 3589fe symbol parameter conditions min typ max units t su_sta repeated start condition set-up time 0.6 s t su_sto stop condition set-up time 0.6 s t hd_dat(o) data hold time output 0 900 ns t hd_dat(i) data hold time input 0ns t su_dat data set-up time 100 ns t low scl clock low period 1.3 s t high scl clock high period 0.6 s t f data fall time c b = capacitance of one bus line (pf) 20 + 0.1c b 300 ns t r data rise time c b = capacitance of one bus line (pf) 20 + 0.1c b 300 ns t sp input spike supression pulse width 50 ns pushbutton interface v on _th on threshold rising on threshold falling l l 0.4 0.8 0.7 1.2 v v i on on input current on = v in on = 0v C100 40 100 na a t on _pbstat1 on low time to pbstat low 50 ms t on _pbstat2 on high time to pbstat high 0.2 s t on _wake on low time to wake high 400 ms t on _hr on low time to hard reset 5s t pbstat_pw pbstat minimum pulse width 50 ms t pbstat_bk pbstat blanking from wake low 1 s t wake_off minimum wake low time 1s t wake_on wake high time with pwr_on = 0v 5 s t pwr_on pwr_on to wake high (ltc3589) pwr_on to wake high (ltc3589-1/ltc3589-2) 50 2 ms ms t pwr_off pwr_on to wake low (ltc3589) pwr_on to wake low (ltc3589-1/ltc3589-2) 50 2 ms ms status output pins (pbstat, wake, pgood, rsto , irq ) v pbstat pbstat output low voltage i pbstat = 3ma 0.1 0.4 v i pbstat pbstat output high leakage current v pbstat = 3.8v C0.1 0.1 a v wake wake output low voltage i wake = 3ma 0.1 0.4 v i wake wake output high leakage current v wake = 3.8v C0.1 0.1 a v pgood pgood output low voltage i pgood = 3ma 0.1 0.4 v i pgood pgood output high leakage current v pgood = 3.8v C0.1 0.1 a v pgood pgood threshold rising pgood threshold falling C6 C8 % % v nrsto ldo1 power good threshold rising ldo1 power good threshold falling C6 C8 % % v uvlo undervoltage lockout rising undervoltage lockout falling 2.65 2.55 2.7 v v v uvwarn undervoltage warning rising undervoltage warning falling 3 2.9 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = pv in1 = pv in2 = pv in3 = pv in4 = v in_ldo2 = v in_ldo34 = dv dd = 3.8v. all regulators disabled unless otherwise noted.
ltc3589/ltc3589-1/ ltc3589-2 8 3589fe note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3589 are tested under pulsed load conditions such that t j t a . the ltc3589e are guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3589i are guaranteed over the C40c to 125c operating junction temperature range and the ltc3589h are guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (pd, in watts) according to the formula: t j = t a + (pd ? ja ), where the package junction to ambient thermal impedance ja = 33c/w. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: the ltc3589 include overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating temperature may impair device reliability. note 4: dropout voltage is defined as (v in C v ldo ) for ldo1 or (v in_ldo C v ldo ) for other ldos when v ldo is 3% lower than v ldo measured with v in = v in_ldo = 4.3v. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. note 6: soft-start measured in test mode with regulator error amplifier in unity gain mode. electrical characteristics symbol parameter conditions min typ max units v rsto rsto output low voltage i rsto = 3ma 0.1 0.4 v i rsto rsto output high leakage current v rsto = 3.8v C0.1 0.1 a v irq irq output low voltage i irq = 3ma 0.1 0.4 v i irq irq output high leakage current v irq = 3.8v C0.1 0.1 a the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = pv in1 = pv in2 = pv in3 = pv in4 = v in_ldo2 = v in_ldo34 = dv dd = 3.8v. all regulators disabled unless otherwise noted.
ltc3589/ltc3589-1/ ltc3589-2 9 3589fe typical performance characteristics standby i vin vs v in ldo2 to ldo4 i vin vs v in v in = 3.8v, t a = 25c, unless otherwise noted. step-down switching regulator i vin vs v in input supply current vs temperature buck-boost i vin vs v in step-down switching regulator i vin vs v in v in (v) 2.5 i vin (a) 14 4.0 22554 g01 8 4 3.0 3.5 4.5 2 0 12 10 6 5.0 5.5 v in (v) 2.5 i vin (a) 4.0 3589 g02 150 50 3.0 3.5 4.5 0 250 200 100 5.0 5.5 enable two ldos enable one ldo enable three ldos v in (v) 2.5 i vin (a) 4.0 3589 g03 400 500 600 200 100 3.0 3.5 4.5 0 900 800 700 300 5.0 5.5 enable two bucks enable one buck enable three bucks pulse-skipping mode v in (v) 2.5 i vin (a) 4.0 3589 g04 80 100 120 40 20 3.0 3.5 4.5 0 60 5.0 5.5 enable two bucks enable one buck enable three bucks burst mode operation temperature (c) C50 i vin (a) 50 25 3589 g05 800 1000 1200 400 200 C25 0 75 0 600 100 125 150 all regulators enabled burst mode operation standby (only ldo1 on) all regulators enabled pulse-skipping mode v in (v) 2.5 i vin (a) 4.5 4.0 3589 g06 350 400 450 150 200 50 100 3.0 3.5 5.0 0 300 250 5.5 burst mode operation pwm mode oscillator frequency vs temperature switching frequency change vs v in buck-boost efficiency vs i out temperature (c) C50 frequency (mhz) 70 3589 g07 2.20 2.25 2.30 2.10 2.15 2.00 2.05 C10 30 110 1.95 150 v in (v) 2.5 percent change (%) 4.0 3589 g08 0.6 0.8 1.0 C0.2 0 0.2 0.4 C0.6 C0.4 3.0 3.5 4.5 C0.8 5.5 5.0 load current (ma) 0 efficiency (%) 50 40 30 60 70 100 0.01 0.1 1 10 100 1000 3589 g9 20 10 80 90 burst pwm mode v out = 5.0v v out = 2.5v v out = 3.3v v in = 3.8v
ltc3589/ltc3589-1/ ltc3589-2 10 3589fe typical performance characteristics buck-boost efficiency vs i out step-down switching regulator 1 efficiency vs i out step-down switching regulator 2 efficiency vs i out step-down switching regulator 3 efficiency vs i out buck-boost r ds(on) vs temperature step-down switching regulator r ds(on) vs temperature load current (ma) 0 efficiency (%) 50 40 30 60 70 100 0.01 0.1 1 10 100 1000 3589 g10 20 10 80 90 burst pwm mode v in = 5.0v v in = 4.2v v in = 3.0v v out = 3.3v load current (ma) 0 efficiency (%) 50 40 30 60 70 100 0.01 0.1 1 10 100 1000 3589 g12 20 10 80 90 forced continuous pulse-skipping burst v out = 1.8v load current (ma) 0 efficiency (%) 50 40 30 60 70 100 0.01 0.1 1 10 100 1000 3589 g13 20 10 80 90 forced continuous pulse- skipping burst v out = 3.3v temperature (c) C50 r ds(on) () 70 3589 g14 0.35 0.40 0.15 0.20 0.25 0.30 0.05 0.10 C10 30 0 150 110 buck2, 3 pmos buck1 pmos buck2, 3 nmos buck1 nmos temperature (c) C50 r ds(on) () 70 3589 g15 0.15 0.20 0.25 0.05 0.10 C10 30 0 150 110 pmos nmos load current (ma) 0 efficiency (%) 50 40 30 60 70 100 0.01 0.1 1 10 100 1000 3589 g11 20 10 80 90 pulse-skipping forced continuous v out = 1.2v burst v in = 3.8v, t a = 25c, unless otherwise noted. step-down switching regulator current limit vs temperature step-down switching regulator soft-start buck-boost current limit vs temperature temperature (c) C50 current limit (a) 75 100 3589 g17 2.5 3.0 3.5 0.5 2.0 1.5 1.0 C25 0 25 50 0 150 125 peak limit clamp limit 3589 g18 200s/div 500mv/div 200ma/div v out i l temperature (c) C50 current limit (a) 75 100 3589 g16 2.5 3.0 3.5 0.5 2.0 1.5 1.0 C25 0 25 50 0 150 125 buck1 buck2, buck3 buck2, buck3 (ltc3589-1/ltc3589-2)
ltc3589/ltc3589-1/ ltc3589-2 11 3589fe typical performance characteristics buck-boost switching regulator soft-start dynamic voltage slew step-down switching regulator 1 load step buck-boost switching regulator 1 load step maximum buck-boost load current vs v in step-down switching regulator 1 load step 3589 g19 100s/div 1v/div 5 00ma/div v out i l 3589 g20 200s/div 1v/div 5v/div 5v/div v out v stb pgood v rrcr = 1.75mv/s 3589 g21 40s/div v out i load load capacitance = 44 f 50mv/div 1a/div pulse-skipping mode 3589 g22 40s/div v out i load load capacitance = 44f 50mv/div 1a/div burst mode operation v in (v) 2.5 load current (a) 4.0 3589 g24 1.5 0.5 3.0 3.5 4.5 0 2.5 2.0 1.0 5.0 5.5 v out = 1.8v v out = 3.3v v out = 5v 3589 g23 40s/div v out i load 200mv/div 1a/div load capacitance = 22f v in = 3.8v, t a = 25c, unless otherwise noted. ldo1 dropout voltage vs temperature ldo1 output change vs v in ldo1 short-circuit current vs temperature temperature (c) C50 short-circuit current (ma) 75 100 3589 g27 60 70 80 30 50 40 C25 0 25 50 20 150 125 v in (v) 2 change in v ldo1 (%) 3589 g26 0.0 0.5 C1.5 C0.5 C1.0 34 C2.0 5 v ldo1 = 25ma v ldo1 = 1.2v v ldo1 = 1.8v v ldo1 = 2.8v v ldo1 = 3.3v temperature (c) C50 dropout voltage (mv) 75 100 3589 g25 400 500 100 300 200 C25 0 25 50 0 150 125 v ldo1 = 1.8v v ldo1 = 3.3v
ltc3589/ltc3589-1/ ltc3589-2 12 3589fe typical performance characteristics ldo2, ldo3, ldo4 dropout voltage vs temperature ldo2, ldo3, ldo4 dropout voltage vs load current ldo2, ldo3, ldo4 short-circuit current vs temperature ldo2, ldo3, ldo4 enable response ldo2, ldo3, ldo4 load step response ldo1 load step response 3589 g33 40s/div load capacitance = 1f 20ma v ldo1 50mv/div i ldo1 10ma/div 1ma 1.2v 3589 g32 10s/div 220ma 10ma v ldo 50mv/div i ldo 100ma/div 1.8v load capacitance = 1f 3589 g31 100s/div v en_ldo2 ,v en_ldo34 1v/div v ldo2 =1.2v v ldo4 =2.8v v ldo3 =1.8v temperature (c) C50 short-circuit current (ma) 75 100 3589 g30 400 450 500 250 350 300 C25 0 25 50 200 150 125 load current (ma) 0 dropout voltage (mv) 150 200 3589 g29 300 400 500 200 100 50 100 0 250 v ldo = 1.2v v ldo = 1.8v v ldo = 3.3v temperature (c) C50 dropout voltage (mv) 75 100 3589 g28 300 400 500 200 100 C25 0 25 50 0 150 125 v ldo = 1.2v v ldo = 1.8v v ldo = 3.3v v in = 3.8v, t a = 25c, unless otherwise noted.
ltc3589/ltc3589-1/ ltc3589-2 13 3589fe pin functions v in_ldo2 (pin 1): power input for ldo2. this pin should be bypassed to ground with a 1f or greater ceramic capacitor. ldo2 (pin 2): output voltage of ldo2. nominal output voltage is set with a resistor feedback divider that servos to an i 2 c register controlled dac reference. this pin must be bypassed to ground with a 1f or greater ceramic capacitor. ldo3 (pin 3): output voltage of ldo3. nominal output voltage is ? xed at 1.8v or 2.8v (ltc3589-1/ltc3589-2). this pin must be bypassed to ground with a 1f or greater ceramic capacitor. ldo4 (pin 4): output voltage of ldo4. output voltage is selected via the i 2 c port. this pin must be bypassed to ground with a 1f or greater ceramic capacitor. v in_ldo34 (pin 5): power input for ldo3 and ldo4. this pin should be bypassed to ground with a 1f or greater ceramic capacitor. pv in1 (pin 6): power input for step-down switching regulator 1. tie this pin to v in supply. this pin should be bypassed to ground with a 4.7f or greater ceramic capacitor. sw1 (pin 7): switch pin for step-down switching regulator 1. connect one side of step-down switching regulator 1 inductor to this pin. rsto (pin 8): reset output. open-drain output pulls low when the always-on regulator ldo1 is below regulation and during a hard reset initiated by a pushbutton input. en_ldo2 (pin 9): enable ldo2 logic input. active high input to enable ldo2. a weak pull-down forces en_ldo2 low when left ? oating. en1 (pin 10): enable step-down switching regulator 1. active high input to enable step-down switching regulator 1. a weak pull-down forces en1 low when left ? oating. en2 (pin 11): enable step-down switching regulator 2. active high input to enable step-down switching regulator 2. a weak pull-down forces en2 low when left ? oating. sw4ab (pin 12): switch pin for buck-boost switching regulator 4. connected to the buck-boost internal power switches a and b. connect an inductor between this pin and sw4cd (pin 19). en3 (pin 13): enable step-down switching regulator 3. active high input to enable step-down switching regulator 3. a weak pull-down forces en3 low when left ? oating. en4 (pin 14): enable buck-boost switching regulator 4. active high input to enable buck-boost switching regulator 4. a weak pull-down forces en4 low when left ? oating. pv in4 (pin 15): power input for switching regulator 4. tie this pin to v in supply. this pin should be bypassed to ground with a 4.7f or greater ceramic capacitor. bb_out (pin 16): output voltage of buck-boost switching regulator 4. this pin must be bypassed to ground with a 22f or greater ceramic capacitor. irq (pin 17): interrupt request output. open-drain driver is pulled low for power good, undervoltage, and overtemperature warning and fault conditions. clear irq by writing to the i 2 c clirq command register. en_ldo34 (pin 18): ltc3589 enable ldo3 and ldo4 logic input. active high to enable ldo3 and ldo4. disable ldo4 via i 2 c software commands using i 2 c command registers oven or l2dtv2. a weak pull-down forces en_ldo34 low when left ? oating. en_ldo3 (pin 18): ltc3589-1/ltc3589-2 enable ldo3 logic input. active high to enable ldo3. a weak pull-down forces en_ldo3 low when left ? oating. sw4cd (pin 19): switch pin for buck-boost switching regulator 4. connected to the buck-boost internal power switches c and d. connect an inductor between this node and sw4ab (pin 12). pwr_on (pin 20): external power-on. handshaking pin to acknowledge successful power-on sequence. pwr_on must be driven high within ? ve seconds of wake going high to keep power on. it can be used to activate the wake output by driving high. drive low to shut down wake.
ltc3589/ltc3589-1/ ltc3589-2 14 3589fe pin functions on (pin 21): pushbutton input. a weak internal pull-up forces on high when left ? oating. a normally open push- button is connected from on to ground to force a low state on this pin. pbstat (pin 22): pushbutton status. open-drain output to be used for processor interrupts. pbstat mirrors the status of on pushbutton pin. pbstat is delayed 50ms from on pin for debounce. wake (pin 23): system wake up. open-drain driver output releases high when signaled by pushbutton activation or pwr_on input. it may be used to initiate a pin-strapped power-up sequence by connecting to a regulator enable pin to initiate a pin-strapped power-on sequence. pvin2 (pin 24): power input for step-down switching regulator 2. tie this pin to v in supply. this pin should be bypassed to ground with a 4.7f or greater ceramic capacitor. sw2 (pin 25): switch pin for step-down switching regula- tor 2. connect one side of step-down switching regulator 2 inductor to this pin. sw3 (pin 26): switch pin for step-down switching regula- tor 3. connect one side of step-down switching regulator 3 inductor to this pin. pvin3 (pin 27): power input for step-down switching regulator 3. tie this pin to the v in supply. this pin should be bypassed to ground with a 4.7f or greater ceramic capacitor. vstb (pin 28): voltage standby. when vstb is low, dac reference registers are selected by bit values in command register vccr. when vstb is high, the dac registers are forced xxdvt2 registers. tie vstb to ground if unused. pgood (pin 29): power good output. open-drain output pulls down when any regulator falls below power good threshold and during regulator dynamic voltage slew unless disabled in i 2 c register. pulls down when all regula- tors are disabled. scl (pin 30): clock input pin for the i 2 c serial port. the i 2 c logic levels are scaled with respect to dv dd . sda (pin 31): data input pin for the i 2 c serial port. the i 2 c logic levels are scaled with respect to dv dd . dv dd (pin 32): supply voltage for i 2 c serial port. this pin sets the logic reference level of scl and sda i 2 c pins. dv dd resets i 2 c registers to power on state when driven to <1v. scl and sda logic levels are scaled to dv dd . con- nect a 0.1f decoupling capacitor from this pin to ground. buck2_fb (pin 33): feedback input for step-down switching regulator 2. set full-scale output voltage using resistor divider connected from the output of step-down switching regulator 2 to this pin to ground. buck3_fb (pin 34): feedback input for step-down switching regulator 3. set full-scale output voltage using resistor divider connected from the output of step-down switching regulator 3 to this pin to ground. ldo1_fb (pin 35): feedback input for ldo1. set out- put voltage using a resistor divider connected from ldo1_stdby to this pin to ground. ldo1_stdby (pin 36): always-on ldo1 output. this pin provides an always-on supply voltage useful for light loads such as a watchdog microprocessor or a real-time clock. connect a 1f capacitor from ldo1_stby to ground. v in (pin 37): supply voltage input. this pin should be bypassed to ground with a 1f or greater ceramic capacitor. ldo2_fb (pin 38): feedback input for ldo2. set full-scale output voltage using a resistor divider connected from ldo2_out to this pin to ground. buck1_fb (pin 39): feedback input for step-down switching regulator 1. set full-scale output voltage using resistor divider connected from the output of step-down switching regulator 1 to this pin to ground. bb_fb (pin 40): feedback input for buck-boost switching regulator 4. set the output voltage using resistor divider connected from bb_out to this pin to ground. gnd (exposed pad pin 41): ground. the exposed pad must be connected to a continuous ground plane on the second layer of the printed circuit board by several interconnect vias directly under the ltc3589 for maximum heat transfer.
ltc3589/ltc3589-1/ ltc3589-2 15 3589fe block diagram 3589 bd power good 1.8v, 2.5v, 2.8v, 3.3v (ltc3589) 1.2v, 1.8v, 2.5v, 3.2v (ltc3589-1/ ltc3589-2) at 250ma ldo1_stdby ldo1_fb irq always on ldo1 0.8v to v in at 25ma v in v ref ok on (pb) pbstat wake pwr_on vstb en1 en2 en3 en4 en_ldo2 control + sequence en_ldo34 en_ldo3 (ltc3589-1/ ltc3589-2) dv dd sda scl i 2 c pgood n rsto v in_ldo34 ldo4 gnd (exposed pad) ldo4 v ref ok en v ref buck-boost pv in4 bb_out 1.8v to 5.0v at 1.2a 0.5v to v in at 1.6a 0.5v to v in at 1a/1.2a 0.5v to v in at 1a/1.2a 0.36v to v in at 250ma 1.8v (ltc3589) 2.8v (ltc3589-1/ ltc3589-2) at 250ma bb_fb pv in1 sw1 buck1_fb pv in2 sw2 sw3 buck2_fb buck3_fb pv in3 v in_ldo2 ldo2_fb ldo2 ldo3 sw4ab sw4cd en ok en ok en ok en ok v ref buck 1 v ref buck 2 v ref buck 3 ldo3 v ref ok en ldo2 dac dac dac dac en-pins en-i 2 c v ref ok en 7
ltc3589/ltc3589-1/ ltc3589-2 16 3589fe operation introduction the ltc3589 is a complete power management solution for portable microprocessors and peripheral devices. it generates a total of eight voltage rails for supplying power to the processor core, sdram, system memory, pc cards, always-on real-time clock and hdd functions. supplying the voltage rails are an always-on low quiescent current 25ma ldo, one 1.6a and two 1a (1.2a for ltc3589-1/ ltc3589-2) step-down regulators, a 1.2a buck-boost regulator, and three 250ma low dropout regulators. sup- porting the multiple regulators is a highly con? gurable power-on sequencing capability, dynamic voltage slewing dac output voltage control, a pushbutton interface con- troller, regulator control via an i 2 c interface, and extensive status and interrupt outputs. the ltc3589 operates over an input supply range of 2.7v to 5.5v. the input supplies for the 250ma ldo regulators may operate as low as 1.7v to limit power loss at low output voltages. the always-on ldo1 provides a resistor programmable output voltage as low as 0.8v and is capable of supplying 25ma. with only the always-on ldo active the ltc3589 draws just 8a (typical). always-on ldo1 will continue to operate with v in levels as low as 2.0v (typical) to maintain memory and rtc function as long as possible. each of the 250ma ldo regulators has unique output voltage con? gurations. ldo3 has a ? xed 1.8v (2.8v for ltc3589-1/ltc3589-2) output. ldo4 has four output levels selectable via the i 2 c interface. its possible outputs are 1.8v, 2.5v, 2.8v, and 3.3v (1.2v, 1.8v, 2.5v, 3.2v for ltc3589-1/ ltc3589-2). ldo2 has a dynamically slewing dac set point reference and an external feedback pin to set the output voltage range with a resistive divider. each ldo draws 60a (typical) quiescent current. the ltc3589 includes three internally compensated constant frequency current mode step-down switching regulators two capable of supplying 1a of output cur- rent and one capable of supplying 1.6a. the ltc3589-1/ ltc3589-2 step-down regulators can supply 1.2a, 1.2a, and 1.6a. step-down regulator switching frequencies of 2.25mhz or 1.125mhz are independently selected for each step-down regulator using the i 2 c command registers. the power-on default frequency is 2.25mhz. each of the step-down regulators have dynamically slewing dac input references and external feedback pins to set output voltage range. the step-down regulators three operating modes, pulse-skipping, burst, or forced continuous, are set using the i 2 c interface. in pulse-skipping mode the regulator will support 100% duty cycle. for best ef? ciency at low output loads select burst mode operation. forced continu- ous mode minimizes output voltage ripple at light loads. the 4-switch buck-boost dc/dc voltage mode converter generates a user-programmable output voltage rail from 1.8v to 5v. utilizing a proprietary switching algorithm, the buck-boost converter maintains high ef? ciency and low noise operation with input voltages that are above, below or equal to the required output rail. the buck-boost error ampli? er uses a ? xed 0.8v reference and the output voltage is set by an external resistor divider. burst mode operation is enabled through the i 2 c control registers. no external compensation components are required for the buck-boost converter. the reference inputs for the three step-down regulators and ldo2 are 5-bit d to a converters with up-down ramp- ing at selectable slew rates. the slew endpoint voltages and select bits are stored in i 2 c registers for each dac. a select bit in the i 2 c command registers chooses which register to use for each target voltage. variable reference slew rates from 0.88mv/s to 7mv/s are selectable in the i 2 c register. each of the four dacs has independent voltage, voltage select, and slew rate control registers. the ltc3589 is equipped with a pushbutton control circuit that will activate the wake output, indicate pushbutton status via the pbstat pin, and initiate a hard reset shut- down of the regulators. grounding the on pin with the pushbutton for 400ms will force the wake pin to release high. the wake pin output can be tied to the enable pin of the ? rst regulator in a power-on sequence. once in the power-on state, subsequent pushes of the button longer than 50ms are mirrored by the pbstat output. holding on low for ? ve seconds disables all the regulators, pulls down the wake pin, and pulls down rsto for one second to indicate to the processor that a hard reset occurred. all regulator enables and pushbutton inputs are inhibited for one second following the hard reset.
ltc3589/ltc3589-1/ ltc3589-2 17 3589fe the ltc3589 has ? exible options for enabling and sequenc- ing the regulator enables. the regulators are enabled us- ing input pins or the i 2 c serial port. to de? ne a power-on sequence tie the enable of the ? rst regulator to be powered up to the wake pin. connect the ? rst regulators output to the enable pin of the second regulator, and so on. one or more regulators may be started in any sequence. each enable pin has a 200s (typical) delay between the pin and the internal enable of the regulator. when the system controllers are satis? ed that power rails are up, the con- troller must drive pwr_on high to keep wake active. to ensure correct start-up sequencing, the regulators outputs are monitored by voltage comparators which require each output to discharge below 300mv before re-enabling. a software control command register function is available which sets the regulators to effectively ignore their enable pins but respond to i 2 c register enables. this function enables software-only control of any combination of pin- strapped regulators and is useful for implementing system power saving modes. keep-alive mode exempts selected regulators from turning off during normal shutdown. in keep-alive mode, the ltc3589 powers down normally and is ready for the next start-up sequence, but selected regulators are kept on to power memory or other functions during system standby modes. the ltc3589 will shut down all regulators and pull down the wake pin under high temperature, v in undervoltage, and extended low regulator output voltage conditions. status of a hard shutdown is reported by the irq status pin and the irqstat status register. the i 2 c serial port on the ltc3589 contains 13 command registers for controlling each of the regulators, one read- only register for monitoring each regulators power good status, one read-only register for reading the cause of an irq event, and one clear irq command register. the ltc3589 i 2 c supports random addressing of any register. ltc3589, ltc3589-1, and ltc3589-2 functional comparison table 1. summarizes the functional differences between the ltc3589, ltc3589-1, and ltc3589-2. table 1. ltc3589, ltc3589-1, and ltc3589-2 functional differences ltc3589 ltc3589-1 ltc3589-2 power-on inhibit enable delay 1 second <2ms <2ms buck2 current output 1a 1.2a 1.2a buck3 current output 1a 1.2a 1.2a pgood fault timeout enabled by default. i 2 c disable. disabled by default. i 2 c enable. disabled by default. i 2 c enable. pwr_on to wake delay 50ms 2ms 2ms ldo3 v out 1.8v 2.8v 2.8v ldo4 v out * indicates default v out 1.8v, 2.5v, 2.8v*, 3.3v 1.2v*, 1.8v, 2.5v, 3.2v 1.2v*, 1.8v, 2.5v, 3.2v default ldo4 enable ldo34_en pin i 2 ci 2 c wait to enable until output < 300mv yes by default. i 2 c select. yes by default. i 2 c select. no by default. i 2 c select. insert 2k discharge resistor when disabled yes if start-up is wait to enable until output < 300mv yes if start-up is wait to enable until output < 300mv always details of the operation of the ltc3589 are found in the following sections. always-on ldo the ltc3589 includes a low quiescent current low dropout regulator that remains powered whenever a valid supply is present on v in . the always-on ldo will remain active until v in drops below 2.0v (typical). this is below the 2.5v operation
ltc3589/ltc3589-1/ ltc3589-2 18 3589fe undervoltage threshold in effect for the rest of the ltc3589 circuits. the always-on ldo is used to provide power to a standby microcontroller, real-time clock, or other keep- alive circuits. the ldo is guaranteed to support a 25ma load. a 1f low impedance ceramic bypass capacitor from ldo1_stby to gnd is required for compensation. a power good monitor pulls rsto low for a minimum of 14ms (typical) whenever ldo1_stby is 8% below its regulation target. an ldo1_stby undervoltage condition is reported in the pgood status register. the output voltage of ldo1 is set with a resistor divider connected from ldo1_stby to the feedback pin ldo1_fb, as shown in figure 1. v ldo_stby = 0.8 ? 1 + r1 r2 (v) typical values for r1 are in the range of 40k to 1m. ldo1_stby is protected from short-circuits and over- loading. 250 m a ldo regulators three ldo regulators on the ltc3589 will each deliver up to 250ma output. the ldo regulators are enabled by pin input or i 2 c command register. pin en_ldo2 enables ldo2 and the ltc3589 en_ldo34 pin enables ldo3 and ldo4 together. an i 2 c command register bit is available to decouple ldo4 from pin en_ldo34 so that ldo4 is under command register control only. the ltc3589-1/ltc3589-2 en_ldo3 pin enables ldo3 only. ldo4 is controlled using the i 2 c command registers. all the regulators have current operation 3589 f02 pv in 0.3625v to 0.75v ea fb ldo2 r1 1f r2 dac 5 figure 2. ldo2 application circuit C + 3589 f01 v in 0.8v ldo1_fb ldo1_stby r1 1f r2 figure 1. always-on ldo application circuit limit protection circuits. default operation for the ltc3589 is when an ldo regulator is disabled, a 2.5k pull-down resistor is connected to its output. to help reduce ldo power loss in the system, the regula- tors have dedicated supply inputs that may be lower than the main v in supply. connect a low esr 1f capacitor to each of the output pins ldo2, ldo3, and ldo4. ldo regulator 2 one of the ltc3589 dynamic slewing dacs serves as the reference input of ldo2. the output range of ldo2 is set using an external resistor divider connected from ldo2 to the feedback pin ldo2_fb, as shown in figure 2. set the output voltage of ldo2 using the following formula: v out = 1 + r1 r2 ? (0.3625 + l2dtvx ? 0.0125) l2dtvx is the ? ve bit word contained in the ldo2 dynamic target voltage 1 (l2dtv1) or the ldo2 dynamic target voltage 2 (l2dtv2) command registers. the default value of l2dtvx[4-0] is 11001 to output a reference voltage of 0.675v. ldo2 is enabled by writing bit 4 in the output voltage enable (oven) command register to 1 or driving the ldo2_en pin high. whenever the command is given to slew ldo2 dac reference to a lower voltage an integrated 2.5k pull-down resistor is connected to ldo2 output.
ltc3589/ltc3589-1/ ltc3589-2 19 3589fe table 2. shows the i 2 c command register settings used to control ldo2. table 2. ldo 2 command register settings command register[bit] value setting oven[4] 0* 1 disable enable scr2[4] ltc3589/ltc3589-1 0* 1 wait for output below 300mv before enable enable immediately scr2[4] ltc3589-2 0* 1 enable immediately wait for output below 300mv before enable vccr[5] 0* 1 select register l2dtv1 (v1) reference select register l2dtv2 (v2) reference vccr[6] 1 initiate dynamic voltage slew vrrcr[7-6] 00 01 10 11* reference slew rate = 0.88mv/s reference slew rate = 1.75mv/s reference slew rate = 3.5mv/s reference slew rate = 7mv/s l2dtv1[4-0] 11001* dac dynamic target voltage v1 l2dtv1[5] 0* 1 force pgood low when slewing normal pgood operation when slewing l2dtv1[7] 0* 1 shutdown ldo2 normally keep ldo2 alive l2dtv2[4-0] 11001* dac dynamic target voltage v2 * denotes default power-on value ldo regulator 3 ldo3 is a ? xed 1.8v or 2.8v (ltc3589-1/ltc3589-2) output regulator. ldo3 is enabled by driving pin en_ldo34 or en_ld03 high or by writing command register oven[5] to 1. table 3 shows the i 2 c command register settings used to control ldo3. table 3. ldo 3 command register settings command register[bit] value setting oven[5] 0* 1 disable enable scr2[5] ltc3589/ltc3589-1 0* 1 wait for output below 300mv before enable enable immediately scr2[5] ltc3589-2 0* 1 enable immediately wait for output below 300mv before enable * denotes default power-on value operation ldo regulator 4 ldo4 has four output voltage options that are controlled by the contents of command register bits l2dtv2[6] and l2dtv2[5]. when pin en_ldo34 is low, ldo3 and ldo4 are controlled by writing to command register bits oven[5] and oven[6] respectively. by default, the ltc3589 pin en_ldo34 enables and disables ldo3 and ldo4 simultaneously when command register bits oven[5] and oven[6] are low. when command register bit l2dtv2[7] is high, control of ldo4 is disconnected from pin en_ldo34 and controlled by command register bit oven[6] regardless of the status of en_ldo34. the ltc3589-1/ltc3589-2 pin en_ldo3 enables only ldo3. control of ldo4 on the ltc3589-1/ltc3589-2 is under i 2 c control only. table 4 shows the i 2 c command register settings that control ldo4. table 4. ltc3589 ldo4 command register settings command register[bit] value setting oven[6] 0* 1 disable enable scr2[6] 0* 1 wait for output below 300mv before enable enable immediately l2dtv2[6-5] 00* 01 10 11 v ldo4 = 2.8v v ldo4 = 2.5v v ldo4 = 1.8v v ldo4 = 3.3v l2dtv2[7] 0* 1 ldo4 enable controlled by en_ldo34 ldo4 enable controlled by oven[6] ltc3589-1/ltc3589-2 ldo4 command register settings oven[6] 0* 1 disable enable scr2[6] ltc3589-1 0* 1 wait for output below 300mv before enable enable immediately scr2[6] ltc3589-2 0* 1 enable immediately wait for output below 300mv before enable l2dtv2[6-5] 00* 01 10 11 v ldo4 = 1.2v v ldo4 = 1.8v v ldo4 = 2.5v v ldo4 = 3.2v l2dtv2[7] 0* 1 unused * denotes default power-on value
ltc3589/ltc3589-1/ ltc3589-2 20 3589fe step-down switching regulators output voltage programming each of the step-down converters uses a dynamically slewing dac output for its reference. the full-scale output voltage is set by using a resistor divider connected from the step-down switching regulator output to the feedback pins (b1_fb, b2_fb, and b3_fb), as shown in figure 3. set the output voltage of step-down switching regulators using the following formula: v out = 1 + r1 r2 ? (0.3625 + bxdtvx ? 0.0125)(v) bxdtvx is the decimal value of the ? ve bit binary number in the i 2 c bxdtv1 or bxdtv2 command registers. bxdtv1 and bxdtv2 default to 11001 to output a reference voltage of 0.675v. typical values for r1 are in the range of 40k to 1m. the capacitor c fb cancels the pole created by the feedback resistors and the input capacitance on the fb pin and also helps to improve load step transient response. a value of 10pf is recommended for most applications. experimentation with capacitor sizes between 10pf and 33pf may yield improved transient response. operating modes the step-down switching regulators include three possible operating modes to meet the noise and power needs of a variety of applications. in pulse-skipping mode, at the start of every cycle, a latch is set that turns on the main p-channel mosfet switch. during the cycle, a current comparator compares the peak inductor current to the output of an error ampli? er. the output of the current comparator resets the latch. at this time the p-channel mosfet switch turns off and the n-channel mosfet synchronous recti? er turns on. the n-channel mosfet synchronous recti? er will turn off when the end of the clock cycle is reached or if the inductor current drops through zero. using this method of operation, the error ampli? er adjusts the peak inductor current to deliver the required output power. all necessary loop compensation is internal to the step-down switching regulator requiring only a single ceramic output capacitor for stability. at light loads in pulse-skipping mode, the inductor current may reach zero on each pulse that will turn off the n-channel mosfet synchronous recti? er. in this case the switch node (sw1, sw2, or sw3) goes high impedance and the switch node will ring. this is discon- tinuous operation and is normal behavior for a switching regulator. at very light loads in pulse-skipping mode, the step-down switching regulators will automatically skip pulses as needed to maintain output regulation. at high duty cycle (v outx > v in /2) it is possible for the inductor current to reverse at light loads causing the step-down switching regulator to operate continuously. when operat- ing continuously, regulation and low noise output voltage are maintained, but input operating current will increase to a few milliamps. in the forced continuous mode of operation, the inductor current is allowed to be less than zero over the full range of duty cycles. operating in forced continuous mode is a lower noise option at light loads than pulse-skipping operation but with the drawback of higher v in current operation figure 3. step-down switching regulator application circuit 3589 f03 pv in pwm control 0.3625v to 0.75v sw fb l1 en mode r1 c out r2 c fb dac 5
ltc3589/ltc3589-1/ ltc3589-2 21 3589fe due to the continuous operation of the mosfet switch and recti? er. since the inductor current is allowed to be negative in forced continuous operation the step-down switching regulator has the ability to sink output current. the ltc3589 automatically forces the step-down switching regulator into forced continuous mode when dynamically slewing the dac voltage reference down. when the ltc3589 step-down switching regulators are in burst mode operation, they automatically switch between ? xed frequency pulse-skipping operation and hysteretic burst mode control as a function of the load current. at light loads the step-down switching regulators control the inductor current directly and use a hysteretic control loop to minimize both noise and switching losses. while in burst mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. the step-down switching regulator then goes into a low power sleep mode during which the output capacitor provides the load current. in sleep mode, most of the switching regulators circuitry is powered off to conserve battery power. when the output voltage drops below the regulation point the regulators circuitry is powered on and another burst cycle begins. as the load current increases, the time between burst cycles decreases. above a load current about one-quarter rated output load, the step-down switching regulators will switch to low noise constant-frequency pwm operation. set the mode of operation for the step-down switching regulators by using the i 2 c command register scr1. each of the three regulators has independent mode control. a step-down switching regulator may enter a dropout condi- tion when its input voltage drops to near its programmed output voltage. for example, a discharging battery voltage of 3.4v dropping to the regulators programmed output voltage of 3.3v. when this happens the duty cycle of the p-channel mosfet switch is increased until it turns on continuously with 100% duty cycle. in dropout, the regu- lators output voltage equals the regulators input voltage minus the voltage drops across the internal p-channel mosfet and the inductor dc resistance. operation table 5, table 6, and table 7 show the i 2 c command register settings used to control the step-down switching regulators. table 5. step-down switching regulator 1 command register settings command register[bit] value setting scr1[1-0] 00* 01 10 pulse-skipping mode burst mode operation forced continuous mode oven[0] 0* 1 disable enable scr2[0] ltc3589/ltc3589-1 0* 1 wait for output below 300mv before enable enable immediately scr2[0] ltc3589-2 0* 1 enable immediately wait for output below 300mv before enable vccr[1] 0* 1 select register b1dtv1 (v1) reference select register b1dtv2 (v2) reference vccr[0] 1 initiate dynamic voltage slew vrrcr[1-0] 00 01 10 11* reference slew rate = 0.88mv/s reference slew rate = 1.75mv/s reference slew rate = 3.5mv/s reference slew rate = 7mv/s b1dtv1[5] 0* 1 force pgood low when slewing normal pgood operation when slewing b1dtv1[4-0] 11001* dac dynamic target voltage v1 b1dtv2[4-0] 11001* dac dynamic target voltage v2 b1dtv2[5] 0 * 1 2.25mhz switching frequency 1.125mhz switching frequency b1dtv2[6] 0* 1 switch on clock phase 1 switch on clock phase 2 b1dtv2[7] 0* 1 shutdown regulator 1 normally keep regulator 1 alive * denotes default power-on value s oft-start soft-start is accomplished by gradually increasing the input reference voltage on each step-down switching regulator from 0v to the dynamic reference dac output level at a rate of 0.8v/ms. this allows each output to rise slowly, helping minimize inrush current required to charge up the regulator output capacitor. a soft-start cycle occurs whenever a regulator is enabled either initially or
ltc3589/ltc3589-1/ ltc3589-2 22 3589fe while powering up following a fault condition. a soft-start cycle is not triggered by a change of operating modes or a dynamic voltage slew. during soft-start the converter is forced to pulse-skipping mode regardless of the settings in the scr1 command register. table 6. step-down switching regulator 2 command register settings command register[bit] value setting scr1[3-2] 00* 01 10 pulse-skipping mode burst mode operation forced continuous mode oven[1] 0* 1 disable enable scr2[1] ltc3589/ltc3589-1 0* 1 wait for output below 300mv before enable enable immediately scr2[1] ltc3589-2 0* 1 enable immediately wait for output below 300mv before enable vccr[3] 0* 1 select register b2dtv1 (v1) reference select register b2dtv2 (v2) reference vccr[2] 1 initiate dynamic voltage slew vrrcr[3-2] 00 01 10 11* reference slew rate = 0.88mv/s reference slew rate = 1.75mv/s reference slew rate = 3.5mv/s reference slew rate = 7mv/s b2dtv1[5] 0* 1 force pgood low when slewing normal pgood operation when slewing b2dtv1[4-0] 11001* dac dynamic target voltage v1 b2dtv2[4-0] 11001* dac dynamic target voltage v2 b2dtv2[5] 0 * 1 2.25mhz switching frequency 1.125mhz switching frequency b2dtv2[6] 0* 1 switch on clock phase 1 switch on clock phase 2 b2dtv2[7] 0* 1 shutdown regulator 2 normally keep regulator 2 alive * denotes default power-on value switching emi control the step-down switching regulators contain new pat- ent pending circuitry to limit the edge rate of the switch nodes sw1, sw2, and sw3. this new circuitry controls the transition of the switch node over a period of a few nanoseconds, signi? cantly reducing radiated emi and conducted supply noise while maintaining high ef? ciency. operation since slowing the slew rate of the switch nodes causes ef? ciency loss, the slew rate of the step-down switching regulators is adjustable using the i 2 c command register b1dtv1 bits 6 and 7. optimize ef? ciency or emi as neces- sary with four different slew rate settings. the power-on default is the fastest slew rate, highest ef? ciency setting. table 7. step-down switching regulator 3 command register settings command register[bit] value setting scr1[5-4] 00* 01 10 pulse-skipping mode burst mode operation forced continuous mode oven[2] 0* 1 disable enable scr2[2] ltc3589/ltc3589-1 0* 1 wait for output below 300mv before enable enable immediately scr2[2] ltc3589-2 0* 1 enable immediately wait for output below 300mv before enable vccr[5] 0* 1 select register b3dtv1 (v1) reference select register b3dtv2 (v2) reference vccr[4] 1 initiate dynamic voltage slew vrrcr[5-4] 00 01 10 11* reference slew rate = 0.88mv/s reference slew rate = 1.75mv/s reference slew rate = 3.5mv/s reference slew rate = 7mv/s b3dtv1[5] 0* 1 force pgood low when slewing normal pgood operation when slewing b3dtv1[4-0] 11001* dac dynamic target voltage v1 b3dtv2[4-0] 11001* dac dynamic target voltage v2 b3dtv2[5] 0 * 1 2.25mhz switching frequency 1.125mhz switching frequency b3dtv2[6] 0* 1 switch on clock phase 1 switch on clock phase 2 b3dtv2[7] 0* 1 shutdown regulator 3 normally keep regulator 3 alive * denotes default power-on value operating frequency the switching frequency of each of the ltc3589 step- down switching regulators may be independently set using i 2 c command register bits b1dtv2[5], b2dtv2[5] and b3dtv2[5]. the power-on default frequency is 2.25mhz. writing bit bxdtv2[5] high will reduce the switching fre-
ltc3589/ltc3589-1/ ltc3589-2 23 3589fe operation quency to 1.125mhz. selection of the operating frequency is determined by desired ef? ciency, component size and converter duty cycle. operation at lower frequency improves ef? ciency by reduc- ing internal gate charge and switching losses but requires larger inductance and capacitance values for comparable output ripple voltage. the lowest duty cycle of the step- down switching regulator is determined by the converters minimum on-time. minimum on-time is the shortest time duration that the converter is capable of turning its top pmos on and off again. the time consists of the gate charge time plus internal delays associated with peak current sensing. the minimum on-time of the ltc3589 is approximately 90ns. if the duty cycle falls below what can be accommodated by the minimum on-time, the converter will begin to skip cycles. the output voltage will continue to be regulated but the ripple voltage and current will increase. with the switching frequency set to 2.25mhz, the minimum supported duty cycle is 20%. switching at 1.125mhz the converter can support a 10% duty cycle. phase selection to reduce the cycle by cycle peak current drawn by the switching regulators, the clock phase of each of the ltc3589 step-down switching regulators can be set using i 2 c com- mand register bits b1dtv2[6], b2dtv2[6] and b3dtv2[6]. the internal full-rate clock has a nominal duty cycle of 20% while the half-rate clocks have a 50% duty cycle. setting the command register bits high will delay the start of each converter switching cycle by 20% or 50% depending on the selected operating frequency. inductor selection the choice of step-down switching regulator inductor in? u- ences the ef? ciency of the converter and the magnitude of the output voltage ripple. larger inductance values reduce inductor current ripple and therefore lower output voltage ripple. a larger value inductor improves ef? ciency by low- ering the peak current to be closer to the average output current. larger inductors, however, generally have higher series resistance that counters the ef? ciency advantage of reduced peak current. inductor ripple current is a function of switching frequency, inductance, v in , and v out , as shown in this equation: i l = 1 f?l ?v out 1C v out v in in an example application the ltc3589 step-down switching regulator 3 has a maximum load of 1a, v in equals 3.8v, and v out is set for 1.2v. a good starting design point for inductor ripple is 30% of output current or 300ma. using the equation for ripple current, a 1.2h inductor should be selected. an inductor with low dc resistance will improve converter ef? ciency. select an inductor with a dc current rating at least 1.5 times larger than the maximum load current to ensure the inductor does not saturate during normal operations. if short-circuit is a possible condition, the inductor should be rated to handle the maximum peak current speci? ed for the step-down converter. table 8 shows inductors that work well with the step-down switching regulators. input/output capacitor selection low esr (equivalent series resistance) ceramic capacitors should be used at both the output and input supply of the switching regulators. only x5r or x7r ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. a 22f capacitor is suf? cient for the step-down switching regulator outputs. for good transient response and stability the output capacitor should retain at least 10f of capacitance over operating temperature and bias voltage. place at least 4.7f decoupling capacitance as close as possible to each pv in pin. refer to table 12 for recommended ceramic capacitor manufacturers.
ltc3589/ltc3589-1/ ltc3589-2 24 3589fe operation buck-boost switching regulator output voltage programming set the output voltage of the ltc3589 buck-boost switch- ing regulator using an external resistor divider connected from bb_out to the feedback pin bb_fb and to gnd, as shown in figure 4. v bb _ out = 0.8 ? 1 + r1 r2 (v) the value of r1 plays a role in setting the dynamics of the buck-boost voltage mode control loop. in general, a larger value for r1 will increase stability but reduce the speed of the transient response. a good starting point is to choose r1 equal to 1m and calculate the value of r2 needed to set the target output voltage. if a large output capacitor is used, the bandwidth of the converter is reduced and r1 may be reduced to improve transient response. if a large inductor or small output capacitor is used then a larger r1 should be used to bring the loop toward more stable operation. table 8. inductors for step-down switching regulator 1 manufacturers part number value (h) dcr () max dc current (a) size (mm) w l h coilcraft xpl4020-102ml xpl4020-152ml xpl4020-222ml lps6225-222ml lps6225-332ml lps6225-472ml 1.0 1.5 2.2 2.2 3.3 4.7 0.029 0.036 0.060 0.045 0.055 0.065 4.00 3.60 2.60 3.90 3.50 3.00 4.2 4.2 2.0 4.2 4.2 2.0 4.2 4.2 2.0 6.0 6.0 2.0 6.0 6.0 2.0 6.0 6.0 2.0 cooper sd14-1r2-r sd14-1r5-r sd14-2r0-r sd25-2r2-r 1.2 1.5 2.0 2.2 0.034 0.039 0.045 0.031 3.35 2.91 2.56 2.80 5.2 5.2 1.45 5.2 5.2 1.45 5.2 5.2 1.45 5.2 5.2 2.5 sumida cdrh5d16np-3r3n 3.3 0.045 2.60 5.6 5.6 1.8 tdk vlf5014st-1r0n2r7 vlf5014st-2r2n2r3 vlcf5020t-2r2n2r6-1 1.0 2.2 2.2 0.050 0.073 0.071 2.7 2.3 2.6 4.8 4.6 1.4 4.8 4.6 1.4 5.0 5.0 2.0 toko 1124bs-1r2n 1124bs-1r8n 1.2 1.8 0.047 0.056 2.9 2.7 4.5 4.7 1.8 4.5 4.7 1.8 tokin h-di-0520-2r2 h-di-0630-2r4 h-di-0630-3r8 2.2 2.4 3.8 0.048 0.028 0.040 2.6 2.5 2 5.3 5.3 2.0 6.3 6.3 3.0 6.3 6.3 3.0 wurth 744042001 744052002 744053003 7440530047 7440430022 1.0 2.5 3.0 4.7 2.2 0.028 0.030 0.024 0.030 0.023 2.60 2.4 2.8 2.4 2.5 4.8 4.8 1.8 5.8 5.8 1.8 5.8 5.8 2.8 5.8 5.8 2.8 4.8 4.8 2.8
ltc3589/ltc3589-1/ ltc3589-2 25 3589fe table 9. inductors for step-down switching regulators 2 and 3 manufacturers part number value (h) dcr () max dc current (a) size (mm) w l h coilcraft xpl4020-102ml xpl4020-152ml xpl4020-472ml 1.0 1.5 4.7 0.029 0.036 0.130 4.00 3.60 1.90 4.2 4.2 2.0 4.2 4.2 2.0 4.2 4.2 2.0 cooper sd14-1r2-r sd14-3r2-r sd25-3r3-r 1.2 3.2 3.3 0.034 0.066 0.038 3.35 2.00 2.21 5.2 5.2 1.45 5.2 5.2 1.45 4.8 4.8 2.5 sumida cdrh5d16np-4r7n cdrh38d16rhpnp-3r3m 4.7 3.3 0.064 0.059 2.05 1.46 5.6 5.6 1.8 4.2 4.2 1.8 tdk vlf5014st-2r2n2r3 vlcf5020t-2r7n2r2-1 vlcf5020t-3r3n2r0-1 2.2 2.7 3.3 0.073 0.083 0.096 2.3 2.2 2 4.8 4.6 1.4 5.0 5.0 2.0 5.0 5.0 2.0 toko 1124bs-2r4n 1124bs-3r3n 2.4 3.3 0.065 0.074 2.30 2.10 4.5 4.7 1.8 4.5 4.7 1.8 tokin h-di-0520-3r3 h-di-0520-4r7 h-di-0630-3r8 h-di-0630-4r7 3.3 4.7 3.8 4.7 0.062 0.090 0.040 0.043 2.00 1.80 2.00 1.90 5.3 5.3 2.0 5.3 5.3 2.0 6.3 6.3 3.0 6.3 6.3 3.0 wurth 744043004 744052002 7440530047 744042003 7440430022 4.7 2.5 4.7 3.3 2.2 0.052 0.030 0.030 0.055 0.023 1.55 2.4 2.4 1.95 2.5 5.0 5.0 3.0 5.8 5.8 1.8 5.8 5.8 2.8 4.8 4.8 1.8 4.8 4.8 2.8 operation figure 4. buck-boost switching regulator application circuit 3589 f04 p vin4 bb_out sw4ab sw4cd a bc d pwm control 0.8v en mode bb_fb r1 22f r2 C +
ltc3589/ltc3589-1/ ltc3589-2 26 3589fe operating modes table 10 shows the i 2 c command registers used to control the operating modes of the ltc3589 buck-boost converter. when command register scr1 bit 6 is low, the ltc3589 buck-boost switching regulator operates in a ? xed fre- quency pulse width modulation mode using voltage mode feedback control. a proprietary switching algorithm allows the converter to transition between buck, buck-boost, and boost modes without discontinuity in inductor current or loop characteristics. the switch topology is shown in the application circuit in figure 4. when the input voltage is significantly greater than the output voltage, the buck-boost converter operates in buck mode. switch d turns on continuously and switch c remains off. switches a and b are pulse width modulated to produce the required duty cycle to support the output regulation voltage. as the input voltage decreases, switch a remains on for a larger portion of the switching cycle. when the duty cycle reaches approximately 85%, the switch pair ac begins turning on for a small fraction of the switching period. as the input voltage decreases further, the ac switch pair remains on for longer durations and the duration of the bd phase decreases proportionately. as the input voltage drops below the output voltage, the ac phase will eventually increase to the point that there is no longer any bd phase. at this point, switch a remains on continuously while switches cd operate as a boost converter to regulate the desired output voltage. the buck-boost is set to burst mode operation by writing a 1 to command register scr1 bit 6. using burst mode operation at light loads improves efficiency and reduces standby current at zero loads. in burst mode operation, the inductor is charged with bursts of fixed peak amplitude current pulses. the current pulses are repeated as often as necessary to maintain the target output voltage. the maximum output current that can be supplied in burst mode operation is dependent upon the input and output voltage. typically i out(max) in burst mode operation is equal to: i out(max) = 0.28 ? v in v out + v in (a) operation if the buck-boost load exceeds the maximum burst mode current capability then the output rail will lose regula- tion and the power good comparator will indicate a fault condition. when the ltc3589 buck-boost is not enabled, a 2.5k pull- down resistor is connected between bb_out and ground. soft-start the buck-boost converter has an internal voltage mode soft- start circuit that ramps the buck-boosts error amp reference from 0v to 800mv at a rate of 2v/ms. during soft-start, the converter is regulating to the ramping reference and will respond to output load transients. during soft-start the buck-boost converter is forced into continuous mode opera- tion regardless of the state of the scr1 command register. current limit operation the ltc3589 buck-boost regulator has current limit circuits to limit forward current through the a switch and reverse current through the d switch. the primary forward cur- rent limit circuit injects a small fraction of the inductor current into the feedback node whenever the inductor current exceeds 2.7a (typical). forcing the current into the feedback node in the high gain feedback circuit has the effect of lowering the output voltage until the aver- age current in switch a is equal to the current limit. the average limit uses the error amplifier in its active linear state so once the fault condition is removed the recovery is smooth with little overshoot. a hard short on the output of the buck-boost will cause the inductor current to exceed the 2.7a average current limit. a second current limit turns off switch a in the event peak inductor current reaches 3a (typical). the instantaneous forward current limit provides extra protection in the event of a sudden hard short. the reverse current comparator on the d switch moni- tors the current entering the bb_out pin. when this current exceeds 1a (typical) switch d will turn off for the remainder of the switching cycle. this feature protects the buck-boost converter from excessive reverse current if the buck-boost output is held above the regulation point by an external source.
ltc3589/ltc3589-1/ ltc3589-2 27 3589fe table 11. inductors for buck-boost switching regulator manufacturers part number value (h) dcr () max dc current (a) size (mm) w l h coilcraft xpl4020-152ml xpl4020-222ml xpl4020-332ml lps6225-332ml lps6225-472ml 1.5 2.2 3.3 3.3 4.7 0.036 0.060 0.085 0.055 0.065 3.60 2.60 2.40 3.50 3.00 4.2 4.2 2.0 4.2 4.2 2.0 4.2 4.2 2.0 6.0 6.0 2.0 6.0 6.0 2.0 cooper sd14-1r5-r sd14-2r0-r sd14-2r5-r sd14-3r2-r sd25-3r3-r 1.5 2.0 2.5 3.2 3.3 0.039 0.045 0.060 0.066 0.038 2.91 2.56 2.29 2.00 2.21 5.2 5.2 1.45 5.2 5.2 1.45 5.2 5.2 1.45 5.2 5.2 1.45 4.8 4.8 2.5 sumida cdrh5d16np-3r3n cdrh5d16np-4r7n 3.3 4.7 0.045 0.064 2.60 2.05 5.6 5.6 1.8 5.6 5.6 1.8 tdk vlf5014st-2r2n2r3 vlcf5020t-2r7n2r2-1 vlcf5020t-3r3n2r0-1 2.2 2.7 3.3 0.073 0.083 0.096 2.3 2.2 2 4.8 4.6 1.4 5.0 5.0 2.0 5.0 5.0 2.0 toko 1124bs-1r8n 1124bs-3r3n 1.8 3.3 0.056 0.074 2.70 2.10 4.5 4.7 1.8 4.5 4.7 1.8 tokin h-di-0520-3r3 h-di-0630-3r8 3.3 3.8 0.062 0.040 2.00 2.00 5.3 5.3 2.0 6.3 6.3 3.0 wurth 744052002 7440420027 744053003 7440530047 2.5 2.7 3.0 4.7 0.030 0.047 0.024 0.030 2.4 2.2 2.8 2.4 5.8 5.8 1.8 4.8 4.8 1.8 5.8 5.8 2.8 5.8 5.8 2.8 inductor selection inductor selection criteria for the buck-boost are similar to those given for the step-down switching regulators. the buck-boost converter is designed to work with inductors in the range of 1h to 3.3h. for most applications use a 1.5h inductor. choose an inductor with a dc current rating at least two times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. if output short-circuit is a possible condition, the inductor should be rated to handle the maximum peak current specified for the buck-boost converter. table 10 shows several inductors that work well with the ltc3589 buck-boost regulator. table 10. buck-boost command register settings command register[bit] value setting scr1[6] 0* 1 continuous mode burst mode operation oven[3] 0* 1 disable enable scr2[3] ltc3589/ltc3589-1 0* 1 wait for output below 300mv before enable enable immediately scr2[3] ltc3589-2 0* 1 enable immediately wait for output below 300mv before enable * denotes default power-on value operation
ltc3589/ltc3589-1/ ltc3589-2 28 3589fe table 13. slewing dac command register control summary command register[bit] function vccr[0], vccr[2], vccr[4], vccr[6] voltage change control register g0 / slew write a 1 to initiate a slew to the voltage selected in vccr[1], vccr[3], vccr[5], vccr[7] respectively. bits are reset to 0 at the end of the slew operation. vccr[1], vccr[3], vccr[5], vccr[7] voltage change control register dynamic target select write a 0 to select voltage v1 stored in registers b1dtv1[4-0], b2dtv1[4-0], b3dtv1[4-0], l2dtv1[4-0]. write a 1 to select voltage v2 in registers b1dtv2[4-0], b2dtv2[4-0], b3dtv2[4-0], l2dtv2[4-0]. b1dtv1[4-0], b2dtv1[4-0], b3dtv1[4-0], l2dtv1[4-0] dynamic target voltage 1 five bits corresponding to v1 output from each dac. b1dtv1[5], b2dtv1[5], b3dtv1[5], l2dtv1[5] pgood mask write a 1 to continue normal pgood operation when slewing. write a 0 to force pgood to pull low during slew. b1dtv2[4-0], b2dtv2[4-0], b3dtv2[4-0], l2dtv2[4-0] dynamic target voltage 2 five bits corresponding to v2 output from each dac. vrrcr[1-0], vrrcr[3-2], vrrcr[5-4], vrrcr[7-6] voltage ramp rate control two bits that set the dac output slew rate for step-down switching regulator and ldo2. setting and slewing the dac outputs the 5-bit word in dynamic target voltage command reg- isters b1dtv1, b2dtv1, b3dtv1, and l2dtv1 programs reference voltage v1. the 5-bit word in command regis- ters b1dtv2, b2dtv2, b3dtv2, and l2dtv2 programs reference voltage v2. a resistor divider network on the output and feedback pins of the regulators set their output voltage. capacitor selection low esr ceramic capacitors should be used at both the output and input supply of the buck-boost switching regulator. only x5r or x7r ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. a 22f capacitor is sufficient for the buck-boost switch- ing regulator output. for good transient response and stability the output capacitor should retain at least 10f of capacitance over operating temperature and bias voltage. place at least 4.7f decoupling capacitance as close as possible to pv in4 pin. refer to table 12 for recommended ceramic capacitor manufacturers. table 12. ceramic capacitor manufacturers avx www.avxcorp.com murata www.murata.com taiyo yuden www.t-yuden.com vishay siliconix www.vishay.com tdk www.tdk.com slewing dac reference operation controlling the dac references the three ltc3589 step-down switching regulators and linear regulator ldo2 have programmable dac reference inputs. each dac is programmable from 0.3625v to 0.75v in 12.5mv steps: v out = 1 + r1 r2 ? (0.3625 + bxdtvx ? 0.0125)(v) the dac references may be commanded to independently slew between two voltages at one of four selectable slew rates. table 13 summarizes the command registers used to control slewing dac operation. operation
ltc3589/ltc3589-1/ ltc3589-2 29 3589fe figure 5. pushbutton controller state diagram operation writing a 0 or 1 to the odd bits of voltage change control register vccr selects dac output voltages v1 or v2, respectively. a slew of the dac is initiated by writing a 1 to an even bit of register vccr. the dac output will slew to either voltage, v1 or v2, as selected by the odd bits of register vccr. slew begins when the i 2 c stop condition is detected. at the end of the slewing operation the go bits in command register vccr are cleared. the slew rate for each regulator is set in the ramp rate control register vrrcr. each dac has independent output voltage registers, voltage register select, and slew rate and start controls. the regulators do not have to be enabled to change the dac outputs. the vstb pin is used to set the dac controlled output rails to a low power standby condition. when vstb is driven high, all four of the dac references will immediately slew to v2. to use vstb to set the rails to standby voltage, select v1 for normal rail voltages and v2 for standby rail voltages. drive vstb high to immediately slew all the dac outputs to v2. when vstb is driven low, the dac outputs will slew to v1. the default power-up value of all the dynamic target voltage registers is 11001 corresponding to a dac output volt- age of 0.675v. the dtv registers may be reprogrammed prior to initiating a power-up sequence or at any time for dynamic slewing. when a step-down switching regulator output is slewing down its mode is automatically switched to forced continu- ous to enable the regulator to sink current. when ldo2 is slewing down, a 2.5k pull-down is connected to its output. table 14 shows command register and feedback divider settings to enable slewing step-down switching regulator 1 between 1.2v and 1v in 70s. the voltage ramp rate control register bits vrrcr[1:0] are set to 01 which selects a ramp rate of 1.75mv/s at the dac output. the slew rate at the regulator output is a function of the feedback resistor divider gain. in this example, the slew is equal to 1.75 ? (1 + 301/499) = 2.8mv/s. therefore, a slew of 200mv will take 70s. to initiate a change from 1.2v to 1v write 11 to voltage change control register bits vccr[1:0]. vccr[1] selects target register b1dtv2 to set the regulator reference input to 0.625v. vccr[0] set to 1 initiates the dynamic slew to go to the new voltage. to slew back to 1.2v write 01 to command register bits vccr[1:0]. table 14. dynamic slewing example for step-down switching regulator 1 command register v out =1.2v v out =1v vrrcr[1:0] 01 01 dynamic slew rate vccr[1] 01 select dtv b1dt v1[4:0] 11111 11111 resistor divider shown in figure 3 r1 = 301k r2 = 499k b1dtv2[4:0] 10101 10101 pushbutton operation state event diagram figure 5 shows the ltc3589 pushbutton state diagram. upon the first power application to the ltc3589 v in pin an internal power-on reset circuit puts the pushbutton into the power-down (pdn) state and initiates a one second timer. the ltc3589 status pin rsto is pulled low until one second times out and the always-alive ldo1 is indicating power good status. after the one second interval the pushbutton circuit will transition to the power-off (poff) standby state. the ltc3589-1/ltc3589-2 powers on directly to the poff state bypassing the one second delay. status pin rsto will be released high when ldo1 indicates power good status. the ltc3589 will not leave the poff state and enter the 1 sec por 5 sec ltc3589 ltc3589-1/ltc3589-2 on or pwr_on fault or pwr_on or hard reset pup pon poff pdn 1 sec por 3589 f05 5 sec on or pwr_on fault or pwr_on or hard reset pup pon poff pdn
ltc3589/ltc3589-1/ ltc3589-2 30 3589fe operation power-up state (pup) until on is held low for at least 400ms (pb400ms) or until pwr_on is activated by the pwr_on pin. when the controller enters the pup state the open-drain wake pin releases high. the wake pin is typically used to enable the first regulator in a start-up sequence. the pushbutton state will stay in pup for five seconds before transitioning to the power-on (pon) state. before leaving pup , the pwr_on pin must be brought high by the application to indicate that the system rails are correct. if pwr_on is not active at the end of five seconds the pushbutton controller will continue directly through pon to the power-down (pdn) state and pull the wake pin down. three events will cause the pushbutton to leave the pon state: 1) lowering the pwr_on pin, 2) forcing a hard reset by holding the on pin low for five seconds, and 3) a fault condition is detected. fault condi- tions are low v in , device over temperature, or extended undervoltage of one of the regulator outputs. all regulator enables, the on input, and pwr_on signals are inhibited for one second while in the pdn state. after one second in pdn the pushbutton controller returns to poff. pbstat operation pbstat goes low 50ms after the initial pushbutton ap- plication ( on low) and will stay low for a minimum of 50ms. pbstat will go high coincident with on going high unless on goes high before the 50ms minimum on-time. power-up using the pushbutton when in the poff standby state, the ltc3589 is in com- plete shutdown except the always active ldo1 and any regulators enabled with the keep-alive control bits. pull the on pin to ground with a pushbutton for 400ms to begin a power-up sequence with the wake pin tied to an enable pin. drive pwr_on high within five seconds to signal the ltc3589 to remain in the power-on state. power-down using the pushbutton the pushbutton power-down operation is performed by the system microprocessor by monitoring the pbstat pin. once in the pon state, the system controller is responsible for deciding what action to take with a pushbutton event. when the on pin is held low for a 50ms debounce period, the pbstat pin is pulled low. the system controller should monitor the pbstat pin to determine the pushbutton has been pushed. if the controller decides that a power-down is desired, then it should drive the pwr_on pin low. power-up and down using pwr_on pin an alternate power-up method is to drive the pwr_on pin to a high state. after a delay of 50ms from the pwr_on signal, the wake pin will pull high to drive regulator en- able pins. when pwr_on is high for five seconds, the sequence controller will enter the pon state. to power down, drive the pwr_on pin low. 50ms later wake will pull low, all enabled regulators are disabled and the oven command register is reset to 0x00. hard reset using the pushbutton when the on pin is pulled low for five seconds, a hard reset is initiated. at the end of five seconds, wake is pulled low, the i 2 c command registers are reset to por states, enable pin states are ignored, and the one second power-down timer is started. during the power-down time, the enables continue to be ignored to allow the regulator outputs to discharge. the rsto pin is pulled low for the power-down time to indicate a pushbutton hard reset occurred. if the pwr_on pin is low at the end of the one second power-down time, the ltc3589 will remain in standby mode. if pwr_on is high at the end of one second and there are no fault conditions, the ltc3589 will power-up in the same way shown in figure 8. hard reset due to a fault condition a hard reset due to v in undervoltage, extended undervolt- age of an output rail, or an overtemperature condition initiates a hard shutdown of the ltc3589. when the fault occurs, wake is pulled low, the i 2 c command registers are reset to por states, enable pin inputs are ignored, and the one second power-down timer is started. dur- ing the power-down time, the enables continue to be ignored to allow the regulator outputs to discharge. if the pwr_on pin is low at the end of the power-down time, the ltc3589 will remain in standby mode with just the
ltc3589/ltc3589-1/ ltc3589-2 31 3589fe figure 11. pin-strap start-up sequence application circuit on (pb) pbstat fault wake pwr_on clirq irq 3589 f10 c/p control <1 sec figure 10. hard reset due to a fault condition operation figure 6. power-up using the pushbutton pbstat wake pwr_on 3589 f06 on (pb) c/p control 400ms <5 sec figure 9. hard reset using the pushbutton pbstat wake pwr_on rsto 3589 f09 on (pb) c/p control 50ms 1 sec 5 sec figure 7. power down using pushbutton figure 8. power-up and down using pwr_on pin 3589 f11 en1 en2 en3 en4 en_ldo2 en_ldo34 on pwr_on ltc3589 pwr_on wake sw1 sw2 sw3 bb_out ldo2 ldo3 ldo4 1v to 1.2v v in 1.8v 0.8v to 1v 3.3v 1.2v 1.8v 2.8v always-active ldo operating. if pwr_on is high at the end of one second and the fault condition has cleared, the ltc3589 will power-up in the same way shown in figure 8. neither irq nor the status registers are cleared by the fault induced shutdown. enable and power-on sequencing enable input pin operation the regulator enable input pins facilitate pin-strapping an output rail to the enable pin of the next regulator in the desired sequence. the regulator enable inputs normally have a 0.8v (typical) input threshold. if any enable is driven high, the remaining enable input thresholds switch to a more accurate 500mv (typical) threshold. figure 11 shows an application circuit for a typical pin- strapped start-up sequence. holding on low for 400ms brings up the wake pin that is tied to en1 and en3 to en- able step-down switching regulators 1 and 3. the output of regulator 1 is tied to en2 and en4 that enables step-down switching regulator 2 and the buck-boost switching regu- lator 4. the output of step-down switching regulator 2 is tied to en_ldo2 and en_ldo34 to enable ldo2, ldo3 and ldo4. within five seconds of wake going high, the microprocessor or microcontroller must drive pwr_on high to tell ltc3589 that rails are good and to stay in the power-on state. pbstat wake pwr_on 3589 f08 on (pb) c/p control 50ms 5 sec 50ms - ltc3589 2ms - ltc3589-1/ltc3589-2 pbstat wake 3589 f07 on (pb) 50ms <5 sec pwr_on c/p control 50ms - ltc3589 2ms - ltc3589-1/ ltc3589-2
ltc3589/ltc3589-1/ ltc3589-2 32 3589fe operation figure 12 shows the start-up timing for the application shown in figure 11. there is a 200s (typical) delay between the enable pin and the internal enable signal to each regulator. less of the status of pwr_on and wake. writing a 1 to a regulators keep-alive bit in its dynamic target voltage register will keep a regulator alive when the ltc3589 is in standby (poff) mode. a regulator with its keep-alive bit set will stay enabled until the bit is reset writing the bit low, resetting the ltc3589 with a pushbutton hard reset, or a fault condition (uvlo, pgood, timeout or thermal shutdown) occurs. pgood and fault status are reported in the irqstat and pgstat registers and on the irq and pgood pins for keep-alive regulators when pwr_on and wake are low. software control mode once a power-up sequence is completed each regulator may be enabled and disabled individually by the system as needed for power mode requirements. setting the out- put voltage enable command register bit oven[7] high disconnects each regulator from its enable pin so control is solely through the oven command register. to enter software control mode, set command bit oven[7] high and the desired enable bits in oven[6:0] high. any of the regulators enabled in oven[6:0] will stay on regardless of the state of their enable pins when oven[7] is high. set- ting the regulator enable bits and the software control bit in oven[7] may occur on the same i 2 c start-stop sequence. a normal shutdown using pwr_on resets all eight bits of the oven register to 0x00 to ensure all regulators are shut off. fault detection, shutdown, and reporting the ltc3589 monitors v in , output rail voltages and internal die temperature. a warning condition is indicated when v in is less than 2.9v and when internal die temperature approaches the thermal shutdown temperature. a fault condition occurs when v in is less than 2.6v, any regulator output is 8% low for 14ms, or the internal die temperature is high. warning and fault states are reported via the irq , pgood, and rtso pins. specific fault states are read via the i 2 c serial port status registers irqstat and pgstat. to help ensure startup sequencing, the ltc3589 is de- signed to block the internal enable of a regulator until its output has discharged to less than 300mv. the i 2 c system control register 2 (scr2) controls whether the ltc3589 waits or enables immediately. the por default setting for the ltc3589 and ltc3589-1 is to wait for the output to be less than 300mv before enabling. the output discharge resistors on the ltc3589 and ltc3589-1 regulators are tied to the settings in scr2. for use in systems that might back drive the regulator outputs higher than 300mv, the ltc3589-2 por default setting is to always enable regardless of output voltage and to always engage the discharge resistors whenever the regulator is not enabled. keep-alive operation for systems which require an active supply rail when in system standby, any of the three ltc3589 step-down switching regulators or ldo2 may be kept alive regard- v1 v3 v2 v4 ldo2 ldo3 ldo4 3589 f12 wake 1.8v 2.8v 1.2v 3.3v 0.5v 0.5v 1.8v 1v 1.2v 200s 200s 200s figure 12. pin-strap sequencing timing
ltc3589/ltc3589-1/ ltc3589-2 33 3589fe figure 14. pgood pin and pgstat status register timing v outx pgood irq 3589 f14 enx 200s 25s 25s 1sec 14ms 250s 250s enable disable undervoltage disabled if wake low wake high after 1sec if pwr_on high extended undervoltage (fault) wake 250s figure 13. initial power-up and ldo1 undervoltage rsto timing rsto pin function the rsto (reset output) pin is an open-drain output for use as a power-on reset signal. it is pulled low at initial power until ldo1 is within 8% of its target and the initial one second start-up timer is finished. rsto remains high during normal operation and will be pulled low if ldo1 loses regulation for more than 25s or a pushbutton hard reset is initiated. rsto is released high 14ms after ldo1 returns to regulation. figure 13 shows a initial power-up for the rsto pin. if v in is not above its undervoltage thresholds at the end of the 1 second start-up time, the irq pin will be pulled low and an undervoltage bit will be set in the irqstat status register. voltage for longer than 25s (typical), the pgood pin is pulled low and the appropriate bit in the pgstat status register (table 15) is set. table 15. pgstat read-only register bit definitions pgstat[bit] value setting 00 1 ldo1_stby output low ldo1_stby output good 10 1 step-down switching regulator 1 output low step-down switching regulator 1 output good 20 1 step-down switching regulator 2 output low step-down switching regulator 2 output good 30 1 step-down switching regulator 3 output low step-down switching regulator 3 output good 40 1 buck-boost regulator 4 output low buck-boost regulator 4 output good 50 1 ldo2 output low ldo2 output good 60 1 ldo3 output low ldo3 output good 70 1 ldo4 output low ldo4 output good figure 14 shows the pgood pin and pgstat status reg- ister timing. when no regulator is enabled, the pgood pin is pulled low and pgstat bits are low. pgood and the pgstat bits are high 250s after the last enabled regulator is within 7% of its target. pgood pin and pgstat status register function each ltc3589 regulator has an internal power good out- put that is active whenever the regulators feedback pin is closer than 7% (typical) from its input reference voltage. if any of the internal power good signals indicate a low operation ldo1 rsto v in 2.7v C8% 1 sec initial power-up ltc3589 ldo1 undervoltage 25s 14ms 3589 f13 ldo1 rsto v in C8% initial power-up ltc3589-1/ltc3589-2 ldo1 undervoltage 25s 14ms 14ms
ltc3589/ltc3589-1/ ltc3589-2 34 3589fe operation figure 16. irq and irqstat status register warning timing irq irqstat clirq 3589 f16 tsd or uv warning if any enabled regulator output falls more than 7% low for longer than 25s pgood is pulled low and a cor- responding status bit in the pgstat register is set to 0. the pgood pin and pgstat status bit remain low for as long as the low voltage condition persists plus 250s. an extended low output rail causing the pgood pin to be low for longer than 14ms defines a pgood timeout fault condition that triggers a hard reset if not masked in i 2 c register bit scr2[7]. when scr2[7] is high, pgood remains in normal operation. during a dynamic voltage slew, pgood is pulled low unless bit 5 in the dynamic target voltage register for each regulator is set high. the status register pgstat is unaffected by a dynamic voltage slew. undervoltage detection the ltc3589 undervoltage (uv) detection circuit will out- put a fault condition, locking out regulator operation, until v in reaches 2.7v. once v in is above 2.7v the ltc3589 will operate normally until v in drops to 2.55v (typical). when v in drops below 2.55v, the fault condition initiates a hard shutdown reset. figure 15 shows undervoltage warning and fault detection levels. thermal shutdown fault and warning similar to the v in undervoltage detection circuits the over- temperature detection circuits check for warning and fault levels. an overtemperature fault will initiate a fault induced shutdown. an overtemperature warning sets register bit irqstat[6] and pulls the irq pin low. irq pin and irqstat status register function the irq pin and irqstat status register report pgood timeout fault, v in undervoltage warning and fault, and high temperature warning and fault. table 16 shows the meaning of the irqstat read-only status register bits. table 16. irqstat read-only register bit definitions irqstat[bit] value setting 31 pgood timeout fault (pgood low > 14ms) 41 v in undervoltage warning (v in < 2.9v) 51 v in undervoltage fault (v in < 2.6v) 61 thermal limit warning (t j > 130c) 71 thermal limit fault (t j > 150c) figure 16 shows the timing of the irq and irqstat status register following a warning (v in <2.9v or high temperature warning) event. when a warning occurs, irq is latched low and bit irqstat[4] or irqstat[5] is set. irq remains low and the irqstat status bits remain active until the i 2 c clirq command is given and the warning condition has passed. figure 15. uv detection hard reset and warning levels v in undervoltage v in fault warning 3589 f15 2.55v 2.65v 2.9v 3v an undervoltage warning sets register bit irqstat[4] and pulls the irq pin low. to minimize standby quiescent current the uvlo and thermal sensor circuits are disabled when all the regula- tors are off.
ltc3589/ltc3589-1/ ltc3589-2 35 3589fe figure 17. irq and irqstat status register fault timing irq irqstat clirq 3589 f17 tsd, uv, or pgood fault 1 sec 1 sec figure 19. ltc3589 i 2 c serial port multiple write pattern 123456789 0 1 1 0 1 0 0 wr s7 s6 s5 s4 s3 s2 s1 s0 d7 d6 d5 d4 d3 d2 d1 d0 s7 s6 s5 s4 s3 s2 s1 s0 d7 d6 d5 d4 d3 d2 d1 d0 123456789123456789123456789123456789 scl address sub address data sub address data 3589 f19 ack ack ack ack ack 0 110 000 1 start sda stop figure 18. ltc3589 i 2 c timing t su, dat t hd, sta t hd, dat sda scl t hd, sta t hd, sta t su, sto 3589 f18 t buf t low t high start condition repeated start condition stop start t r t f t sp operation figure 17 shows the timing of the irq pin and irqstat status register following a fault induced hard shutdown event. when a fault occurs, irq is latched low and bit irqstat[3], irqstat[5], or irqstat[7] is set. irq re- mains low until the clirq command is issued. when the clirq command has been issued, the irqstat status bit remains set for the one second enable inhibit time or as long as the fault condition persists, whichever is longer. fault induced shutdown any of the three fault conditions will initiate a hard reset shutdown triggering the following events: 1) a bit corre- sponding to the fault is set in status register irqstat, 2) irq and wake pins are pulled low, 3) enable pin inputs are ignored and the regulators are disabled, 4) all enable bits and software control mode bit in the output voltage enable oven command register are cleared, and 5) the pushbutton controller is sent to the pdn state for one second and then to poff. re-enabling of regulators is inhibited until both the fault condition and the one second time out have passed to allow regulator outputs sufficient time to discharge. when one second timeout and the fault condition are both passed, if pwr_on is high, wake will come up and the ltc3589 will respond to any enable pins that are also high.
ltc3589/ltc3589-1/ ltc3589-2 36 3589fe i 2 c operation i 2 c interface the ltc3589 communicates with a bus master using the standard i 2 c 2-wire interface. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 smbus accelerator, are required on these lines. the ltc3589 is both a slave receiver and slave transmitter. the i 2 c control signals, sda and scl are scaled internally to the dv dd supply. dv dd should be connected to the same power supply as the bus pull-up resistors. the i 2 c port has an undervoltage lockout on the dv dd pin. when dv dd is below approximately 1v, the i 2 c serial port is reset to power-on states and registers are set to default values. i 2 c bus speed the i 2 c port operates at speeds up to 400khz. it has built-in timing delays to ensure correct operation when addressed from an i 2 c compliant master device. it also contains input filters designed to suppress glitches should the bus become corrupted. i 2 c start and stop conditions a bus master signals the beginning of communications by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. the master may transmit either the slave write or the slave read address. once data is written to the ltc3589, the master may transmit a stop condition that commands the ltc3589 to act upon its new command set. a stop condition is sent by the master by transition- ing sda from low to high while scl is high. the bus it then free for communication with another i 2 c device. i 2 c byte format each byte sent to or received from the ltc3589 must be 8 bits long followed by an extra clock cycle for the acknowledge bit. the data should be sent to the ltc3589 most significant bit (msb) first. i 2 c acknowledge the acknowledge signal is used for handshaking between the master and the slave. when the ltc3589 is written to, it acknowledges its write address and subsequent register address and data bytes. when reading from the ltc3589, it acknowledges its read address and 8-bit status byte. an acknowledge pulse (active low) generated by the ltc3589 lets the master know that the latest byte of information was transferred. the master generates the clock cycle and releases the sda line (high) during the acknowledge clock cycle. the ltc3589 pulls down the sda line during the write acknowledge clock pulse so that it is a stable low during the high period of this clock pulse. i 2 c slave address the ltc3589 responds to factory programmed read and write addresses. the write address is 0x68. the read ad- dress is 0x69. the least significant bit of the address byte, known as the read/write bit, is 0 when writing data to the ltc3589 and 1 when reading from it. operation figure 20. ltc3589 i 2 c serial port read pattern ack ack ack ack start stop 1 0 23 11 address 4 0 5678 000 9123456789 12345678 01101001 9123456789 1 01 1 0 100wr start sda scl sub address s7 s6 s3 s4 s5 s2 s1 s0 address 01 1 0 100rd data r7 r6 r3 r4 r5 r2 r1 r0 3589 f20
ltc3589/ltc3589-1/ ltc3589-2 37 3589fe operation i 2 c sub-addressed writing the ltc3589 has 14 command registers for control inputs. they are accessed by the i 2 c port via a sub-addressed writing system. each write cycle of the ltc3589 consists of a series of three or more bytes beginning with the ltc3589 write address. the second byte is the sub address of the command reg- ister being written to. the sub address is a pointer to the register where the data in the third byte will be stored. the third byte is the data to be written to the just-received sub address. continue alternating sub address and data bytes to write multiple registers in a single start sequence. i 2 c bus write operation the master initiates communication with the ltc3589 with a start condition and the ltc3589 write address. if the address matches that of the ltc3589, the ltc3589 returns an acknowledge pulse. the master should then deliver the sub address. again the ltc3589 acknowl- edges and the cycle is repeated for the data byte. the data byte is transferred to an internal holding latch upon the return of its acknowledge by the ltc3589. continue writing sub address and data pairs into the holding latches. addressing the ltc3589 is not required for each sub address and data pair. if desired a repeat- start condition may be initiated by the master where another device on the i 2 c bus is addressed. the ltc3589 remembers the valid data it has received. once all the devices on the i 2 c have been addressed and sent valid data and a global stop has been sent, the ltc3589 will update its command latches with the data it has received. i 2 c sub-addressed reading the ltc3589 i 2 c interface supports random address reading of the i 2 c command and status registers. before reading a register, the registers sub address must be written. send a start condition followed by the ltc3589 write address followed by the sub address of the register to be read. the sub address is now stored as a pointer to the register. send a repeat-start condition followed by the ltc3589 read address. following the acknowledg- ment of its read address the ltc3589 returns one bit of information for each of the next 8 clock cycles. a stop condition is not required for the read operation. the read sub address is stored until a new sub address is written. verify the data written to the internal data hold latches prior to committing date to the command registers by reading back the data before sending a stop condition. continuously poll a register by repeatedly sending a start condition followed by the ltc3589 read address, and then clocking the data out after the read address acknowledge. i 2 c command and status registers table 17 and table 18 show the ltc3589 i 2 c command and status registers. system control register (scr1) sets the operating modes of the switching regulators. each step-down switching regulator has pulse-skipping, burst mode operation, or forced continuous operation. the buck-boost switching regulator can be put in continuous or burst mode operation. the output voltage enable (oven) command register controls the individual enables of each regulator. when oven[7] is set to a logic low value, bits oven[6-0] are ored with their respective enable pins. when oven[7] is high, the input pins en1, en2, en3, en4, en_ldo2, and en_ldo34, are ignored and the ltc3589 regulators respond only to the oven register. when the regulators are configured in a hard wired power-up sequence, setting oven[7] allows software control of individual regulators. when the pwr_on pin is pulled low all bits in the oven register are reset to por state of 0x00. system control register 2 (scr2) controls the operation of the regulator start-up and regulator power good (pgood) hard shutdown operation. command register bit scr2[7] controls the ltc3589 behavior during an extended pgood fault condition longer than 14ms. bit scr2[7] does not alter pgood status reporting by the irq pin or irqstat status register. the bits in scr2[6-0] control whether a regulator will wait to turn on when its output is greater than 300mv. default por low cause the ltc3589 and ltc3589-1 regulators to wait for the output to discharge to less than 300mv. default por low of the ltc3589-2 allows the regulators to start at any output voltage.
ltc3589/ltc3589-1/ ltc3589-2 38 3589fe operation table 17. ltc3589 command register table reg name b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] default 0x07 scr1 buck-boost mode: 0 = continuous 1 = burst mode step-down switching regulator 3 mode : 0 0 = pulse-skipping 0 1 = burst 1 0 = forced continuous step-down switching regulator 2 mode : 0 0 = pulse-skipping 0 1 = burst 1 0 = forced continuous step-down switching regulator 1 mode : 0 0 = pulse-skipping 0 1 = burst 1 0 = forced continuous 0000 0000 0x10 oven software control mode: 0 = enable with pin or oven register 1 = enable/ disable with oven register only en_ldo4 en_ldo3 en_ldo2 en4 en3 en2 en1 0000 0000 0x12 ltc3589 scr2 mask pgood hard shutdown: 0 = allow pgood timeout hard shutdown. 1 = inhibit pgood hard shutdown. ldo4 start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. ldo3 start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. ldo2 start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. buck-boost start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. step-down switching regulator 3 start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. step-down switching regulator 2 start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. step-down switching regulator 1 start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. 0000 0000 0x12 ltc3589-1 scr2 mask pgood hard shutdown: 0 = inhibit pgood timeout hard shutdown. 1 = allow pgood hard shutdown. ldo4 start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. ldo3 start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. ldo2 start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. buck-boost start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. step-down switching regulator 3 start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. step-down switching regulator 2 start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. step-down switching regulator 1 start-up: 0 = wait for output < 300mv before enable 1 = dont wait and disable discharge resistor. 0000 0000
ltc3589/ltc3589-1/ ltc3589-2 39 3589fe operation table 17. ltc3589 command register table reg name b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] default 0x12 ltc3589-2 scr2 mask pgood hard shutdown: 0 = allow pgood timeout hard shutdown. 1 = allow pgood hard shutdown. ldo4 start-up: 0 = dont wait for output < 300mv before enable 1 = wait for output < 300mv before enable ldo4 start-up: 0 = dont wait for output < 300mv before enable 1 = wait for output < 300mv before enable ldo4 start-up: 0 = dont wait for output < 300mv before enable 1 = wait for output < 300mv before enable ldo4 start-up: 0 = dont wait for output < 300mv before enable 1 = wait for output < 300mv before enable ldo4 start-up: 0 = dont wait for output < 300mv before enable 1 = wait for output < 300mv before enable ldo4 start-up: 0 = dont wait for output < 300mv before enable 1 = wait for output < 300mv before enable ldo4 start-up: 0 = dont wait for output < 300mv before enable 1 = wait for output < 300mv before enable 0000 0000 0x20 vccr ldo2 reference select: 0 = l2dtv1[4-0] 1 = l2dtv2[4-0] start ldo2 slew: 0 = went 1 = go step-down switching regulator 3 reference select: 0 = b3dtv1[4-0] 1 = b3dtv2[4-0]2 start step-down switching regulator 3 slew: 0 = went 1= go step-down switching regulator 2 reference select: 0 = b2dtv1[4-0] 1 = b2dtv2[4-0] start step-down switching regulator 2 slew: 0 = went 1= go step-down switching regulator 1 reference select: 0 = b1dtv1[4-0] 1 = b1dtv2[4-0]2 start step-down switching regulator 1 slew: 0 = went 1= go 0000 0000 0x21 clirq 0x23 b1dtv1 step-down switching regulator switch dv/dt control: 00 = 1ns 01 = 2ns 10 = 4ns 11 = 8ns pgood mask: 0 = pgood low when slewing 1 = pgood not forced low when slewing. step-down switching regulator 1 feedback reference input (v1) 00000 = 362.5mv 11001 = 675mv 11111 = 750mv 12.5mv step size 0001 1001 0x24 b1dtv2 keep-alive mode: 0 = normal shutdown 1 = keep-alive phase select: 0 = clock phase 1 1 = clock phase 2 step-down switching regulator 1 clock rate 0 = 2.25mhz 1 = 1.12mhz step-down switching regulator 1 feedback reference input (v2) 00000 = 362.5mv 11001 = 675mv 11111 = 750mv 12.5mv step size 0001 1001 0x25 vrrcr ldo2 dynamic reference slew rate: 00 = 0.88mv/s 01 = 1.75mv/s 10 = 3.5mv/s 11 = 7mv/s step-down switching regulator 3 dynamic reference slew rate: 00 = 0.88mv/s 01 = 1.75mv/s 10 = 3.5mv/s 11 = 7mv/s step-down switching regulator 2 dynamic reference slew rate: 00 = 0.88mv/s 01 = 1.75mv/s 10 = 3.5mv/s 11 = 7mv/s step-down switching regulator 1 dynamic reference slew rate: 00 = 0.88mv/s 01 = 1.75mv/s 10 = 3.5mv/s 11 = 7mv/s 1111 1111
ltc3589/ltc3589-1/ ltc3589-2 40 3589fe operation table 17. ltc3589 command register table reg name b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] default 0x26 b2dtv1 unused pgood mask: 0 = pgood low when slewing 1 = pgood not forced low when slewing. step-down switching regulator 2 feedback reference input (v1) 00000 = 362.5mv 11001 = 675mv 11111 = 750mv 12.5mv step size 0001 1001 0x27 b2dtv2 keep-alive mode: 0 = normal shutdown 1 = keep-alive phase select: 0 = clock phase 1 1 = clock phase 2 step-down switching regulator 2 clock rate 0 = 2.25mhz 1 = 1.125mhz step-down switching regulator 2 feedback reference input (v2) 00000 = 362.5mv 11001 = 675mv 11111 = 750mv 12.5mv step size 0001 1001 0x29 b3dtv1 unused pgood mask: 0 = pgood low when slewing 1 = pgood not forced low when slewing. step-down switching regulator 3 feedback reference input (v1) 00000 = 362.5mv 11001 = 675mv 11111 = 750mv 12.5mv step size 0001 1001 0x2a b3dtv2 keep-alive mode: 0 = normal shutdown 1 = keep-alive phase select: 0 = clock phase 1 1 = clock phase 2 step-down switching regulator 3 clock rate 0 = 2.25mhz 1 = 1.125mhz step-down switching regulator 3 feedback reference input (v2) 00000 = 362.5mv 11001 = 675mv 11111 = 750mv 12.5mv step size 0001 1001 0x32 l2dtv1 keep-alive mode: 0 = normal shutdown 1 = keep-alive unused pgood mask: 0 = pgood low when slewing 1 = pgood not changed when slewing. ldo 2 feedback reference input (v1) 00000 = 362.5mv 11001 = 675mv 11111 = 750mv 12.5mv step size 0001 1001
ltc3589/ltc3589-1/ ltc3589-2 41 3589fe table 18. ltc3589 read-only status register table reg name b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] 0x02 irqstat thermal limit hard shutdown occurred near thermal limit undervoltage hard shutdown occurred near undervoltage limit pgood timeout hard shutdown occurred unused unused unused 0x13 pgstat ldo4 status: 0 = v out low 1 = v out good ldo3 status: 0 = v out low 1 = v out good ldo2 status: 0 = v out low 1 = v out good buck_boost status: 0 = v out low 1 = v out good step-down switching regulator 3 status: 0 = v out low 1 = v out good step-down switching regulator 2 status: 0 = v out low 1 = v out good step-down switching regulator 1 status: 0 = v out low 1 = v out good ldo1 status: 0 = v out low 1 = v out good table 17. ltc3589 command register table reg name b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] default 0x33 ltc3589 l2dtv2 ldo4 control mode: 0 = ldo4 enable with en_ldo34 1 = ldo4 enable with oven[6] ldo4 output voltage: 00 = 2.8v 01 = 2.5v 10 = 1.8v 11 = 3.3v ldo 2 feedback reference input (v2) 00000 = 362.5mv 11001 = 675mv 11111 = 750mv 12.5mv step size 0001 1001 0x33 ltc3589-1 ltc3589-2 l2dtv2 unused ldo4 output voltage: 00 = 1.2v 01 = 1.8v 10 = 2.8v 11 = 3.2v ldo 2 feedback reference input (v2) 00000 = 362.5mv 11001 = 675mv 11111 = 750mv 12.5mv step size 0001 1001 operation
ltc3589/ltc3589-1/ ltc3589-2 42 3589fe ldo2 and step-down switching regulators 1 to 3 each have a pair of control bits in the voltage change control register vccr. the reference select bit selects which of two 5-bit words are used as inputs to the regulators feedback refer- ence dac inputs. the slew go bit initiates a dac slew to the voltage selected by the reference select bit. when the slew is complete, the slew go bits are reset low. accessing the clirq command register will clear the irq pin and will let the irq pin to release high. the pin is cleared when the ltc3589 acknowledges the sub address. data written to the clirq command register is ignored. there are eight command registers that are used to store the 5-bit dynamic target voltage input to the feedback reference slewing dacs C b1dtv1, b1dtv2, b2dtv1, b2dtv2, b3dtv1, b3dtv2, l2dtv1 and l2dtv2. the registers ending with v2 use bits 4 through 0 to store the v2 feedback reference voltage for the regulators. the regulators input reference voltage is set to v2 by setting the reference select bits high in vccr and writing to the go bits in vccr. the v2 voltage is also selected whenever the vstb pin is driven high. the registers ending with v1 use bits 4 through 0 to store the v1 feedback voltage reference for the regulators. the regulators input refer- ence voltage is set to v1 voltage by setting the reference select bits low in command register vccr. whenever a new dynamic target voltage is set, either by changing the 5-bit value or by changing the reference select bits in vccr, the go bits in vccr must be written to initiate the dynamic voltage slew. when bit 5 in b1dtv1, b2dtv1, b3dtv1, and l2dtv1 is low the pgood pin pulls low during a dynamic voltage slew. bits 7 and 6 in b1dtv1 set the switch dv/dt rate for all the step-down switch- ing regulators. bit 5 in registers b1dtv2, b2dtv2 and b3dtv2 selects the switching frequency of step-down switching regulators 1, 2 and 3. writing the bit low sets the switching frequency to 2.25mhz. writing the bit high sets the switching frequency to 1.125mhz. the dynamic slew rates of the four feedback reference dacs are independently set using bits in voltage ramp rate command register (vrrcr). the rate shown is the slew of the dac output as it slews up or down to its target value. the slew rate of the output voltage is scaled by the gain of the resistor divider network that sets the regulator output voltage. for example, a regulator set to an output voltage of 1.2v when the dynamic target voltage reference is 0.75v has a gain of 1.6. slewing the regulator output from 1.2v to 1v requires slewing the dac output down 125mv from 750mv to 625mv. with a vrrcr slew rate setting of 01 the slew time of the regulator output is 71s. thermal considerations and board layout printed circuit board power dissipation in order to ensure optimal performance and the ability to deliver maximum output power to any regulator, it is critical that the exposed ground pad on the backside of the ltc3589 package be soldered to a ground plane on the board. the exposed pad is the only gnd connection for the ltc3589. correctly soldered to a 2500mm 2 ground plane on a double sided 1oz copper board the ltc3589 has a thermal resistance ( ja ) of approximately 34c/w. failure to make good thermal contact between the exposed pad on the backside of the package and an adequately sized ground plane will result in thermal resistances far greater than 34c/w. to ensure the junction temperature of the ltc3589 die does not exceed the maximum rated limit and to prevent overtemperature faults, the power output of the ltc3589 must be managed by the application. the total power dissipation in the ltc3589 is approximated by summing the power dissipation in each of the switching regulators and the ldo regulators. the power dissipation in a switching regulator is esti- mated by: p d(swx ) = (v outx ?i outx )? 100 C eff 100 where v outx is the programmed output voltage, i outx is the load current and eff is the % efficiency that can be measured or looked up in an efficiency table for the programmed output voltage. operation
ltc3589/ltc3589-1/ ltc3589-2 43 3589fe operation the power dissipated by an ldo regulator is estimated by: p d(ldox) = (v in(ldox) Cv ldox )?i ldox where v ldox is the programmed output voltage, v in(ldox) is the ldo supply voltage, and i ldox is the output load current. if one of the switching regulator outputs is used as an ldo supply voltage, remember to include the ldo supply current in the switching regulator load current for calculating power loss. an example using the equations above with the parameters in table 19 shows an application that is at the maximum junction temperature of 125c at an ambient temperature of 85c. ldo2, ldo3, and ldo4 are powered by step- down switching regulator 2 and the buck-boost switching regulator. the total load on those two switching regula- tors is the sum of the application load and the ldo load. this example is with the ldo regulators at one half rated current and the switching regulators at three quarters rated current. table 19. t j calculation example output v in v out app load total load eff power diss ldo1_vstb 3.8v 1.2v 10ma 10ma 30mw ldo2 1.8v 1.2v 100ma 100ma 60mw ldo3 3.3v 1.8v 100ma 100ma 150mw ldo4 3.3v 2.5v 100ma 100ma 80mw v out1 3.8v 1.2v 1.2a 1.2a 80% 290mw v out2 3.8v 1.8v 0.65a 0.75a 90% 140mw v out3 3.8v 1.25v 0.75a 0.75a 85% 140mw v out4 3.8v 3.3v 0.70a 0.90a 90% 300mw total power 1180mw internal junction temperature at 85c ambient 125c printed circuit board layout when laying out the printed circuit board, the following checklist should be followed to ensure proper operation of the ltc3589: 1. connect the exposed pad of the package (pin 41) directly to a large ground plane to minimize thermal and electrical impedance. 2. the switching regulator input supply traces and their decoupling capacitors should be as short as possible. connect the gnd side of the capacitors directly to the ground plane of the board. the decoupling capacitors provide the ac current to the internal power mosfets and their drivers. it is important to minimize inductance from the capacitors to the ltc3589 pins. 3. minimize the switching power traces connecting sw1, sw2, sw3, and buck-boost switch pins sw4ab and sw4cd to the inductors to reduce radiated emi and parasitic coupling. keep sensitive nodes such as the feedback pins away from or shielded from the large voltage swings on the switching nodes. 4. minimize the length of the connection between the step-down switching regulator inductors and the output capacitors. connect the gnd side of the output capaci- tors directly to the thermal ground plane of the board. 5. minimize the length of the connection between the buck-boost regulator output (bb_out) and the output capacitor. connect the gnd side of the output capacitor directly to the thermal ground plane of the board.
ltc3589/ltc3589-1/ ltc3589-2 44 3589fe applications information the ltc3589 is optimized to support several families of advanced portable applications processors including the marvell pxa3xx and pxa168 xscale processors, the fre- escale i.mx family including the new i.mx53 and i.mx51, the ti omap processors utilizing their smart reflex, and many additional arm processors. pxa3xx monahans processor support the pxa3xx processors are hard-coded to communicate with a pmic at specific command register addresses in order to power up the processor supply rails from the low power state. the ltc3589 i 2 c device address and command register addresses map to pxa3xx command register sub-address requirements. the ltc3589 write address is 0x68. the key command register addresses for pxa3xx support are the output voltage enable (oven) register at address 0x10. vcc_apps/a_en is mapped to oven bit 0 (enable step-down switching regulator 1). vcc_sram/s_en is mapped to oven bit 2 (enable step- down switching regulator 3). the voltage change control register (vccr) at command register address 0x20 con- trols the dynamic voltage select and go bits required to command a voltage change and slew when coming out of low voltage standby or sleep modes into run mode. the dynamic target voltage (xxdtv[1,2]) registers map to the mandatory command register addresses. the full register map for the ltc3589 shown in table 16 and table 17 supports monahans, hard-coded i 2 c commands for start-of-day operation, voltage-change sequence, supply enable, and return-to-d0 state sequence. the ltc3589 does not specifically reference the mona- hans sys_en and pwr_en enable pins but supports these signals with individual enable input pins en[1-4] and en_ldo[2,34] that should be hard-wired to sys_en or pwr_en as required for proper system-level power sequencing. the ltc3589 rsto signal is used to drive the monahans hard reset signal nreset and is based on the state of the always-active regulator output ldo1_stby and by a pushbutton hard reset request. the release of the rsto output is delayed a minimum of 10ms as required or as long as 1s when the ltc3589 is reset using its pushbut- ton controller. pxa16x armada processor support ltc3589 includes spare register bits that can be accessed by the processor for setting and recalling hibernate and resume operation. the keep-alive function allow a step-down switching regulator to maintain system memory during a hibernate shutdown state of the armada processor. i.mx53 and i.mx51 processor support the ltc3589 has hardware features specifically designed for the latest i.mx family of processors from freescale semiconductor. the i.mx53 and i.mx51 control the vstb input pin of the ltc3589 to command transitions between the run mode core voltage and the lower level standby voltage. the run and standby voltage levels are initially programmed in i 2 c command registers xxbtv1 and xxbtv2. when the vstb pin is asserted high all four dynamically controlled output supply rails will slew to the xxbtv2 set point. when xxbtv1 and xxbtv2 are set at the same value, as they are by default, then no slewing occurs. this allows the single vstb pin to control any combination of the four dac controlled regulators to slew between two programmed output voltages. when vstb is de-asserted back to a zero value the regulators slew back up to the xxbtv1 set point.
ltc3589/ltc3589-1/ ltc3589-2 45 3589fe applications information earlier i.mx family processors such as the i.mx31 included two vstb pins used for controlling the regulator outputs for a low voltage standby mode, nominal voltage run mode, and a higher voltage overdrive mode. the ltc3589 can be used with these processors using the vstb input pin to select between run and standby voltages and using minimal software overhead to set the overdrive voltage in i 2 c command registers. the default dac reference value in all xxbtvx registers is 0x19. this accommodates i.mx processors and others requiring an overdrive voltage. the value can be increased up to 0x1f for overdrive or supply margining above the nominal run voltage. once programmed into the i 2 c com- mand registers xxbtvx two voltage outputs are selected by the vstb pin. all voltage levels and changes are fully controllable using the i 2 c serial port. reference designs and drivers reference designs, schematics, and software drivers are available to assist the development of freescale i.mx53 systems that use the ltc3589. please contact your local linear technology sales representative for details. omap3 and davinci processor support the omap3 family of arm processors has similar require- ments to the processors described above. the ltc3589 i 2 c control can fully accommodate the smart reflex dynamic voltage control with proper embedded software drivers tailored to the ltc3589 register mapping. the ltc3589 demo board demonstrates configuring and dynamically slewing and sequencing the outputs using i 2 c control. the same provisions can be incorporated into embedded soft- ware drivers for the omap3 or any other target processor. back-driving ltc3589 outputs multirail processors or board level designs may have surprise leakage paths between power rails. during a start-up sequence an ltc3589 regulator output may be pulled higher than 300mv. this violates the default set- tings for a ltc3589 and ltc3589-1 start-up sequence. the ltc3589-2 power up default is to allow its regulators to enable at any output voltage and is recommended for designs with rail back-drive conditions.
ltc3589/ltc3589-1/ ltc3589-2 46 3589fe typical application v in v in pv in1 37 6 7 39 24 25 33 27 26 34 15 16 40 12 19 1 2 38 5 3 4 32 31 30 28 8 29 17 22 23 sw1 158k 10pf 22f 100k ldo1_stdby ldo1_fb en1 en2 en3 en4 en_ldo2 en_ldo3 on ltc3589-2 gnd buck1_fb pv in2 sw2 pv in3 pv in4 buck2_fb 36 v rtc 1.3v 25ma 35 11 10 imx_ldo_1v8 wake sw2_vcc ddr_1v5 enable_ddr_1v5 13 14 9 18 20 21 100k 158k sw3 sw4ab sw4cd v in_ldo2 ldo2_fb v in_ldo34 ldo2 ldo3 ldo4 1f buck3_fb bb_out bb_fb 41 gnd 1-95 pwr_on pwr_on dv dd sda scl vstb rst0 pgood pbstat wake irq 3589 ta02 vdda_1-4 vddal1 vp1-2 nvcc_emi_dram_1-5 ddr_ref fastr_ana fastr_dig vdd_fuse i2c2_sda (key_row3) i2c2_scl (emi_eb2) pmic_stby_req pmic_on_req gpio/pmic_rdy gpio/irq gpio ddr_1v5 ddr_ref nvcc_lcd_1-2 nvcc_jtag tvdac_ahvddrgb_1-2 tvdac_dhvdd vdd_reg(imx_ldo_1v8_in) nvcc_xtal nvcc_lvds nvcc_lvds_bg usb_otg_vdda25 usb_h1_vdda25 vph1 vhp2 nvcc_nandf nvcc_eim_main_1 nvcc_eim_main_2 nvcc_eim_sec nvcc_sd1 nvcc_sd2 nvcc_pata nvcc_fec nvcc_gpio nvcc_csi nvcc_keypad usb_h1_vdda33 usb_otg_vdda33 vdd_dig_pll(ldo_out) vddgp_1-15 vcc_1-33 vdd_ana_pll(ldo_out) nvcc_ckih nvcc_reset nvcc_srtc_pdw pwr_on 10f 1h 1.5h 2.2h 10f 10f 10f 10f 22f 191k 10pf 22f imx_ldo_1v8 sw2_vcc peripheral core 1.31v run 0.95v stby 1.2a 2.5v 1.2a 1.3v vi-o 3.35v 1.2a analog 2.8v 250ma 3.2v 250ma analog 1.3v 250ma arm core 1.10v run 0.85v stby 1.6a 180k 22f 22f 100k 10pf 22f 270k 158k 22f 1f 2.5h 511k 10pf 191k 180k 4.7k 4.7k 47k 47k 47k 2.2f 10f 2.2f 2.2f freescale i.mx536 47k v in
ltc3589/ltc3589-1/ ltc3589-2 47 3589fe typical application v in v in pv in1 37 6 7 39 24 25 33 27 26 34 15 16 40 12 19 1 2 38 5 3 4 32 31 30 28 23 22 29 17 8 sw1 768k 10pf 22f 604k ldo1_stdby ldo1_fb en1 en2 en3 en4 en_ldo2 en_ldo34 on ltc3589 gnd buck1_fb pv in2 sw2 pv in3 pv in4 buck2_fb 36 v rtc 1.2v 25ma 35 11 10 13 14 9 18 20 21 511k 1.02m sw3 sw4ab sw4cd v in_ldo2 ldo2_fb v in_ldo34 ldo2 ldo3 ldo4 1f buck3_fb bb_out bb_fb 41 gnd pwr_on wake v sram v core 10k 9.09k 9.09k 18.2k pwr_on dv dd sda scl vstb wake pbstat pgood irq rst0 i2c2_sda i2c2_scl pmic_vstby_req gpio gpio pmic_rdy gpio1/irq por_b 3589 ta03 nvcc_ipu vdd_tvsupply ahvddrgb nvcc_dac vdda vdd_dig_pll_a&b vdd_tvdig vdd_ava_pll_a&b vdda33 vddgp vdd_fuse nvcc__emi nvcc_per13,14 v cc(core) nvcc_srtc_pow fastr_ana fastr_dig nvcc_emi_dram nvcc_cntl_emi nvcc_per2,3,4,5,6,8,9 nvcc_emi(nand+emi) nvcc_tv_back nvcc_usbphy nvcc_osc gpio pwr_on 10f 1h 1.5h 1.5h 10f 10f 10f 10f 22f 422k 10pf 22f v sram /ddr 1.8v 1a v soc 0.676v to 1.4v 1a v io 3.3v 1.2a v analog 1.8v 250ma v aux 2.8v 250ma v memory 0.647v to 1.34v 250ma v core 0.647v to 1.34v 1.6a 715k 787k 10pf 22f 681k 316k 22f 1f 2.7h 1m 4.7pf 768k 604k 1f 1f 1f 4.7k 4.7k 47k 1f freescale i.mx51 10k 10k v soc 47k 47k 47k 47k
ltc3589/ltc3589-1/ ltc3589-2 48 3589fe 6.00 0.10 (4 sides) note: 1. drawing is a jedec package outline variation of (wjjd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.45 or 0.35 45 chamfer 0.40 0.10 40 39 1 2 bottom viewexposed pad 4.50 ref (4-sides) 4.42 0.10 4.42 0.10 4.42 0.05 4.42 0.05 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uj40) qfn rev ? 0406 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.50 0.05 (4 sides) 5.10 0.05 6.50 0.05 0.25 0.05 0.50 bsc package outline r = 0.10 typ uj package 40-lead plastic qfn (6mm 6mm) (reference ltc dwg # 05-08-1728 rev ?) package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc3589/ltc3589-1/ ltc3589-2 49 3589fe information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 9/10 removed 0v from ldo4 on block diagram 15 b 12/10 updated part marking in order information section 3 c 02/11 ltc3589-1 part added. changes reflected throughout the data sheet 1-46 d 01/12 updated part numbers on imx application processors updated absolute maximum ratings and pin configuration sections added reference designs and drivers section added typical application updated typical application 1, 42 3 43 44 45 e 03/12 added ltc3589-2 throughout updated table 1: ltc3589/-1/-2 functional differences clarified enable and power-on sequencing section clarified i 2 c command and status register sections enhanced command register table added section on back-driving outputs 1-50 17 31-32 37 38-39 45
ltc3589/ltc3589-1/ ltc3589-2 50 3589fe linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0312 rev e ? printed in usa related parts part number description comments ltc3101 1.8v to usb, multioutput dc/dc converter with low loss usb power controller seamless transition between multiple input power sources, v in range: 1.8v to 5.5v, buck-boost converter v out range: 1.5v to 5.25v, 3.3v out at 800ma for v in 3v, dual 350ma buck regulators, v out : 0.6v to v in , 38a quiescent current in burst mode operation, 24-lead 4mm 4mm 0.75mm qfn package LTC3556 switching usb power manager pmic with li-ion/polymer charger complete multifunction pmic: switching power manager, 1a buck-boost + 2 buck regulators + ldo, 4mm 5mm qfn-28 package ltc3577/ ltc3577-1/ ltc3577-3/ ltc3577-4 highly integrated portable/ navigation pmic complete multifunction pmic: linear power manager and three buck regulators, 10-led boost reg, 4mm 7mm qfn-44 package, -1 and -4 versions have 4.1v v float , -3 version for sirf atlas iv processors ltc3586/ ltc3586-1 switching usb power manager pmic with li-ion/polymer charger complete multifunction pmic: switching power manager, 1a buck-boost + 2 bucks + boost + ldo, 4mm 6mm qfn-38 package, -1 version has 4.1v v float . typical application integrated power ic for mobile processor system with usb/automotive battery charger 10f 10f v in p vin1 p vin2 p vin3 p vin4 v bus v c wall acpr usb to c to c c2 10f 0805 c5 10f 0805 c1 4.7f c6 68nf c4 22f c3 0.1f 0603 r7 100k r11 499k r2 150k 4 2 3 7 3 7 9, 21 6 9 20 18 19 14 12 10 11 m5 11 1 6 8 5 10 13 r9 2.94k r10 1k m4 l1 3.3h l2 10h clprog prog ltc4098 lt3480 gnd sw batsens ovgate ovsens d0Cd2 chrg ntcbias ntc 2 1 15-17 8 4 5 v out idgate bat li-ion + r8 100k t r6 40.2k r12 100k r t v in run/ss pg gnd v c bd sync sw fb boost v in c7 0.47f hvbuck ovgate rsto en1 en2 en3 en4 en_ldo2 en_ldo34 wake pwr_on pgood irq ldo1_stdby ldo1_fb 1m 3.3v, 25ma 68k v b1 v l2 v b3 v b2 v bb 68k 68k 316k dv dd sda scl v bb vstb pbstat on 68k 68k 4.7k 4.7k to p 1h 10pf v b1 1.2v 1.6a v b2 1.8v 1a v b3 1.2v 1a v bb 3.3v 1a v l2 1.2v 250ma ltc3589 v l3 1.8v 250ma v l4 2.8v 250ma 3589 ta04 604k 768k 22f 22f 1.5h 10pf 715k 422k 22f 1.5h 10pf 681k 787k 22f 4.7pf 1m 316k 22f 604k 768k 1f 1f 1f 1f 10f 10f 10f 25 7 37 36 35 8 10 11 13 14 9 18 23 20 29 17 31 30 28 22 21 32 6242715 39 33 26 34 16 40 12 19 1 2 38 5 3 4 41 2.7h sw1 sw2 buck1_fb buck2_fb buck3_fb bb_out sw3 bb_fb sw4ab sw4cd vin_ldo2 ldo2 ldo2_fb ldo3 ldo4 gnd v bb v b2 vin_ldo34 automotive, firewire, etc. r5 10k r1 1k r3 33k r4 10k d1 mmbz524- 0blt1g 10v m3 zxmn10a08e6 m1 zxmp10a18g m2 zxmp10a18g hvin

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