(preliminary) pl611s-19 0.5khz-55mhz mhz to khz programmable clock tm 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 1 features ? designed for very low-power applications ? offered in tiny green /rohs compliant packages o 6-pin dfn (2.0mmx1.3mmx0.6mm) o 6-pin sc70 (2.3mmx2.25mmx1.0mm) o 6-pin sot23 (3.0mmx3.0mmx1.35mm) ? input frequency: o reference input: 1mhz to 200mhz o non pll mode, ref input down to 10khz ? accepts >0.1v reference signal input voltage ? output frequency up to 55mhz cmos. o < 65mhz @ 1.8v operation o < 90mhz @ 2.5v operation o < 125mhz @ 3.3v operation ? one programmable i/o pin can be configured as power down (pdb) input, output enable (oe), or frequency selection switching input. ? disabled outputs programmable as hiz or active low. ? low current consumption: o <1.0ma with 27mhz & 32khz outputs o < 5ba when pdb is activated ? single 1.8v, 2.5v, or 3.3v 10% power supply ? operating temperature range from -40 c to 85 c description the pl611s-19 is a low-cost general purpose frequency synthesizer and a member of phaselinks factory programmable quick turn clock (qtc) family. phaselinks pl611s-19 offers the versatili ty of using a single reference clock input and producing up to two (khz or mhz) system clock outputs. designed for low-power applications with very stringent space requirement, pl611s-19 consumes <1.0ma, while producing 2 distinct outputs of 27mhz and 32khz. the power down feature of pl611s-19, when activated, allows the ic to consume less than 5ba of power. pl611s-19 fits in a small dfn, sc70, or sot23 package. cascading of the pl611s-19 with other phaselink programmable clocks allow generating system level clocking requirements, thereby reducing the overall system implementation cost. in addition, one programmable i/o pin can be configured as power down (pdb) input, output enable (oe), or frequency switching (fsel). clk1 can be programmed as (clk0, f ref , f ref /2) output. block diagram phase detector charge pump loop filter vco fin r-counter (5-bit) f vco = f ref * (2 * m/r) f out = f vco / (2 * p) clk [0:1] f ref programming logic oe, pdb, fsel m-counter (8-bit) p-counter (14-bit) programmable function
(preliminary) pl611s-19 0.5khz-55mhz mhz to khz programmable clock tm 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 2 key programming parameters clk output frequency output drive strength programmable input/output f out = f ref * m / (r * p) where m = 8 bit r = 5 bit p = 14 bit clk0 = f out , f ref or f ref / (2*p) clk1 = f ref , f ref /2, clk0 or clk0/2 three optional drive strengths to choose from: ? low: 4ma ? std: 8ma (default) ? high: 16ma one output pin can be configured as: ? oe - input ? fsel - input ? pdb C input ? hiz or active low disabled state pin configuration and description pin assignment name dfn pin# sc70 pin# sot pin # type description clk1 2 1 1 i/o programmable clock output gnd 3 5 2 p gnd connection fin 1 3 3 i reference input pin oe, pdb, fsel 6 2 4 o this programmable i/o pin can be configured as an o utput enable (oe) input, power down input (pdb) or on-the-fly frequen cy switching selector (fsel). this pin has an internal 60ko pul l up resistor for oe, pdb & fsel. the oe and pdb features can be programmed to allow the output to float (hi z), or to operate in the active low mode. vdd 5 4 5 p vdd connection clk0 4 6 6 o programmable clock output oe and pdb function description oe pdb osc. pll clk0 clk1 1 n/a on on on on 0 n/a on off hiz or active low on n/a 1 on on on on n/a 0 off off hiz or active low hiz or active low note: hiz or active low states are programmable fun ctions and will be set per request. 1 2 3 4 5 6 clk1 gnd fin vdd oe, pdb, fsel clk0 dfn dfn dfn dfn- -- -6 66 6l l l l ( (( (2 22 2. .. .0 00 0mmx mmx mmx mmx1 11 1. .. .3 33 3mmx mmx mmx mmx0 00 0. .. .6 66 6mm mmmm mm) )) ) sot sot sot sot23 2323 23- -- -6 66 6l l l l ( (( (3 33 3. .. .0 00 0mmx mmx mmx mmx3 33 3. .. .0 00 0mmx mmx mmx mmx1 11 1. .. .35 3535 35mm mmmm mm) )) ) 12 3 4 5 6 vdd gnd clk0 oe, pdb, fsel sc scsc sc70 7070 70- -- -6 66 6l l l l ( (( (2 22 2. .. .3 33 3mmx mmx mmx mmx2 22 2. .. .25 2525 25mmx mmx mmx mmx1 11 1. .. .0 00 0mm mmmm mm) )) ) fin clk1 fin oe, pdb, fsel gnd vdd clk0 clk1 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 1 1 1 1 9 9 9 9 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 1 1 1 1 9 9 9 9 12 3 65 4 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 1 1 1 1 9 9 9 9
(preliminary) pl611s-19 0.5khz-55mhz mhz to khz programmable clock tm 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 3 functional description pl611s-19 is a highly featured, very flexible, adva nced programmable pll design for high performance, low- power, small form-factor applications. the pl611s- 19 accepts a reference clock input of 1mhz to 200mh z and is capable of producing two outputs up to 125mhz. thi s flexible design allows the pl611s-19 to deliver a ny pll generated frequency, f ref (ref clk) frequency or f ref /(2*p) to clk0 and/or clk1. some of the design fe atures of the pl611s-19 are mentioned below: pll programming the pll in the pl611s-19 is fully programmable. the pll is equipped with an 5-bit input frequency divider (r-counter), and an 8-bit vco frequency feedback loop divider (m-counter). the output of the pll is transferred to a 14-bit post vco divider (p-counter). the output frequency is determined by the following formula [f out = f ref * m / (r * p) ]. clock output (clk0) the output of clk0 can be configured as the pll outp ut (f vco /(2*p)), f ref (ref clk frequency) output, or f ref /(2*p) output. the output drive level can be programmed to low drive (4ma), standard drive (8ma) or high drive (16ma). the maximum output frequency is 125mhz. clock output (clk1) the output of clk1 can be configured as: f ref - reference ( ref clk ) frequency f ref / 2 clk0 clk0 / 2 when using the oe function clk1 will remain always on and will not be disabled when oe is pulled low. when using the pdb function clk1 will be disabled along with clk0. the output drive leve l can be programmed to low drive (4ma), standard drive (8ma) or high drive (16ma). the maximum output frequency is 125mhz. programmable i/o (oe/pdb/fsel) the pl611s-19 provides one programmable i/o pin which can be configured as one of the following functions: output enable (oe) the output enable feature allows the user to enable and disable clk0 clock output by toggling the oe pin. clk1 remains active when oe is pulled low. the oe pin incorporates a 60ko pull up resistor giving a default condition of logic 1. the oe feature can be programmed to allow the output to float (hi z), or to operate in the activ e low mode. power-down control (pdb) the power down (pdb) feature allows the user to put the pl611s-19 into sleep mode. when activated (logic 0), pdb disables the pll, the oscillator circuitry, counters, and all other active circuitry . in power down mode the ic consumes <5ba of power. the pdb pin incorporates a 60ko pull up resistor giving a default condition of logic 1. the pdb feature can be programmed to allow the output to float (hi z), or to operate in the activ e low mode. frequency select (fsel) the frequency select (fsel) feature allows the pl611s-19 to switch between two pre-programmed outputs allowing the device on the fly frequency switching. the fsel pin incorporates a 60ko pull u p resistor giving a default condition of logic 1.
(preliminary) pl611s-19 0.5khz-55mhz mhz to khz programmable clock tm 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 4 electrical specifications absolute maximum ratings parameters symbol min. max. units supply voltage range v dd - 0.5 7 v input voltage range v i - 0.5 v dd + 0.5 v output voltage range v o - 0.5 v dd + 0.5 v soldering temperature (green package) 260 c data retention @ 85 c 10 year storage temperature t s -65 150 c ambient operating temperature* -40 85 c exposure of the device under conditions beyond the limits specified by maximum ratings for extended pe riods may cause permanent damage to the device and affect product reliability. these conditions r epresent a stress rating only, and functional opera tions of the device at these or any other condition s above the operational limits noted in this specification is not implied. *operating temperature is guarante ed by design. parts are tested to commercial grade only. ac specifications parameters conditions min. typ. max. units @ v dd =3.3v 200 @ v dd =2.5v 166 input (fin) frequency @ v dd =1.8v 1 133 mhz input (fin) signal amplitude internally ac/dc coupl ed (high frequency) 0.9 v dd vpp input (fin) signal amplitude internally ac/dc coupled (low frequency) 3.3v < 50mhz, 2.5v < 40mhz, 1.8v < 15mhz 0.1 v dd v pp @ v dd =3.3v 125 mhz @ v dd =2.5v 90 mhz output frequency @ v dd =1.8v 65 mhz settling time at power-up (after v dd increases over 1.62v) 2 ms oe function; ta=25o c, 15pf load 10 ns output enable time pdb function; ta=25o c, 15pf load 2 ms output rise time 15pf load, 10/90% v dd , high drive, 3.3v 1.2 1.7 ns output fall time 15pf load, 90/10% v dd , high drive, 3.3v 1.2 1.7 ns duty cycle pll enabled, @ v dd /2 45 50 55 % period jitter,pk-to-pk* (measured from 10k samples) with capacitive decoupling between v dd and gnd. 70 ps * note: jitter performance depends on the programmi ng parameters.
(preliminary) pl611s-19 0.5khz-55mhz mhz to khz programmable clock tm 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 5 dc specifications parameters symbol conditions min. typ. max. units supply current, dynamic, with loaded cmos outputs i dd @ v dd =3.3v, 27mhz, load=15pf 4.0 ma supply current, dynamic, with loaded cmos outputs i dd @ v dd =2.5v, 27mhz, load=10pf 2.7 ma supply current, dynamic with loaded cmos outputs i dd @ v dd =1.8v, 27mhz, load=5pf 0.9 ma pll off: supply current, dynamic, with loaded cmos output i dd @ v dd =3.3v, 32khz, load=15pf 0.6 ma pll off: supply current, dynamic, with loaded cmos output i dd @ v dd =2.5v, 32kmhz, load=15pf 0.5 ma pll off: supply current, dynamic with loaded cmos output i dd @ v dd =1.8v, 32khz, load=15pf 0.2 ma pll off: supply current, dynamic with loaded cmos output i dd @ v dd =1.8v, hz output, load=15pf 0.2 ma supply current, dynamic, with loaded outputs i dd when pdb=0 5 ba operating voltage v dd 1.62 3.63 v output low voltage v ol i ol = +4ma standard drive 0.4 v output high voltage v oh i oh = -4ma standard drive v dd C 0.4 v output current, low drive i osd v ol = 0.4v, v oh = 2.4v 4 ma output current, standard drive i osd v ol = 0.4v, v oh = 2.4v 8 ma output current, high drive i ohd v ol = 0.4v, v oh = 2.4v 16 ma * note: please contact phaselink, if super-low-powe r is required.
(preliminary) pl611s-19 0.5khz-55mhz mhz to khz programmable clock tm 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 6 pcb layout considerations for performance optimizat ion the following guidelines are to assist you with a pe rformance optimized pcb design: - keep all the pcb traces to pl611s-19 as short as possible, as well as keeping all other traces as fa r away from it as possible. - when a reference input clock is generated from a crystal, place the pl611s-19 fin as close as possible to the xout crystal pin. this will redu ce the cross-talk between the reference input and the other signals. - place a 0.01bf~0.1bf decoupling capacitor between vdd and gnd, on the component side of the pcb, clos e to the vdd pin. it is not recommended to place this component on the backside of the pcb. going throug h vias will reduce the signal integrity, causing addi tional jitter and phase noise. - it is highly recommended to keep the vdd and gnd traces as short as possible. - when connecting long traces (> 1 inch) to a cmos output, it is important to design the traces as a t ransmission line or stripline, to avoid reflections or ringin g. in this case, the cmos output needs to be matched to the tr ace impedance. usually striplines are designed for 5 0o impedance and cmos outputs usually have lower than 50o impedance so matching can be achieved by adding a resistor in series with the cmos output pin to the stripline trace. - please contact phaselink for the application note on how to design outputs driving long traces or for additi onal layout assistance. dfn-6l evaluation board
(preliminary) pl611s-19 0.5khz-55mhz mhz to khz programmable clock tm 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 7 d e pin1 dot d1 b e e1 l a3 a a1 pin 6 id chamfer package drawings ( green package compliant) sot23-6 l sc70-6l dfn-6l dimension in mm symbol min. max. a 1.05 1.35 a1 0.05 0.15 a2 1.00 1.20 b 0.30 0.50 c 0.08 0.20 d 2.80 3.00 e 1.50 1.70 h 2.60 3.0 l 0.35 0.55 e 0.95 bsc dimension in mm symbol min. max. a 0.80 1.00 a1 0.00 0.09 a2 0.80 0.91 b 0.15 0.30 c 0.08 0.25 d 1.85 2.25 e 1.15 1.35 h 2.00 2.30 l 0.21 0.41 e 0.65bsc dimension in mm symbol min. max. a 0.50 0.60 a1 0.00 0.05 a3 0.152 0.152 b 0.15 0.25 e 0.40bsc d 1.25 1.35 e 1.95 2.05 d1 0.75 0.85 e1 0.95 1.05 l 0.20 0.30 c l a2 e h d a1 e b a pin1 dot c l a2 e h d a1 e b a pin1 dot
(preliminary) pl611s-19 0.5khz-55mhz mhz to khz programmable clock tm 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 8 ordering information ( green package) for part ordering, please contact our sales departm ent: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492-0990 fax: (510) 492-0991 part number the order number for this device is a combination of the following: part number, package type and operating temperature range pl611 s-19-xxx x x x part /order number marking ? package option pl611s-19-xxxgc-r xxx 6-pin dfn (tape and reel) pl611s-19-xxxuc-r xxx 6-pin sc70 (tape and reel) pl611s-19-xxxtc-r 19xxx 6-pin sot23 (tape and reel) ? note: xxx designates marking identifier that, at times, could be independent of the part number. pl ease consult your phaselink sales f or marking information. phaselink corporation, reserves the right to make c hanges in its products or specifications, or both a t any time without notice. the information furnished by phaselink is believed to be accurate a nd reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any lo ss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselinks products are not authorized for use a s critical components in life support devices or sy stems without the express written approval of the president of phasel ink corporation. solder reflow profile available at www.phaselink.com/qa/solderinggreen.pdf part number temperature c=commercial i = industrial package type g=dfn-6l u=sc70-6l t=sot-6l 3 digit id code * (will be assigned at programming time) r=tape and reel
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