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r em4150 em4350 em microel e ctronic - marin sa cop y right ? 200 4, em microelectronic-marin sa 1 www.emmicroele c tronic.com 1 kbit read / write contactless identification device des c ription t he em4150/ em435 0 (pr e vi ousl y nam ed p415 0/p43 50) is a cmos int egrate d circu i t inten d e d for us e in e l ectron ic rea d /w rite rf t r anspon ders. t he chip cont ains 1 kbit of eeprom w h ic h can be configured by the user, allo w i ng a w r it e inh i bit e d area, a read protected are a , and a rea d area outp u t co ntinu ousl y at p o w e r on. t he memor y ca n be s e cure d b y usin g th e 3 2 bi t pass w o r d for all w r ite an d read pr otected oper ations. t he pass w o r d ca n be up date d , but nev er re ad . t he fixed c o de ser i al num b e r an d d e vice ide n tificatio n a r e laser pro g r a mmed mak i n g ever y c h ip uni que. t he em4150 w i ll transm i t data to the transce iver b y modu latin g the amplitu de of t he el ectroma g netic fiel d, an d receiv e d a ta and c o mma nd s in a simi lar w a y. sim p le comman d s w i ll en abl e w r ite t o eeprom, t o u pdat e the pass w o r d, to r ead a s pec ific memor y are a , an d to r e set the log i c. t he coil of th e tuned c i rcuit is the on l y e x ter n al com pon ent requ ired, al l re maini ng functi o n s are inte grat ed in the c h ip. t he onl y differ ence b e t w ee n em415 0 and e m 435 0 is that em415 0 com e s w i th sta n dard s i zed p ads, w h ereas em435 0 come s w i th ov ersize d (mega) pa ds, ideal for use w i t h bum ps on die (f ig. 27). features 1 kbit of eeprom organiz ed i n 32 w o r d s of 32 bits 32 bit dev i ce s e rial n u mb er (rea d onl y las er rom) 32 bit dev i ce identific atio n (read onl y l a ser rom) po w e r-on r e s e t seque nce po w e r c heck for eeprom w r ite oper atio n user defi ned r ead mem o r y a r ea at po w e r o n user defi ned w r ite inhibite d memor y ar ea user defi ned r ead protect ed memor y ar ea data t r ansmission p e rformed b y ampl itud e modu latio n t w o d a ta rate options 2 kbd (opt64) or 4 kbd (opt32) bit period = 64 or 32 per io ds of field frequ e n c y 170 pf 2% o n chip r e so na nt capac itor -40 to + 85c t e mper ature ra nge 100 to 1 50 khz f i eld f r equ en c y ran ge on chip rectifi e r and vo ltag e limiter no e x tern al su ppl y b u ffer cap a citanc e ne ede d due to lo w p o w e r co n s umptio n applica t ions t i cketing automotive im mobil i zer w i t h rolli ng co de high s e curit y hands free access control industria l auto m ation w i t h por table d a tab a se manufactur i ng automati on prepa ym ent d e vices t y p i cal operating co nfig uration em 4150 coil 2 coil 1 l typical value of inductance at 125 khz is 9.5 mh fig. 1 pin assignm ent coil 1 coil terminal / clock input coil 2 coil terminal em 41 50 coil2 coil1 coil2 coil1 fig. 2
r em4150 em4350 absolu te ma ximum ratin g s pa rame t e r s y m b o l condit i ons maximum ac peak curr ent ind u ced on co il1 and coil 2 i coil 30 ma po w e r supply v dd -0.3 to 6.0v maximum volt a ge other p ads v max v dd + 0.3v minimum vo lta ge other p ads v mi n v ss ? 0.3v storage temp e r ature t store -55 to 125 c electrostatic di scharg e maximum to mil-st d-883c method 3 0 1 5 v esd 100 0v stresses ab ov e these l i sted maximum rati n g s ma y c aus e perma nent da mage to th e devic e. e x p o s u re be yo nd specifi ed op era t ing c ond itio ns ma y affect d e vi ce rel i a b il it y or cause ma lfu n ction. handling pr ocedur es t h is device h a s bu ilt-in pro t ection a g a i nst hig h static voltag es or electric fi elds; h o w e v e r, anti-static preca u tions s h oul d be tak e n as for an y o t her cmos compo nent. unless other wise sp ecifie d, pr op er op erati on ca n on l y occur w h e n a ll termi nal volt ages are kept w i thi n th e supp l y v o lta ge rang e. opera t ing conditions p a r a m e t e r s y m b o l m i n t y p m a x u n i t s oper ating temperatu r e t op - 4 0 + 8 5 c max i mum coil current i coil 1 0 m a ac voltage on coil v co i l 1 ) v p p suppl y freq uenc y f co i l 1 0 0 1 5 0 k h z note 1): ma ximu m voltage is defined b y fo rcing 10ma on coil1- coil2 antenna driv e r os c i l l at or d e modu l a t o r fil t er an d ga i n d a t a dec o der da ta re ceiv e d f r om tr a n s p o nde r tr anc e i v er tr an sp on de r c o il1 c o il2 em 41 50 s i g nal o n t r ans p o n der c o i l s i g nal o n tra n sceive r co il dat a rf car r ie r read mode s i gn al on t r an sp on d e r c o il s i gna l on tr a n sce iver coil da ta rf ca rr ier rec e i ve mode mo du lat o r da ta to b e se nt t o tr an s pon de r fig. 3 cop y right ? 200 4, em microelectronic-marin sa 2 www.emmicroele c tronic.com
r em4150 em4350 copyright ? 2004, em microelectronic-marin sa 3 www.emmicroelectronic.com electrical characteristics v dd = 2.5v, v ss = 0v, f coil = 125 khz sine wave, v coil = 1v pp , t op = 25c unless otherwise stated parameter symbol test conditions min typ max units supply voltage v dd 2.0 5.5 v minimum eeprom write voltage v ddee 2.6 v power check eeprom write i pwcheck v dd = 3v 80 a supply current / read i rd read mode 3.0 5.0 a suppy current / write i wr write mode (v dd = 3v) 40 70 a modulator on voltage drop v on v (coil1?vss) and v (coil2-vss) i coil = 100 a v (coil1?vss) and v (coil2-vss) i coil = 5ma 0.50 2.50 v v resonance capacitor c r 166.5 170 173.5 pf power on reset level high v prh rising supply 2.0 2.6 v clock extractor input min. v clkmin minimum voltage for clock extraction 1.0 v pp clock extractor input max. v clkmax maximum voltage to detect modulation stop 50 mv pp eeprom data endurance n cy erase all / write all at v dd = 5v 100'000 cycles eeprom retention t ret t op = 55c after 100'000 cycles (note 1) 10 years note 1: based on 1000 hours at 150c timing characteristics v dd = 2.5v, v ss = 0v, f coil = 125 khz sine wave, v coil = 1v pp , t op = 25c unless otherwise stated all timings are derived from the field frequency and are specified as a number of rf periods. parameters symbol test conditions value units option : 64 clocks per bit opt64 read bit period liw/ack/nack pattern duration read 1 word duration processing pause time write access time initialization time eeprom write time trdb tpatt trdw tpp twa tinit twee including liw vdd = 3 v 64 320 3200 64 64 2112 3200 rf periods rf periods rf periods rf periods rf periods rf periods rf periods option : 32 clocks per bit opt32 read bit period liw/ack/nack pattern duration read 1 word duration processing pause time write access time initialization time eeprom write time trdb tpatt trdw tpp twa tinit twee including liw vdd = 3 v 32 160 1600 32 32 1056 2624 rf periods rf periods rf periods rf periods rf periods rf periods rf periods rf periods represent periods of the carrier frequency emitted by the transciever unit. for example, if 125 khz is used : the read bit period (opt64) would be : 1/125'000*64 = 512 s, and the time to read 1 word : 1/125'000*3200 = 25.6 ms. the read bit period (opt32) would be : 1/125'000*32 = 256 s, and the time to read 1 word : 1/125'000*1600 = 12.8 ms. attention due to amplitude modulation of the co il-signal, the clock-extractor may miss clocks or add spurious clocks close to the edges of the rf-envelope. this desynchronisation will not be larger than 3 clocks per bit and must be taken into account when deve loping reader software.
r em4150 em4350 block diagra m cont r o l logic m odulat or encoder power cont r o l cloc k ex tr a c to r sequencer dat a ex tr a c to r com m and decoder eepro m ro m +v gnd c o il 2 c o il 1 se ri a l da t a r eset w r ite e n able c s c r ac/ d c conver t e r volt age regulat ion vdd f i g . 4 function al descriptio n general t he em4150 is sup p li ed b y m eans of a n ele c tromagn etic field i n d u ced on the attach ed coi l . t he ac volta ge is rectified in or d e r to provi d e a dc inter nal su ppl y volta ge. w hen th e d c volta ge cr oss e s the po w e r- on lev e l, the chip e n ters the standar d r ead mo de an d sends d a ta contin uo usl y . t he data to be s ent in this mode is us er defin ed b y st orin g the first an d l a st a d d r esses to b e output. w hen the last ad d r ess is sent, the chi p w i l l contin ue w i th the first addr es s unti l the tran sceiver s e n d s a requ est. in the rea d mode, a listen w i nd o w ( l iw ) is gen erate d bef ore e a ch w o r d . duri ng thi s time, the em415 0 w i l l turn to the recei v e mode (rm) if it receives a val i d rm pattern. t he chip th en e x p e cts a val i d command. mode of ope r a t ion st andar d read m ode s end wo rd po we r-o n wr it e word w r i t e p a ssw or d s e lec t iv e r ead login ye s no re ce i v e m ode r eques t ? res e t g e t c o m m and e x ec ut e c o m m and in i t f i g . 5 me mory organis a t ion t he 1024 bit eeprom is o r gan ised in 32 w o rds of 32 bits. t he first three w o r d s are assign ed to the pass w o r d , the protectio n w o r d , and th e contro l w o r d . in order to w r it e one of th ese thr e e w o r d s, it is nec es sar y to s e n d the vali d pass w o r d. at fabr ication, the e m 415 0 comes w i t h al l bits of the pass w o r d progr ammed t o a lo gic " 0 ". t he pass w o rd cann ot b e re ad out. t he mem o r y co ntains t w o e x tra w o r d s of l a ser r o m. t hese w o rds ar e l a ser progr ammed d u rin g fabric atio n for ever y c h i p , are u n iq ue and ca nn ot be altere d. memory map pr o t ect i on wor d 0 - 7 8 - 15 16 - 23 24 - 31 pa ssw or d wr i t e o n l y - n o r ead a ccess d e vi ce i d ent i f i cat i on wor d & se r i al n u m b er wor d la ser pr ogr am m e d - read o n l y fi r s t wor d r ead pr ot ect ed last wor d r ead pr ot ect ed fi r s t w o r d w r i t e i nhi bi t e d last w o r d w r i t e i nhi bi t e d c o n t ro l wo rd f i rs t wo rd r e a d last wor d r ead passw or d c h eck o n / o f f r ead a f t e r wr i t e o n / o f f u ser avai l a bl e 0 - 7 8 - 15 16 17 18 - 31 o n m eans bi t set t o l ogi c ' 1 ' o f f m eans bi t set t o l ogi c ' 0 ' bi t 0 b i t 3 1 928 bi t s of u ser eepro m pa ssw o r d p r ot e c t i on w o r d co ntr o l w o rd devi ce ser i a l num ber devi ce i d e n ti fi cati o n wo rd 0 1 2 31 32 33 ee ee ee ee laser laser fig. 6 cop y right ? 200 4, em microelectronic-marin sa 4 www.emmicroele c tronic.com
r em4150 em4350 standa rd re ad mode after a po w e r-on reset a nd u p o n com p leti on of a comman d , the chi p w i ll e x ecute th e sta ndar d r e a d mode, in w h ic h it w i ll se nd data c onti nuo u s l y , w o rd b y w o rd from th e memor y secti o n defi n e d bet w een th e f i rst w o rd rea d (f w r ) and last w o rd read ( l w r ). w hen the l a st w o rd is outp u t, the chi p w i ll conti n u e w i t h th e first w o rd until th e transceiv er se nds a r equ est. if fw r and lw r ar e the same, th e same w o rd w i ll b e se nt repetitiv el y. t he l i sten w i ndo w (liw ) i s gen erate d before each word to ch eck if the transce ive r is send in g data. t he liw has a dur atio n of 320 (16 0 opt 32) peri ods of the rf field. f w r and lw r have to b e progr amme d as vali d ad dres ses (f w r lw r and 33). t he w o r d s s e nt b y th e em4 150 compr i se 32 data bits and par it y bit s . t he par it y bits are not s t ored i n th e eeprom, but gener ated w h ile the mess ag e is sent as descri bed b e l o w . t he parit y is eve n fo r ro w s a n d colum n s, mea n in g that the t o ta l n u mber of "1' s " is ev en (inclu di ng the p a rit y b i t). word or gani sation (wor d s 0 to 32 ) d0 d8 d1 6 d2 4 pc0 d1 d9 d1 7 d2 5 pc1 d2 d1 0 d1 8 d2 6 pc2 d3 d1 1 d1 9 d2 7 pc3 d4 d1 2 d2 0 d2 8 pc4 d5 d1 3 d2 1 d2 9 pc5 d6 d1 4 d2 2 d3 0 pc6 d7 d1 5 d2 3 d3 1 pc7 p0 p1 p2 p3 0 fi rst bi t output r o w e v en p a ri ty last bi t output l ogi c " 0 " co lu m n eve n pa r i ty da ta fig. 7a w hen a w o rd i s read pr otecte d, the outp u t w ill co nsist of 45 b i ts set to l ogic " 0 ". t he p a ss w o r d has t o be used t o output correctl y a re ad prot ec ted memor y ar ea. word or gani sation (wor d 33) c0 id2 r0 ck0 pc 0 c1 id3 r1 ck1 pc1 c2 id4 r2 ck2 pc2 c3 id5 r3 ck3 pc3 c4 id6 r4 ck4 pc4 c5 id7 r5 ck5 pc 5 id0 id8 r6 ck6 pc6 id1 id9 r7 ck7 pc7 p0 p1 p2 p3 0 : p 4150 c ode set to h e xadecimal 32 : v e rsion c ode : e m reserved, an d c heck bits c0 id 0 r0 - c 5 - id 9 - r7 / ck0 - ck 7 fig. 7b read se que nce por ou t p u t li w d 0-d 7 p 0 d 8 -d 15 p1 d 16-d 2 3 p 2 d 24-d 3 1 p 3 p c 0 -pc 7 "0" t0 = p e r i od of rf car r i e r f r equency in it li w fwr l i w fwr+1 l wr li w f wr l i w li w li w coded dat a dat a 1 bit - 64 t 0 periods (op t 64) 32 t 0 periods (op t 32) t 0 perio ds : 32 32 128 64 64 (opt 64) 16 16 64 32 32 (opt 32) fig. 8 rec e iv e mode t o activate the receive mode , the t r ansceiver sends to the chip the r m pattern ( w h i l e in the mod u l a ted ph ase o f a liste n w i nd o w liw ) . t he em415 0 w i ll stop sen d i n g data upo n r e ce ption of a val i d rm. t he chip t hen e x p e cts a comma nd. t he rm pattern consists of 2 bits "0" s e n t b y th e transce iver. t he first bit "0" transmit t ed is to be detected duri n g the 64 (3 2 opt 32) p e rio d s w h ere th e modu latio n is " o n" in liw. output word n liw input rm command rm : two consecutive bits set to logic "0" fig. 9 c o mmands t he command s are compos ed of nin e bits : eight data bits and o ne even p a rit y bit (total amount of "ones" is even i n clu d i ng the parit y bit). login write password write word selective read mode reset 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 command bits function parity bit first bit received fig. 10 selectiv e read mode t he selectiv e rea d mo de is used to r ead ot her data tha n that defin ed be t w e en f w r a n d lw r. t o enter sel e ctive rea d mod e , the t r ansceiver has to sen d duri ng liw a receiv e mo de pattern ( r m) to turn the em415 0 i n receiv e mod e . t hen the selective rea d mod e comman d is s ent b y t he tra n sceiver f o ll o w e d b y t he f i rst and last a ddr esses to b e re ad. t he f w r and lw r ar e then re pl aced b y the ne w addr esses an d the c h ip is oper ating in th e same w a y a s the standar d read mo de. t he control w o rd is n o t mod i fied b y this c o mmand, a n d the n e x t stand ard re ad m o d e op erati on w i ll w o rk w i t h origi n a l f w r and lw r (sel e c ted area is re ad onc e an d then the ch ip r e turns to stand ard re ad mod e ). t o read w o r d s w h ic h ar e rea d protecte d, a l ogi n comman d has to be se nt b y the transc e iver prior to th e selectiv e r e a d comma nd. t he log in c o m m and is to be used onl y once for all su bseq uent comm and s requir i ng a pass w o r d. cop y right ? 200 4, em microelectronic-marin sa 5 www.emmi croel e c troni c.com
r em4150 em4350 selectiv e read mode con t . t he selective rea d mod e co mmand is f o ll o w e d b y a si ngl e 32- bi t w o r d c ontai nin g the n e w first an d las t address e s. bi ts 0 to 7 corres pon d to the f i rst w o rd rea d a n d bits 8 to 1 5 c o rresp ond to t he l a st w o rd rea d . bits 16 t o 31 have to b e sent but ar e n o t us ed i n th e ch ip. t he parities m u st be sent ac cordi ng to the w o rd org anis a tion as descri b ed i n fi g.7. n o te that bit 31 is transmitted first. t o read the d e vice id entifica t ion or th e ser i al n u mb er, t he sel e ctive r e ad c o mman d allo w s dir e ct a ccess to the l a ser progr ammed w o rds. t hese w o rds c an a l so b e a ddr es sed i n the stand ard r ead mode b y se le cting th e a ddr esses accordingly . o u t p ut wo rd n li w in pu t rm se le c t iv e r d ad d r esse s li w fw r li w ac k/n a k li w t pp f i g . 1 1 lw 7 lw 6 lw 5 lw 4 lw 3 lw 2 lw 1 lw 0 p1 fw 7 fw 6 f w 5 fw 4 fw 3 fw 2 f w 1 fw 0 p0 p c 7 pc6 p c 5 p c 4 pc3 pc2 p c 1 pc0 "0" addresses bit s t ream form a t fi r s t bi t recei v ed xx xx xx x x x x xx x x x x p 3 xx xx xx xx x x x x x x x x p 2 f i g . 1 2 r e set command t he reset command w i ll ret u rn from an y m ode to the stan dard r ead mo de. t he next w o rd out is the f w r. ou tp u t wo rd n li w in pu t rm re s e t li w fw r li w li w ac k/n a k t pp t init f i g . 1 3 login t he login co mmand is use d to access protected memo r y ar e a s. t h is command ha s to be used onl y o n ce to perfo r m severa l pass w ord protecte d comman d s. t he po w e r-on s equ enc e and t he res e t command w i ll rese t the pass w o r d entr y , and a n e w l ogi n comman d ha s to be receive d to perform further pass w o r d protected o per ations. upo n recepti o n of a correct pass w o r d, the em415 0 w i l l re spon d w i th a n ackno w l e dg e p a ttern (ack) a nd then co ntin ue in standar d r e a d mode. if the l ogi n is c o rrect then pass w o r d protected op er ations are al lo w e d. if the pas s w o r d is i n corr ect, a nak p a ttern is issu ed an d p a ss w o r d pr ote c ted o per ation s w i l l not be p o ssibl e (r efer t o w r ite w o r d for pass w o r d data structure). ou tp u t wo rd n li w in pu t rm logi n passw o r d li w fw r li w li w ac k/n a k t pp f i g . 1 4 if bit 16 of the control w o r d i s disa ble d (pa s s w o r d check on /off), the log in is still m and ator y to m odif y th e prote c tio n word, the cont rol word, and t he pass w o r d , but not to w r ite in the eepro m w h ic h is not w r it e inhibited. in order t o modif y a w r it e in hib i ted w o rd, the prot ection w o rd h a s to be modifi e d first. t he read protect ed ar ea al w a ys re qu ires the lo gi n to be read. if the w r ite protection w o rd is w r ite p r otected, the w r ite protectio n conf ig uratio n is locked. cop y right ? 200 4, em microelectronic-marin sa 6 www.emmi croel e c troni c.com
r em4150 em4350 write pa ss w o rd w hen a w r ite pass w o r d com m and is r e ceiv ed, the ch ip n e xt e x p e cts i n formatio n o n th e actu al v a l i d pass w o r d. t he ch i p sends back a n ack pattern i f the pass w or d is correct. t h en t he c h ip e x pects the n e w pass w or d co n s isting of 3 2 bi ts + parit y b i t to b e stored in th e eeprom. t h e chip w i ll r e sp ond w i th an a c k patter n for a corr ect rece ption of d a ta u p o n recepti on of th e ne w p a ss w o r d , an d the n w i ll send an other a ckno w l e dg e p a ttern (ack) to ann ou nce th at the d a ta is sto r e d in the eepro m . t he read after write f unction has no effect on this command. if the pass w o r d is w r ong or t he transmissio n is fault y , the c h i p w i ll : se nd a nak patter n ; return to th e st and ard rea d mode; a nd, th e pass w o r d w i l l remai n the same. (ref er to w r ite w o rd for pass w or d data structure) . ou t p u t wo rd n liw in pu t ac k rm w r it e pw ac t u al pw fw r ac k liw liw ac k ne w p w rm liw t r an sc eiver r f f i eld " o n " t pp t wa t we e f i g . 1 5 write word t he w r ite mod e a llo w s mo difi cation of th e e eprom conte n ts w o r d b y word. t o modif y ad dress 1 (pr o tection w o r d ) a n d addr ess 2 (c o n trol w o rd), it i s man dator y t o first sen d a l ogi n comm an d in ord e r to l o g i n (l ike in a computer). t he n e w w r itte n va lu es w i ll take effect onl y after p e rforming a rese t command. it is strong l y rec o mmen ded to check th e res u lt of modif y i ng the c ontents of thes e addr esses ef fecting the fun c tion of the chi p . address 0 ( p ass w or d) can not be mo difie d w i t h this comman d but can b e cha nge d w i th the w r ite pass w o r d comman d . address e s 3 to 31 are pr ogr a mmable accor d in g to the defi ned pr ot ectio n s . if the pass w o rd ch eck bit i s off (bit 16 of control w o rd) a nd th e w o rd is not w r it e inh i b i ted, the selecte d w o r d can b e freel y modifi ed w i t h o u t pass w or d. if the pass w o rd check bit is on an d the w o r d is n o t w r it e in hib i ted , the selecte d w o rd ca n b e modifi ed w i t h a previ ous log in. in an y cas e , if th e w o rd is w r ite i n hibit ed, the pro t ection w o r d ha s to be chan ge d before pr ogr amming c an oc cur. w r ite to a d d r ess ch eck pa ss w o rd b i t (16 bit / control w o r d ) write inh i bi t (protection w o rd) w r ite op eratio n 0 x x onl y w i t h w r ite pass w o rd co mmand 1 ? 2 x of f log in al w a ys r equ ired 1 ? 2 x on w r ite configur a t ion locked 3 ? 31 of f of f f r eel y pro g ram m abl e 3 ? 31 on of f log in req u ir ed 3 ? 31 x on cha nge protec tion w o r d first d 31 d 30 d29 d 28 d 27 d 26 d 25 d 24 p3 d 23 d 22 d 21 d 20 d 1 9 d 18 d 17 d 16 p2 d 15 d 1 4 d 1 3 d 1 2 ...... .................... d 0 2 d 0 1 d 0 0 p 0 p c 7 p c 6 p c 5 p c 4 p c 3 p c 2 p c 1 p c 0 " 0 " 0 0 a 5 a 4 a 3 a 2 a 1 a 0 padd addr ess da t a f i rs t b i t re c e i v e d n o te : a5 in w r it e m ode alw a ys " 0 " ( addr esses l a ser r o m ) fig. 16 t he w r ite w o rd comman d is follo w e d b y the address a nd d a ta. t he addre ss consists of a 9 bit block co ntain i ng 8 d a ta bits and 1 even p a r it y bit. onl y 6 bits from the d a ta secti on are us e d for th e w o rd a ddr essin g , and t he first t h ree bits s ent must be "0". t he dat a cons ists of 4 times 9 bi t blocks, each bloc k consisti ng of 8 data bits and 1 assoc i ated even parit y bit and one a d d i tion al block co nsistin g of 8 column parit y bits an d "0" as stop b i t (refer to fig. 7) cop y right ? 200 4, em microelectronic-marin sa 7 www.emmi croel e c troni c.com
r em4150 em4350 write word (cont.) after reception of the command, the address, and the data, t he em4150 w ill check the parit y , the w r ite protection status, the log in status, a nd a l so if the a v aila bl e p o w e r from the rf fie l d is s u fficie n t. if all the con d iti ons ar e satisfi e d, an ackn o w l e dge pattern (ack) w i ll be iss u e d after w a r d and t he eeprom w r iting pr ocess w i ll start. at the en d of pro g r a mming, th e chip w i l l send an ackno w l e d g e pattern (ack). if at le ast on e of th e checks fai l s, th e chi p w i ll issu e a no ackno w l edg e p a ttern ( n ak) instea d of ack and r e turn to t he stan dar d r ead m o d e . t he t r an sceiver w i ll ke ep th e rf field perm a n ent l y "on" d u rin g the w h ol e w r iti ng p r ocess time. t he read after w r ite function (bit 17 of co ntrol w o rd) co ntrols th e m o d e of op er ati on follo w i n g a w r ite o per ation. w h e n "on" the l a test w r itten w o rd w ill b e re ad out and outp u t ne xt to the ack p a ttern an d t w o listen w i ndo ws (liw -liw ) even if the w o r d is r e a d protect ed. w hen "of f " , the ack is fo llo w e d imme diate l y b y a liw - liw and f w r. t he last w r itten w o rd i s not outp u t. if a request fro m the transce iv er to return in r e ceiv e mod e ( r m) is ge ner ated d u rin g the l i w , another w o rd can be w r itten i n . other w i se, the em415 0 w i l l re turn in the stan dard r ead mo de. ou tp u t w o rd n li w in p u t ac k rm wri t e w o rd ad d r ess da t a ac k li w ou tp u t w o rd n li w in p u t na k rm wri t e w o rd ad d r ess da t a li w w r it e 1 w o rd w r it e se veral wo rd s r ead a f t e r w r it e f u n c t i o n ou tp u t w o rd n li w in p u t ac k rm wri t e w o rd ad d r ess da t a ac k li w rm wr ite wor d ad d r ess da t a ou tp u t w o rd n li w in p u t ac k rm wri t e w o rd ad d r ess da t a ac k l a s t wr i tte n li w f w r li w fwr li w li w fwr li w not e : the last w r i t t en i s ou t pout even i f r ead pr ot e c t ed. t r an sc ei ver r f f i el d "o n " t r an sc ei ver r f f i el d "o n " t r an sc ei ver r f f i el d "o n " t r an sc ei ver r f f i el d "o n " li w t wa t we e t wa t we e t wa t we e t wa fig. 17 cop y right ? 200 4, em microelectronic-marin sa 8 www.emmi croel e c troni c.com
r em4150 em4350 po w e r on reset (p or) w hen the e m 415 0 w i th it s attached co il enters a n electrom agn eti c field, the b u ilt in ac/dc c onverter w i ll supp l y th e ch i p . t he dc vo ltage is mon i tored a nd a reset si gn al i s ge nerate d t o in itia lise the log i c. t he contents of the contro l w o rd and protectio n w o rd w i ll b e do w n lo ad ed to ena bl e the f u nctions (init ) . t he po w e r on res e t is al so pr ovid ed in order to mak e sure th at the chip w i ll start issuing correct data. h y st eresi s is provide d to avoid im pro per op erati on a t the limit level. t vd d t re s e t v v e m 4150 a c ti ve t in it prh prhys fig. 18 lock all / lock memor y area t he em4150 can be co nverte d to a read onl y c h ip or b e config ured to rea d /w rite and re ad o n l y are a s b y progr ammin g the pr otectio n w o rd. t h is con f igurati on c a n be l o cked b y w r it e i nhi bitin g the w r ite pro t ection w o rd. great care sh oul d b e tak e n in d o in g th is oper ation a s there is no further p o ssi bil i t y to c h a n g e the w r ite protection w o rd. t he co ntrol w o rd c an also b e protected in th e sam e w a y t hus fre e zin g t he oper atio n mode. clock ex trac tor t he clock extr actor w i ll gen e r ate a s y stem clock w i th a freque nc y corr espo ndi ng to t he fre que nc y o f the rf fie l d. t he sy stem cl ock is used b y a seque ncer to gen erate al l internal timings. data extr actor t he transceiv er ge nerate d field w i ll b e ampl itud e modu lated to transmit data to the em415 0. t he data extract o r dem odu lates the i n comi ng sig n a l to gener ate logic l e ve ls, an d deco des the i n comi ng dat a. modulato r t he data mod u lator is driv e n b y the s e ria l data o u tput from the memor y w h ich is manch e ster e n cod ed. t h e modu lator w i ll dra w a l a rg e curre nt fro m both c o il terminals, thu s amp litud e modu latin g th e rf fi el d accord ing to th e memor y data . ac/ dc conv erter a nd voltage limiter t he ac/dc converter is ful l y integr ated o n chip a nd w i ll extract the po w e r from the in cide nt rf fi eld. t he inter n a l dc vo ltag e w i ll b e cl amp e d to av oid hi gh inter nal dc voltag e in stron g rf fields. reso nanc e capa citor t he resona nc e cap a citor is i n tegrate d , and its toleranc e is adj usted to 2% over the w hol e prod uctio n . typical capacitor variation versus temperature temperature [c] 99.7 99.8 99.9 100.0 100.1 100.2 100.3 -50 -30 -10 10 30 50 70 90 cr tolerance [%] fig. 19 special timings t he processin g paus e t i me (tpp), w r ite access t i me (t w a ) a nd ee prom w r ite t i me (t w e e) are timings w h er e the e m 415 0 is e x ecut in g inter n al o perati ons. durin g these p auses, the rf field w i ll be infl u ence d . d u ring t w a and t w ee, t he signal on t he c o il is dam ped due t o a higher c u rr ent c ons um pt ion. 32 32 r f periods : t pp sam e m odula t ion as f o r a normal bit 16 16 (opt 64) (opt 32) 64 32 (opt 64) (opt 32) t wa 3200 2624 (opt 64) (opt 32) t wee f i g . 2 0 cop y right ? 200 4, em microelectronic-marin sa 9 www.emmi croel e c troni c.com
r em4150 em4350 communica tion from tra n spond er to the tra n scei v e r ( read mode ) t he em4150 modu lates the amplit ude of th e rf field to transmit data to the transceiv er . data are outp u t serial l y from the eeprom and manch e ster en code d. 1 b i t 64 per iods of rf f i eld ( o pt 64) 32 per iods of rf f i eld ( o pt 32) c oded d a t a m easur ed on t he c o i l dat a f r om eepro m 32 per iods ( o pt 6 4 ) 16 per iods ( o pt 3 2 ) 1 bit 1 bit 1 bit o p t 6 4 is t he c h ip opt ion wit h a bit per iod c o r r e s ponding t o 64 per iods of t he rf f i eld o p t 3 2 is t he c h ip opt ion wit h a bit per iod c o r r e s ponding t o 32 per iods of t he rf f i eld fig. 21 t he em4150 u s es differe nt p a tterns to se nd status informa tion to th e tran sceiver. t heir s t ructure can no t be conf used w i t h a bit pattern seq uenc e. t hese patterns are th e listen w i n d o w (l iw ) to info rm the transcei v er that data can be acc epte d , th e ackno w l e d ge ( a ck) ind i cati n g pro per com m unic a tion an d en d of eep rom w r it e, an d the n o ackn o w le dg e (nak ) w h e n somethi ng is w r ong. t he liw , due to its spec ial str u cture, c an be used to s y n c hr oniz e the trans ceiver d u ri ng a read oper atio n. t he liw is sen t before e a ch w o rd, and is se n t t w ice b e fore f w r. liw ack nak al l num ber s r epr es ent number of per i ods of rf f i el d 32 32 1 2 8 6 4 6 4 32 32 96 32 64 32 32 32 32 96 32 96 32 16 16 48 16 32 16 16 16 16 48 16 48 1 6 16 16 64 32 32 ( o pt 64 ) ( o pt 32 ) ( o pt 64) ( o pt 32) ( o pt 64) ( o pt 32) o p t 64 is t h e c h ip opt ion wit h a bit per iod c o r r es ponding t o 64 per iods of t he rf f i eld o p t 32 is t h e c h ip opt ion wit h a bit per iod c o r r es ponding t o 32 per iods of t he rf f i eld fig. 22 communica tion from the transc eiv e r to the tr ans ponder (re c eive mode) t he em4150 c an b e s w itc hed to the r e ceiv e mode on ly during a lis t en window. t he t r an sceiver is s y nc hron iz e d w i t h the incom i ng d a ta from th e transp o n der and e x pects a li w before e a c h w o r d . duri n g the p has e w here th e chi p h a s its modu lator "on " (64/ 32 per iod s of rf [opt6 4 /op t32] ), the tr ansce iver has to se nd a bit "0" . a certai n ph a s e sh ift in the r ead path of the tra n sceiv er can b e acce pted d u e to the fact that w h e n enter i ng re c e iv e mode, the t r ans ceiver b e com e s the master. at recepti on of the first " 0 ", th e chi p immed i atel y sto p s the liw seq uenc e a nd th en e x pects a noth e r bit "0 " to activ a te th e receiv e mode. once the em4 150 h a s rece iv ed the first bit "0", the transcei v er is imposi n g t he timing for s y nc hro n isati o n. t he em4150 turns "on" its modu lator at th e beg in nin g of each fr ame of a bit peri od. t o send a l ogic " 1 " bit, the trans ceiver contin ues to s end c l ocks w i t hout m odu lati o n . after half a bit per io d, the modu latio n d e v ice of th e em 415 0 is t u rne d "off" allo w i n g rech a r ge of the inte rnal su ppl y ca pacitor. t o s end a lo gic "0 " bit, the transceiver stops se ndi ng clocks ( 100 % modulation) during the first half of a bit per iod. t he transceiver must not turn "off" the field after 7/4 c l ocks of the bit pe ri od (opt64/opt32). t he field is st opp ed for the r e mai n in g first half of t he bit p e rio d , an d the n turne d "on" a gai n for th e se con d half of the bit p e rio d . t he 32rd/16th clock (op t 64/opt32) defi nes the e nd of the bit t o ensure s y n c hron isatio n b e t w e e n the tra n sceiv er and t he tr ansp o n d e r , a logic bit s e t to "0" has to be transmitt ed at regu lar i n terval s. t he rm pattern cons ists of t w o bits set to "0" thus a l l o w i ng in itia l s y nch r oni s a tion. in a dditi on, the ch o s e n data structure contai ns ev e n parit y bits w h i c h w i ll not all o w mor e than ei g h t consec utive bits set to logic " 1 " w h er e n o modu latio n occ u rs. cop y right ? 200 4, em microelectronic-marin sa 10 www.emmi croel e c troni c.com
r em4150 em4350 communica tion from the transc eiv e r to the tr ans ponder (re c eive mode) (cont.) w h ile the tran sceiver is sen d i ng d a ta to the transpon der, tw o di ffere nt modu latio n s w i l l be obs erved o n both coi l s. durin g the first half of the bit p e rio d , the em4 1 5 0 is s w itc h in g "on" its modu latio n devic e caus in g a mod u lati on of the rf fiel d. t h is modu latio n ca n als o b e o b s e rved on th e t r ansce iver' s co il. t he transcei v er sen d i ng a bit "0" w i ll s w it ch "of f " the field , causi ng a 1 0 0 % modu latio n bei ng o b serve d on the trans p ond er coil. tr ansceiver coil transponder coil "1" " 1" "1" "0" " 0" "0" 16 16 per i ods of r f f i el d ( o pt 32) : bit per i od data : m odu l a t i on i nduced by t he tr anscei v er m odul at ion induced by t he tr ansponder 16 * * r e com m ended mi n i mu m : 7/ 4 per i ods ( o pt 64/ o p t 32) 16 per i ods of r f f i el d ( o pt 64) : 32 32 32 32 : 1 per i o d fig. 23 cop y right ? 200 4, em microelectronic-marin sa 11 www.emmi croel e c troni c.com
r em4150 em4350 pad des c ription 9 1 8 7 6 5 4 3 2 pa d n a me func tio n 1 2 3 4 5 6 7 8 9 coil1 vpos te s t _ i n vdd te s t _ o u t te s t t e st _clk vss coil2 coil t e rminal 1 internal supply t e st input w i th pull- do w n positive internal supply voltage t e st output t e st mode inp u t w i t h pul l-do w n t e st clock inp u t w i t h pul l-do w n negative internal supply voltage coil termi na l 2 packag es f f g c2 c1 ma rk i n g are a d a b e j k fro n t v i e w t o p vi ew r y x z sym b o l m i n t y p m ax x8 . 0 y4 . 0 z1 . 0 d i m e ns i o ns a r e i n m m d i m ens ions a r e i n m m cid pa ckage pcb pack age c2 c 1 sym bo l m i n t y p m ax a8 . 2 8 . 5 8 . 8 b3 . 8 4 . 0 4 . 2 d5 . 8 6 . 0 6 . 2 e 0 .3 8 0 .5 0 . 6 2 f 1 .2 5 1 .3 1 . 3 5 g0 . 3 0 . 4 0 . 5 j 0 .4 2 0 .4 4 0 .4 6 k 0 . 1 15 0. 1 2 7 0 . 1 3 9 r0 . 4 0 . 5 0 . 6 fig. 24 fig. 25 chip dimens ions f i g . 2 6 f i g . 2 7 cop y right ? 200 4, em microelectronic-marin sa 12 www.emmi croel e c troni c.com
r em4150 em4350 ordering information die form t h is chart show s g e n e ral offe ring; for detai le d part number to order, ple a s e see the tab l e ?standard v e rsions? b e lo w . - c i rcuit n b : c ust o m e r version: e m 4150: s t andard p a d s %%% = o n l y fo r cu sto m s p e c ific v e r s io n e m 4350: m e g a p ads v ersi on: bum p in g : a6 = m a n c h e s te r , 6 4 cl o cks p er bi t " " ( bl ank ) = no bum p s a5 = m a n c h e s te r , 3 2 cl o cks p er bi t e = w i t h gol d b u m p s ( not e 2 ) di e form : t hi ckness: ww = wa f e r 6 = 6 m i l s ( 152um ) ws = s a w n wa f e r / f r a m e 7 = 7 m i l s ( 178um ) wt = s t i c k y ta p e 11 = 11 m i l s ( 280um ) wp = wa f f l e p a c k ( not e 1 ) 21 = 21 m i l s ( 533um ) 27 = 27 m i l s ( 686um ) em 4150 a6 w s 11 %%% packag ed dev i ces t h is chart show s g e n e ral offe ring; for detai le d part number to order, ple a s e see the tab l e ?standard v e rsions? b e lo w . - circ uit nb : c u s to mer ver s io n: e m 4 150 : s t a nda r d pa ds %% % = o n l y fo r c u st o m spe c if i c ver s ion ve r s i o n : a 6 = m a n c he st er , 64 c l oc ks pe r bit a 5 = m a n c he st er , 32 c l oc ks pe r bit pa ck ag e / ca rd & de liv ery f o rm: ci2 l b = ci d pa c k , 2 lo ng p i n s (2 .5mm), in ta pe c i 2l c = c i d p a c k , 2 lon g pi ns ( 2 .5 m m ) , i n b u lk c i 2s b = c i d p a c k , 2 sho r t p i n s (1 . 25m m ) , i n t ape c i 2s c = c i d p a ck, 2 sh or t p i n s ( 1 . 25m m ) , i n bu lk c b 2r c = p c b p a c k ag e, 2 pi ns, i n bul k s o 8a = s o - 8 p a c k ag e, in s t i ck ( n o t e 1) ci 2l c % % % em4150 a6 rem a rk s: ? f o r orderi ng pl ease us e t abl e of ?st andard v e rsio n? t able b e lo w . ? f o r specif icat i o ns of deliv er y f o rm, includ in g gol d bum ps, t ape an d bu lk, as w e ll as poss i ble ot her d e liv er y f o rm or packa ges, pl ea se cont act em microel ect r on ic -marin s. a. ? note 1: t h is is a non-stan dar d packa ge. ple a se contact e m microelectro n ic-mari n s.a for avai lab ilit y. ? note 2: em43 50 is pref er abl y us ed w i t h g o l d bumps. use of em4150 w i t h gol d bum p t oget her w i t h dir e ct t e chnol og y is subj ect t o licen se, pleas e cont act em sales of f i ce. cop y right ? 200 4, em microelectronic-marin sa 13 www.emmi croel e c troni c.com
r em4150 em4350 copyright ? 2004, em microelectronic-marin sa 14 www.emmicroelectronic.com standard versions & samples: for samples please order exclusively: part number bit coding cycle/ bit pads package delivery form em4150 a6ci2lc manchester 64 standard cid pa ckage, 2 pins (length 2.5mm) bulk em4150 a6cb2rc manchester 64 standard pcb package, 2 pins bulk the versions below are considered standards and should be readily available. for other versions or other delivery form, please contact em microelectronic-marin s.a. please make sure to give complete part number when ordering, without spaces between characters . part number bit coding cycle/ bit pads package/die form delivery form / bumping em4150 a5cb2rc manchester 32 standard pcb package, 2 pins bulk em4150 a5ci2lc manchester 32 standard cid pa ckage, 2 pins (length 2.5mm) bulk em4150 a5ci2sc manchester 32 standard cid pa ckage, 2 pins (length 1.25mm) bulk em4150 a6cb2rc manchester 64 standard pcb package, 2 pins bulk em4150 a6ci2lb manchester 64 standard cid pa ckage, 2 pins (length 2.5mm) tape em4150 a6ci2lc manchester 64 standard cid pa ckage, 2 pins (length 2.5mm) bulk em4150 a6ci2sb manchester 64 standard cid pa ckage, 2 pins (length 1.25mm) tape em4150 a6ci2sc manchester 64 standard cid pa ckage, 2 pins (length 1.25mm) bulk em4150 a6so8a manchester 64 standard so-8 package stick em4150 a6ws6 manchester 64 standard sawn wafer, 6 mils no bumps em4150 a6ws7 manchester 64 standard sawn wafer, 7 mils no bumps em4150 a6ww27 manchester 64 standard unsawn wafer, 27 mils no bumps em4150 a6ww7 manchester 64 standard unsawn wafer, 7 mils no bumps em4150 xxyyy-%%% manchester 32/64 standard custom custom em4350 a6wp11e manchester 64 mega die in waffle pack, 11 mils with gold bumps em4350 a6ws11e manchester 64 mega sawn wafer, 11 mils with gold bumps em4350 a6wt11e manchester 64 mega die on sticky tape, 11 mils with gold bumps em4350 xxyyy-%%% manchester 32/64 mega custom custom product support check our web site under products/rf identification section. questions can be sent to info@emmicroelectronic.com em microelectronic-marin sa cannot assume responsibility for use of any circuitry described other t han circuitry entirely embod ied in an em microelectronic-marin sa product. em microelectronic-marin sa re serves the right to change the circuitry and specifications without notice at any time. you are strongly urged to ensure that the information given has not been superseded by a more up-to-date ve rsion. ? em microelectronic-marin sa, 08/04, rev. f

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