View HI1386_4200566.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 1-888-intersil or 321-724-7143 | copyright intersil corporation 1999 using intersil high speed a/d converters introduction table 1 shows the wide range of high-speed adcs available from intersil. maintaining the accuracy of these converters in a high-speed environment can be quite a challenge. this note will point out considerations for board layout, grounding, power management, and suggest various support circuits. board layout, ground and power considerations the cost of multilayer boards has decreased to the point where they are now commonly used with high-speed mixed signal circuits. this technology enables the use of solid ground and power planes which will result in the lowest impedance possible while minimizing any shared imped- ances. figure 1 illustrates the sequencing of the layers used on the hi1276 evaluation board. the dimensions called out were those required to achieve 50 ? microstrip for the signal lines. figure 1. hi1276 evaluation board layers there are many board layout techniques that can be used on a mixed signal board to keep digital noise from corrupting the analog signal path. the ground layer should be sepa- rated into an analog and a digital ground with an eighth of an inch spacing between them to minimize coupling.analog components should be separated from the digital compo- nents. this is simpli?d if the converter has separate analog and digital supply and ground pins making it fairly obvious where to locate the components in relation to the adc. component / signal layer 0.3mm 0.3mm 0.1mm 0.5mm ground layer power layer solder layer table 1. intersil high-speed converters table bits conversion speed logic levels input bandwidth technology ca3304 4 25 msps cmos 13mhz cmos flash ca3306 6 18 msps cmos 9mhz cmos flash hi5701 6 30 msps cmos/ttl 20mhz cmos flash ca3318 8 15 msps cmos 2.5mhz cmos flash hi5700 8 20 msps cmos/ttl 18mhz cmos flash hi1175 8 20 msps cmos 18mhz cmos two-step hi1176 8 20 msps cmos 18mhz cmos two-step HI1386 8 75 msps ecl 150mhz bipolar flash hi1396 8 125 msps ecl 200mhz bipolar flash hi1166 8 250 msps ecl 200mhz bipolar flash hi1276 8 500 msps ecl 300mhz bipolar flash hi5800 12 3 msps ttl 20mhz bicmos two-step application note october 1993 an9214.2
2 position the components and signal lines over their corre- sponding analog or digital ground plane. this will minimize inductive loops, and thereby reduce ringing and magnetic coupling into sensitive analog areas. it also results in a cer- tain measure of high frequency decoupling on the supply lines. route all controlled impedance signal lines on the component layer minimizing the number of through holes. the holes will make it dif?ult to maintain a controlled imped- ance and will tend to generate additional noise on the board. additional power or noncontrolled impedance signal lines could be run on the solder side. pay particular attention to the analog input and reference traces to the adc. route them so as to minimize capacitive coupling from any digital lines. unexpected frequency components in a spectrum plot for the adc might be caused by digital noise coupling onto the analog traces. it is especially critical for the ecl convert- ers with multiple v in pins to equalize the line lengths to these pins. the analog and digital grounds should only be tied together in one place. the choices are under the adc, at the edge of the board, or back at the supplies. when the system has a single adc then the best place is usually under the adc. a wise decision in the prototype phase of a design is to allow for all three choices so the optimum scheme can be deter- mined. do not tie the grounds together back at the supplies and under the adc. this will create a ground loop and gen- erate additional noise. if the system has multiple adcs, then treat each one as an analog part, and group it close to the other analog components. tie the grounds together either at the edge of the board or back at the supplies. avoid mounting high-speed converters in ic sockets. their parasitic resistance, inductance, and capacitance will usually degrade the performance of the part. instead use ?in sock- ets?amp part no. 5-330808-3. all the parts in table 1, except the ca3304 and ca3318, have evaluation boards available. copies of the layout are provided with the documentation that comes with the board, and it is suggested that it be used in a system design to get the best performance from the part. figure 2. suggested power scheme again, in the interest of keeping digital noise out of the ana- log signal path, the adc should have separate analog and digital supplies. figure 2 shows a suggested scheme for bypassing the supplies. each supply is bypassed to its respective ground. a 10 f tantalum cap is usually placed at the edge of the board to keep any low frequency noise from getting on the board. since a bulk capacitor will look induc- tive at higher frequencies, an additional 0.1 f chip cap is placed at the adc supply pins. the ferrite bead performs two functions. first, it will damp the resonant circuit formed by the 10 f cap, the parasitic inductance of the trace to the power pin of the adc, and the 0.1 f cap. and, if system cost constraints do not allow separating the analog and digital supplies, then the bead will keep the digital noise off the analog supply. the hi1175 could latchup if at power up there is a time skew between the analog and digital supplies. therefore, do not separate these supplies or insert a ferrite bead between them, but instead tie both to the +5v analog supply. figure 3. remote power supply connections figure 3 is a suggested scheme for bringing power to a motherboard with remote power supplies. the analog and digital grounds are tied together at the edge of the board along with earth ground. allow for a large number of ground connections to the board to minimize voltage drops across the backplane. notice the use of twisted pair lines to mini- mize the inductance of the supply lines. the 150 ? resistor ensures that the power supplies have a reference to earth ground at all times and is large enough to prevent ground- loop currents. try to avoid using switching power supplies whenever possi- ble. the large spikes, 100mv or more at about 100khz, found on these supplies have frequency components that can extend into many megahertz. since the psrr of the adc will tend to rolloff signi?antly from its dc value, there can be a reduction in the overall signal to noise ratio (snr) of the converter. if it is necessary to use a switching power supply, then ?ter its output with commercially available dc power ?ters. a linear regulator could also be used to provide a certain amount of isolation on an analog supply. 10 f 0.1 f 0.1 f 10 f fb fb ferrite bead (fair rite 2743001111) fb - v a v d agnd dgnd avcc dvcc adc power source #1 + 150 ? 150 ? - + - +v cc #1 +v cc #2 power source #2 motherboard application note 9214
3 references a number of factors must be considered when designing a reference for a converter. accuracy must be maintained over the temperature range of the adc, and the noise it gener- ates must not degrade the snr of the converter. the refer- ence voltage terminals for a ?sh converter are typically subjected to internal transient currents during conversion. therefore, it is important to drive the adc reference pin from a low impedance source and to decouple thoroughly between the v ref + and v ref - pins. the reference must also be able to drive the low impedance of the reference lad- der (as low as 75 ? for the ecl ?sh converters). figure 4 is a reference circuit capable of producing a positive and a negative reference voltage of about 4v that has a 40ppm/ o c drift over temperature. the positive side of the reference could be used with the cmos converters, while the negative side could be used with the ecl parts. the feedforward and feedback resistors of the op-amps would be scaled for the required reference voltage.the hi1166 and hi1276 have the provision for bypassing the rs parasitic resistance using the sense pins (v rts and v rbs ). all the other ?shes do not have this option, so they would close the feedback loop at the converter reference input pin. figure 4. flash reference circuit figure 5. hi5800 reference circuit +5v 10 2n3904 ca3193 220 +12v + -12v 10 33pf 3.9k 8k 2k +5 2k 0.1 + 10 f 12k 2k 2n3906 10 -5v 33pf 220 + +12v -12v ca3193 3.9k 10 icl8069 reference ladder r s r s flash v rt v rts v rbs v rb +15 -15 + +15 -15 +15v + 10 f 0.1 f v out v fb r a r b c 10k low tc 10 + 10 f 0.1 f hi5800 ref in ref101 resistor ha5177 ha5002 + application note 9214
4 the ca3306 has an internal 6.2v zener that can be used to generate the reference voltage for the part. however, this technique is not recommended for converters with greater than 6 bits of resolution, because of the noise generated by the zener diode. for these parts, a bandgap reference such as the icl8069 should be used. the internal reference for the hi1175 and hi1176 are resis- tors to +5v and ground that in combination with the refer- ence ladder sets v rt to 2.6v and v rb to 0.6v. these voltages are speci?d at a nominal supply and will be very sensitive to the actual supply voltage used in a system. bypass the v rt and v rb pins heavily in order to ensure that power supply noise does not get into the converter refer- ence. the hi5800 12 bit sampling converter has an internal 2.5v 20ppm/ o c reference. if a user decides to provide an external reference, then they will be faced with various problems. the drift of the reference over temperature must be low, and it also must be capable of driving the 200 ? input impedance seen at the ref in pin of the hi5800. figure 5 is a recom- mended circuit for doing this that is capable of 2ppm/ o c drift over temperature. notice that in this case a ref101 is used to supply the reference voltage capable of 12 bit perfor- mance. a slightly cheaper ref102 can be used if a larger t c can be tolerated. analog input buffers in general, the analog input to an adc needs to be ampli?d or buffered for the following reasons: to adjust gain and off- set, to sink any spurious clock kickback generated during the conversion process, to drive the adcs input capacitance, or to maintain circuit bandwidth. figure 6. non inverting amplifier figure 6 is an example of a high input impedance nonin- verting ampli?r that will level shift an input to an offset determined by v offset . the gain can be calculated from: figure 7 is an example of an ampli?r that will also offset the input depending on v offset ; but, in this case, the input will be inverted and the input impedance is equal to the value of r1. the equation for the circuit gain is: figure 7. inverting amplifier these circuits could be used to level shift unipolar inputs to the 2.5v range of the hi5800 or translate them up to the levels required by the hi1175 and hi1176. several factors need to be considered when selecting an ampli?r to drive an adc. first, the dc performance of the ampli?r must match the desired system accuracy. refer to references 1, 2, and 3 for an excellent discussion of the dif- ferences between voltage and current feedback op-amps and the dc accuracy that can be expected of them. table 2 shows some of the ?st-pass approximations of the required bandwidth for a given type of input signal. the nyquist criterion would then set the minimum sampling rate at twice the bandwidth. there are a number of reasons why the bandwidth of the input circuitry to the adc is usually much wider than these approximations. all applications will suffer a loss of dynamic range as the input to the adc approaches the -3db band- width. in ccd or muxed input applications (pulsating dc) a wide bandwidth system will settle faster to a new input and recover quicker from an overrange. signal distortion of base- band (sinusoidal) or pulse signals (complex periodic) will be avoided if the input is operating over a ?t portion of the sys- tem frequency response and has a zero phase shift over its entire frequency range. a more realistic goal is a phase shift that is proportional to frequency. that is, the second har- + v offset r 3 r 1 v in v out v in r 2 adc v out 1 r 2 r 1 r 3 --------------------- - + ?? ?? ?? ?? v in r 1 r 1 r 3 + ----------------------- - ?? ?? ?? v offset = r 1 r 3 r 1 r 3 r 1 r 3 + ----------------------- - = table 2. bandwidth approximations input signal approximate bandwidth required pulsating dc rate of change (v/s)/1v sinusoidal 1/period complex periodic 20/fundamental period single event 1/pulse width v out r 2 r 1 -------- ?? ?? ?? v in r 2 r 3 -------- ?? ?? ?? v offset = + v offset r 3 v out v in r 2 v in r 1 adc application note 9214
5 monic should be delayed twice as much as the fundamental, the third three times as much, and so on. when this occurs, all the frequency components will end up having the same amount of time delay resulting in a signal that is only delayed slightly in time and can easily be adjusted for. for a single pole system, the attenuation factor and phase shift at a particular frequency relative to the f -3db can be cal- culated from: (1) and (2). taking these error terms into account, the complete equation for a sinewave including the effects of the system would now be: . once the phase shift has been calculated the corresponding time delay at frequency f will be: . in equation 1, when f equals 4mhz (video) and the attenua- tion a(f) is one 8 bit lsb (0.4%), the required small signal bandwidth f 3db would be 40mhz. the corresponding phase shift at 4mhz would be 5.7 o and the time delay is 4ns. con- sult the datasheet for a particular op-amp to ?d out if it will provide the desired gain ?tness and phase response over the required bandwidth. keep in mind the signal levels required for a full scale swing to the adc and at what level the bandwidth for the op-amp is speci?d. there are many ways to spec the bandwidth of a converter, but the important point is its accuracy at the desired operating frequencies. figure 8 is a model for the analog input circuit for a typical ?sh converter. the inductance l includes the lead induc- tance of the part and the inductance due to the v in trace on the board. resistor r includes the output resistance of the op-amp. figure 8. flash input circuit the circuitry driving the analog input of one of the 8 bit ecl ?shes must drive 255 bipolar comparators. each compara- tor will have a parasitic capacitance formed by a reverse biased p-n semiconductor junction. the capacitance will be a nonlinear function of voltage and temperature. normally, the adc analog input would present a total capacitive load (c in ) which would also vary depending on the state of the comparators internal to the converter. however, the design used in the intersil ecl converters has minimized this effect and the resulting kickback on the analog input. the circuit in figure 8 can be optimized for a particular ecl ?sh and board layout by the proper selection of resistor r. too low a value for r will cause peaking in the frequency response and too high a value will result in a loss of band- width. the process to select the correct value for r will involve plotting the bandwidth for the total system at a num- ber of different values of r. in some cases additional band- width can be gained by adding ropt and copt but it will require a more complicated selection process. a user should refer to the evaluation board available for a particular adc for a suggested layout, op-amp, and component values. the input capacitance (c in ) for a cmos ?sh depends on the state of the convert clock signal. for example, the analog input capacitance of the hi5700 is typically 60pf during the sample phase and 15pf during the auto-balance phase. the charging current for these capacitors will generate a current pulse that is present at the input at the beginning of every sample and auto-balance period. the peak current transient is dependent upon the applied voltage, input capacitance during sample phase, and the driving source impedance. ideally, the input to the adc should settle fast enough in one sample period so the accuracy of the conversion is not degraded. these transients can be quite large for the cmos converters and is the primary reason why a wide bandwidth buffer is always recommended to drive the analog input to these parts. the circuit depicted in figure 8 can be tuned for the best settling time for a particular cmos adc by the proper choice of r and will occur when: . since the values for r and l are hard to quantify, the calcu- lated value will probably have to be adjusted a few ohms one way or the other in an actual system before an opti- mum value is found. an r of 27 ? was determined to be appropriate for a ha5020 driving a hi5700 mounted on its evaluation board. the ha5020 is a good choice for an op- amp to use with the family of cmos converters. the settling time for the above circuit, neglecting l, can be calculated from t s = 0.69 x n x r x c. n is the desired reso- lution. this equation applies only to cmos converters with switched capacitor inputs. if the ?sh is the 8 bit hi5700, and r is equal to 27 ? , then the settling time would come out to 9ns, well within the sample time of the hi5700 running at a 20mhz encode rate. an op-amp with adequate slew rate, full power bandwidth (fpbw), and drive current should be selected to drive an adc. the minimum required slew rate can be calculated from: sr min =2x xv peak x fpbw. an hi1276 500 af () 1 1 f f 3db --------------- - ?? ?? 2 + -------------------------------------- - = f () f f 3db --------------- - ?? ?? atan = vt () a 1 f f 3db --------------- - ?? ?? 2 + -------------------------------------- - t f f 3db --------------- - ?? ?? atan + ?? ?? sin = t d f () 360 f ----------------- = c in v in flash op-amp r l c r * * * optional opt opt r2 l c --- - ?? ?? = application note 9214
6 msps converter with a 2v reference would have a vpeak equal to 1v and the required fpbw would equal 250mhz (nyquist). the minimum slew rate needed from the op-amp would then be 1571v/ s. the minimum required output drive current is a function of the maximum slew rate, termination load impedance, and feedback current, if any. given the required slew rate, the minimum output current needed from an ampli?r just to charge the hi1276 input capacitance load of 20pf, is found by: the hfa1100 is one of a family of high-speed op-amp and buffers that have suf?ient slew rate and output current to drive the analog input of the intersil family of ecl convert- ers. the overall system performance at a particular frequency will not be degraded if the harmonic distortion of input circuit to an adc is less than that of the converter. given that the dynamic range for a perfect 8 bit converter is 50db, for a 0.5db reduction in the overall system distortion, the ampli? ers contribution must be less than 58db. a 3db reduction would result if the harmonic distortion of both the adc and ampli?r were equal. sometimes it is dif?ult to get from the ampli?rs data sheet a clear picture of what distortion to expect at the particular levels and frequencies the user will be operating. the gain ?tness spec can also be used to give an indication of the op-amp linearity. for example, for 8 bit accuracy the op-amp should have a gain ?tness of 0.2db out to the frequency of interest. an ampli?r circuit driving an adc must also minimize the total rms noise voltage that it generates or it will reduce the system snr. the objective is to keep this noise less than q/ ( 12 ) (q is the lsb size), which is the theoretical rms quantization noise of the adc. figure 9. op-amp noise model figure 9 is a ha-2841 op-amp driving an hi5800 with the voltage noise (v n ) and current noise (i n ) sources modeled. the equation for the total rms noise over the bandwidth of interest is: where: v tot is the total rms noise voltage at the input to the adc. r 1 is the feedforward resistor. r 2 is the feedback resistor. r p is the noninverting input resistor. v n is input voltage noise spectral density. i nn is the inverting input current noise spectral density. i np is the noninverting input current noise spectral density. f bw is the bandwidth over which the noise is to be inte- grated. note that i nn and i np are equal in the case of voltage feed- back op-amps but will not be for current feedback op-amps. if the small signal bandwidth is not given for the converter, then use its full power bandwidth for f bw . for the values given in the ?ure, v tot is found to be equal to 180 v. this is about a factor of two less than the 352 v of quantization noise for a hi5800 12 bit adc with a 5v range. keep in mind that the amount of quantization noise is inherent to any adc given its lsb size. overall the ha2841 a good choice for driv- ing the hi5800. the circuits in ccd or muxed input applications must pro- cess large signal pulse type waveforms. in order to get the highest throughput possible, they must slew and settle quickly so, as depicted in figure 10, the adc can then accu- rately digitize the analog information. figure 10. time division multiplexed signal op-amp settling time is made up of two parts. initially the signal must slew until it enters a region where small signal analysis takes over. for a single pole frequency response, the error will then decay with a time constant determined by the small signal bandwidth of the op-amp. the settling time in an actual system is very much a function of the circuit par- asitics and the overall frequency response of the circuit. as such, it is dif?ult to calculate an accurate number before- hand. reference 2 has a more thorough discussion of set- tling time and the calculations involved. the extremely fast sr min outputcurrent capacitorload ------------------------------------------------ - i c ---- == i min sr min c 1571 10 6 () 20 10 12 () 31ma == = + r 2 2k hi5800 v in v tot ha2841 i np i nn v n r 1 1k r p 667 v n 16 nv () () hz ? = i nn i np 2pa () hz ? == f bw 20mhz = v tot 1.57 f bw = v n () 2 1 r 2 r 1 ---- - + ?? ?? 2 r 2 () 2 i nn () 2 r p () 2 i np () 2 1 r 2 r 1 ---- - + ?? ?? 2 ++ ?? ?? ccd output encode adc application note 9214
7 settling time of the hfa family of op-amps (11ns to 0.1%) make these parts very useful in these types of applications. additional large signal time domain converter speci?ations such as overvoltage recovery time and transient response time become important in these applications. transient response is a dif?ult test to perform especially to the 12 bit level. however, as in the case of the hi5800, if the converter is tested close to nyquist then its input will see full scale swings on alternate samples giving an indication of the over- all settling time of the part. this note has tried to give some of the important consider- ations when selecting an op-amp to drive a high-speed adc. it is advisable to breadboard up an application circuit on an evaluation board provided by intersil for a particular adc and verify the performance with the converter. increased accuracy adjustments can be made to the converter offset, gain, and linearity in applications where accuracy is of upmost impor- tance. the triming of an hi5700 will be used here as an example. however, the techniques are the same for all the cmos and ecl ?shes as long as the relationship of the output codes to the input voltage is noted. offset correction is trimmed ?st and is usually done in the preamp driving the adc (figure 6 and figure 7). another method to produce the desired offset is to adjust the lowside the low side of the reference (v ref- for the hi5700). what- ever method is used, a voltage 0.5 lsb up from the desired v ref- is applied to the input and the offset is trimmed until the code 0 to 1 transition occurs. gain correction is trimmed next. it can also be done in the preamp circuit, but a better choice is in the reference circuit by adjusting the fullscale reference voltage to the adc (v ref+ for the hi5700). the 2k pots in the reference circuit of figure 4 can be used for this purpose. a voltage 1.5 lsb down from the desired v ref+ is applied to the input and the gain is trimmed until the code 254 to 255 transition occurs. linearity errors in a ?sh converter can many times result in a bowed transfer curve rather than a straight line through the endpoints. if taps on the reference ladder are provided, the user can make external adjustments to reduce this nonlin- earity and improve the ac performance. figure 11 illustrates a transfer curve with these kinds of errors before and after adjustment of a midpoint tap. figure 11. linearity adjustment figure 12 is a circuit that might be used to drive the midpoint tap of a ?sh. the op-amp will isolate the resistors r from the ladder impedance allowing improved performance over temperature. the values of these resistors are not critical as long as they match well and do not load down the reference source. if the resistors do not match to 0.5% then it might be necessary to replace them with a potentiometer and adjust the tap voltage to one-half the voltage between v ref+ and v ref- . this adjustment should be made after the offset and gain errors have been trimmed. the capacitor value shown is that recommended for the hi5700. consult the datasheet for the value suggested for a particular ?sh converter. if the ?sh has the 1/4 and 3/4 taps available, as in the case of the hi5700 and the ca3318, the resistor string can be modi?d to generate the required tap reference voltages and the appropriate buffers added to drive the taps. figure 12. driving the reference tap linearity adjustment can improve the performance of the hi5700 and ca3318. this technique is not useful for the ecl ?sh converters because they already have linearity correction on the chip and therefore have excellent inl num- bers to begin with. another use for the ladder taps is to implement a nonlinear ideal linearity tap floating tap driven v in code 1/2 v ref v ref reference ladder flash r r 30pf v ref+ v ref- v ref+ v ref- 1/2r + 100 ca3193 application note 9214
8 transfer characteristic for the converter. a companding adc will reduce the midscale voltage from its normal value to increase the snr for low level signals. digital inputs and outputs table 1 shows that the intersil family of high-speed convert- ers has a wide range of logic families. consult the datasheet to make sure the input and output logic levels and clock speeds are compatible with the accompanying logic. in order to minimize noise, use the slowest logic family that will still work. there are a number of reasons for placing a data latch or buffer in close proximity to a converter. first, it could drive the large load capacitance normally seen on a digital buss, which can cause large digital power supply transient currents. for example, if all bits of an 8 bit ttl converter change simultaneously and the rise/fall time of the outputs are 5ns and the load capacitance is 15pf, the resulting transient current is 120ma. if the supply has a significant impedance, the resulting noise may not be adequately rejected by the psrr of the adc. in order to get the required isolation the supplies for the buffer must be separate from the supplies on the converter. a ferrite bead, in some cases, might be sufficient to provide the required isolation between the supplies. the buffer or latch could also be used to isolate the adc from a busy data buss. depending on the design and layout of a converter a significant parasitic coupling may exist between the digital outputs and the analog circuitry. a buffer or latch would shield the converter from the buss noise and avoid the resulting reduction in snr. the rise and fall times of the digital logic for the ecl flash converters will approach 1ns. this will infer a corresponding interface bandwidth of 350mhz. in order to attain these speeds a 50 ? system is used and usually requires microstrip or stripline techniques in the board layout. the HI1386 and hi1396 have single ended digital outputs. place buffers close to the part to minimize line lengths and ringing. the hi1166 and hi1276 have differential digital out- puts for the best noise rejection at the high data rates. refer to references 4, 5, and 6 for additional information on high-speed board design. it is possible to run the ecl family of high-speed flashes parts off a single +5v supply instead of the normal -5.2v supply. this will not effect the performance of the part but, as shown in figure 13, the analog input levels and digital output levels will be changed. if an op-amp from the hfa family of parts is used to drive the input, then its supply voltages will have to be skewed to get the output swings required. the digital output levels can be translated to ttl levels by using a positive ecl logic family (pecl) provided by motorola. figure 13. positive ecl levels reference 7 and reference 8 have more information on using this logic family. when running the ecl parts at the normal -5.2v supply the ecl logic levels can be translated to ttl levels using parts provided by motorola and texas instruments. ti provides a wide range of parts that includes buffers, transceivers, and latches. reference 7 and reference 9 have a complete listing of the parts available from these vendors. extraneous digital noise should be kept out of the convert clock source in order to minimize the timing jitter on this line and the resulting reduction of the signal to noise ratio (snr) of the adc. given a 250mhz input frequency to an hi1276 and an rms jitter (t a ) of 2ps on the clock source, the snr that can be expected only due to the effects of timing jitter can be found from: it is not a trivial task to design a clock source with 2ps of jitter and in this case it might be bene?ial to use a highly stable discrete bipolar sinewave crystal oscillator with heavy ?ter- ing to remove as much wideband and narrowband noise as possible. figure 14 is a circuit that can be used to convert a sinewave from the clock source to the ecl levels required by the converter. figure 14. clock circuit in the interest of keeping out any digital noise, the convert clock source should be treated as an analog circuit and as such grouped with the other analog components. be careful not to let this clock couple into the other analog circuitry. many times an application requires that a high sample rate ecl converter be interfaced to slower ttl dsp or buffer memories. figure 15 is a circuit that can be used to demux v cc = v rt = +5v v rb = +3v v oh = +4v v ol = +3.3v gnd snr 20 1 2 f in t a --------------------------------------- - ?? ?? log = sn r20 1 2 250 10 6 210 12 ----------------------------------------------------------------------------------- ?? ?? ?? log 50db = = -2v -2v 50 50 10h116 clock in q q v bb 0.1 f 50 application note 9214
9 the ecl digital data out of a converter effectively cutting the output data rate in half. this reduction in data rate can be extended by adding additional latches and the appropriate timing signals. figure 15. data demux circuit antialiasing filters figure 16. aliasing effects figure 16 shows the effect of sampling a bandlimited signal at less than nyquist (f s /2). the shaded area are signals at frequencies that were not in the original information but have been aliased into the baseband and will now limit the overall dynamic range of this system to 30db. if this was intended to be a 12 bit system, then the dynamic range is signi?antly less then the desired 74db. an antialiasing lowpass ?ter would be used to modify the rolloff from fa to f s /2 so that the aliased signals would now be below 74db in the baseband. several considerations need to be taken into account when designing the ?ter. the designer must know the required passband ?tness, the rolloff rate of the transition band, the ?al attenuation, and the phase characteristics. the lower the sampling rate, the steeper the rolloff has to be, the more poles required by the ?ter, and the greater the complexity of the ?ter design. there are a number of types of lowpass antialiasing ?ters and each one has certain characteristics. a butterworth ?ter has the ?ttest response near dc and has a moderately fast rolloff. this ?ter emphasizes constant amplitude versus con- stant phase shift therefore, the pulse response would have overshoot. a chebyshev ?ter has a rapid attenuation above the cutoff frequency with some passband ripple. it has a squarer amplitude response than the butterworth but less desirable phase and time delay. the cauer (elliptical) ?ter surpasses other ?ter designs for critical amplitude applica- tions. its very sharp rolloff rate with some ripple has the squarest possible amplitude response with poor phase and transient response. the bessel ?ter has an optimized phase response over a wide input frequency. the passband response is not as ?t as the butterworth and it has a mod- erate attenuation rate. this ?ter is most useful for pulse applications since it avoids overshoot/undershoot. refer- ence 10 gives an excellent discussion of these and other considerations in choosing an antialiasing ?ter. passive ?ters are usually recommended for higher fre- quency ?ters (>200khz). they will have impedances of around 50 ? to 100 ? . if the signal source can drive the ?ter, and the adc has a high input impedance, then place these ?ters directly ahead of the converter so the output noise of any buffer circuit will also be band limited. active ?ters are useful below 200khz. keep in mind the con- siderations that have already been pointed out when select- ing an op-amp to use with this type of ?ter. hi5800 step input applications in order to get the best performance in muxed or ccd appli- cations that use an hi5800, the step input to the converter should be timed correctly. as shown figure 17, the overall digital system should be quiet during the time the hi5800 is doing its ?al pass to 12 bit accuracy (t b to t c ). the pre- ferred time to switch the input is between t a and t b because it allows about 200ns for the input to settle to 12 bits prior to the hi5800 sample-and-hold acquisition time. if the input is switched at t c , then the overall conversion time of the hi5800 has to be extended to let the input to settle and still allow for the acquisition time of the sample-and-hold. con- sult the hi5800 datasheet for the exact timing values. it is dif?ult to ?d muxes that will settle to 0.01% accuracy in less than 200ns. the hi-508 is a 8 channel single ended mux that will settle to 0.01% in typically 600ns. the acquisi- tion time of the hi5800 would have to be extended by 400ns to accommodate the mux settling time which would decrease the system throughput rate to 1.3mhz. if the user wants higher throughput, they will have to settle for fewer channels. the hi-201hs is a four channel mux which will settle to 0.1% (10 bits) in typically 180ns. another choice is the ha-2444. it is a selectable four channel opera- tional ampli?r with a settling time of 120ns to 0.1%. if very high switching speeds are required, then dmos switches can be used. siliconix provides a series of high-speed dmos switches in the dg6xx series that will switch in about 25ns and can be driven by standard ttl logic. since 12 bit settling times are highly dependent on the board layout and enc clka clkb clkb ecl flash latch latch latch buffer memory or dsp 8 8 (ttl) sn10kht5574 clka enc 8 (ttl) < < < f a f s /2 f s - f a f s f s + f a 0db - 30db frequency dynamic range application note 9214
10 numerous other factors, it is unlikely the user will be able to calculate an exact number for the throughput of a particular system from data sheet information. input clamping there are various reasons for clamping the input to a con- verter. in muxed input application the converter might be subject to frequent over range conditions as the mux switches from channel to channel. a clamp circuit that limits the input to small overranges would protect the converter and also signi?antly reduce the amount of time it would take the adc to recover from the overrange. the analog input to the converter could also be severely overdriven if the sup- plies to an input buffer come up before the supplies to the adc. the obvious solution to this problem is to power the input circuitry off the same supplies as the adc. however, many ?shes can operate at input levels that are above the maximum output voltage capability of an op-amp operated at the same rails that power the converter. therefore, the input op-amp must operate off different supplies and the situation exists for power sequencing problems. the hi1175 is sus- ceptible to this effect, and therefore it is recommended the input be diode clamped to v dd and gnd. figure 17. hi5800 timing figure 18 is a circuit that might be used to clamp the input to the voltages set on v+ and v-. these voltages could be the rails of the converter or the reference circuit in figure 4 could be used to generate the required voltages. resistor r should be calculated to limit the current to a safe level through the clamp diodes and the analog input of the ?sh. as discussed in the op-amp, section the value of this resistor should be kept as small as possible to maximize circuit performance. the diodes will add a voltage dependent capacitance at the input to the ?sh which will put an additional load on the op- amp drive requirements. figure 18. input clamp circuit the analog input to the hi5800 can be clamped to 2.5v .it should not be clamped to the supply rails because these levels on the input will damage the part. the positive clamp voltage can be derived from the hi5800 +2.5v reference out- put but it should be buffered by an op-amp because the adc t ad acquisition time n acquisition time n + 1 t a t b t c n-1 data n data n-2 data conv irq data valid t ad = t a = aperture delay (~20ns) t irq = irq high time (~200ns) t acq = sample and hold acquisition time (~130ns) t s 188ns 56ns 0ns t conv t f t irq t acq t conv = conversion time (~333ns) t f = first pass (~56ns) t s = second pass (to 12 bits ~133ns) 1n5712 1n5712 r v- v+ v in flash op-amp application note 9214
11 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 reference is not designed to sink large clamp currents. another op-amp can be used to invert the +2.5v to generate the negative clamp voltage. an elegant solution to the clamp problem for the ecl con- verters is to use an hfa1130 clamped amp. this op-amp has the electrical characteristics of the hfa1100 with the addition of two pins, v h and v l , which can be used to set the level at which the output is clamped. the clamp pins are a high impedance so they can be driven by simple resistive divider circuit or a dac. references [1] harvey, barry, ?ake advantage of current-feedback amps for high-frequency gain? electronic design, 18 march, 1993. [2] fredrickson, thomas m.,?ntuitive operational ampli? ers, mcgraw-hill inc., new york, ny, 1988. [3] lan, bruce, ?atching ampli?rs with adc convert- ers? electronic products, august, 1992. [4] ?ecl system design handbook fourth edition, motorola, 1983. [5] demler, michael j., ?igh-speed analog-to-digital conversion,?academic press inc., 1992. [6] buchanan, james, ?mos/ttl digital systems design? mcgraw-hill inc., new york, ny, 1990. [7] ?otorola device data? motorola databook, 1993. [8] ?esigning with pecl logic? motorola application note an1406/d, 1992. [9] ?dvanced logic and bus interface logic? texas insturments databook, 1992. [10] robert w. steer, ?ntialiasing filters reduce errors in a/d converters? edn, march 30, 1989. application note 9214

▲Up To Search▲

Price & Availability of HI1386

	To Download HI1386 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .