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d a t a sh eet product speci?cation file under integrated circuits, ic20 1998 aug 26 integrated circuits SZF2002 low voltage 8-bit microcontroller with 6-kbyte embedded ram
1998 aug 26 2 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 contents 1 features 2 general description 3 applications 4 ordering information 5 block diagram 6 functional diagram 7 pinning information 7.1 pinning 7.2 pin description 8 functional description 8.1 general 8.2 cpu timing 9 memory organization 9.1 program memory 9.2 data memory 9.3 special function registers (sfrs) 9.4 addressing 9.5 paging logic 10 program status word (psw) 11 i/o facilities 11.1 ports 11.2 port configuration 12 timer/event counters 12.1 timer 0 and timer 1 12.2 timer 2 12.3 timer/counter 2 control register (t2con) 12.4 timer/counter 2 mode register (t2mod) 12.5 watchdog timer (t3) 13 pulse width modulated output 13.1 prescaler frequency control register (pwmp) 13.2 pulse width register (pwm) 14 analog-to-digital converter (adc) 14.1 adc control register (adcon) 14.2 adc result register (adch) 15 reduced power modes 15.1 idle mode 15.2 power-down mode 15.3 wake-up from power-down mode 15.4 status of external pins 15.5 power control register (pcon) 16 i 2 c-bus serial i/o 16.1 serial control register (s1con) 16.2 serial status register (s1sta) 16.3 data shift register (s1dat) 16.4 address register (s1adr) 17 standard serial interface sio0: uart 17.1 multiprocessor communications 17.2 serial port control and status register (s0con) 17.3 baud rates 18 interrupt system 18.1 external interrupts int2 to int8 18.2 interrupt priority 18.3 interrupt related registers 19 clock circuitry 20 reset 20.1 external reset using the rst pin 20.2 power-on-reset 21 special function registers overview 22 debugging support 22.1 recommended equipment 22.2 connecting the pod 22.3 powering the pod 22.4 bank switching support 22.5 software recommendations 23 instruction set 24 limiting values 25 dc characteristics 26 adc characteristics 27 ac characteristics 28 package outline 29 soldering 29.1 introduction 29.2 reflow soldering 29.3 wave soldering 29.4 repairing soldered joints 30 definitions 31 life support applications 32 purchase of philips i 2 c components
1998 aug 26 3 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 1 features fully static 80c51 central processing unit (cpu) 8-bit cpu, rom, ram and i/o in a 80 lead lqfp package 6-kbytes rom program memory, expandable externally to 256 kbytes 6144 + 256 bytes low power ram data memory, expandable externally to 32 kbytes internal aux ram can be used for program execution (only in combination with internal rom) three 8-bit ports; 24 i/o lines three 16-bit timer/event counters flash memory interface optimized, with power saving and programming options internal demultiplexing and latching of address/data bus to reduce system component count interfaces to up to 256-kbyte flash memory (banked) fifteen source, fifteen vector nested interrupt structure with two priority levels full duplex serial port (uart) i 2 c-bus interface for serial transfer on two lines analog-to-digital converter (adc) with power-down mode; 6 input channels and 8-bit adc pulse width modulated (pwm) output (8-bit resolution) watchdog timer enhanced architecture with: C non-page oriented instructions C direct addressing C four 8-byte ram register banks C stack depth limited only by available internal ram (maximum 256 bytes) C multiply, divide, subtract and compare instructions modes of reduced activity: power-down and idle modes wake-up via external interrupts at int0 to int8 frequency range: up to 16 mhz (only limited by external memory and adc performance) supply voltage: 3.0 v very low power consumption: operational 0.65 mw/mhz; idle 0.25 mw/mhz at 3.0 v operating temperature: - 40 to +85 c. 2 general description the SZF2002 low power system controller is manufactured in an advanced 0.5 m m cmos technology. the instruction set of the SZF2002 is based on that of the 80c51 and consists of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte. the device has low power consumption and two software selectable modes for power reduction: idle and power-down. this data sheet details the specific properties of the SZF2002; for details of the 80c51 core and peripheral functions such as timers, uart and i/o, see data handbook ic20 . for the i 2 c-bus refer to the i 2 c-bus and how to use it , ordering number 9398 393 40011. 3 applications the SZF2002 is an 8-bit general purpose microcontroller especially suited for wireless telephone and battery powered applications. the SZF2002 also functions as an arithmetic processor having facilities for both binary and bcd arithmetic plus bit-handling capabilities. 4 ordering information type number package name description version SZF2002hl lqfp80 plastic low pro?le quad ?at package; 80 leads; body 12 12 1.4 mm sot315-1
1998 aug 26 4 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 5 block diagram fig.1 block diagram. mgm180 ramce rst xclk d0 to d7 a0 to a17 ce oe we v ss v dda v ssa v dd rxd txd p3 p1 t0 t1 int0 int1 parallel i/o ports and ext. bus serial uart port two 16-bit timer/ event counters (t0, t1) 80c51 core excluding rom/ram cpu p4 8-bit i/o ports watchdog timer (t3) program memory data memory pwm adc adc0 to adc5 6-kbyte rom pwm 6144 + 256 bytes ram debug ea SZF2002 t2ex t2 16-bit timer/ event counter sda scl i 2 c-bus interface int2 to int8 3 3 (1) address lines a0 to a5 have alternative functions during debug; see section 7.2.
1998 aug 26 5 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 6 functional diagram fig.2 functional diagram. handbook, full pagewidth mgm181 port 1 0 0 0 0 0 port 3 address bus data bus port 4 rst ea debug adc0 adc1 adc2 adc3 adc4 adc5 v ss v dd v dda rst true_a15 rd wr psen ale rxd txd t0 t1 int1 int0 SZF2002 pwm ce ramce oe we xclk v ssa t2 int2 t2ex int3 int5 int4 int6 scl sda int8 int7 3 3
1998 aug 26 6 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 7 pinning information 7.1 pinning fig.3 pin configuration. p1.6/int8/scl handbook, full pagewidth SZF2002 mgm182 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 n.c. a12 a7 a6 a5 a4 pwm rst xclk v dd v ss p3.7 p3.6 p3.5/t1 p3.4/t0 p3.3/int1 p3.2/int0 p3.1/txd p3.0/rxd n.c. 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 n.c. a15 a16 we a17 a14 a13 a8 a9 v ss v dd a11 oe a10 ce d7 d6 d5 d4 n.c. n.c. p1.7/sda p1.5/int7 p1.4/int6 p1.3/int5 p1.2/int4 p1.1/int3/t2ex p1.0/int2/t2 v dda v ssa adc5 adc4 adc3 adc2 adc1 adc0 ea debug n.c. n.c. d3 d2 d1 d0 a0 a1 a2 a3 v ss v dd p4.0/ramce p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 n.c.
1998 aug 26 7 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 7.2 pin description table 1 lqfp80 package symbol pin description program memory interface; note 1 a0 55 a0/ rd. address line 0, used as rd during debug. a1 54 a1/ wr. address line 1, used as wr during debug. a2 53 a2/ale. address line 2, used as ale during debug. a3 52 a3/ psen. address line 3, used as psen during debug. a4 6 a4/rst. address line 4, used as rst during debug. a5 5 a5/true_a15. address line 5, used as a15 = p2.7 during debug. a6 4 a6. address line 6 (not needed during debug, see d6). a7 3 a7. address line 7 (not needed during debug, see d7). a8 73 address lines a8 to a14. during debug these lines are used as p2.0 to p2.6. a9 72 a10 67 a11 69 a12 2 a13 74 a14 75 a15 79 address lines a15 to a17. page selection; during debug these lines are the page register. each bank is 32 kbytes. a16 78 a17 76 d0 56 data bus. during debug these line are p0.0 to p0.7. d1 57 d2 58 d3 59 d4 62 d5 63 d6 64 d7 65 ce 66 chip enable. enable strobe to external program memory. oe 68 output enable. output read strobe to external memory. we 77 write enable. write strobe to external memory.
1998 aug 26 8 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 i/o ports p1.0/ int2/t2 29 port 1 ( p1.0 to p1.7). 8-bit bidirectional i/o port with internal pull-ups; int2 to int8 : external interrupt inputs; t2: timer t2 i/o; t2ex: timer 2 external input; scl: i 2 c-bus interface clock; sda: i 2 c-bus interface data. port 1 pins that have logic 1s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs (note p1.6 and p1.7 are open-drain only). as inputs, port 1 pins that are externally pulled low will source current (i il , see chapter 25) due to the internal pull-ups. p1.1/ int3/t2ex 28 p1.2/ int4 27 p1.3/ int5 26 p1.4/ int6 25 p1.5/ int7 24 p1.6/ int8/scl 23 p1.7/sda 22 p3.0/rxd 19 port 3 (p3.0 to p3.7). 8-bit bidirectional i/o port with internal pull-ups; rxd: serial port receiver data input (asynchronous); txd: serial port transmitter data output (asynchronous); int0: external interrupt 0; int1: external interrupt 1; t0 : timer 0 external input; t1: timer 1 external input. port 3 pins that have logic 1s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current (i il , see chapter 25) due to the internal pull-ups. p3.1/txd 18 p3.2/ int0 17 p3.3/ int1 16 p3.4/t0 15 p3.5/t1 14 p3.6 13 p3.7 12 p4.0/ ramce 49 port 4 (p4.0 to p4.7). 8-bit bidirectional i/o port; ramce chip enable for external ram. port 4 pins that have logic 1s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. as inputs, port 4 pins that are externally pulled low will source current (i il , see chapter 25) due to the internal pull-ups. p4.1 48 p4.2 47 p4.3 46 p4.4 45 p4.5 44 p4.6 43 p4.7 42 adc interface adc0 37 input channels to the adc. adc1 36 adc2 35 adc3 34 adc4 33 adc5 32 symbol pin description
1998 aug 26 9 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 note 1. the pin layout has been optimized for easy connection of 256 kbytes flash rom (e.g. atmel at29lv010a, sgs-thomson m28v201, or amd am29f010). general pwm 7 pulse width modulation output. rst 8 reset . a high level on this pin for at least 12 clock cycles resets the device. xclk 9 clock input. ea 38 external access. when ea is high the cpu executes out of internal program memory (unless the program counter exceeds 7fffh). a low ea forces the cpu to execute out of external memory regardless of the value of the program counter. this signal is latched at the falling edge of reset (rst pin). the ea pin has an internal pull-down. when it is not connected the cpu executes from external memory. debug 39 debug enable. if high, forces standard 80c51 timing signals output at address and databus. in this mode the databus is multiplexed with the lower 8 bits of the address bus, and the a0 to a3 lines are used for the rd, wr, ale and psen signals. this allows a standard 80c51 in-circuit emulator to be connected. for normal operation connect debug to v ss . power v dd 10, 50, 70 power supply digital core and digital i/o pads. v ss 11, 51, 71 ground: circuit ground potential. v dda 30 analog power. v ssa 31 analog ground. n.c. 1, 20, 21, 40, 41, 60, 61, 80 not connected. symbol pin description
1998 aug 26 10 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 8 functional description detailed descriptions of each function are described in: chapter 9 memory organization chapter 10 program status word (psw) chapter 11 i/o facilities chapter 12 timer/event counters chapter 13 pulse width modulated output chapter 14 analog-to-digital converter (adc) chapter 15 reduced power modes chapter 16 i2c-bus serial i/o chapter 17 standard serial interface sio0: uart chapter 18 interrupt system chapter 19 clock circuitry chapter 20 reset chapter 21 special function registers overview chapter 22 debugging support. 8.1 general the SZF2002 is a stand-alone high-performance cmos microcontroller designed for use in real-time applications such as wireless telephone and mobile communications, instrumentation, industrial control, intelligent computer peripherals and consumer products. the device provides hardware features, architectural enhancements and new instructions to function as a controller for applications requiring up to 256 kbytes of program memory and/or up to 6144 + 256 bytes of on-chip data memory. the SZF2002 contains a 6-kbyte program memory; a static 6144 + 256 byte data memory (ram); 24 i/o lines; three 16-bit timer/event counters; a fifteen-source two priority-level, nested interrupt structure, a 6-channel 8-bit adc, a watchdog timer and a pulse width modulation output. two serial interfaces are provided on-chip: a standard uart serial interface a standard i 2 c-bus serial interface with a transfer speed of up to 400 kbits/s (depending on clock frequency). the i 2 c-bus serial interface has byte oriented master and slave functions allowing communication with the whole family of i 2 c-bus compatible devices. the device has two software selectable modes of reduced activity for power reduction: idle mode: freezes the cpu while allowing the derivative functions (timers, serial i/o, ram, adc and pwm) and interrupt system to continue functioning power-down mode: saves the ram contents but stops the clock causing all other chip functions to be inoperative. 8.2 cpu timing a machine cycle consists of a sequence of 6 states. each state lasts one clock period, thus a machine cycle takes 6 clock periods or 1 m s if the clock frequency (f clk ) is 6 mhz.
1998 aug 26 11 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 9 memory organization the SZF2002 has 6 kbytes of program memory plus 6 kbytes + 256 bytes of data memory on chip. the device has separate address spaces for program and data memory (see fig.4). the SZF2002 can directly address up to 256 kbytes of external data memory. the cpu generates the read strobe ( oe), the write strobe ( we) and chip select ( ce) for external program memory (flash), and read strobe ( oe) and write strobe ( we) and chip select ( ramce) for external data memory. 9.1 program memory the SZF2002 contains 6 kbytes of internal rom and 6144 + 256 bytes of ram. the lower 6 kbytes of program memory can be implemented in either on-chip rom or external program memory. the 6 kbytes of program memory is implemented as mask programmable rom. there are two modes for the program memory, depending on the state of the ea pin (latched during reset) and on the address range: 1. ea = 0. all program fetches are directed to the external program memory. after reset the cpu begins execution at location 8000h. 2. ea = 1. after reset the cpu begins execution at location 0000h. fetches from addresses 2000h to 37ffh are redirected to the auxiliary ram. the processor can fill this ram with normal write operations to the data memory (movx to addresses 0000h to 17ffh). program memory fetches from addresses 0000h to 17ffh are directed to the internal rom. program counter values greater than 7fffh are automatically addressed to external memory regardless of the state of the ea pin. 9.2 data memory the SZF2002 contains 6144 + 256 bytes of ram and a number of special function registers (sfrs). all these data spaces are addressed differently. figure 4 shows the internal data memory space divided into the lower 128 bytes, the upper 128 bytes, auxiliary ram, and the sfrs space. internal ram locations 0 to 127 are directly and indirectly addressed. internal ram locations 128 to 255 are only indirectly addressed. the special function register locations 128 to 255 are only directly addressed. auxiliary ram is accessible via movx instructions to the lower 32-kbyte address space. movx @r0/r1 instructions use sfr p2 as page selector. the upper 32-kbyte address space is redirected to the program memory, to accommodate flash programming. 9.3 special function registers (sfrs) the upper 128 bytes are the address locations of the sfrs. figures 6 and 7 show the special function registers space. the sfrs include the port latches, timers, peripheral control, serial i/o registers, etc. these registers are accessed by direct addressing. there are 128 directly addressed locations in the sfr address space. bit addressed sfrs are those that end in 000b. 9.4 addressing the SZF2002 has five methods for addressing source operands: register direct indirect immediate base-register plus index-register-indirect. the first three methods can be used for addressing destination operands. most instructions have a destination/source field that specifies the data type, addressing methods and operands involved. for operations other than movs, the destination operand is also a source operand. access to memory addressing is as follows: registers in one of the four register banks through direct or indirect (see fig.5) lower 128 bytes of internal ram through direct or register indirect; upper 128 bytes of internal ram through indirect special function registers through direct program memory look-up tables through base-register plus index-register-indirect extended data memory access through register indirect.
1998 aug 26 12 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 table 2 memory spaces; note 1 notes 1. execution from internal memory is only possible when ea = 1 during reset. 2. page select is used to access all 8 banks in the 256-kbyte address space. memory space address mode used signal internal ram 00h to 7fh direct and indirect - internal ram 80h to ffh indirect - sfrs 80h to ffh direct - internal aux ram (on-chip) 0000h to 17ffh movx - external ram (off-chip) 1800h to 7fffh movx ramce, oe and we external rom (off-chip) 0000h to ffffh; note 2 program execution ce, oe internal aux ram (on-chip) 2000h to 37ffh program execution - external flash rom write (off-chip) 8000h to ffffh; note 2 movx ce, oe and we fig.4 memory map. (1) accessible via indirect addressing only. (2) accessible via direct and indirect addressing. (3) accessible via direct addressing. (4) gaps in the address map are undefined, and should not be used. handbook, full pagewidth mgm183 external flash rom (banked) ffffh 8000h external rom bank 0 7fffh 0000h external ram internal aux ram (movx) 7fffh 0000h 1800h 17ffh internal aux ram 6-kbyte internal rom ea = 1 (4) 37ffh 0000h 2000h 17ffh external flash rom (banked) ffffh 8000h overlapped space internal ram 00h ffh 80h special function registers ea = 0 (1) (2) (3) internal memory data memory program memory
1998 aug 26 13 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 9.5 paging logic the SZF2002 contains paging logic to handle the extended address range. table 3 paging of external memory; notes 1 and 2 notes 1. during debug a<17-15> are used to output the bank register. the true_ a15 line is output at the a5 pin. 2. during debug rom and ram access is done via psen, wr and rd. true_a15 (internal) bank sfr [2 : 0] a<17-15> pins bank remark 0 xxx 000 0 lower 32 kbytes always bank 0 1 000 000 0 bank 0 1 001 001 1 bank 1 1 010 010 2 bank 2 1 011 011 3 bank 3 1 100 100 4 bank 4 1 101 101 5 bank 5 1 110 110 6 bank 6 1 111 111 7 bank 7 fig.5 the lower 128 bytes of internal ram. handbook, halfpage mgd675 r7 r0 07h 0 r7 r0 0fh 08h r7 r0 17h 10h r7 r0 1fh 18h 2fh 7fh 20h 30h 4 banks of 8 registers (r0 to r7)
1998 aug 26 14 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.6 special function register memory map. mgm184 fe ff fd fc fb fa f9 f8 f6 f7 f5 f4 f3 f2 f1 f0 ee ef ed ec eb ea e9 e8 e6 e7 e5 e4 e3 e2 e1 e0 de df dd dc db da d9 d8 d6 d7 d5 d4 d3 d2 d1 d0 ce cf cd cc cb ca c9 c8 c6 c7 c5 c4 c3 c2 c1 c0 bit address register mnemonic ffh t3 direct byte address (hex) feh fdh fch pwmp pwm f8h f7h f0h efh eeh edh ech ebh eah e8h e0h dbh dah d9h d8h d0h cfh ceh cdh cch cbh cah c9h c8h c5h c4h c0h c1h sfrs containing directly addressable bits ip1 wdtkey b ien1 acc s1adr s1dat s1sta s1con psw th2 tl2 rcap2h rcap2l t2con t2mod adch adcon p4 irq1 ix1 e9h
1998 aug 26 15 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.7 special function register memory map (continued from fig.6). mgm185 be bd bc bb ba b9 b8 b6 b7 b5 b4 b3 b2 b1 b0 ae af ad ac ab aa a9 a8 a6 a7 a5 a4 a3 a2 a1 a0 9e 9f 9d 9c 9b 9a 99 98 96 97 95 94 93 92 91 90 8e 8f 8d 8c 8b 8a 89 88 86 87 85 84 83 82 81 80 bit address register mnemonic direct byte address b8h b0h afh aeh adh ach abh aah a8h a0h 99h 9ah 98h 90h 91h 8dh 8ch 8bh 8ah 89h 88h 87h 83h 82h 81h 80h sfrs containing directly addressable bits ip0 p3 p2 (used as address bus) (used as address bus) s0buf s0con rombank p1 th1 th0 tl1 tl0 tmod pcon dph dpl sp p0 ien0 tcon a9h
1998 aug 26 16 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 10 program status word (psw) the program status word contains several status bits that reflect the current state of the cpu. the psw, shown in table 4, resides in the sfr memory space. it contains the carry bit, the auxiliary carry (for bcd operations), the two register bank select bits, the overflow flag, a parity bit and two user-definable status flags. the carry bit, other than serving the function of a carry bit in arithmetic operations, also serves as the accumulator for a number of boolean operations. bits rs0 and rs1 are used to select one of the four register banks; see table 5. a number of instructions refer to these ram locations as r0 through to r7. the selection of which of the four register banks is being referred to is made on the basis of the state of rs0 and rs1 at execution time. the parity bit reflects the number of 1s in the accumulator: p = 1, if the accumulator contains an odd number of 1s, and p = 0, if the accumulator contains an even number of 1s. thus, the number of 1s in the accumulator plus p is always even. the bits f0 and usr are uncommitted and may be used as general purpose status flags. table 4 program status word (sfr address d0h) table 5 description of psw bits 76543210 cy ac f0 rs1 rs0 ov usr p bit symbol description 7cy carry ?ag. the carry ?ag receives carry out from bit 7 of alu operands. 6ac auxiliary carry ?ag. the auxiliary carry ?ag receives carry out from bit 3 of addition operands. 5f0 general purpose status ?ag. 4 rs1 register bank select 1 . this bit selects register bank 1. 3 rs0 register bank select 0. this bit selects register bank 0. 2ov over?ow ?ag. this ?ag is set by arithmetic operations. 1 usr usr. this is a user-de?nable ?ag. 0p parity. if the accumulator contains an odd number of 1s this bit is set to a logic 1 by hardware. otherwise, the state of this bit is a logic 0.
1998 aug 26 17 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 11 i/o facilities 11.1 ports the SZF2002 has 24 i/o lines: ports p1, p3 and p4 of which ports p1 and p3 are bit addressed (p0 and p2 are always used as address/data bus). ports 0 to 4 have the following alternative functions: port 0 used internally. port 1 used for a number of special functions: provides the inputs for the external interrupts: int2 to int8 the i 2 c-bus interface: scl and sda counter inputs: t2 and t2ex. port 2 used internally. port 3 pins can be configured individually to provide: external interrupt request inputs: int1 and int0 counter input: t1 and t0 uart input and output: rxd and txd. port 4 provides chip select for external data memory: ramce. to enable a port pin alternative function, the port bit latch in its sfr must contain a logic 1. each port consists of a latch (sfrs p0 to p4), an output driver and input buffer. ports 1, 3 and 4 have internal pull-ups (except p1.6 and p1.7). figure 8 shows that the strong transistor p1 is turned on for only 2 clock periods after a low-to-high transition in the port latch. when on, it turns on p3 (a weak pull-up) through the inverter. this inverter and p3 form a latch which holds the logic 1. in port 0 the pull-up p1 is only on when emitting logic 1s for external memory access. 11.2 port con?guration the port pins (except for p1.6 and p1.7) are configured as shown in fig.8. this is a quasi-bidirectional i/o with pull-up. the strong booster pull-up p1 is turned on for one clock period after a low-to-high transition in the port latch. all port pins will be set to high during reset. fig.8 port configuration. handbook, full pagewidth mbk456 p1 p2 p3 input data read port pin 2 clock periods n strong pull-up i/o pin v dd q from port latch input buffer
1998 aug 26 18 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 12 timer/event counters the SZF2002 contains three 16-bit timer/event counter registers; timer 0, timer 1 and timer 2 which can perform the following functions: measure time intervals and pulse duration count events generate interrupt requests. in the timer operating mode the register increments every machine cycle. since a machine cycle consists of 6 clock periods, the count rate is 1 6 f clk . in the counter operating mode, the register increments in response to a high-to-low transition. since it takes 2 machine cycles (12 clock periods) to recognize a high-to-low transition, the maximum count rate is 1 12 f clk . to ensure a given level is sampled, it should be held for at least one complete machine cycle. 12.1 timer 0 and timer 1 timer 0 and timer 1 can be programmed independently to operate in four modes: mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler. mode 1 16-bit time-interval or event counter. mode 2 8-bit time-interval or event counter with automatic reload upon overflow. mode 3 timer 0 establishes tl0 and th0 as two separate counters. 12.2 timer 2 timer 2 is a 16-bit timer/up-down counter that can operate (like timer 0 and 1) either as a timer or as an event counter. these functions are selected by the state of the c/ t2 bit in the t2con register; see section 12.3. three operating modes are available: capture, auto-reload and baud rate generator, which also are selected via the t2con register. 12.2.1 c apture mode figure 9 shows the capture mode. two options in this mode may be selected by the exen2 bit in t2con: if exen2 = 0, then timer 2 is a 16-bit timer or counter that sets the timer 2 overflow bit (tf2) on overflow, this can be used to generate an interrupt. if exen2 = 1, timer 2 operates as already described but with the additional feature that a high-to-low transition at external input t2ex causes the current value in tl2 and th2 to be captured into registers rcap2l and rcap2h respectively. in addition, the transition at t2ex causes the exf2 bit in t2con to be set; this may also be used to generate an interrupt. 12.2.2 a uto - reload mode figure 10 shows the auto-reload mode. counting up (dcen = 0) in the auto-reload mode and counting up, registers rcap2l/rcap2h are used to hold a reload value for tl2 /th2 when timer 2 rolls over. by setting/clearing bit exen2 in t2con the external trigger input pin t2ex can be enabled/disabled. if exen2 = 0, then timer 2 is a 16-bit timer/counter which upon overflow sets tf2, and reloads tl2/th2 with the reload value held in rcap2l/rcp2h. if exen2 = 1, then timer 2 performs as above, but with the added feature that a high-to-low transition at pin t2ex causes the current timer 2 value (tl2/th2 data) to be reloaded with the value held in rcap2l/rap2h, and bit exf2 in t2con to be set. timer 2 interrupt will be set if exf2 is set or tf2 is set. counting up (dcen = 1 and t2ex = 1). in this mode timer 2 will count up. when the timer overflows (ffffh state), tf2 bit will be set. this will reload tl2 and th2 with the contents of t2capl and t2caph, respectively. also bit exf2 will be toggled. bit exf2 can be used as the 17th bit if desired. timer 2 interrupt will be set only if tf2 is set. counting down (dcen = 1 and t2ex = 0. in this mode timer 2 will be counting down. underflow will occur when the contents of tl2/th2 matches the contents of rcap2l/rcap2h. a timer 2 roll-over from 0000h to ffffh is not considered as an underflow. upon underflow, bit tf2 will be set and registers tl2/th2 will be loaded with ffffh. in addition, an underflow will cause bit exf2 to toggle, such that it can be used as the 17th bit if desired. timer 2 interrupt will be set only if tf2 is set. 12.2.3 b aud r ate g enerator mode the baud rate generator mode is selected when rclk0 = 1 or tclk0 = 1 or rclk1 = 1 or tclk1 = 1. it will be described in conjunction with the serial port (uart); see section 17.3.2.
1998 aug 26 19 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.9 timer 2 in capture mode. handbook, full pagewidth mgm136 tl2 (8 bits) th2 (8 bits) rcap2l rcap2h exf2 tf2 timer 2 interrupt exen2 control transition detector t2ex pin capture tr2 control c/t2 = 0 c/t2 = 1 t2 pin 6 f clk fig.10 timer 2 in auto-reload mode. handbook, full pagewidth mgm137 tl2 (8 bits) tr2 control th2 (8 bits) rcap2l rcap2h exf2 tf2 timer 2 interrupt exen2 control c/t2 = 0 c/t2 = 1 t2 pin 6 f clk transition detector t2ex pin reload
1998 aug 26 20 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 12.3 timer/counter 2 control register (t2con) table 6 timer/counter 2 control register (sfr address c8h) table 7 description of t2con bits 76543210 tf2 exf2 rclk0 tclk0 exen2 tr2 c/ t2 cp/ rl2 bit symbol description 7 tf2 timer 2 over?ow ?ag. set by a timer 2 under?ow or over?ow and must be cleared by software. tf2 will not be set when in either the baud rate generation mode or clock out mode. 6 exf2 timer 2 external ?ag. set when either a capture or reload is caused by a negative transition on t2ex and when exen2 = 1. in auto-reload mode it is toggled on an under?ow or over?ow. cleared by software. 5 rclk0 receive clock 0 ?ag. when set, causes the uart to use timer 2 over?ow pulses. rclk0 = 0, causes timer 1 over?ow pulses to be used. 4 tclk0 transmit clock 0 ?ag. when set, causes the uart to use timer 2 over?ow pulses. tclk0 = 0, causes timer 1 over?ow pulses to be used. 3 exen2 timer 2 external enable ?ag. when set, allows a capture or reload to occur, together with an interrupt, as a result of a negative transition on input t2ex (if in capture mode or auto-reload mode with dcen reset). if in auto-reload mode and dcen is set, this bit has no in?uence. in the other modes exf2 is set and an interrupt is generated on a high-to-low transition on t2ex pin. in all modes exen2 = 0, causes timer 2 to ignore events at t2ex. 2 tr2 timer 2 start/stop control. when tr2 = 1, timer 2 is started. 1c/ t2 timer or counter select for timer 2. c/ t2 = 0, selects the internal timer with a clock frequency of 1 6 f clk . c/ t2 = 1, selects the external event counter; negative edge triggered. 0 cp/ rl2 capture/reload ?ag. selection of capture or auto-reload mode.
1998 aug 26 21 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 12.4 timer/counter 2 mode register (t2mod) table 8 timer/counter 2 mode register (sfr address c9h) description of t2mod bits table 9 timer 2 operating modes; note 1 note 1. x = dont care 76543210 -- rclk1 tclk1 - t2rd t2oe dcen bit symbol description 7 - these 2 bits are reserved. 6 - 5 rclk1 receive clock 1 ?ag. reserved for future uart2. when set, causes the uart to use timer 2 over?ow pulses. rclk1 = 0, causes timer 1 over?ow pulses to be used. 4 tclk1 transmit clock 1 ?ag. reserved for future uart2. when set, causes the uart to use timer 2 over?ow pulses. tclk1 = 0, causes timer 1 over?ow pulses to be used. 3 - this bit is reserved. 2 t2rd timer 2 read ?ag. this bit is set by hardware if following a tl2 read and before a th2 read, th2 is incremented. it is reset on the trailing edge of the next tl2 read. 1 t2oe timer 2 output enable. when set, output is activated to output a clock at the t2 pin (clock output mode). 0 dcen down count enable. when set, this allows timer 2 to be con?gured as an up/down counter. rclk0 + tclk0 + rclk1 + tclk1 cp/ rl2 t2oe c/ t2 mode 0 0 0 x 16-bit auto-reload 0 1 0 x 16-bit capture 1 x x x baud rate generator
1998 aug 26 22 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 12.5 watchdog timer (t3) in addition to timer 2 and the standard timers, a watchdog timer (consisting of an 11-bit prescaler and an 8-bit timer) is also available. the watchdog timer is controlled by the watchdog enable register (wdtkey). when wdtkey = 55h, the timer is disabled and the power-down mode is enabled. otherwise, the timer is enabled and the power-down mode is disabled. in the idle mode the watchdog timer and reset circuitry remain active. the watchdog timer is shown in fig.11. the timer frequency is derived from the clock frequency using the formula shown below: when a timer overflow occurs, the microcontroller is reset. to prevent a system reset the timer must be reloaded in time by the application software. f timer f clk 62048 () t3 ------------------------------------------ - = if the processor suffers a hardware/software malfunction, the software will fail to reload the timer.this failure will produce a reset upon overflow thus preventing the processor running out of control. the watchdog timer can only be reloaded if the condition flag wle (pcon.4) has been previously set by software. at the moment the counter is loaded the condition flag is automatically cleared. after reset the watchdog timer is off. the watchdog timer is started by loading a value into t3. the time interval between the timer reloading and the occurrence of a reset is dependent upon the reloaded value. the time interval is derived from the clock and the value programmed into t3 and may be calculated as shown below: for example, this time period may range from 2 to 500 ms when using a clock frequency f clk = 6 mhz. t reload 256 t3 C () f timer ----------------------------- = fig.11 functional diagram of the watchdog timer (t3). handbook, full pagewidth mgm141 internal bus write t3 prescaler 11-bit timer t3 (8-bit) load clear overflow internal reset loaden sfr wdtkey loaden pcon.4 pcon.1 clear wle pd r rst rst internal bus f clk /6
1998 aug 26 23 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 13 pulse width modulated output one pulse width modulated output channel pwm is provided which outputs pulses of programmable length and interval. the repetition frequency is defined by an 8-bit prescaler (pwmp) that generates the clock for the counter. the 8-bit counter counts modulo 255, i.e. from 0 to 254 inclusive. the value held in the 8-bit counter is compared to the contents of the register pwm. if a new prescaler value is written in register pwmp the 8-bit counter finishes uninterrupted, and the new prescaler value is used in the next count cycle. provided the contents of this register are greater than the counter value, the pwm output is set high. if the contents of register pwmp are equal to, or less than the counter value, the pwm output is set low. the pulse-width-ratio is therefore defined by the contents of register pwm. the pulse-width-ratio will be in the range 0to 255 255 and may be programmed in increments of 1 255 . the repetition frequency (f pwm ) at the pwm output is given by: for f clk = 12 mhz, the above formula gives a repetition frequency range of 92 hz to 23.5 khz. by loading the pwm register with either 00h or ffh, the pwm output can be retained at a constant low or high level respectively. when loading ffh into the pwm register, the 8-bit counter will never actually reach this value. the pwm output pin is not shared with any other function. f pwm f clk 1 ( pwmp ) 255 + 2 ---------------------------------------------------------------- - = fig.12 functional diagram of pulse width modulated output (pwm). handbook, full pagewidth mgm140 i n t e r n a l b u s f clk pwmp + divide-by-2 8-bit counter pwm 8-bit comparator output buffer pwm
1998 aug 26 24 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 13.1 prescaler frequency control register (pwmp) table 10 prescaler frequency control register (sfr address feh) table 11 description of pwmp bits 13.2 pulse width register (pwm) table 12 pulse width register (sfr address fch) table 13 description of pwm bits 76543210 pwmp.7 pwmp.6 pwmp.5 pwmp.4 pwmp.3 pwmp.2 pwmp.1 pwmp.0 bit symbol description 7 to 0 pwmp.7 to pwmp.0 prescaler division factor = (pwmp) + 1 76543210 pwm.7 pwm.6 pwm.5 pwm.4 pwm.3 pwm.2 pwm.1 pwm.0 bit symbol description 7 to 0 pwm.7 to pwm.0 high/low ratio of fig.13 pwm signals. handbook, full pagewidth mgm186 pwm pwm 2 (pwmp + 1) t clk 255 2 (pwmp + 1) t clk pwm signal pwm () 255 pwm () C {} ---------------------------------------------- - =
1998 aug 26 25 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 14 analog-to-digital converter (adc) the analog input circuitry consists of a 6-input analog multiplexer and an adc with 8-bit resolution. the analog supply (v dda ) and analog ground (v ssa ) are connected via separate input pins. for clock frequencies higher than 8 mhz the clock prescaler is needed (divide-by-2). the functional diagram of the adc is shown in fig.14. the adc is controlled using the adc control register (adcon). input channels are selected by the analog multiplexer via the adcon register bits aadr0 to aadr2. a conversion is started by setting the adcs bit in the adcon register. the completion of the 8-bit adc conversion is flagged by adci in the adcon register, which will generate an interrupt if this is enabled (ead). the result is stored in the special function register adch (address c5h). to save power the adc current is switched on only during conversion and is independent of the processor mode (active, idle or power-down). if the processor goes into idle or power-down mode, the adc interrupt must be used to wake-up the cpu again. while adcs = 1 or adci = 1, a new adc start will be blocked and consequently lost, however an adc conversion already in progress will finish uninterrupted. an adc conversion already in progress is aborted when the power-down mode is entered. the result of a completed conversion (adci = 1) remains unaffected when entering the idle or power-down mode. when no result of a completed conversion (adci = 0) is available, the adcon and adch registers will be reset when entering the power-down mode. note that aadrx and ckdiv have to be set explicitly to restore their previous values for the first conversion after power-down mode. table 14 conversion time in clock cycles condition max. remark f clk 8 mhz, ckdiv = 0 288 normal conversion f clk > 8 mhz, ckdiv = 1 576 prescaler used fig.14 functional diagram of analog input. (1) for the descriptions of adcon bits see table 16. handbook, full pagewidth mgm187 analog input multiplexer 8-bit adc (succesive approximation) adcon (1) 12 34567 0 123456 power-down 7 0 v dda v ssa adch internal bus adc0 adc1 adc2 adc3 adc4 adc5
1998 aug 26 26 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 14.1 adc control register (adcon) table 15 adc control register (sfr address c4h) table 16 description of adcon bits table 17 selection of analog input channel 14.2 adc result register (adch) table 18 adc result register (sfr address c5h) table 19 description of adch bits 76543210 -- ckdiv adci adcs aadr2 aadr1 aadr0 bit symbol description 7 - these 2 bits are reserved. 6 - 5 ckdiv prescaler select. when ckdiv = 1, the adc clock prescaler is used (divide-by-2). prescaling is necessary with clocks over 8 mhz. 4 adci adc interrupt ?ag. this ?ag is set when an adc conversion result is ready to be read. an interrupt is invoked if this is enabled (ead). this ?ag must be cleared by software, (it cannot be set by software). 3 adcs adc start and status ?ag. when this bit is set an adc conversion is started. adcs must be set by software. the adc logic ensures that this signal is high while the adc is busy. on completion of the conversion adci is set and one clock later the adcs ?ag is reset. adcs cannot be reset by software. 2 aadr2 analog input select. these bits are used to select one of the six analog inputs; see table 17. 1 aadr1 0 aadr0 aadr2 aadr1 aadr0 selected channel 0 0 0 adc0 0 0 1 adc1 0 1 0 adc2 0 1 1 adc3 1 0 0 adc4 1 0 1 adc5 1 1 0 reserved 1 1 1 reserved 76543210 adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 bit symbol description 7 to 0 adc7 to adc0 8-bit adc result
1998 aug 26 27 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 15 reduced power modes there are two software selectable modes of reduced activity for further power reduction: idle and power-down. 15.1 idle mode idle mode operation permits the interrupt, serial ports, timer blocks, pwm and adc to continue to function while the clock to the cpu is halted. the following functions remain active during the idle mode: timer 0, timer 1, timer 2 and timer 3 (watchdog timer) uart, i 2 c-bus interface internal interrupt external interrupt pwm adc. these functions may generate an interrupt or reset; thus ending the idle mode. the instruction that sets bit idl (pcon.0) is the last instruction executed in the normal operating mode before the idle mode is activated. once in idle mode, the cpu status is preserved along with the stack pointer, program counter, program status word, sfrs and accumulator. the ram and all other registers maintain their data during idle mode. the status of the external pins during idle mode is shown in table 20. 15.1.1 t ermination of the i dle mode using an enabled interrupt activation of any enabled interrupt will cause idl (pcon.0) to be cleared by hardware thus terminating the idle mode. the interrupt is serviced, and following the reti instruction, the next instruction to be executed will be the one following the instruction that put the device in the idle mode. the flag bits gf0 (pcon.2) and gf1 (pcon.3) may be used to determine whether the interrupt was received during normal execution or during the idle mode. for example, the instruction that writes to pcon.0 can also set or clear one or both flag bits. when the idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. 15.1.2 t ermination of the i dle mode using an external hardware reset the second way of terminating the idle mode is with an external hardware reset, or an internal reset caused by an overflow of timer 3 (watchdog timer). since the clock is still running, the hardware reset is required to be active for two machine cycles (12 clock periods) to complete the reset operation. reset redefines all sfrs but does not affect the on-chip ram. 15.2 power-down mode the power-down operation freezes the SZF2002. the power-down mode can only be activated by setting the pd bit in the pcon register. the instruction that sets pd (pcon.1) is the last executed prior to going into the power-down mode. once in the power-down mode, the internal clock is stopped. the contents of the on-chip ram and the sfrs are preserved. the port pins output the value held by their respective sfrs. oe is held high, but ce is switched to high, so the external rom will not be enabled during power down, to save system power. 15.3 wake-up from power-down mode setting the pd flag in the pcon register forces the controller into the power-down mode. setting this flag enables the controller to be woken-up from the power-down mode with either the external interrupts int0 to int8, or a reset operation. the wake-up operation has two basic approaches as explained in section 15.3.1 and 15.3.2. 15.3.1 w ake - up using int0 to int8 if any of the interrupts int0 to int8 is enabled, the device can be woken-up from the power-down mode with these external interrupts. the user must ensure that the external clock is stable before the controller restarts, the internal clock will remain inactive for 18 clock periods. this is controlled by an on-chip delay counter. 15.3.2 w ake - up using rst to wake-up the SZF2002, the rst pin must be kept high for a minimum of 12 clock cycles. the user must ensure that the external clock is stable before the controller restarts (at rst falling edge), the internal clock will remain inactive for 18 clock periods. this is controlled by an on-chip delay counter.
1998 aug 26 28 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 15.4 status of external pins the status of the external pins during idle and power-down mode is shown in table 20. table 20 status of external pins during idle and power-down modes 15.5 power control register (pcon) idle and power-down modes are activated by software using this sfr. pcon is not bit addressed, the reset value of pcon is 00000000b. table 21 power control register (sfr address 87h) table 22 description of pcon bits mode memory ce oe pwm ports 1, 3 and 4 data bus idle internal 1 1 active port data port 0 data external 1 1 active port data ?oating power-down internal 1 1 halted in last state port data port 0 data external 1 1 halted in last state port data ?oating 76543210 smod ard rfi wle gf1 gf0 pd idl bit symbol description 7 smod double baud rate. when set to a logic 1 the baud rate is doubled when the serial port sio0 is being used in modes 1, 2 or 3 (except when timer 2 is used). 6 ard setting this bit will force all movx instructions to access off-chip memory instead of aux ram. 5 rfi rfi reduction mode. setting this bit will disable the ale toggling during on-chip memory access. the SZF2002 does not have this signal during operational mode, but setting this bit will reduce the number of chip selects ( ce) of the external memory (and thus power). 4 wle watchdog load enable. this ?ag must be set by software prior to loading the watchdog timer (t3). it is cleared when t3 is loaded. 3 gf1 general purpose ?ag 1. 2 gf0 general purpose ?ag 0. 1pd power-down mode selection. setting this bit activates the power-down mode. if a logic 1 is written to both pd and idl at the same time, pd takes precedence. 0 idl idle mode selection. setting this bit activates the idle mode.
1998 aug 26 29 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 16 i 2 c-bus serial i/o the serial port supports the twin line i 2 c-bus, which consists of a data line (sda) and a clock line (scl). these lines also function as the i/o port lines p1.7 and p1.6 respectively. the system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. the i 2 c-bus serial i/o has complete autonomy in byte handling and operates in 4 modes: master transmitter master receiver slave transmitter slave receiver. these functions are controlled by the serial control register (s1con). s1sta is the status register whose contents may also be used as a vector to various service routines. s1dat is the data shift register and s1adr is the slave address register. slave address recognition is performed by on-chip hardware. figure 15 shows the block diagram of the i 2 c-bus serial i/o. fig.15 block diagram of i 2 c-bus serial i/o. mlb199 slave address s1adr gc shift register s1dat sda arbitration sync logic scl bus clock generator s1sta internal bus 70 s1con 70 70 70 control register status register
1998 aug 26 30 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 16.1 serial control register (s1con) table 23 serial control register (sfr address d8h) table 24 description of s1con bits 76543210 cr2 ens1 sta sto si aa cr1 cr0 bit symbol description 6 ens1 enable serial i/o. when ens1 = 0, the serial i/o is disabled. sda and scl outputs are in the high-impedance state; p1.6 and p1.7 function as open-drain ports. when ens1 = 1, the serial i/o is enabled. output port latches p1.6 and p1.7 must be set to logic 1. 5sta start ?ag. when this bit is set in slave mode, the sio hardware checks the status of the i 2 c-bus and generates a start condition if the bus is free or after the bus becomes free. if sta is set while the sio is in master mode, sio will generate a repeated start condition. 4sto stop ?ag. with this bit set while in master mode a stop condition is generated. when a stop condition is detected on the i 2 c-bus, the sio hardware clears the sto ?ag. sto may also be set in slave mode in order to recover from an error condition. in this case no stop condition is transmitted to the i 2 c-bus. however, the sio hardware behaves as if a stop condition has been received and releases the sda and scl lines. the sio then switches to the not addressed slave receiver mode. the stop ?ag is cleared by the hardware. 3si sio interrupt ?ag. this ?ag is set and an interrupt is generated, after any of the following events occur: a start condition is generated in master mode own slave address has been received during aa = 1 the general call address has been received while gc (s1adr.0) = 1 and aa = 1 a data byte has been received or transmitted in master mode (even if arbitration is lost) a data byte has been received or transmitted as selected slave a stop or start condition is received as selected slave receiver or transmitter. 2aa assert acknowledge. when this bit is set, an acknowledge (low level to sda) is returned during the acknowledge clock pulse on the scl line when: own slave address is received general call address is received; gc (s1adr.0) = 1 a data byte is received while the device is programmed to be a master receiver a data byte is received while the device is a selected slave receiver. when this bit is reset, no acknowledge is returned. consequently, no interrupt is requested when the own slave address or general call address is received. 7 cr2 clock rate selection. these 3 bits determine the serial clock frequency when sio is in the master mode. see table 25. 1 cr1 0 cr0
1998 aug 26 31 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 table 25 selection of the serial clock frequency (scl) in a master mode of operation 16.2 serial status register (s1sta) s1sta is a read-only register. the contents of this register may be used as a vector to a service routine. this optimizes the response time of the software and consequently that of the i 2 c-bus. the status codes for all possible modes of the i 2 c-bus interface is given in table 29. the register has only a valid vector to a service routine if the si bit of the s1con register is set, otherwise it is invalid, usually f8h. table 26 serial status register (sfr address d9h) table 27 description of s1sta bits table 28 symbols used in table 29 cr2 cr1 cr0 f clk divisor bit rate (khz) at f clk = 1 mhz 0 0 0 128 7.81 0 0 1 112 8.93 0 1 0 96 10.42 0 1 1 80 12.50 1 0 0 480 2.08 1 0 1 60 16.67 1 1 0 30 33.33 1 1 1 reserved - 76543210 sc4 sc3 sc2 sc1 sc0 0 0 0 bit symbol description 3 to 7 sc4 to sc0 5-bit status code; see table 29. 0to2 - these three bits are always zero. symbol description sla 7-bit slave address r read bit w write bit ack acknowledgement (acknowledge bit is logic 0) ack no acknowledgement (acknowledge bit is logic 1) data data byte to or from i 2 c-bus mst master slv slave trx transmitter rec receiver
1998 aug 26 32 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 table 29 status codes s1sta value description mst/trx mode 08h a start condition has been transmitted. 10h a repeated start condition has been transmitted. 18h sla and w have been transmitted, ack has been received. 20h sla and w have been transmitted, ack received. 28h data of s1dat has been transmitted, ack received. 30h data of s1dat has been transmitted, ack received. 38h arbitration lost in sla, r/w or data. mst/rec mode 08h a start condition has been transmitted. 10h a repeated start condition has been transmitted. 38h arbitration lost while returning ack. 40h sla and r have been transmitted, ack received. 48h sla and r have been transmitted, ack received. 50h data has been received, ack returned. 58h data has been received, ack returned. slv/rec mode 60h own sla and w have been received, ack returned. 68h arbitration lost in sla, r/w as mst. own sla and w have been received, ack returned. 70h general call has been received, ack returned. 78h arbitration lost in sla, r/w as mst. general call has been received. 80h previously addressed with own sla. data byte received, ack returned. 88h previously addressed with own sla. data byte received, ack returned. 90h previously addressed with general call. data byte has been received, ack has been returned. 98h previously addressed with general call. data byte has been received, ack has been returned. a0h a stop condition or repeated start condition has been received while still addressed as slv/rec or slv/trx. slv/trx mode a8h own sla and r have been received, ack returned. b0h arbitration lost in sla and r/w as mst. own sla and r have been received, ack returned. b8h data byte has been transmitted, ack received. c0h data byte has been transmitted, ack received. c8h last data byte has been transmitted (aa = 0), ack received. miscellaneous 00h bus error during mst mode or selected slv mode, due to an erroneous start or stop condition. f8h no relevant state information available, si = 0.
1998 aug 26 33 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 16.3 data shift register (s1dat) s1dat contains the serial data to be transmitted or data which has just been received. the msb (bit 7) is transmitted or received first; i.e. data shifted from right to left. the data received is only valid while the si bit of the s1con register is set. table 30 data shift register (sfr address dah) 16.4 address register (s1adr) this 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receiver/transmitter. table 31 address register (sfr address dbh) table 32 description of s1adr bits 76543210 s1dat.7 s1dat.6 s1dat.5 s1dat.4 s1dat.3 s1dat.2 s1dat.1 s1dat.0 76543210 sla6 sla5 sla4 sla3 sla2 sla1 sla0 gc bit symbol description 7 to 1 sla6 to sla0 own slave address. 0 gc this bit is used to determine whether the general call address is recognized. when gc = 0, the general call address is not recognized; when gc = 1, the general call address is recognized.
1998 aug 26 34 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 17 standard serial interface sio0: uart this serial port is full duplex which means that it can transmit and receive simultaneously. it is also receive-buffered and can commence reception of a second byte before a previously received byte has been read from the register. (however, if the first byte has not been read by the time the reception of the second byte is complete, one of the bytes will be lost). the serial port receive and transmit registers are both accessed via the special function register s0buf. writing to s0buf loads the transmit register and reading s0buf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received (lsb first). the baud rate is fixed at 1 6 f clk . see figs 17 and 18. mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb first), and a stop bit (logic 1). on receive, the stop bit goes into rb8 in the sfr s0con. the baud rate is variable. see figs 19 and 20. mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logic 0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (logic 1). on transmit, the 9th data bit (tb8 in s0con) can be assigned the value of a logic 0 or logic 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in s0con, while the stop bit is ignored. the baud rate is programmable to either 1 16 or 1 32 f clk . see figs 21 and 22. mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb first), a programmable 9th data bit and a stop bit (logic 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. see figs 23 and 24. in all four modes, transmission is initiated by any instruction that uses s0buf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. 17.1 multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received. the 9th bit goes into rb8. the following bit is the stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated, but only if rb8 = 1. this feature is enabled by setting bit sm2 in s0con. one use of this feature, in multiprocessor systems, is as follows. when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is high in an address byte and low in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be sent. the slaves that were not being addressed leave their sm2 bits set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
1998 aug 26 35 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 17.2 serial port control and status register (s0con) the serial port control and status register is the special function register s0con. the register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). table 33 serial port control register (sfr address 98h) table 34 description of s0con bits table 35 selection of the serial port modes 76543210 smo sm1 sm2 ren tb8 rb8 ti ri bit symbol description 7 sm0 mode select. these 2 bits are used to select the serial port mode; see table 35. 6 sm1 5 sm2 enables the multiprocessor communication feature in modes 2 and 3. in these modes, if sm2 = 1, then ri will not be activated if the received 9th data bit (rb8) is a logic 0. in mode 1, if sm2 = 1, then ri will not be activated unless a valid stop bit was received. in mode 0, sm2 should be a logic 0. 4 ren enable serial reception. ren is set by software to enable reception, and cleared by software to disable reception. 3 tb8 is the 9th data bit that will be transmitted in modes 2 and 3. set or cleared by software as desired. 2 rb8 in modes 2 and 3, is the 9th data bit received. in mode 1, if sm2 = 0, then rb8 is the stop bit that was received. in mode 0, rb8 is not used. 1ti transmit interrupt ?ag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit time in the other modes, in any serial transmission. must be cleared by software. 0ri receive interrupt ?ag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial transmission (except see sm2). must be cleared by software. smo sm1 mode description baud rate 0 0 mode 0 shift register 1 6 f clk 0 1 mode 1 8-bit uart variable 1 0 mode 2 9-bit uart 1 16 f clk or 1 32 f clk 1 1 mode 3 9-bit uart variable
1998 aug 26 36 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 17.3 baud rates the baud rate in mode 0 is fixed and may be calculated as: the baud rate in mode 2 depends on the value of the smod bit in special function register pcon and may be calculated as: if smod = 0 (value on reset), the baud rate is 1 32 f clk if smod = 1, the baud rate is 1 16 f clk . 17.3.1 u sing t imer 1 to generate baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of the smod bit as follows: the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either timer or counter operation in any of its 3 running modes. in typical applications, it is configured for timer operation, in the auto-reload mode (high nibble of tmod = 0010b). in this case the baud rate is given by: by configuring timer 1 to run as a 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload, very low baud rates can be achieved. 17.3.2 u sing t imer 2 to generate baud rates timer 2 is selected as a baud rate generator by setting the rclk0, tclk0, rclk1, or tclk1 bit in t2con. the baud rate generator mode is similar to the auto-reload mode, in that a roll-over in th2 causes timer 2 registers to be reloaded with the 16-bit value held in the registers rcap2h and rcap2l, which are preset by software. baud rate f clk 6 ------ - = baud rate 2 smod 32 ---------------- - f clk = baud rate 2 smod 32 ---------------- - timer 1 overflow rate = baud rate 2 smod 32 ---------------- - f clk 6 256 th1 C () {} ---------------------------------------------------- - = baud rates in modes 1 and 3 are determined by timer 2's overflow rate as specified below: timer 2 can be configured for either timer or counter operation. in the most typical applications, it is configured for timer operation (c/ t2 = 0). timer operation is slightly different for timer 2 when it is being used as a baud rate generator. normally, as a timer it would increment every machine cycle at a frequency of 1 6 f clk . however, as a baud rate generator it increments every state time at a frequency of f clk . in this case, the baud rate in modes 1 and 3 is determined as shown by the following equation: where (rcap2h; rcap2l) is the content of registers rcap2h and rcap2l taken as a 16-bit unsigned integer. note that the maximum baud rate depends on clock frequency and is determined by the following equation: the baud rate generator mode for timer 2 is shown in fig.16. this figure is only valid if rclk0 = 1 or tclk0 = 1 or rclk1 = 1 or tclk1 = 1. at roll-over th2 does not set the tf2 bit in t2con and therefore, will not generate an interrupt. consequently, the timer 2 interrupt does not need to be disabled when in the baud rate generator mode. if exen2 is set, a high-to-low transition on t2ex will set the exf2 bit, also in t2con, but will not cause a reload from (rcap2h; rcap2l) to (th2 and tl2). therefore, in this mode t2ex may be used as an additional external interrupt. when timer 2 is operating as a timer (tr2 = 1), in the baud rate generator mode, registers th2 and tl2 should not be accessed (read or write). under these conditions the timer increments every state time and therefore the results of a read or write may not be accurate. the registers rcap2h and rcap2l however, may be read but not written to. a write might overlap a reload and cause write and/or reload errors. if a write operation is required, timer 2 or rcap2h/rcap2l should first be turned off by clearing the tr2 bit. baud rate timer 2 overflow rate 16 ------------------------------------------------------- - = baud rate f clk 16 65536 rcap2h; rcap2l () C {} ----------------------------------------------------------------------------------------------------- - = maximum baud rate f clk 16 6 --------------- - =
1998 aug 26 37 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.16 timer 2 in baud rate generator mode. handbook, full pagewidth mgm138 tl2 (8 bits) th2 (8 bits) rcap2l rcap2h exf2 timer 2 interrupt (additional external interrupt) 16 rtclk reload clk uart receive/ transmit clock smod 10 1 0 2 timer 1 overflow exen2 control transition detector t2ex pin tr2 control c/t2 = 0 c/t2 = 1 t2 pin f clk
1998 aug 26 38 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.17 serial port mode 0. handbook, full pagewidth mgc752 start shift t1 tx control tx clock send serial port interrupt rx clock r1 shift rx control start input shift register s0 buffer internal bus read sbuf shift load sbuf s0 buffer zero detector shift d cl s q internal bus tb8 write to sbuf 11111110 ren s6 ri rxd p3.0 alt output function receive shift clock txd p3.1 alt output function rxd p3.0 alt input function
1998 aug 26 39 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth mla567 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 ...s6 write to sbuf s6p2 d0 d1 d2 d3 d4 d5 d6 d7 s3p1 s6p1 write to scon (clear r1) d0 d1 d2 d3 d4 d5 d6 d7 s5p2 ale send shift rxd (data out) tsc (shift clock) ri t1 receive shift rxd (data in) txd (shift clock) t r a n s m i t r e c e i v e fig.18 serial port mode 0 timing.
1998 aug 26 40 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.19 serial port mode 1. handbook, full pagewidth mgm145 start shift data t1 tx control tx clock send 16 serial port interrupt 16 rx clock r1 load sbuf shift rx control start sample input shift register (9-bits) bit detector s0 buffer internal bus read sbuf shift load sbuf s0 buffer zero detector shift d cl s q tb8 internal bus write to sbuf rxd txd high-to-low transition detector 0 smod tclk0 1 0 1 0 1 2 timer 1 overflow timer 2 overflow rclk0
1998 aug 26 41 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth mla569 d0 d1 d2 d3 d4 d5 d6 d7 start bit d0 d1 d2 d3 d4 d5 d6 d7 tx clock write to sbuf data shift txd ti start bit s1p1 stop bit 16 reset rx clock rxd stop bit bit detector sample time shift ri send t r a n s m i t r e c e i v e fig.20 serial port mode 1 timing.
1998 aug 26 42 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.21 serial port mode 2. handbook, full pagewidth mgm144 start stop bit shift data t1 tx control tx clock send 16 serial port interrupt 16 rx clock r1 load sbuf shift rx control start sample input shift register (9-bits) bit detector s0 buffer internal bus read sbuf shift load sbuf s0 buffer zero detector shift d cl s q tb8 internal bus write to sbuf 2 f clk rxd txd 0 smod at pcon.7 1 high-to-low transition detector
1998 aug 26 43 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth tx clock stop bit gen rx clock bit detector sample time shift mla571 d0 d1 d2 d3 d4 d5 d6 d7 tb8 write to sbuf send data shift txd ti start bit s1p1 stop bit 16 reset start bit rxd d0 d1 d2 d3 d4 d5 d6 d7 stop bit ri rb8 t r a n s m i t r e c e i v e fig.22 serial port mode 2 timing.
1998 aug 26 44 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.23 serial port mode 3. handbook, full pagewidth mgm143 start shift data t1 0 smod tclk0 1 0 1 0 1 tx control tx clock send 16 serial port interrupt 16 rx clock r1 load sbuf shift rx control start high-to-low transition detector sample input shift register (9-bits) bit detector s0 buffer internal bus read sbuf shift load sbuf s0 buffer zero detector shift d cl s q tb8 internal bus write to sbuf 2 timer 1 overflow timer 2 overflow rxd txd rclk0
1998 aug 26 45 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth mla573 d0 d1 d2 d3 d4 d5 d6 d7 tx clock write to sbuf send data shift txd ti start bit s1p1 stop bit 16 reset start bit rx clock rxd d0 d1 d2 d3 d4 d5 d6 d7 stop bit bit detector sample time shift ri tb8 tb8 t r a n s m i t r e c e i v e fig.24 serial port mode 3 timing.
1998 aug 26 46 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 18 interrupt system external events and the real-time-driven on-chip peripherals require service by the cpu asynchronously to the execution of any particular section of code. to tie the asynchronous activities of these functions to normal program execution a multiple-source, two-priority-level, nested interrupt system is provided. the SZF2002 acknowledges interrupt requests from fifteen sources as follows: int0 to int8 timer 0, timer 1 and timer 2 i 2 c-bus serial i/o uart adc. each interrupt vectors to a separate location in program memory for its service routine. each source can be individually enabled or disabled by corresponding bits in the interrupt enable registers (ien0 and ien1). the priority level is selected via the interrupt priority registers (ip0 and ip1). all enabled sources can be globally disabled or enabled. figure 25 shows the interrupt system. 18.1 external interrupts int2 to int8 port 1 lines serve an alternative purpose as seven additional interrupts int2 to int8. when enabled, each of these lines (as well as int0 and int1) may wake-up the device from the power-down mode. using the interrupt polarity register (ix1), each pin may be initialized to be either active high or active low. irq1 is the interrupt request flag register. if the interrupt is enabled, each flag will be set on an interrupt request but must be cleared by software, i.e. via the interrupt software or when the interrupt is disabled. a low priority interrupt can be interrupted by a high priority interrupt but not by another low priority interrupt. a high priority interrupt routine can not be interrupted by any other interrupt. if two interrupt requests of different priority levels are received simultaneously, the request having the highest priority level will be serviced. if interrupt requests of the same priority level are received simultaneously an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence (see fig.25). port 1 interrupts are level sensitive. a port 1 interrupt will be recognized when a level (longer than 2 machine cycles, high or low, depending on the interrupt polarity register) on p1.n is made. the interrupt request is not serviced until the next machine cycle. figure 26 shows the external interrupt system. 18.2 interrupt priority each interrupt source can be set to either a high priority or to a low priority. if interrupts of the same priority are requested simultaneously, the processor will branch to the interrupt polled first, according to table 36. a low priority interrupt routine can only be interrupted by a high priority interrupt. a high priority interrupt routine can not be interrupted. table 36 shows the interrupt vectors in order of priority. the vector indicates the rom location where the appropriate interrupt service routine starts. table 36 interrupt vectors symbol vector address (hex) source x0 (highest) 0003 external interrupt 0 s1 002b i 2 c-bus port x5 0053 external interrupt 5 t0 000b timer 0 t2 0033 timer 2 x6 005b external interrupt 6 x1 0013 external interrupt 1 x2 003b external interrupt 2 x7 0063 external interrupt 7 t1 001b timer 1 x3 0043 external interrupt 3 x8 006b external interrupt 8 so 0023 uart x4 004b external interrupt 4 adc (lowest) 0073 adc
1998 aug 26 47 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.25 interrupt system. handbook, full pagewidth interrupt sources registers priority global enable x0 s1 x5 t0 t2 x6 x1 x2 x7 t1 x3 x8 so x4 adc ien0/1 ip0/1 high low interrupt polling sequence mgd623
1998 aug 26 48 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 18.3 interrupt related registers the registers ien0, ien1, ip0, ip1, ix1 and irq1 are used in conjunction with the interrupt system. table 37 special function registers related to the interrupt system address register description a8h ien0 interrupt enable register 0 e8h ien1 interrupt enable register 1 ( int2 to int8) b8h ip0 interrupt priority register 0 f8h ip1 interrupt priority register 1 ( int2 to int8 and adc) e9h ix1 interrupt polarity register c0h irq1 interrupt request flag register fig.26 external interrupt configuration. handbook, full pagewidth mgm139 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 x8 x7 x6 x5 x4 x3 x2 x1 x0 ix1 ien1/ien0 irq1 wake-up global enable
1998 aug 26 49 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 18.3.1 i nterrupt e nable r egister 0 (ien0) bit values: 0 = interrupt disabled; 1 = interrupt enabled. table 38 interrupt enable register 0 (sfr address a8h) table 39 description of ien0 bits 18.3.2 i nterrupt e nable r egister 1 (ien1) bit values: 0 = interrupt disabled; 1 = interrupt enabled. table 40 interrupt enable register 1 (sfr address e8h) table 41 description of ien1 bits 76543210 ea et2 es1 es0 et1 ex1 et0 ex0 bit symbol description 7ea general enable/disable control. if ea = 0, no interrupt is enabled; if ea = 1, any individually enabled interrupt will be accepted. 6 et2 enable t2 interrupt 5 es1 enable i 2 c-bus interrupt 4 es0 enable uart sio interrupt 3 et1 enable timer 1 interrupt (t1) 2 ex1 enable external interrupt 1 1 et0 enable timer 0 interrupt (t0) 0 ex0 enable external interrupt 0 76543210 ead ex8 ex7 ex6 ex5 ex4 ex3 ex2 bit symbol description 7 ead enable adc interrupt (external interrupt 9) 6 ex8 enable external interrupt 8 5 ex7 enable external interrupt 7 4 ex6 enable external interrupt 6 3 ex5 enable external interrupt 5 2 ex4 enable external interrupt 4 1 ex3 enable external interrupt 3 0 ex2 enable external interrupt 2
1998 aug 26 50 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 18.3.3 i nterrupt p riority r egister 0 (ip0) bit values: 0 = low priority; 1 = high priority. table 42 interrupt priority register 0 (sfr address b8h) table 43 description of ip0 bits 18.3.4 i nterrupt p riority r egister 1 (ip1) bit values: 0 = low priority; 1 = high priority. table 44 interrupt priority register 1 (sfr address f8h) table 45 description of ip1 bits 76543210 - pt2 ps1 ps0 pt1 px1 pt0 px0 bit symbol description 7 - reserved 6 pt2 timer 2 interrupt priority level 5 ps1 i 2 c-bus interrupt priority level 4 ps0 uart sio interrupt priority level 3 pt1 timer 1 interrupt priority level 2 px1 external interrupt 1 priority level 1 pt0 timer 0 interrupt priority level 0 px0 external interrupt 0 priority level 76543210 padc px8 px7 px6 px5 px4 px3 px2 bit symbol description 7 padc adc interrupt priority level 6 px8 external interrupt 8 priority level 5 px7 external interrupt 7 priority level 4 px6 external interrupt 6 priority level 3 px5 external interrupt 5 priority level 2 px4 external interrupt 4 priority level 1 px3 external interrupt 3 priority level 0 px2 external interrupt 2 priority level
1998 aug 26 51 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 18.3.5 i nterrupt p olarity r egister (ix1) writing either a logic 1 or logic 0 to any interrupt polarity register bit sets the polarity level of the corresponding external interrupt to an active high or active low respectively. table 46 interrupt polarity register (sfr address e9h) table 47 description of ix1 bits 18.3.6 i nterrupt r equest f lag r egister (irq1) table 48 interrupt request flag register (sfr address c0h) table 49 description of irq1 bits 76543210 - il8 il7 il6 il5 il4 il3 il2 bit symbol description 7 - reserved 6 il8 external interrupt 8 polarity level 5 il7 external interrupt 7 polarity level 4 il6 external interrupt 6 polarity level 3 il5 external interrupt 5 polarity level 2 il4 external interrupt 4 polarity level 1 il3 external interrupt 3 polarity level 0 il2 external interrupt 2 polarity level 76543210 - iq8 iq7 iq6 iq5 iq4 iq3 iq2 bit symbol description 7 - reserved 6 iq8 external interrupt 8 request ?ag 5 iq7 external interrupt 7 request ?ag 4 iq6 external interrupt 6 request ?ag 3 iq5 external interrupt 5 request ?ag 2 iq4 external interrupt 4 request ?ag 1 iq3 external interrupt 3 request ?ag 0 iq2 external interrupt 2 request ?ag
1998 aug 26 52 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 19 clock circuitry the SZF2002 is clocked with an external digital clock. the input must be driven with a digital square wave. note that the duty cycle influences the timing to the external components, since both the positive and negative clock edges are used. 20 reset to initialize the SZF2002 a reset is performed by either of two methods: applying an external signal to the rst pin watchdog timer overflow. 20.1 external reset using the rst pin the reset input for the SZF2002 is rst. a reset is accomplished by holding the rst pin high for at least two machine cycles (12 clock periods) while the clock is running. the cpu responds by executing an internal reset. port pins adopt their reset state immediately after the rst goes high. during reset, we and oe, and ce are held high. the external reset is asynchronous to the internal clock. the rst pin is sampled during state 5, phase 2 of every machine cycle. after a high is detected at the rst pin, an internal reset is repeated until rst goes low. the reset circuitry is also affected by the watchdog timer as described in section 12.5. the internal ram is not affected by reset. when v dd is turned on, the ram contents are indeterminate. 20.2 power-on-reset the device contains on-chip circuitry which switches the port pins to high as soon as rst goes high. the user must ensure that the rst pin is held high until the external clock has stabilised. when rst goes low a further 3 cycles elapse before execution starts.
1998 aug 26 53 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 21 special function registers overview address (hex) name reset value (b) function ff t3 0000 0000 watchdog timer fe pwmp (1) 0000 0000 prescaler frequency control register fc pwm (1) 0000 0000 pulse width register f8 ip1 (1)(2) 0000 0000 interrupt priority register 1 ( int2 to int8 and adc) f7 wdtkey (1) 0000 0000 watchdog timer enable f0 b (2) 0000 0000 b register e9 ix1 (1) x 000 0000 interrupt polarity register 1 e8 ien1 (1)(2) 0000 0000 interrupt enable register 1 e0 acc (2) 0000 0000 accumulator db s1adr (1) 0000 0000 i 2 c-bus slave address register da s1dat (1) 0000 0000 i 2 c-bus data shift register d9 s1sta (1) 1111 1000 i 2 c-bus serial status register d8 s1con (1)(2) 0000 0000 i 2 c-bus serial control register d0 psw (2) 0000 0000 program status word cd th2 (1) 0000 0000 timer 2 high byte cc tl2 (1) 0000 0000 timer 2 low byte cb rcap2h (1) 0000 0000 timer 2 reload/capture register high byte ca rcap2l (1) 0000 0000 timer 2 reload/capture register low byte c9 t2mod (1) xx 00 x 000 timer/counter 2 mode control c8 t2con (1)(2) 0000 0000 timer/counter 2 control register c5 adch (1) 1111 1111 adc result register c4 adcon (1) x 000 0000 adc control register c1 p4 (1) 1111 1111 digital i/o port register 4 c0 irq1 (1)(2) x 000 0000 interrupt request flag register b8 ip0 (2) x 000 0000 interrupt priority register 0 b0 p3 (2) 1111 1111 digital i/o port register 3 a8 ien0 (2) 0000 0000 interrupt enable register 0 a0 p2 (2) 1111 1111 digital i/o port register 2
1998 aug 26 54 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 notes 1. SZF2002 specific sfrs. 2. bit addressed register. 99 s0buf xxxx xxxx serial data buffer register 0 98 s0con (2) 0000 0000 serial port control register 0 91 rombank (1) xxxx x 000 rom bank selection register 90 p1 (2) 1111 1111 digital i/o port register 1 8d th1 0000 0000 timer 1 high byte 8c th0 0000 0000 timer 0 high byte 8b tl1 0000 0000 timer 1 low byte 8a tl0 0000 0000 timer 0 low byte 89 tmod 0000 0000 timer 0 and 1 mode control register 88 tcon (2) 0000 0000 timer 0 and 1 control/external interrupt control register 87 pcon 0000 0000 power control register 83 dph 0000 0000 data pointer high byte 82 dpl 0000 0000 data pointer low byte 81 sp 0000 0111 stack pointer 80 p0 (2) 1111 1111 digital i/o port register 0 address (hex) name reset value (b) function
1998 aug 26 55 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 22 debugging support for software development the SZF2002 is made compatible with the nohau 80c51 in-circuit emulator (ice). 22.1 recommended equipment 1. nohau emul51-pc/ea768-bsw-42 42 mhz, 768-kbyte emulator memory board. 2. nohau emul51-pc/atr64-33, 33 mhz, 64-kbyte advanced trace memory board. 3. nohau emul51-pc/pod-c32hf-42, external memory mode pod for a.o. 80c51/80c32. 22.2 connecting the pod the nohau in-circuit emulator requires the following 80c51 pins: p0.0 to p0.7, p2.0 to p2.7, ale, psen, rd, wr, ea and rst. when setting the SZF2002 in debug mode (force debug high), these signals become available on the pins as described in section 7.2 the connection between the SZF2002 and the emulator is shown in fig.27. for emulation the target board must be configured with the SZF2002 mounted, but without external flash and ram, or disabled by disconnecting the oe. on the target board a 40-pin connector is required that has all the necessary 80c51 signals (port 0, port 2, psen, ale, ea, rst, v dd and v ss ). the 16 port pins are optional. the three banking bits are not standard 80c51 signals and are not available at the dil40 80c51-connector of the pod. these three bits must be connected via three separate wires to the signals bs0 (lsb), bs1 and bs2 (msb) on the pod. the emulator pod has a dil40 socket for the 80c51 processor (on the upper side). by connecting the 40-pin connector to this socket the emulator will approach the SZF2002 as if it were a 80c51. the connector on the lower side of the pod is not used. the emulator acts as a memory emulator. 22.3 powering the pod because the SZF2002 is a 3 v circuit, the ice pod must be powered by the target (supply from pc is not possible, see documentation for emul51-pc/pod-c32hf-42). therefore, v dd and v ss for the SZF2002 are also required. the clock signal is not required on the pod. the digital power v dd has to be connected to the pod. the ground of the pod must be connected to the ground of the target board via the black gnd-wire soldered to the pod because the target supplies the pod the following power-up/power-down sequence is required: 1. switch on target. 2. switch on pc. 3. switch off target. when using 3 v power from the target, note that the pod will drive the inputs up to 3.5 v. some current will also flow through the v dd connection to the target. if the emulator is used together with an i 2 c-bus interface to a pc or together with an rs232-connection, use 3.3 v power for the target. this will reduce noise and disturbance on all input and output signals. in practice, it is seen that this will result in a more robust communication between the SZF2002 and nohau. both i 2 c-bus pins (sda and scl) need an external pull-up resistor. 22.4 bank switching support if bank switching is required, the in-circuit emulator also needs the true_a15 and the three banking bits a15 to a17. 16 port pins (selection of ports 3 and 4) can also be connected to the emulator pod, however this is not necessary. when connected, the state of these ports can be traced. to set up the banking configuration the bm jumpers on the emulator board have to be set. the following set-up is recommended: 1. jumper bm3 is out. 2. jumper bm2 is out. 3. jumper bm1is dont care. 4. jumper bm0 is in. 22.5 software recommendations the keil/franklin assembler and banked linker is well suited for use with the nohau ice (especially for banking configurations). the nohau ice communicates with the SZF2002 using movx instructions. therefore, all movx instructions must be forced to access off-chip memory instead of internal aux ram by setting the ard bit of the sfr pcon.
1998 aug 26 56 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.27 in-circuit emulation. handbook, full pagewidth mbk834 SZF2002 flash SZF2002 connector target pcb (flash is disabled, doesn't need to be mounted) adapter pcb socket for target processor this socket not used flat cable to pc type 31a pod nohau emulator pc with emulator cards
1998 aug 26 57 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 23 instruction set the SZF2002 uses a powerful instruction set which optimizes byte efficiency and execution speed. assigned opcodes add new high-power operation and permit new addressing modes. the instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. when using a 12 mhz clock, 64 instructions execute in 0.5 m s and 45 instructions execute in 1 m s. multiply and divide instructions execute in 2 m s. for the description of the data addressing modes and hexadecimal opcode cross-reference see table 54. table 50 instruction set description: arithmetic operations mnemonic description bytes cycles opcode (hex) arithmetic operations add a,rr add register to a 1 1 2* add a,direct add direct byte to a 2 1 25 add a,@ri add indirect ram to a 1 1 26 and 27 add a,#data add immediate data to a 2 1 24 addc a,rr add register to a with carry ?ag 1 1 3* addc a,direct add direct byte to a with carry ?ag 2 1 35 addc a,@ri add indirect ram to a with carry ?ag 1 1 36 and 37 addc a,#data add immediate data to a with carry ?ag 2 1 34 subb a,rr subtract register from a with borrow 1 1 9* subb a,direct subtract direct byte from a with borrow 2 1 95 subb a,@ri subtract indirect ram from a with borrow 1 1 96 and 97 subb a,#data subtract immediate data from a with borrow 2 1 94 inc a increment a 1 1 04 inc rr increment register 1 1 0* inc direct increment direct byte 2 1 05 inc @ri increment indirect ram 1 1 06 and 07 dec a decrement a 1 1 14 dec rr decrement register 1 1 1* dec direct decrement direct byte 2 1 15 dec @ri decrement indirect ram 1 1 16 and 17 inc dptr increment data pointer 1 2 a3 mul ab multiply a and b 1 4 a4 div ab divide a by b 1 4 84 da a decimal adjust a 1 1 d4
1998 aug 26 58 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 table 51 instruction set description: logic operations mnemonic description bytes cycles opcode (hex) logic operations anl a,rr and register to a 1 1 5* anl a,direct and direct byte to a 2 1 55 anl a,@ri and indirect ram to a 1 1 56 and 57 anl a,#data and immediate data to a 2 1 54 anl direct,a and a to direct byte 2 1 52 anl direct,#data and immediate data to direct byte 3 2 53 orl a,rr or register to a 1 1 4* orl a,direct or direct byte to a 2 1 45 orl a,@ri or indirect ram to a 1 1 46 and 47 orl a,#data or immediate data to a 2 1 44 orl direct,a or a to direct byte 2 1 42 orl direct,#data or immediate data to direct byte 3 2 43 xrl a,rr exclusive-or register to a 1 1 6* xrl a,direct exclusive-or direct byte to a 2 1 65 xrl a,@ri exclusive-or indirect ram to a 1 1 66 and 67 xrl a,#data exclusive-or immediate data to a 2 1 64 xrl direct,a exclusive-or a to direct byte 2 1 62 xrl direct,#data exclusive-or immediate data to direct byte 3 2 63 clr a clear a 1 1 e4 cpl a complement a 1 1 f4 rl a rotate a left 1 1 23 rlc a rotate a left through the carry ?ag 1 1 33 rr a rotate a right 1 1 03 rrc a rotate a right through the carry ?ag 1 1 13 swap a swap nibbles within a 1 1 c4
1998 aug 26 59 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 table 52 instruction set description: data transfer note 1. mov a,acc is not permitted. mnemonic description bytes cycles opcode (hex) data transfer mov a,rr move register to a 1 1 e* mov a,direct (note 1) move direct byte to a 2 1 e5 mov a,@ri move indirect ram to a 1 1 e6 and e7 mov a,#data move immediate data to a 2 1 74 mov rr,a move a to register 1 1 f* mov rr,direct move direct byte to register 2 2 a* mov rr,#data move immediate data to register 2 1 7* mov direct,a move a to direct byte 2 1 f5 mov direct,rr move register to direct byte 2 2 8* mov direct,direct move direct byte to direct 3 2 85 mov direct,@ri move indirect ram to direct byte 2 2 86 and 87 mov direct,#data move immediate data to direct byte 3 2 75 mov @ri,a move a to indirect ram 1 1 f6 and f7 mov @ri,direct move direct byte to indirect ram 2 2 a6 and a7 mov @ri,#data move immediate data to indirect ram 2 1 76 and 77 mov dptr,#data 16 load data pointer with a 16-bit constant 3 2 90 movc a,@a+dptr move code byte relative to dptr to a 1 2 93 movc a,@a+pc move code byte relative to pc to a 1 2 83 movx a,@ri move external ram (8-bit address) to a 1 2 e2 and e3 movx a,@dptr move external ram (16-bit address) to a 1 2 e0 movx @ri,a move a to external ram (8-bit address) 1 2 f2 and f3 movx @dptr,a move a to external ram (16-bit address) 1 2 f0 push direct push direct byte onto stack 2 2 c0 pop direct pop direct byte from stack 2 2 d0 xch a,rr exchange register with a 1 1 c* xch a,direct exchange direct byte with a 2 1 c5 xch a,@ri exchange indirect ram with a 1 1 c6 and c7 xchd a,@ri exchange low-order digit indirect ram with a 1 1 d6 and d7
1998 aug 26 60 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 table 53 instruction set description: boolean variable manipulation and program and machine control mnemonic description bytes cycles opcode (hex) boolean variable manipulation clr c clear carry ?ag 1 1 c3 clr bit clear direct bit 2 1 c2 setb c set carry ?ag 1 1 d3 setb bit set direct bit 2 1 d2 cpl c complement carry ?ag 1 1 b3 cpl bit complement direct bit 2 1 b2 anl c,bit and direct bit to carry ?ag 2 2 82 anl c,/bit and complement of direct bit to carry ?ag 2 2 b0 orl c,bit or direct bit to carry ?ag 2 2 72 orl c,/bit or complement of direct bit to carry ?ag 2 2 a0 mov c,bit move direct bit to carry ?ag 2 1 a2 mov bit,c move carry ?ag to direct bit 2 2 92 program and machine control acall addr11 absolute subroutine call 2 2 1 lcall addr16 long subroutine call 3 2 12 ret return from subroutine 1 2 22 reti return from interrupt 1 2 32 ajmp addr11 absolute jump 2 2 1 ljmp addr16 long jump 3 2 02 sjmp rel short jump (relative address) 2 2 80 jmp @a+dptr jump indirect relative to the dptr 1 2 73 jz rel jump if a is zero 2 2 60 jnz rel jump if a is not zero 2 2 70 jc rel jump if carry ?ag is set 2 2 40 jnc rel jump if carry ?ag is not set 2 2 50 jb bit,rel jump if direct bit is set 3 2 20 jnb bit,rel jump if direct bit is not set 3 2 30 jbc bit,rel jump if direct bit is set and clear bit 3 2 10 cjne a,direct,rel compare direct to a and jump if not equal 3 2 b5 cjne a,#data,rel compare immediate to a and jump if not equal 3 2 b4 cjne rr,#data,rel compare immediate to register and jump if not equal 3 2 b* cjne @ri,#data,rel compare immediate to indirect and jump if not equal 3 2 b6 and b7 djnz rr,rel decrement register and jump if not zero 2 2 d* djnz direct,rel decrement direct and jump if not zero 3 2 d5 nop no operation 1 1 00
1998 aug 26 61 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 table 54 description of the mnemonics in the instruction set mnemonic description data addressing modes rr working registers r0 to r7. direct 128 internal ram locations and any special function register (sfr). @ri indirect internal ram location addressed by register r0 or r1 of the actual register bank. #data 8-bit constant included in instruction. #data 16 16-bit constant included as bytes 2 and 3 of instruction. bit direct addressed bit in internal ram or sfr. addr16 16-bit destination address. used by lcall and ljmp. the branch will be anywhere within the 64 kbytes program memory address space. addr11 111-bit destination address. used by acall and ajmp. the branch will be within the same 2 kbytes page of program memory as the ?rst byte of the following instruction. rel signed (two's complement) 8-bit offset byte. used by sjmp and all conditional jumps. range is - 128 to + 127 bytes relative to ?rst byte of the following instruction. hexadecimal opcode cross-reference * 8, 9, a, b, c, d, e and f. 1, 3, 5, 7, 9, b, d and f. 0, 2, 4, 6, 8, a, c and e.
1998 aug 26 62 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 55 instruction map note 1. mov a, acc is not a valid instruction. first hexadecimal character of opcode ? second hexadecimal character of opcode ? 0123 456789abcdef 0 nop ajmp addr11 ljmp addr16 rr a inc a inc direct inc @ri inc rr 0 1 01234567 1 jbc bit,rel acall addr11 lcall addr16 rrc a dec a dec direct dec @ri dec rr 0 1 01234567 2 jb bit,rel ajmp addr11 ret rl a add a,#data add a,direct add a,@ri add a,rr 0 1 01234567 3 jnb bit,rel acall addr11 reti rlc a addc a,#data addc a,direct addc a,@ri addc a,rr 0 1 01234567 4 jc rel ajmp addr11 orl direct,a orl direct,#data orl a,#data orl a,direct orl a,@ri orl a,rr 0 1 01234567 5 jnc rel acall addr11 anl direct,a anl direct,#data anl a,#data anl a,direct anl a,@ri anl a,rr 0 1 01234567 6 jz rel ajmp addr11 xrl direct,a xrl direct,#data xrl a,#data xrl a,direct xrl a,@ri xrl a,rr 0 1 01234567 7 jnz rel acall addr11 orl c,bit jmp @a+dptr mov a,#data mov direct,#data mov @ri,#data mov rr,#data 0 1 01234567 8 sjmp rel ajmp addr11 anl c,bit movc a,@a+pc div ab mov direct,direct mov direct,@ri mov direct,rr 0 1 01234567 9 mov dtpr,#data16 acall addr11 mov bit,c movc a,@a+dptr subb a,#data subb a,direct subb a,@ri sub a,rr 0 1 01234567 a orl c,/bit ajmp addr11 mov bit,c inc dptr mul ab mov @ri,direct mov rr,direct 0 1 01234567 b anl c,/bit acall addr11 cpl bit cpl c cjne a,#data,rel cjne a,direct,rel cjne @ri,#data,rel cjne rr,#data,rel 0 1 01234567 c push direct ajmp addr11 clr bit clr c swap a xch a,direct xch a,@ri xch a,rr 0 1 01234567 d pop direct acall addr11 setb bit setb c da a djnz direct,rel xchd a,@ri djnz rr,rel 0 1 01234567 e movx a,@dtpr ajmp addr11 movx a,@ri clr a mov a,direct (1) mov a,@ri mov a,rr 0 1 0 1 01234567 f movx @dtpr,a acall addr11 movx @ri,a cpl a mov direct,a mov @ri,a mov rr,a 0 1 0 1 01234567
1998 aug 26 63 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 24 limiting values in accordance with the absolute maximum rating system (iec 134). 25 dc characteristics v dd = 2.7 to 3.3 v; v ss = 0 v; t amb = - 40 to +85 c; see note 1; all voltages are with respect to v ss ; unless otherwise speci?ed. notes to the dc characteristics 1. loading ports and busses may cause spurious noise pulses to be superimposed on the output voltage. symbol parameter min. max. unit v dd supply voltage - 0.5 +5 v v i input voltage on any pin with respect to ground (v ss ) - 0.5 v dd + 0.5 v i i and i o dc current on any input or output - tbf ma p tot total power dissipation - 500 mw t stg storage temperature - 65 +150 c t amb operating ambient temperature - 40 +85 c t j operating junction temperature - 40 +125 c symbol parameter conditions min. typ. max. unit supply v dd operating supply voltage 2.7 - 3.3 v i dd operating supply current v dd = 3.0 v; f clk = 8 mhz; note 2 -- 9ma v dd = 3.0 v; f clk = 3.58 mhz; note 2 -- 2.5 ma i dd(idle) idle mode supply current v dd = 3.0 v; f clk = 8 mhz; note 3 -- 5.0 ma v dd = 3.0 v; f clk = 3.58 mhz; note 3 -- 1.5 ma i dd(pd) power-down mode current v dd = 3.0 v; t amb =25 c; note 4 -- 10 m a inputs (note 5) v il low-level input voltage v ss - 0.2v dd v v ih high-level input voltage 0.8v dd - v dd v i li input leakage current v ss 1998 aug 26 64 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 2. the operating supply current is measured with all output pins disconnected; clk driven with t r =t f =10ns; v il =v ss ;v ih =v dd ; ea = rst = port 0 = v dd . 3. the idle mode supply current is measured with all output pins disconnected; clk driven with t r =t f = 10 ns; v il =v ss ; v ih =v dd ; ea = port 0 = v dd . 4. the power-down current is measured with all output pins disconnected; clk connected to v ss ; ea = port 0 = v dd ; rst=v ss . 5. the input threshold voltage of p1.6/scl and p1.7/sda meet the i 2 c-bus specification. therefore, an input voltage below 0.3v dd will be recognized as a logic 0 and an input voltage above 0.7v dd will be recognized as a logic 1. 26 adc characteristics notes 1. all adc inputs require an external divide-by-2 voltage divider. 2. gain error: the maximum difference between actual and ideal slope. 3. zero-offset error: the difference between the actual and ideal input voltage corresponding to the first actual code transition. 4. differential non-linearity: the difference between the actual and ideal code widths. 5. integral non-linearity: maximum deviation from straight line. 6. channel-to-channel matching: the difference between corresponding code transitions of actual characteristics taken from different channels under the same temperature, voltage and frequency conditions. not tested, but verified on sampling basis. symbol parameter conditions min. typ. max. unit v in(adc) adc input voltage note 1 v ssa - 0.5v dda v v dda analog supply voltage v dd - 0.5 - v dd + 0.5 v i dda supply current operating v dda = 3.0 v; f clk = 8 mhz -- 0.5 ma c ain analog on-chip input capacitance -- 2pf r ain analog on-chip input impedance 10 -- m w g e gain error; note 2 - 1 - +1 % os e zero-offset error; note 3 - 1 - +1 lsb dnl differential non-linearity; note 4 - 0.5 - +0.5 lsb inl integral non-linearity; note 5 - 1 - +1 lsb m ctc channel-to-channel matching; note 6 -- 1 2 lsb v i(slope) input voltage slope f clk = 8 mhz - 0.15 - +0.15 v/ms
1998 aug 26 65 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.28 analog-to-digital conversion characteristics. (1) the ideal transfer curve. (2) the actual transfer curve. (3) differential non-linearity (dnl). (4) integral non-linearity (inl). (5) gain error (g e ). handbook, full pagewidth mgm135 1 2 3 4 5 6 7 250 251 252 253 254 255 0 1 2 3 4 5 250 251 252 253 254 255 v in(a) (lsb ideal ) code out zero offset error 1 lsb (ideal) (3) (5) (4) (1) (2) 1lsb = v dda - v ssa 255
1998 aug 26 66 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 27 ac characteristics table 56 timing with respect to ce, oe and we symbol parameter min. typ max. unit general (see fig.29) t xclkh xclk high time 31.25 -- ns t xclkl xclk low time 31.25 -- ns t cy(xclk) xclk cycle time 62.5 -- ns memory access (figs 29 and 30) t (cel-oel)1 ce low to oe low (data cycle) -- 1 2 t clk +3 ns t (oel)1 oe low time (data cycle) -- 7 2 t clk +7 ns t (ceh-oeh)1 ce high to oe high (data cycle) 0 - 12 ns t (cel)1 ce low time (data cycle) -- 4t clk ns t (cel-wel)1 ce low to we low (data cycle) -- 1 2 t clk +5 ns t (wel)1 we low time (data cycle) -- 7 2 t clk +8 ns t (ceh-weh)1 ce high to we high (data cycle) 0 - 13 ns t su(oe-d)2 data set-up time from oe (data read cycle) -- 3t clk - 18 ns t su(cel-d)2 data set-up time from ce low (data read cycle) -- 7 2 t clk - 18 ns t su(d-wel)3 data set-up time to we low (data write cycle) -- 1 2 t clk - 3ns t (cel-dv)3 data valid time from ce low (data write cycle) -- 3ns t su(d-sm)2 data set-up time to sample moment (data read cycle); note 1 -- 8ns t h(sm-d)2 data hold time from sample moment (data read cycle); note 1 0 -- ns t h(weh-d)3 data hold time from we high (data write cycle) -- t clk - 20 ns t h(ceh-d)3 data hold time from ce high (data write cycle) -- t clk - 10 ns t su(a-cel)1 address set-up time to ce low (data cycle) -- 1 2 t clk - 5ns t h(ceh-a)1 address hold time from ce high (data cycle) -- t clk ns t (cel-oel)4 ce low to oe low (code fetch cycle) -- 1 2 t clk ns t (oel)4 oe low time (code fetch cycle) -- 3 2 t clk ns t (ceh-oeh)4 ce high to oe high (code fetch cycle) 0 - 2ns
1998 aug 26 67 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 notes 1. sample moment for data read cycles is on negative clock edge in state s3, the internal clock skew must be taken into account also. this results in 3t clk - 10 ns from oe low (or 7 2 t clk - 10 ns from ce low) maximum. 2. sample moment for code fetch cycles is on negative clock edge in state s2 or s4, the internal clock skew must be taken into account also. this results in 3 2 t clk - 10 ns from oe low (or 2t clk - 10 ns from ce low) maximum. t (cel)4 ce low time (code fetch cycle) -- 2t clk ns t su(oe-d)4 data set-up time from oe (code fetch cycle) -- 3 2 t clk - 18 ns t su(cel-d)4 data set-up time from ce low (code fetch cycle) -- 2t clk - 18 ns t su(d-sm)4 data set-up time to sample moment (code fetch cycle), note 2 -- 8ns t h(sm-d)4 data hold time from sample moment (code fetch cycle) 0 -- ns t su(dz-oel) data bus high-impedance set-up time to oe low (data read cycle); (code fetch cycle) 1 2 t clk +12 -- ns t h(dz-oeh) data bus high-impedance hold time from oe high (data read cycle); (code fetch cycle) 1 2 t clk - 2; t clk - 11 -- ns t su(a-cel)4 address set-up time to ce low (code fetch cycle) -- 1 2 t clk - 4ns t h(ceh-a)4 address hold time from ce high (code fetch cycle) -- 1 2 t clk ns symbol parameter min. typ max. unit
1998 aug 26 68 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.29 external program memory access, w.r.t. ce, oe, and we. (1) a0 to a3 alternative functions ( psen, ale, wr and rd) show debug mode timing; data bus carries low address on falling ale edge. (2) skipped ale pulse because of movx instruction. (3) (last) data sample moment. handbook, full pagewidth mgm354 xclk code fetch a0 to a17 d0 to d7 we ce oe a2/ale (1) code in code in data out data in code fetch write( )/read( ) code fetch a3/psen (1) a0/rd (1) a1/wr (1) s1 to s6: one machine cycle s6 s2 s3 s4 s5 s6 s2 s3 s4 s1 s1 s5 s4 t xclkl t (cel-oel)1 t (cel-wel)1 t h(ceh-a)1 t (cel-dv)3 t su(a-cel)4 t su(a-cel)1 t h(ceh-a)4 t h(sm-d)4 t su(d-sm)4 t su(cel-d)2 t su(oe-d)2 t su(d-sm)2 t su(dz-oel) t su(d-wel)3 t h(dz-oeh) t (wel)1 t (oel)1 t (cel)1 t (ceh-oeh)4 t (ceh-oeh)1 (2) t xclkh t cy(xclk) (3) code sample moment t h(sm-d)2 t (ceh-weh)1 t h(weh-d)3 t su(cel-d)4 t su(oe-d)4 code in t (cel-oel)4 (3) data sample moment
1998 aug 26 69 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 table 57 timing ?gures with respect to ramce, oe and wel notes 1. sample moment for data read cycles is on negative clock edge in state s3, the internal clock skew must be taken into account also. this results in 3t clk - 10 ns from oe low (or 7 2 t clk - 10 ns from ramce low) maximum. symbol parameter min. typ. max. unit general (see fig.29) t xclkh xclk high time 31.25 -- ns t xclkl xclk low time 31.25 -- ns t cy(xclk) xclk cycle time 62.5 -- ns memory access (figs 29 and 30) t (rcel-oel) ramce low to oe low -- 1 2 t clk - 3ns t (oel) oe low time -- 7 2 t clk +8 ns t (rceh-oeh) ramce high to oe high 0 - 6ns t (rcel) ramce low time -- 4t clk - 1ns t (rcel-wel) ramce low to we low -- 1 2 t clk - 2ns t (wel) we low time -- 7 2 t clk +7 ns t (rceh-weh) ramce high to we high 0 - 7ns t su(oel-d) data set-up time from oe low -- 3t clk - 18 ns t su(rcel-d) data set-up time from ramce low -- 7 2 t clk - 20 ns t su(d-wel) data set-up time to we low -- 1 2 t clk +3 ns t (rcel-dv) data valid time from ramce low -- 4ns t su(d-sm) data set-up time to sample moment, note 1 -- 8ns t h(sm-d) data hold time from sample moment; note 1 0 -- ns t h(weh-d) data hold time from we high -- t clk - 7ns t h(rceh-d) data hold time from ramce high -- t clk - 14 ns t su(a-rcel) address set-up time to ramce low -- 1 2 t clk ns t h(rceh-a) address hold time from ramce high -- t clk - 7ns t su(dz-oel) data bus high-impedance set-up time to oe low 1 2 t clk +1 -- ns t h(oeh-dz) data bus high-impedance hold time from oe high 1 2 t clk - 10 -- ns
1998 aug 26 70 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 fig.30 external ram access w.r.t. ramce, oe and we. (1) a0 to a3 alternative functions ( psen, ale, wr and rd) show debug mode timing (data bus carries low address on falling ale edge. (2) skipped ale pulse because of movx instruction. (3) (last) data sample moment. (4) code fetch only if ce is active (not shown). ce and ramce are never active at the same time. handbook, full pagewidth mgm355 xclk code fetch (4) we d0 to d7 a0 to a17 ramce oe a2/ale (1) code in code in code in data out data in code fetch (4) write( )/read( ) code fetch (4) a3/psen (1) a0/rd (1) a1/wr (1) s1 to s6: one machine cycle s6 s2 s3 s4 s5 s6 s2 s3 s4 s1 s1 s5 s4 t xclkh t xclkl t (cel) t (rcel-oel) t (oel) t (rcel-wel) t (wel) t (rceh-oeh) (2) t (rceh-weh) t su(rcel-d) t su(oel-d) t h(weh-d) t h(oeh-dz) t su(dz-oel) t su(d-wel) t (rcel-dv) t su(a-rcel) t su(d-sm) t h(sm-d) data sample moment (3) code sample moment (3) t h(rceh-a)
1998 aug 26 71 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 28 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o o 0.15 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 sot315-1 97-07-15 95-12-19 d (1) (1) (1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
1998 aug 26 72 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 29 soldering 29.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). 29.2 re?ow soldering reflow soldering techniques are suitable for all lqfp packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. 29.3 wave soldering wave soldering is not recommended for lqfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. caution wave soldering is not applicable for all lqfp packages with a pitch (e) equal or less than 0.5 mm. if wave soldering cannot be avoided, for lqfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 29.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 aug 26 73 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 30 definitions 31 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 32 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1998 aug 26 74 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 notes
1998 aug 26 75 philips semiconductors product speci?cation low voltage 8-bit microcontroller with 6-kbyte embedded ram SZF2002 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca60 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors 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communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. 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novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 455104/100/01/pp76 date of release: 1998 aug 26 document order number: 9397 750 02944

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