View PT7A6526_3964417.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) pt7a6525/6526 demo board instruction brief this application note describes a simple application demonstration for serial communication interface consisting of pt7a6525, at89c51 (cpu) and pt7a4401 (clock circuit), etc. since there is no long- distance driving circuit available, it only adapts to short-distance data communication with transfer rate up to 4mbps. it demonstrates three typical functions of pt7a6525 in connection with at89c51 and pt7a4401 consist of synchronous or asynchro- nous communications system in different clock modes, such as clock mode 1 and clock mode 5 for synchronous communications, and clock mode 3 for asynchronous communications. this demo board adopts lvds as its serial interface driver, it is suitable for flat-wire transmission and back-board driving, and it can be used at point-to-point configuration. the system utilizes pt7a4401?s phase locked loop to operate in the synchronous communication mode, thus the master station supplies only one reference to the slave station. the slave station recovers the main clock and the synchronous signal from the reference clock. the schematics and 89c51 assemble supervision program of demo board are list in sch and pro.pdf .
2 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) brief ............................................................................................................................... ..................... 1 introduction ............................................................................................................................... ......... 3 functional description ......................................................................................................... ............... 3 pt7a6525/6526 .................................................................................................................. ...... 5 principle of demo system ....................................................................................................... .. 6 auto mode ...................................................................................................................... .6 non-auto mode ............................................................................................................... 6 transparent mode............................................................................................................. 7 clock modes .................................................................................................................... 7 hardware principle ............................................................................................................. ...... 9 communication between pc and at89c51..................................................................... 9 interface between at89c51 and hdlc (pt7a6525)................................................... 11 demo board ................................................................................................................... 12 software functions ............................................................................................................. ..... 13 operational guide of demo system ............................................................................................... .14 hardware configuration ......................................................................................................... .14 software ....................................................................................................................... ........... 15 appendix a: clock modes and cpu interface connection ............................................................ 25 appendix b: source file of at89c51 assemble supervisor program .................................................. 28 notes .......................................................................................................................... ....................... 29 contents page contents
3 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) introduction this application note describes a simple application demo system for serial communication interface by using pt7a6525, at89c51 and pt7a4401 (clock circuit). this combination system can operate in clock mode 1, clock mode 3, and clock mode 5 of pt7a6525/6526 by revising epld?s internal logic and setting software. it can also operate in the address recognition mode and the non-ad- dress recognition mode by rewriting the mode register of pt7a6525/6526. this application note also describes how to set registers of pt7a6525 for adapting to the different operation modes, and how to observe the status of the pt7a6525/6526 via pc. functional description refer to the functional block diagram in figure 1. the computer (pc) communicates with the monolithic pro- cessor (at89c51) via rs232, and at89c51 accesses di- rectly hdlc (pt7a6525/6526) according to instructions from pc, i.e., pc can control pt7a6525 indirectly, receiv- ing/transmitting message from/to pt7a6525/6526 via at89c51. in other word, pc can reliably communicate with each other via hdlc (pt7a6525) serial interface, the serial data meets with hdlc protocol. the reliabilityof serial communication is improved by the hdlc, and the software cost is greatly reduced. pc supervisor at89c51 hdlc pt7a6525 /6526 epld clock source pt7a4401 hdlc pt7a6525 /6526 at89c51 pc supervisor epld clock source pt7a4401 lvds figure 2. hdlc data format g a l f s s e r d d a 1 d l e i f s s e r d d a 2 d l e i f l o r t n o cn o i t a m r o f n ic r cg a l f figure 1. functional block diagram of demonstration system
4 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) figure 3. overview of demonstration board for pt7a6525/6526 lvds driver interface for hdlc serial link power plug reset key rs232 interface dut(PT7A6526) jmp power switch
5 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) pt7a6525/PT7A6526 pt7a6525/6526 is the key part in this system. its func- tions are introduced in the following paragraphs. the demonstration system can operate in the different clock modes. these operation modes are changeable by revising epld and rewriting the register contents of pt7a6525/6526. for clock mode 1, master clock (4.1mhz) is applied to rxclk, transmission strobe signal is applied to txclk, receive strobe signal is applied to axclk. the binary data ?10011001? should be written into channel con- figuration register 1 (ccr1). thus txd pin is a push- pull outputs; continuous flag sequence (?01111110? pat- tern) is output during the interframe fill. data rate up to 8.192mhz can be performanced via modifying epld. for clock mode 3, master clock(4.1mhz) is applied to rxclk, this mode is an asynchronous communication, it can recover the receive clock from the received data stream. ccr1 register should be initialized as ?10011011?. figure 4. wave diagram in clock mode 5 rxclk axclk txclk txd for clock mode 5, master clock(4.1mhz) should applied to rxclk, a frame sync signal(8khz) is applied to axclk. ccr1 should be initialized as ?10011101?, and tio bit in channel configuration register 2 should be set. in clock mode 5, one of up to 64 time-slots can be pro- grammed independently for transmit and receive direc- tions via transmit time-slot assignment register (ttsa) and receive time-slot assignment register (rtsa). the time-slot width (1 to 256 bit) of receive and transmit di- rections can be programmed via transmit channel capac- ity register and receive channel capacity register. but transmit and receive location with respect to the frame synchronization signal is decided by the combination of ttsa, rtsa and ccr2 (details see datasheet), i.e., start of transmit and receive are delayed with respect to the frame synchronization signal by programming ttsa, rtsa and ccr2 registers. when tio in ccr2 is set, txclk output (active low) indicates transmit time-slot. figure 4 shows link signal timing in clock mode 5.
6 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) principle of demo system pc transmits address/data message of registers to the at89c51 via rs232 serial interface, and then at89c51 writes these data to the registers or xfifo of pt7a6525 according to the instructions from pc, thus pt7a6525 can be initialized indirectly, and the information is sent to oppo- site hdlc via hdlc. in turn, the local computer can receive message from the opposite computer. the link operation principle is described in the following paragraphs. there are several link operation modes-- auto mode, non- auto mode, transparent mode, extended transparent mode. the operation mode is selected via initializing bit ?mds1, mds0 and adm? in mode register (mode) of pt7a6525. auto-mode when mds1 mds0 adm = 000, it is in auto mode with 8-bit address field recognition, i.e., the first received ad- dress field is compared with register ral1 (receive ad- dress low 1) and ral2 (receive address low 2). if the address is recognized as valid, this frame information will be accepted. when mds1 mds0 adm = 001, it is in auto mode with 16-bit address field recognition, i.e., the first re- figure 5. frame format in auto mode ceived address field is compared with register rah1 (receive address high), rah2 and the fixed values #feh #fch, the second address field is compared with register ral1 and ral2. only the information with valid address will be accepted. when transmitting i-frame, the address field transmis- sion is implemented via register xad1 (transmit ad- dress 1) and register xad2 (transmit address 2). when transmitting transparent-frame, the address field transmission is implemented via xfifo. the control field is generated automatically. i-frame is transmitted via xif in command register (cmnd), bit xtf of cmnd can also initiate transmitting transparent frame in auto mode. figure 5 shows frame format in auto mode. non-auto mode when mds1 mds0 adm = 010, it is in non-auto mode with 8-bit address field recognition. when mds1 mds0 adm = 011, non-auto mode with 16-bit address field recognition. the address recognition ways are the same as in auto mode except that the transmit address is implemented via xfifo (the first and second address fields). in non-auto mode, only transparent frame is transmit- ted. figure 6 shows frame format in non-auto mode. g a l f s s e r d d a 1 d l e i f s s e r d d a 2 d l e i f l o r t n o cn o i t a m r o f n ic r cg a l f g a l f 1 l a r 2 l a r l l u n o f i f r r c h r n o i t a m r o f n ic r cg a l f g a l f 1 h a r 2 h a r 1 l a r 2 l a r o f i f r r c h r n o i t a m r o f n ic r cg a l f mds1 mds0 adm = 000 mds1 mds0 adm = 001
7 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) figure 6. frame format in non-auto mode transparent mode when mds1 mds0 adm = 100, it is in transparent mode without address recognition. when mds1 mds0 adm = 101, it is in transparent mode with high address recognition, i.e., the first re- ceived address field is compared with rah1 and rah2 values. only the frame with valid address will be ac- cepted. figure 7 shows the frame format in transparent mode figure 8 shows the transparent frame format in non-auto mode and transparent mode. xtf in command register initiates the transmission. figure 7. frame format in transparent mode clock modes pt7a6525/6526 has 8 clock modes: clock mode 0, clock mode 1, clock mode 2, clock mode 3, clock mode 4, clock mode 5, clock mode 6 and clock mode 7. they require different clock sources and control sources (strobe signal). clock mode 0, clock mode 1 and clock mode 5 are mainly applied to the high data rate communication system. these clock modes need a complex circuit configuration. clock modes 2, 3, 4, 6 and 7 are mainly applied to the low data rate communication systems. these clock modes need a simple circuit configuration . this application note describes applications of clock mode 1, clock mode 3 and clock mode 5. g a l f s s e r d d a 1 d l e i f s s e r d d a 2 d l e i f l o r t n o cn o i t a m r o f n ic r cg a l f g a l f 1 l a r 2 l a r l l u n o f i f r r c h r n o i t a m r o f n ic r cg a l f g a l f 1 h a r 2 h a r 1 l a r 2 l a r o f i f r r c h r n o i t a m r o f n ic r cg a l f mds1 mds0 adm = 010 mds1 mds0 adm = 011 g a l f s s e r d d a 1 d l e i f s s e r d d a 2 d l e i f l o r t n o cn o i t a m r o f n ic r cg a l f g a l f 1 l a r o f i f r o f i f r r c h r o f i f r n o i t a m r o f n i c r c o f i f r c r c a t s r g a l f g a l f 1 h a r 2 h a r 1 l a r o f i f r o f i f r r c h r n o i t a m r o f n i c r c o f i f r c r c a t s rg a l f mds1 mds0 adm = 100 mds1 mds0 adm = 101
8 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) . figure 9. transmitted i-frame format in auto-mode ? clock mode 1 when in clock mode 1, rxclk must be connected to an external clock source, txclk to a transmission strobe sig- nal and axclk to a receive strobe signal. this mode can be applied in time division multiplex applications or ad- note: 1. pu = 0, power down (standby); pu = 1, power up (active). 2. sc1 sc0 = 00, nrz data encoding; sc1 sc0 = 10, nrzi data encoding; sc1 sc0 = 01, bus configuration, timing mode 1; sc1 sc0 = 11, bus configuration, timing mode 2. 3. ods = 0, txd pins are open drain outputs (when in bus configuration); ods = 1, txd pins are push-pull outputs. 4. itf/oin: interframe time fill/one insertion 5. cm2 cm1 cm0: clock mode selection, 000 - clock mode 0; 001 - clock mode 1; ...; 111 - clock mode 7. g a l f s s e r d d a 1 d l e i f s s e r d d a 2 d l e i f l o r t n o cn o i t a m r o f n ic r cg a l f g a l f s s e r d d a o f i f x s s e r d d a o f i f x l o r t n o c o f i f x n o i t a m r o f n i o f i f x g a l f figure 8. transmitted transparent frame format in non-auto mode and transparent mode . g a l f s s e r d d a 1 d l e i f s s e r d d a 2 d l e i f l o r t n o cn o i t a m r o f n ic r cg a l f g a l f s s e r d d a 1 d a x s s e r d d a 2 d a x l o r t n o c o t u a n o i t a m r o f n i o f i f x g a l f 7 t i b6 t i b5 t i b4 t i b3 t i b2 t i b1 t i b0 t i b u p1 c s0 c ss d on i o / f t i2 m c1 m c0 m c justing disparate transmit and receive data rate configura- tion. maximum frequency of rxclk is 8.192mhz. it is a synchronous communication. when txclk and axclk are not used, they must be tied to vcc. the ccr1 (channel configuration register 1) determines which clock mode is chosen. each bit of ccr1 is defined as figure 10 (details sees data sheet of pt7a6525/6526). figure 10. bit definition of ccr1
9 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) ? clock mode 5 in clock mode 5, main clock (rxclk) and frame syn- chronizing signal (axclk) need be supplied. this mode is mainly used in synchronous communication system. the maximum data rate is 4.1mb/s. the transmission time-slot and receive time-slot are programmable. so it can be ap- plied in time-slot oriented pcm system. hardware principle communication between pc and at89c51 the computer and at89c51 communicate with each other via rs232. figure 11 shows the schematic diagram. max232 is a level transfer and drive circuit for rs232 interface. it includes dc/dc internally. to use max232cpe, c3, c4, c5 and c6 are 1uf respec- tively; to used max232a or max202, c3, c4, c5 and c6 are 0.1uf respectively. ? clock mode 3 pt7a6525/6526 offers the advantage of recovering re- ceive clock from the received data stream by internal dpll circuitry, thus no additional clock information needed via the serial link. in clock mode 3, the receive and the transmit clock sources come from dpll. dpll?s reference source comes from rxclk. thus baud rate factor is set as ?1?, rxclk di- vided by 16 is data rate, and the receive station and the transmit station may have no phase relationship. this is an asynchronous communication. the maximum data rate is 1.2mbits/s (rxclk = 19.2mhz). when the clock is generated internally, the device can op- erate in the other clock mode, such as clock mode 6 and clock mode 7. the internal clock is generated by connect- ing a crystal between pin axclka and pin rxclka. both channel a and channel b adopt axclka and rxclka for crystal connection. figure 11. schematic diagram of microprocessor and at89c51
10 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) ? rs232 serial communication interface mode setting: computer (pc) sets com1 or com2 11-bit format per frame as shown in figure 12. figure 12. serial frame format computer (pc) sets com baud rate to 19200. data are received in either interrupt way or inquiry way, i.e., acknowl- edging interrupt signal or inquiring status register. computer reads/write the data from/to the receive/transmit buffer . ? at89c51 serial communication interface mode setting: the serial data format is the same as that of rs232 by setting the a t89c51?s scon register and making serial interface in operation mode 3. baud rate is implemented by setting timer 1. set timer 1 in its operation mode 2 (auto- load time constant). to generate 19200bps(baud rate), an 11.0592mhz crystal oscillator is adopted, and time constant value is fdh (fdh is written to th1 and tl1). at89c51 adopts interrupt way or inquiry way to read the data from rs232 interface, i.e., it accepts buffer full interrupt or inquires ri (if receive buffer is filled) to start data reading. at89c51 serial interface scon and timer 1 are set by the following program: mov tmod, #20h ; set timer as time mode 2 mov pcon,#80h ; mov tl1, #0fdh ; load time constant mov th1, #0fdh setb tr1 ;start timer mov scon, #0d0h ;set serial interface mode 3 t i b t r a t sa t a d t i b - 8t i b y t i r a pt i b d n e
11 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) interface between at89c51 and hdlc(pt7a6525) figure 13 shows connection between at89c51 and pt7a6525. /cs pin of the pt7a6525 is connected to p20 pin of the at89c51, so that the register and fifo address of the pt7a6525/6526 is from 100h to 1ffh, namely the original register address of the pt7a6525/6526 plus 100h. for example, original address 6fh turns out 16fh (6fh+100h). on the demo board, the /cs of the pt7a6525/6526 is connected to ground, so its address is the same as the original address in the data sheet. connecting im1 to ground, the cpu interface of pt7a6525/6526 will operate in intel bus mode. if data transfer is performed in interrupt mode, an in- terrupt signal will be sent to at89c51 by pt7a6525. at89c51 reads the interrupt status register and finds out the cause of the interrupt, then the interrupt service pro- gram in at89c51 will accomplish the data transfer re- quested by pt7a6525. figure 13. connection between pt7a6525/6526 and cpu figure 14. interrupt status register assignment rme rpf rsc xpr tin rme rpf rsc xpr tin ica exa exb xmr xdu pce rfo csc rfs xmr xdu pce rfo csc rfs ista channel a exir channel b
12 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) the data transmission and receive are executed by inquir- ing star and rsta registers. the details of bit functions of the star in application are explained as follows. xdov : when xdov = 1, transmit data overflow, i.e., more than 32 bytes have been written into xfifo and cause data loss. xfw : when xfw = 1, xfifo is empty and data can be written into xfifo. xrnr : it indicates the status of hdlc: 0 - receiver ready; 1 - receiver not ready (valid in auto mode only). rrnr : it indicates the status of the remote station: 0 - receiver ready; 1 - receiver not ready (valid in auto mode only). rli : when 1, it indicates neither flags as interframe time fill nor frames are received via the receiver. cec : when 0, no command is currently executed and the cmnd register can be written; when 1, a command is currently executed, no more command can be writ- ten at present via cmnd register. this bit is mainly used to query if the current command is executed. cts : when the cie bit in ccr2 is set, this bit indicates the state of cts pin: 0 - high level at cts pin, inactive; 1 - low level at the cts pin, active. wfa : when 1, indicates waiting for acknowledgment status. xdov xfw xrnr rrnr rli cec cts wfa more details of rsta register can be found in datasheet of pt7a6525/6526. the functions of rsta register are explained as fol- lows: this register is mainly used to judge validity of current received frame, overflow of receive data, crc check/ comparison, abortion of received message. if abortion is identified, this frame will be discarded by the cpu. in address recognition mode, it can indicates if the valid address is detected. when a frame has been received, the rsta should be read to determine this frame is valid or invalid. demo board figure 15 is the block diagram of the demo board. it is possible to adapt the demo system to a selected operation mode by setting up proper hardware con- nection and revising the epld, including such opetation modes as clock modes, strobe signals and cpu interfaces. by appending delay gates to epld, it can offer vari- ous signals for pt7a6525 to realize various setup and hold time, thus the tolerance of setup time and hold time can be measured. the logic diagram of at89c51 and pt7a6525 interfacing to the epld is illustrated in appendix d.
13 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) software functions in order to debug pt7a6525 easily, pc can be arranged to control at89c51 in the demo system. as pc can read/ write all the registers of pt7a6525/6526 indirectly via rs- 232 interface, the contents of registers can be directly dis- played on screen of pc. it is possible to set various opera- tion modes by writing the registers of pt7a6525, simulta- neously, epld can be modified. appendix c is a pc program flow diagram . its operation is depicted in chapter ?operational guide of demo sys- tem? in the following pages. appendix b is an at89c51 supervisory program . its main function is to receive control information from pc and trans- mit information from pt7a6525/6526 to pc. thus it can make control over pt7a6525/6526 according to pc?s in- structions. cpu epld epld clock at89c51 epld7128 pt7a6525 p0 p2 con a/d bus d0-d7 a0-a6 con pt7a4401 epld7128 rxd txd pi90lv031 lvds ref pi90lv032 figure 15. block diagram of demo board the functions of the pc programs are as follows: 1. select operation modes by rewriting the register contents. 2. write transmitted information to transmit fifo. 3. write command to cmnd register for resetting transceiver and starting information transmission. 4. read register contents for arranging pt7a6525 /6526. 5. read rfifo. 6. transmit/receive information to/from hdlc (pt7a6525/ 6526).
14 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) operational guide of demo system hardware configuration two boards can communicate with each other in the demo system, they are completely identical. to operate it, jumper(jmp) must be set on the demo board, it decides which board supplies reference clock as system synchro- nous clock, thus only one board is set as master station, the other one is set as slave station. how to connect the demo boards figure 16 shows how to connect the demo system. the computer can exchange information with the other computer via com1,com2 and demo board. note: plugging or unplugging the connector to pc with power-on may cause damage to system. each demo board has a rs232 9-pin connector. the pin definition is as follows: pin 2: txd pin 3: rxd pin 5: gnd the pin definition of the connector on demo board is the same as a dce. if the demo board is connected to a 9-pin connector of the com1 or com2 port of pc, the pin connection between the pc and the demo board is as follows: pc port demo board connector pin 2 pin 2 pin 3 pin 3 pin 5 pin 5 if the port of pc is a 25-pin connector, the pin connec- tion is as follows: pc port demo board connector pin 2 pin 3 pin 3 pin 2 pin 7 pin 5 figure 16. demo system connection block diagram for single pc or dual pcs pc-1 demo board 1 demo board 2 powe r suppl y (t ser rser refclk) rs-232 rs-232 com1 com2 flat wire idc20 pt p e rico m t e ch n o lo g y i n c. pt p e rico m t e ch n o lo g y i n c. pc-2 com1 com2 * * : this wire is used for single pc way without pc-2
15 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) idc20 connector between two demo boards two demo boards are connected with each other by an idc20 flat wire. the idc20 connector transfers refer- ence clock and txd/rxd data between the two demo boards in lvds level. when a pair of connectors are connected by flat wire, the pin 1 of one connector must be connected to the pin 20 of the other connector, and pin 2 to pin 19, etc. idc20 pins configuration: power connector the power connector is to connect ground and +5v power supply. the pins? mark can be found on the board near to the connector. reset button reset button is used to reset the demo board. when press reset button, at89c51 and pt7a6525/6526 will be reset, and at89c51 will initialize pt7a6525/6526 registers. this process can be found in the program of at89c51. pt7a6525 is operated in clock mode 1 and transparent mode 0, pt7a6525/6526 is at power-up, nrz encoding state. txd pins are push-pull outputs. all mode can be verified via reading ccr1 ccr2 mode register etc. to test more modes of pt7a6525/6526, the registers should be setup manually and epld need be setup again. the user can change the contents of registers by demo pro- gram. 2 n i p d n a 1 n i pt u p n i e c n e r e f f i d b d x r 4 n i p d n a 3 n i pt u p n i e c n e r e f f i d k l c f e r 7 n i p 6 n i p 5 n i p 4 1 n i p 3 1 n i p 8 n i p 6 1 n i p 5 1 n i p d e v r e s e r 0 1 n i p 9 n i p 2 1 n i p 1 1 n i p d n u o r g 8 1 n i p d n a 7 1 n i pt u p t u o e c n e r e f f i d k l c f e r 0 2 n i p d n a 9 1 n i pt u p t u o e c n e r e f f i d b d x t master station or slave station. master station supplies system reference clock, slave station recover synchro- nous clock via reference clock. j-a single board loop mode note: when single board operates in loop mode, jmp must be set as j-a; when two boards communicate with each other, jmp must be set as j-b and j-c. jmp jmp j-b two boards master station jmp j-c two boards slave station jumper jumper function it is set as j-a or j-b for adapting
16 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) software in general, operation flow is as follows: 1) select hardware setup to adapt to desired clock mode. 2) initialize registers of the pt7a6525/6526 (select de- sired operation mode). 3) read the interrupt status register (decide what to do next after current status). 4) write data to xfifo. 5) write command to cmnd register (optional). 6) read interrupt status register (judge if receive and transmit completed) (optional). 7) read rfifo (optional). main menu after connecting the demo system according to figure 16, run file ?demo6525.exe ?, it is for windows 98. figure 17 shows main menu. in order to make connection between pc and demo board. at first, click ?connection? button, connection result will be shown on screen. figure 18 shows connection information. if connection has error, press swrst key on demo board, and then retry connection. now you can control pt7a6525/6526 via clicking the different button on the main menu. click button ?write register?, all the writable register will be shown on screen, and initial contents will be shown simultaneously. figure 19 shows write register window.
17 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) figure 17 main select item menu figure 18 connection between pc and demo board note: re-write cpu speed according to your pc?s cpu type.
18 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) now you can control pt7a6525/6526 via click different buttons on the main menu. write register click button ?w rite register? will display all the writable registers . figure 19 shows write register window. the register contents displayed is the same as initializa- tion contents when reset demo board. write register operating flow: 1. click option button on the left of register to be written. 2. modify the content of the register. 3. select board no.(board 1 or board2) 4. click write button, finish the writting process. figure 19. write register window note: data to be written is hex format
19 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) click ?wr data? button will switch to w rite xfifo window, figure 20 shows the writting xfifo windows. in the window, it can write information to xfifo. up to 31-bytes can be written to xfifo. figure 20. write xfifo window write xfifo its writting flow is as the following: 1. write information to textbox 2. click option button to select board no. 3. click transmit button, finish writting xfifo process. its writting flow is shows as the following: 1. write address of register 2. write the content of register 3. select board no. 4. click write button to finish writting process.
20 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) write command register any writable register can be written in this window. the default is b-channel?s cmdr, transmit the last information. figure 21 shows write register window figure 21 write command register
21 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) read register content all readable registers can be shown in this window. star rsta and ista are usually read in operation, their contents can decide the next step. figure 22 shows read register window read register flow is shown as the following 1. click option button for selecting board no (1,2) and channel no(a,b. a for only pt7a6525) 2. click read button to finish read register process. figure 22. read register content
22 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) read rfifo click rd fifo button, figure 24 will be shown . to read rfifo when ista and rsta indicate rfifo has been filled, the contents of rfifo can be read. note 1: ista is the channel?s interrupt status register, its content includes the information about receiving interrupt, such as reaceive message end, receive pool full and so on. its format is hex, hex(91)=binary(10010001). note 2: reading ista resets ista. note 3: rbcl is receive byte counter low 8-bit. it indicates message length in rfifo, its format is hex too, hex(17)=decimal(23), thus there are 23 characters received in rfifo. read rfifo flow is shown as follows: 1. click option button to select receiving board no(1,2) and channel no(a,b). when two boards communicate each other, the receiving channel is b_channel. when single board loops, the receiving channel is a-ch. 2. click read button to start reading rfifo. figure 24. read rfifo
23 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) setup hardware configuration of a clock mode function description figure 25 shows set hardware window click button ?set m-1?, set hardware configuration as clock mode 1, and simultaneously modify ccr1?s content for meeting with clock mode 1. this result can be verified via read register. click button ?set m-3?, set hardware configuration as clock mode 3, and simultaneously modify ccr1?s content for meeting with clock mode 3. this result can be verified via read register. clock mode 3 can illus- trate clock abstract function via dpll of pt7a6525. click button ?set m-5?, set hardware configuration as clock mode 5, and simultaneously modify ccr1?s content for meeting with clock mode 5. this result can be verified via read register. clock mode 5 is mainly aplied in oriented-pcm tdm system.it can transmit any bits up to 256 in any one of 64 time slot. it is possible to re-write several registers-rccr/tccr/ rtsa/ttsa for meeting with time slot and channel capacity. figure 25. set hardware configuration note:1. when only one serial communication, one board can perform simple demo, here b-ch transmits information, a-ch receives information. so this configu- ration is very suitable for verifying control register function. note 2. the board connected to com1 is defined as board 1. the board connected to com2 is defined as board 2.
24 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) examples example 1 connecting pc to demo board 1. press ?swrst? key on the demo board; 2. click button ?connection? on main menu; 3. demo program can automatically identify com1 or com2 interface, and the connection information will be shown on the screen. example 2 auto demo (note 1) this process is that pt7a6525 b_channel transmits the data, pt7a6525 a_channel receives data from b_channel, jmp is set at single board loop mode. operation flow is as follows: 1. click button ?auto_demo? to begin auto_demo process; 2. click button ?set m-1? ?set m-3? or ?set m-5? for selecting clock mode, this process will automatically set hardware and register with repect to clock mode, click button ?next? to next step; 3. write the data( you are welcome) to xfifo in textbox, then click button ?transmit? to start writing xfifo, click button ?next? to next step; 4. read register to know the status of pt7a6525, select channel a or channel b, click button ?read?, analyze the contents of ccr1, mode, ista etc. click button ?next? to next step; 5. write command register to initiate transmitting, default ?0a? is to transmit complete transparent frame, click button ?write? to begin transmitting, click button ?next? to next step. 6. read the data from rfifo, click button ?read? to show the contents of rfifo on screen, the contents of rfifo should be the string ?you are welcome?. click button ?finish? to return. example 4 two boards communication on one pc board 1 and board 2 are separately connected to com1 and com2, and jumper meets note 2. software operating flow is similar to example 3. 1. click button ?set hardware mode? to select clock mode, board 1 and board 2 have identical clock mode; 2. board 1 writes data(you are welcome) to xfifo of channel_b. 3. board 1 writes command(0a) to cmdr of channel_b, start transmitting a complete transparent frame. 4. board 2 reads rfifo of channel_b, the string ?you are welcome? will be shown on screen. note: 1 when the demo system is operated in single board loop mode, jumper(jmp) should be set as follows: note 2 when two demo boards communicate with each other, jumpers(jmp) is set as follows: master slave example 3 two pcs communication with each other each board is separately connected to com1 or com2 on the difference pc. (note 2) software operating flow is similar to example 2. 1. click button ?set hardware mode? to select clock mode; 2. pc1 writes data(you are welcome) to xfifo of channel_b. 3. pc1 writes command to cmdr, start transmit ting. 4. pc2 reads rfifo of channel_b, the string ?you are welcome? will be shown on screen.
25 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) appendix a clock modes and cpu interface connection figure 26 shows epld connection between pt7a6525 and at89c51. figure 27 shows clock source connection for clock mode 1, where txd strobe signal (high active) and rxd strobe signal (high active) are both tied to high. figure 26. cpu interfacing with epld logic
26 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) figure 28 shows clock source connection for clock mode 3. in clock mode 3, transmission clock and receive clock come from dpll in pt7a6525/6526. the baud rate generator in pt7a6525/6526 supplies reference clock to dpll. refer to figure 28a and figure 28b. when baud rate factor is set to 1, transmission and receive data rate will be 1/16 rxclk. for example, if rxclk is 8.192mhz, data rate is 512kbit/ s. figure 28a. block diagram of clock signal direction rxclk baud rate generator digital phase locked loop receive data transmit clock receive clock figure 27. clock source connection for clock mode 1 figure 28b. clock source connection for clock mode 3
27 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) figure 29 shows clock source connection for clock mode 5. figure 29. clock source connection for clock mode 5.
28 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) appendix b: demo program flow diagram on pc start display the main menu user selection select demo board select register input content select demo board input data select demo board input content of cmdr select demo board display the content of all the registers select demo board read data byte count display data in rfifo loop begin write data to xfifo of board 1 read data from rfifo of board 2 write data to xfifo of board 2 read data from rfifo of board 1 cycle end (if select "back") select clock mode change 6525 6526 register s about clock mode exit end reset connection write register write data to xfifo write data to demo board write command to cmdr read register content read rfifo content setup hardware for differen t clock mode two boards transmit and receive
29 application note pt7a6525/6526 demo board ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||| mk-017a(06/00) notes pericom technology inc. email: support@pti.com.cn china : no. 20 building, 3/f, 481 guiping road, shanghai, 200233, china tel: (86)-21-6485 0576 fax: (86)-21-6485 2181 asia pacific : unit 1517, 15/f, chevalier commercial centre, 8 wang hoi rd, kowloon bay, hongkong tel: (852)-2243 3660 fax: (852)- 2243 3667 u.s.a. : 2380 bering drive, san jose, california 95131, usa tel: (1)-408-435 0800 fax: (1)-408-435 1100 pericom technology incorporation reserves the right to make changes to its products or specifications at any time, without noti ce, in order to improve design or performance and to supply the best possible product. pericom technology does not assume any responsibility fo r use of any circuitry described other than the circuitry embodied in pericom technology product. the company makes no representations that circuitry described herein is free from patent infringement or other rights, of pericom technology incorporation.

▲Up To Search▲

Price & Availability of PT7A6526

	To Download PT7A6526 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .