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? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 1/21 ? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 single chip codec general description the msm6996h/msm6996v/MSM6997H/msm6997v/msm6998/msm6999 are a single-channel codec cmos ics containing filters for a/d and d/a converting of the voice signal ranging from 300 hz to 3400 hz. features ? compliance with itu-t companding law msm6996h/msm6996v/msm6998 : a-law MSM6997H/msm6997v/msm6999 : m -law ? capable of independent operation of transmission and reception ? transmission clock in the range of 64 khz to 2048 khz ? adjustable transmit gain ? 600 w drive for analog output msm6996h/msm6996v/MSM6997H/msm6997v single end drive msm6998/msm6999 push-pull drive ? built-in analog loop back fanction msm6996v/msm6997v ? built-in reference voltage source ? low power dissipation (60 mw to 70 mw typ.) ? package options : 16-pin plastic dip (dip16-p-300-2.54) (product name : msm6996hrs/MSM6997Hrs) (product name : msm6996vrs/msm6997vrs) (product name : msm6998rs/msm6999rs) 16-pin cer dip (dip16-g-300-2.54-1) (product name : msm6996has/MSM6997Has) (product name : msm6996vas/msm6997vas) (product name : msm6998as/msm6999as) 24-pin plastic sop (sop24-p-430-1.27-k) (product name : msm6996hgs-k/MSM6997Hgs-k) (product name : msm6996vgs-k/msm6997vgs-k) (product name : msm6998gs-k/msm6999gs-k) e2u0010-28-81 this version: aug. 1998 previous version: nov. 1996
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 2/21 block diagram C + msm6996h/v MSM6997H/v ain+ ainC gsx v dd v ss ag + C aout xsync xclock pcmout rclock rsync pdn/bs pcmin voltage ref. 5th lpf 3rd hpf auto zero c ladder sar receive controller transmit controller r.pwd comp sample 5th lpf C + msm6998, msm6999 ain+ ainC gsx v dd v ss ag + C aout+ voltage ref. pre filter 5th lpf 3rd hpf auto zero sar comp sample 5th lpf C + aoutC transmit pll receive pll t.pwd *1 dg tmc *2 r r dg xsync xclock pcmout rclock rsync pdn/bs pcmin receive controller transmit controller r.pwd transmit pll receive pll t.pwd *3 * 1 bs : only MSM6997H/v * 2 only msm6996v, msm6997v * 3 bs : only msm6999 pre filter c ladder c ladder c ladder
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 3/21 16-pin plastic dip msm6996hrs MSM6997Hrs 16-pin plastic dip msm6996vrs msm6997vrs 16-pin plastic dip msm6998rs msm6999rs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ain+ ainC gsx ag aout nc v dd pcmin v ss pcmout pdn/bs dg xsync xclock rclock 16-pin cer dip msm6996has MSM6997Has 16-pin cer dip msm6996vas msm6997vas 16-pin cer dip msm6998as msm6999as rsync 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ain+ ainC gsx ag aout tmc v dd pcmin v ss pcmout pdn/bs dg xsync xclock rclock rsync 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ain+ ainC gsx ag aout+ aoutC v dd pcmin v ss pcmout pdn/bs dg xsync xclock rclock rsync 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ain+ ainC gsx ag aout nc v dd pcmin v ss pcmout pdn/bs dg xsync xclock rclock rsync ain+ ainC gsx ag aout tmc v dd pcmin v ss pcmout pdn/bs dg xsync xclock rclock rsync ain+ ainC gsx ag aout+ aoutC v dd pcmin v ss pcmout pdn/bs dg xsync xclock rclock rsync pin configuration (top view) nc : no connect pin nc : no connect pin
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 4/21 24-pin plastic sop msm6996hgs-k MSM6997Hgs-k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ain+ ainC gsx ag aout v ss pcmout pdn/bs dg xsync rsync 24-pin plastic sop msm6996vgs-k msm6997vgs-k v dd pcmin xclock rclock 24-pin plastic sop msm6998gs-k msm6999gs-k ag 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ain+ ainC gsx ag aout tmc v ss pcmout pdn/bs dg xsync rsync v dd pcmin xclock rclock ag 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ain+ ainC gsx ag aout+ aoutC v ss pcmout pdn/bs dg xsync rsync v dd pcmin xclock rclock ag nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc : no connect pin nc : no connect pin nc : no connect pin
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 5/21 pin and functional descriptions ain+, ainC, gsx these three pins are used for the transmit level adjustment. ain+ is a non-inverting analog input pin which is connected to the non-inverting input of a transmit amplifier. ainC is an inverting analog input pin which is connected to the inverting input of the transmit amplifier. gsx is a transmit amplifier output pin. adjustment can be done by following method. r2 + C ainC gain = 1 + ain+ gsx rc active filter analog input r3 r1 c1 r2 r3 ag < 10 notes: 1. r 2 + r 3 > 10 k w 2. when the dc off-set voltage of analog input is more than 20 mv, c1 and r1 should provide for dc blocking. in this case, cut-off frequency of hpf, composed by r 1 and c 1 , should be less than 30 hz. 3. r 1 should be less than 20 k w ag ag is an analog ground. ag is connected to the analog system ground. aout aout is the analog signal output pin for the msm6996h/v and MSM6997H/v. the output voltage range is 5 v pp . this output can drive the 600 w resistor. aout+, aoutC analog output for the msm6998 and msm6999. the output signal amplitudes are 5 v pp . the aoutC output is inverted to the aout+ output. these outputs can drive a 600 w impedance. v dd v dd is the positive power supply. the voltage supplied to this pin should be +5 v 5%.
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 6/21 pcmin pcm signal input. the serial input pcm signal is converted from digital to analog, synchronizing with the synchronous signal rsync and clock signal rclock. the data rate of pcm signal ranges from 64 kbps to 2048 kbps. the pcm signal is read at the falling edge of the clock signal and latched into the internal register when finished to read eight bits data. the top of the pcm data is specified by rsync pulse timing. rclock receive clock pulse input. the frequency of this clock pulse should be identified with the data rate of pcm input signal at the pcmin pin. this rclock signal can be a continuous clock or a burst clock with nine bits or more. in the case of a burst clock, input the following timing. xclock transmit clock input. the pcm output data rate from the pcmout pin is set by this clock frequency. the applicable clock frequencies range from 64 khz to 2048 khz. this xclock signal can be a continuous clock or a burst clock with nine bits or more. in the case of a burst clock, input the following timing. 1234567 89 msd d2 d3 d4 d5 d6 d7 d8 pcmout xclock xsync 9 clocks are required 1234567 89 msdd2d3d4d5d6d7d8 pcmin rclock rsync 9 clocks are required
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 7/21 rsync receive synchronizing signal input. eight required bits are selected from serial pcm signals on the pcmin pin by the receive synchronizing signal. the whole timing signal in the receive section are synchronize by this synchronizing signal. this signal must be synchronize in phase with rclock. the frequency should be 8 khz 50 ppm to guarantee the ac characteristics of receive section. however, same as the rclock frequency, this device can operate in the range of 8 khz 2 khz, with no guarantee of adherence to the electrical characteristics in this specification as a catalogue value. fixing this signal to logic "1" or "0", the receive circuit is driver in a power down state. xsync transmit synchronizing signal input. the pcm output signal from the pcmout pin is output in synchronization with this transmit synchronizing signal. all transmit timing signals are triggered to synchronize with this signal. this signal should be synchronized in phase with xclock pulse. the frequency should be 8 khz 50 ppm to guarantee the ac characteristics of transmit section. fixing this signal to logic "1" or "0", the transmit circuit is driver in a power down state. dg ground of digital signal. this pin is electrically separated from the ag pin in this device. the dg pin must be connected to the ag pin on the printed circuit board to make common to the ag pin. pdn/bs power down signal input. when this input is held at low level more than 1 ms, the device is put into the power-down mode. pcmout pcm signal output. the pcm output signal is output in synchronization with the rising edge of xclock pulse orderly from msd first. (the first bit of the pcm signal may output at the rising edge of xsync pulse, according to the timing of xsync and xclock pulse.). during the pcmout signal output except the 8-bit pulses, the pin is in an open state, therefore, multiple connections by wired-or are easily possible at this pin. the code companding law and output code format depend on itu-t recommendation g.711, and for the msm6996h, msm6996v, and msm6998 (a-law) the output pcm signals are obtained by inverting the even bits of signals. input/output level +full scale +0 C0 Cfull scale pcmin/pcmout msm6996 (a-law) msm6997 ( m -law) 10101010 11010101 01010101 00101010 10000000 11111111 01111111 00000000 msm6998 (a-law) msm6999 ( m -law)
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 8/21 C + ain aout transmit bpf pcmout pcmin ad recv lpf da C + ag signal flow in normal operating mode signal flow in analog loop-back mode v ss negative voltage power supply. the range of power supply voltage is C5 v 5%. tmc control signal input for mode selection. this pin select the normal operating mode or analog loop-back mode. tmc input mode > 2.0 v normal operation < 0.8 v analog loop-back
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 9/21 absolute maximum ratings recommended operating conditions * : the value for the msm6997 and msm6999 parameter power supply voltage analog input voltage digital input voltage storage temperature symbol v dd v ain v din t stg rating 0 to 7 v dd C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 C55 to +150 unit v v v c v ss C7 to 0 v condition (ta = 0c to 70c) parameter symbol condition min. typ. max. unit power supply voltage analog input voltage v dd v ss v ain input high voltage input low voltage v ih v il connect ainC and gsx xsync, xclock, pcmin, rsync, rclock, tmc, pdn/bs 4.75 5 5.25 v C5.25 C5 C4.75 v 5v p-p 2.0 v dd v 0 0.8 v clock frequency f c xclock, rclock khz sync pulse frequency f s xsync, rsync 8 khz clock duty ratio d l xclock, rclock 40 50 60 % digital input rise time t ir 50 ns digital input fall time t if 50 ns xsync, xclock, pcmin, rsync, rclock (fig. 1) transmit sync timing t xs 50 ns t sx 100 ns xclock ? xsync (fig. 2) xsync ? xclock (fig. 2) receive sync timing t rs 50 ns t sr 100 ns rclock ? rsync (fig. 2) rsync ? rclock (fig. 2) t wx 1/fc m s t wr 1/fc m s transmit sync pulse width receive sync pulse width t ds 100 ns t dh 100 ns pcmin set-up time pcmin hold time t bs 200 ns bs set-up time * t bh 200 ns bs hold time * r al 600 w analog output load c al 100 pf r dl 1k w digital output load c dl 100 pf aout, aout+, aoutC v io C200 +200 allowable analog input offset voltage transmit gain stage, gain = 1 64 2048 mv C20 +20 transmit gain stage, gain = 10 10 k w gsk operating temperature ta c 02570
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 10/21 electrical characteristics dc and digital interface characteristics * : the upper is specified for the msm6996/msm6997 and the lower for the msm6998/msm6999 (v dd = +5 v 5%, v ss = C5 v 5%, ta = 0c to 70?c) parameter symbol condition min. typ. max. unit power supply current power supply current (stand-by) i dd1 i ss1 i dd2 i ss2 input high voltage v ih xclock, rclock 2048 khz 7.0 12 ma 6.5 12 3.0 ma 1.5 2.2 v input low voltage v il v i ih < 0.5 2.0 m a input leakage current i il < 0.2 0.5 output leakage current i oh < 510 m a analog output offset voltage v off C150 0 +150 mv input capacitance c in 5pf r in 1m w f in < 3.4 khz analog input resistance (operating) 0.8 0.1 0.4 v output low voltage v ol * 14 14 *
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 11/21 ac characteristics parameter transmit frequency response symbol l oss t1 level 60 min. 20 typ. max. unit (v dd = +5 v 5%, v ss = C5 v 5%, ta = 0c to 70c) freq. condition l oss t2 300 C0.15 +0.25 l oss t3 820 reference db 0 l oss t4 2020 C0.15 +0.25 l oss t5 3000 C0.15 +0.25 l oss t6 3400 0 0.8 receive frequency response l oss r1 300 C0.1 +0.2 l oss r2 820 reference l oss r3 2020 C0.1 +0.2 db 0 l oss r4 3000 C0.1 +0.2 l oss r5 3400 0 0.8 transmit signal to noise sd t1 36 3 sd t2 36 0 sd t3 36 C30 sd t4 1020 31 db C40 sd t5 26 C45 sd r1 36 3 sd r2 36 0 sd r3 36 C30 sd r4 1020 31 db C40 sd r5 26 C45 (dbm0) (hz) ratio *1 receive signal to noise ratio *1 or or 820 820 transmit gain tracking gt t1 C0.2 +0.2 1020 reference db 3 C0.2 +0.2 C0.4 +0.4 C0.8 +0.8 receive gain tracking gt r1 C0.2 +0.2 gt r2 reference gt r3 1020 C0.2 +0.2 gt r4 C0.4 +0.4 gt r5 C0.8 +0.8 gt t2 gt t3 gt t4 gt t5 C10 C40 C50 C55 3 C10 C40 C50 C55 or or 820 820 db note: *1 the measurement is taken with p-message filter
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 12/21 ac characteristics (continued) parameter symbol level min. typ. max. unit (v dd = +5 v 5%, v ss = C5 v 5%, ta = 0c to 70c) freq. condition idle channel n idl t C75 n idl r C75 t gd t1 0.75 0 500 0.35 ms 0.125 t gd r1 0.75 t gd r2 0.35 t gd r3 0.125 ms t gd r4 0.125 (dbm0) (hz) noise *1 transmit group delay time *3 transmit receive dbmop absolute gain *2 av t C0.5 0 +0.5 0 av r C0.5 0 +0.5 0 1020 or 820 transmit receive db 1020 or 820 t d 0.52 0 ms absolute delay time t gd t2 600 t gd t3 1000 t gd t4 2600 t gd t5 2800 0.75 t gd r5 0.75 500 600 1000 2600 2800 0 receive group delay time *3 0.125 crosstalk attenuation c r t 66 c r r 66 1020 or 820 t to r r to t db 1020 or 820 out-of-band spurious s C30 0 dbmo 300 to 3400 imd 1 C35 C4 dbmo f a = 470 intermodulation distortion f b = 320 v dd noise rejection ppsr t 30 ppsr r 30 transmit receive db v ss noise rejection npsr t 30 npsr r 30 200 transmit receive 0 to 300 mvp-p ratio ratio khz discrimination dis 30 0db 4.6 khz to 72 khz t do 20 100 r dl = 2 k w t sd t xd1 t xd2 t xd3 50 150 300 50 100 300 50 100 300 50 180 300 ns digital output delay time digital output fall time ns c dl = 100 pf notes: *1 the measurement is taken with p-message filter *2 msm6996/msm6998 0 db = 1.231 vrms msm6997/msm6999 0 db = 1.227 vrms *3 reference : 1800 hz
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 13/21 timing diagram wave time measurement level t wx t ir t if t dof 2.4 v 1.4 v 0.4 v note: timing between signal waves is judged at 1.4 v 2.4 v 1.4 v 0.4 v t wr basic timing xclock t xs t xd1 1234567 8910 1234567 8910 t xd2 t xd3 t sx 1/f c t wx t sd msd d2 d3 d4 d5 d6 d7 d8 t rs t sr t wr t ds t dh transmitter section receiver section xsync pcmout rclock rsync note 1): when t xs 1/2 fc, the delay of the msd bit is defined as t xd1 . when t sx 1/2 fc, the delay of the msd bit is defined as t sd . note 2): transmit synchronizing and clock pulse, and receive synchronizing and clock pulse may be asynchronous mutually. note 3): the threshold level is 1.4 v. t ds t dh pcmin d8 d7 d6 d5 d4 d3 d2 msd invalid data figure 1 figure 2
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 14/21 rsync allowable range 8 bits decode 7 bits decode 8 bits decode 12345678 12345678 12345678 123456789 123456789 123456789 disable t bs t bh pcmin rclock bs decoder operation notes: follow these procedures when the bit-steal function is used: 1. set the rsync pin to off ("l") after the pdn/bs pin is set at "h" for 10ms or more. 2. set the rsync to on after a pulse is input at the pdn/bs pin. 3. the bit-steal function starts to operate. more than 10ms ~ rsync pcmin rclk more than 10ms pdn/bs 125 m s ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ timing for 7 bits decode (specified for msm6997/6999) figure 3 timing for bit-steal function setting
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 15/21 application circuit basic circuit notes: 1. insert diode for preventing from latch-up at turn on power. recommended diode specification. ? high speed switching ? allowerable power dissipation 250 mw to 300 mw ? forward voltage drop < 1.3 v (at 100 ma) 2. ag and dg must be connected in the printed circuit board mounted this device, for preventing from latch-up. 2 k w in out x r x r dg ag v ss v dd +C out in C+ pcm analog +5 v note 1 0 v C5 v +5 v power down 1 : nor 0 : power down re c r ec 15109 8721 16 6 +5 v 14 +5 v q4 q4 10 m xtal 2.048 mhz 4049 4049 ain+ aout pdn/bs in out m4520rs gsx ainC 10 m f 10 m f clock sync dg
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 16/21 example of multi-channel connections (8ch) 8 7 no. 12345678 no. 12 3 4 5 6 78 msd lsd q c output q b output q a q b q c q h multiple pcm 512k clk 74161(1) 74161(2) 74164 output example of multi-channel timing ck q a 1 k w +5 v multiple pcm xc pcm out pcm in clr q b e p q c e t q d l o c o 9 10 7 1 2 13 14 12 11 15 ck q a clr q b e p e t l o 9 10 7 1 2 13 14 +5 v 512 khz +5 v 5 6 10 9 11 1 12 2 13 4 9 3 74161(1) 74161(2) 74164 no.7 no.6 no.5 no.4 xs rc rs no.1 no.3 no.8 ck q a q b q c q d q e clr q f a q g bq h +5 v no.2
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 17/21 transmit and receive level adjustment (msm6996h/v, MSM6997H/v) 4ws 600 w ain+ aout a. transformer of turns ratio 1 : 1 1 : 1 600 w 20 k w r1 ag 4wr 600 w 1 : 1 600 w attenuator 600 w 1 2 3 5 ainC gsx 4ws 600 w ain+ aout 300 w 20 k w r1 ag 4wr 600 w 300 w attenuator 300 w 1 2 3 5 ainC gsx b. transformer of turns ratio 1 : 2 2 : 1 2 : 1 4ws 600 w ain+ aout+ 1 : 1 600 w 20 k w r1 ag 4wr 600 w 1 : 1 600 w attenuator 300 w 1 2 3 5 ainC gsx 300 w 6 aoutC transmit and receive level adjustment (msm6998, msm6999) when r1 is open and the attenuator is set at 0 db, 4 ws maximum input level = +7.17 + l t (dbm) 4 wr maximum output level = +1.15 C l t (dbm) l t : transformer loss when r1 is open and the attenuator is set at 0 db, 4 ws maximum input level = +10.18 + l t (dbm) 4 wr maximum output level = +4.16 C l t (dbm) l t : transformer loss when r1 is open and the attenuator is set at 0 db, 4 ws maximum input level = +7.17 + l t (dbm) 4 wr maximum output level = +7.17 C l t (dbm) l t : transformer loss
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 18/21 recommendations for actual design ? to assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. ? connect the ag pin and the dg pin each other as close as possible. connected to the system ground with low impedance. ? mount the device directly on the board when mounted on printed circuit board. do not use ic sockets. if an ic socket is unavoidable, use the short lead type socket. ? when mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. ? keep the voltage on the v dd pin not lower than C0.3 v and the voltage on the v ss pin more than +0.3 v even instantaneously to avoid latch-up phenomenon when turning the power on. ? use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 19/21 (unit : mm) package dimensions dip16-p-300-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.99 typ.
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 20/21 (unit : mm) dip16-g-300-2.54 16 7.50max 2.54 0.80typ 4.10 0.40 5.10max 2.54min 0.51min 1 9 8 0.50 0.10 0.25 m 1.50 0.10 1.00 0.10 20.00max 7.62 +0.15 0.25-0.05 0~15 seating plane
? semiconductor msm6996h/6996v/6997h/6997v/6998/6999 21/21 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). sop24-p-430-1.27-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.58 typ. mirror finish

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