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general description the max5949a/max5949b are hot-swap controllers that allow a circuit card to be safely hot plugged into a live backplane. the max5949a/max5949b operate from -20v to -80v and are well-suited for -48v power systems. these devices are pin and function compatible with the lt4250 and pin compatible with the lt1640. the max5949a/max5949b provide a controlled turn-on to circuit cards preventing glitches on the power-supply rail and damage to board connectors and components. the max5949a/max5949b provide undervoltage, over- voltage, and overcurrent protection. these devices ensure the input voltage is stable and within tolerance before applying power to the load. both the max5949a and max5949b protect a system against overcurrent and short-circuit conditions by turn- ing off the external mosfet in the event of a fault con- dition. the max5949a/max5949b also provide protection against input voltage steps. during an input voltage step, the max5949a/max5949b limit the cur- rent drawn by the load to a safe level without turning off power to the load. both devices feature an open-drain power-good status output (pwrgd for the max5949a or pwrgd for the max5949b) that can be used to enable downstream converters. the max5949a/max5949b are available in an 8-pin so package. both devices are specified for the extended -40? to +85? temperature range. applications telecom line cards network switches/routers central-office line cards server line cards base-station line cards central-office switching -48v distributed power systems negative power-supply controls features allow safe board insertion and removal from a live -48v backplane pin and function compatible with lt4250l (max5949a) pin compatible with lt1640l (max5949a) pin and function compatible with lt4250h (max5949b) pin compatible with lt1640h (max5949b) circuit-breaker immunity to input voltage steps and current spikes withstand -100v input transients with no external components programmable inrush and short-circuit current limits operate from -20v to -80v programmable overvoltage protection programmable undervoltage lockout power up into a shorted load power-good control output max5949a/max5949b -48v hot-swap controllers with external r sense ________________________________________________________________ maxim integrated products 1 gate sense v ee 1 + 2 8 7 v dd drain ov uv pwrgd (pwrgd) so top view 3 4 6 5 max5949a max5949b ( ) for max5949b. pin configuration ordering information 19-3494; rev 1; 8/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max5949a esa+ -40? to +85? 8 so max5949b esa+ -40? to +85? 8 so typical operating circuit and selector guide appear at end of data sheet. + denotes a lead(pb)-free/rohs-compliant package.
max5949a/max5949b -48v hot-swap controllers with external r sense 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v ee = 0v, v dd = 48v, t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted.) (notes 2, 5) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages are referenced to v ee , unless otherwise noted.) supply voltage (v dd - v ee ) .................................-0.3v to +100v pwrgd, pwrgd .................................................-0.3v to +100v drain (note 1)........................................................-2v to +100v pwrgd to drain .............................................?-0.3v to +95v pwrgd to v dd ........................................................-95v to +85v sense (internally clamped) .................................-0.3v to +1.0v gate (internally clamped) ....................................-0.3v to +18v uv and ov..............................................................-0.3v to +60v current through sense ...................................................?0ma current into gate...........................................................?00ma current into drain .........................................-100ma to +20ma current into any other pin................................................?0ma continuous power dissipation (t a = +70?) 8-pin so (derate 5.9mw/? above +70?)..................471mw operating temperature range ...........................-40? to +85? junction temperature .....................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units power supplies operating input voltage range v dd 20 80 v supply current i dd (note 3) 0.7 2 ma gate drive and clamping circuits gate pin pullup current i pu gate drive on, v gate = v ee -30 -45 -60 ? gate pin pulldown current i pd gate drive off, v gate = 2v, t a = +25? 24 50 70 ma external gate drive ? v gate v gate - v ee , 20v v dd 80v 10 13.5 18 v gate to v ee clamp voltage v gsclmp v gate - v ee , i gs = 30ma 15 16.4 18 v circuit breaker current-limit trip voltage v cl v cl = v sense - v ee 40 50 60 mv sense input bias current i sense v sense = 50mv 0 -0.2 -2 a undervoltage lockout internal undervoltage-lockout voltage high v uvloh v dd increasing 13.8 15.4 17.0 v internal undervoltage-lockout voltage low v uvlol v dd decreasing 11.8 13.4 15.0 v uv pin uv high threshold v uvh uv voltage increasing 1.240 1.255 1.270 v uv low threshold v uvl uv voltage decreasing 1.105 1.125 1.145 v uv hysteresis v uvhy 130 mv uv input bias current i inuv v uv = v ee 0-0.5a ov pin ov high threshold v ovh ov voltage increasing 1.235 1.255 1.275 v ov low threshold v ovl ov voltage decreasing 1.210 1.235 1.255 v ov hysteresis v ovhy 20 mv ov input bias current i inov v ov = v ee 0-0.5a note 1: test condition per figure 1. drain current must be limited to the specified 100ma maximum.
max5949a/max5949b -48v hot-swap controllers with external r sense _______________________________________________________________________________________ 3 electrical characteristics (continued) (v ee = 0v, v dd = 48v, t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted.) (notes 2, 5) parameter symbol conditions min typ max units pwrgd output signal referenced to drain drain input bias current i drain v drain = 48v 10 80 250 ? d rain thr eshol d for p ow er - g ood v dl v drain - v ee threshold for power-good condition, drain decreasing 1.1 1.4 2.0 v gate high threshold v gh ? v gate - v gate threshold for power-good condition, ?v gate - v gate decreasing 1.0 1.4 2.0 v pwrgd, pwrgd output leakage i oh pwrgd (max5949a) = 80v, v drain = 48v, pwrgd (max5949b) = 80v, v drain = 0v 10 ? pwrgd output low voltage v ol v pwrgd - v ee ; v drain - v ee < v dl , i sink = 5ma (max5949a) 0.11 0.4 v pwrgd output low voltage v ol v pwrgd - v drain ; v drain = 5v, i sink = 1ma (max5949b) 0.11 0.4 v ac parameters ov high to gate low t phlov figures 2a, 3 0.5 ? uv low to gate low t phluv figures 2a, 4 0.4 ? ov low to gate high t plhov figures 2a, 3 4 ? uv high to gate high t plhvl figures 2a, 4 5.5 ? sense high to gate low t phlsense figures 2a, 5a 1 3 ? current limit to gate low t phlcb figures 2b, 5b 350 500 650 ? max5949a, figures 2a, 6a 1.8 drain low to pwrgd low drain low to (pwrgd - drain) high t phldl max5949b, figures 2a, 6a 3.4 ? max5949a, figures 2a, 6b 1.6 gate high to pwrgd low gate high to (pwrgd - drain) high t phlgh max5949b, figures 2a, 6b 2.5 ? turn-off latch-off period t off (note 4) 51 64 78 ms note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to v ee , unless otherwise specified. note 3: current into v dd with uv = 3v, ov = drain = pwrgd = sense = v ee , gate = open. note 4: minimum duration of gate pulldown following a circuit-breaker fault. the circuit breaker can be reset during this time by toggling uv low, but the gate pulldown does not release until t off has elapsed. note 5: limits are 100% tested at t a = +25? and +85?. limits at -40? are guaranteed by design.
max5949a/max5949b -48v hot-swap controllers with external r sense 4 _______________________________________________________________________________________ typical operating characteristics (v dd = 48v, v ee = 0v, t a = +25?, unless otherwise noted.) supply current vs. supply voltage max5949 toc01 supply voltage (v) supply current ( a) 80 60 40 20 100 200 300 400 500 600 700 800 900 0 0100 t a = +85 c t a = +25 c t a = -40 c gate voltage vs. supply voltage max5949 toc02 supply voltage (v) gate voltage (v) 80 60 40 20 9 10 11 12 13 14 15 8 0100 t a = +85 c t a = -45 c t a = +25 c current-limit trip voltage vs. temperature max5949 toc03 temperature ( c) trip voltage (mv) 60 35 10 -15 47 48 49 50 51 52 53 46 -40 85 gate pullup current vs. temperature max5949 toc04 temperature ( c) gate pullup current ( a) 60 35 10 -15 43.2 43.4 43.6 43.8 44.0 44.2 44.4 44.6 44.8 45.0 43.0 -40 85 v gate = 0v gate pulldown current vs. temperature max5949 toc05 temperature ( c) gate pulldown current (ma) 60 35 10 -15 30 35 40 45 50 55 60 65 70 25 -40 85 v gate = 2v pwrgd output low voltage vs. temperature (max5949a) max5920 toc06 temperature ( c) pwrgd output low voltage (mv) 60 35 10 -15 5 10 15 20 25 30 35 40 45 50 0 -40 85 i out = 1ma pwrgd output impedance vs. temperature (max5949b) max5949 toc07 temperature ( c) output impedance (g ?) 75 25 50 0 -25 10 100 1000 10,000 1 -50 100
max5949a/max5949b -48v hot-swap controllers with external r sense _______________________________________________________________________________________ 5 test circuits 2v 100ma max max5949_ pwrgd/pwrgd ov uv v ee v dd drain gate test voltage sense figure 1. -2v drain voltage test circuit v s r 5k? v ov v uv v+ 5v v sense v drain 48v max5949a max5949b pwrgd/pwrgd ov uv v ee v dd drain gate sense figure 2a. test circuit 1 v s v uv 48v max5949a max5949b pwrgd/pwrgd ov uv v ee v dd drain gate sense n irf530 v s 20v 10k? 10? 0.1f 10? figure 2b. test circuit 2
max5949a/max5949b -48v hot-swap controllers with external r sense 6 _______________________________________________________________________________________ timing diagrams 1.255v ov t phlov 0v 2v 1v 1.235v 1v t plhov gate figure 3. ov to gate timing t phluv 1.125v 1v 1v 1.255v t plhuv uv 0v 2v gate figure 4. uv to gate timing 60mv 1v 100mv gate sense v ee t phlsense figure 5a. sense to gate timing t phlcb 50mv uv gate sense 1v 1v figure 5b. active current-limit threshold
max5949a/max5949b -48v hot-swap controllers with external r sense _______________________________________________________________________________________ 7 timing diagrams (continued) drain pwrgd v pwrgd - v drain = 0v pwrgd drain v ee v ee v ee t phldl 1v 1.4v 1.4v t phldl 1v figure 6a. drain to pwrgd/pwrgd timing ?v gate - v gate = 0v gate pwrgd v ee v ee ?v gate - v gate = 0v gate pwrgd v pwrgd - v drain = 0v 1.4v 1.4v 1v 1v t phlgh t phlgh figure 6b. gate to pwrgd/pwrgd timing logic gate driver 500s delay uvlo v cc and reference generator ref v cc ref v dl v ee v gh ?v gate 50mv v dd uv ov v ee sense gate drain pwrgd pwrgd max5949a max5949b output drive block diagram
max5949a/max5949b detailed description the max5949a/max5949b are integrated hot-swap controllers for -48v power systems. they allow circuit boards to be safely hot plugged into a live backplane without causing a glitch on the power-supply rail. when circuit boards are inserted into a live backplane without hot-swap control, the bypass capacitors at the input of the board? power module or switching power supply can draw large inrush currents as they charge. the inrush currents can cause glitches on the system power-supply rail and damage components on the board. the max5949a/max5949b provide a controlled turn-on to circuit cards, preventing glitches on the power-supply rail and damage to board connectors and components. both the max5949a and max5949b provide undervolt- age, overvoltage, and overcurrent protection. the max5949a/max5949b ensure the input voltage is sta- ble and within tolerance before applying power to the load. the devices also provide protection against input voltage steps. during an input voltage step, the max5949a/max5949b limit the current drawn by the load to a safe level without turning off power to the load. -48v hot-swap controllers with external r sense 8 _______________________________________________________________________________________ pin description pin max5949a max5949b name function 1 pwrgd power-good signal output. pwrgd is an active-low open-drain status output referenced to v ee . pwrgd is latched low when v drain - v ee v dl and v gate > ( ? v gate - v gh ), indicating a power-good condition. pwrgd is open drain otherwise. 1 pwrgd power-good signal output. pwrgd is an active-high open-drain status output referenced to drain. pwrgd latches in a high-impedance state when v drain - v ee v dl and v gate > ( ? v gate - v gh ), indicating a power-good condition. pwrgd is pulled low to drain otherwise. 22o v input pin for overvoltage detection. ov is referenced to v ee . when ov is pulled above the v ovh voltage, the gate pin is immediately pulled low. the gate pin remains low until the ov pin voltage reduces to v ovl . 33u v input pin for undervoltage detection. uv is referenced to v ee . when uv is pulled above the v uvh voltage, the gate is enabled. when uv is pulled below v uvl , gate is pulled low. uv is also used to reset the circuit breaker after a fault condition. to reset the circuit breaker, pull uv below v uvl . the reset command can be issued immediately after a fault condition; however, the device does not restart until a t off delay time has elapsed after the fault. 44v ee device negative power-supply input. connect to the negative power-supply rail. 5 5 sense current-sense voltage input. connect to an external sense resistor and the external mosfet source. the voltage drop across the external sense resistor is monitored to detect overcurrent or short-circuit fault conditions. connect sense to v ee to disable the current- limiting feature. 6 6 gate gate-drive output. connect to the gate of the external n-channel mosfet. 7 7 drain output-voltage sense input. connect to the output-voltage node (drain of the external n-channel mosfet). 88v dd positive power-supply rail input. this is the power ground in the negative-supply voltage system. connect to the higher potential of the power-supply inputs.
board insertion figure 7a shows a typical hot-swap circuit for -48v sys- tems. when the circuit board first makes contact with the backplane, the drain to gate capacitance (c gd ) of q1 pulls up the gate voltage to roughly iv ee x c gd / (c gd + c gs )i. the max5949_ features an internal dynamic clamp between gate and v ee to keep the gate-to-source voltage of q1 low during hot insertion, preventing q1 from passing an uncontrolled current to the load. for most applications, the internal dynamic clamp between gate and v ee of the max5949a/ max5949b eliminates the need for an external gate-to- source capacitor c1. resistor r3 limits the current into the clamp circuitry during card insertion. power-supply ramping the max5949_ can reside either on the backplane or the removable circuit board (figure 7a). power is deliv- ered to the load by placing an external n-channel mosfet pass transistor in the power-supply path. after the circuit board is inserted into the backplane and the supply voltage at v ee is stable and within the undervoltage and overvoltage tolerance, the max5949_ turn on q1. the max5949_ gradually turn on the exter- nal mosfet by charging the gate of q1 with a 45? current source. capacitor c2 provides a feedback signal to accurately limit the inrush current. the value of c 2 can be calculated: where c l is the total load capacitance, c3 + c4, and i pu is the max5949_ gate pullup current. figure 7b shows the inrush current waveform. the cur- rent through c2 controls the gate voltage. at the end of the drain ramp, the gate voltage is charged to its final value. the gate-to-sense clamp limits the maxi- mum v gs to about 18v under any condition. board removal if the card is removed from a live backplane, the output capacitor on the card may not be immediately dis- charged. while the output capacitor is discharging, the max5949_ continues to operate as if the input supply were still connected because the output capacitor tem- porarily supplies operating current to the ic. if the cir- cuit is connected as in figure 7a, the voltage at the uv pin falls below the v uvl , and the max5949_ turns off the external mosfet. if r4 in the circuit is connected directly to the -48v return, the external mosfet remains on until the capacitor is discharged sufficiently to drop the uv pin voltage to v uvl . c ixc i pu l inrush 2 = max5949a/max5949b -48v hot-swap controllers with external r sense _______________________________________________________________________________________ 9 v ee sense gate drain v dd ov uv pwrgd max5949b -48v rtn -48v r4 549k? 1% r5 6.49k? 1% r6 10k? 1% r1 0.02? 5% r3 1k? 5% r2 10? 5% c1** 470nf 25v q1 irf530 c2 15nf 100v gate in vicor vi-j3d-cy v in+ v in- c4 100f 100v c3 0.1f 100v c5 100f 10v * 10nf -48v rtn (short pin) *diodes inc. smat70a. **optional. figure 7a. inrush control circuitry
max5949a/max5949b in either case, when the mosfet is turned off, the out- put capacitor continues to discharge by the ic supply current, i dd . the i dd flows into the ic at the v dd termi- nal, out at the v ee terminal, and back to the capacitor through the external mosfet? substrate diode. there is also a parallel current path between the v ee and drain terminals through multiple internal esd-protec- tion diodes. protection circuits built into the ic allow the drain terminal voltage to drop below that of the v ee terminal so long as the allowed absolute-maximum drain terminal current (-100ma) is not exceeded. as i dd is only 2ma maximum, this limiting current will not even be approached. current limit and electronic circuit breaker the max5949_ provides current-limiting and circuit- breaker features that protect against excessive load cur- rent and short-circuit conditions. the load current is monitored by sensing the voltage across an external sense resistor connected between v ee and sense. if the voltage between v ee and sense reaches the cur- rent-limit trip voltage (v cl ), the max5949_ pulls down the gate pin and regulates the current through the external mosfet so v sense - v ee < v cl . if the current drawn by the load drops below v cl / r sense limit, the gate pin voltage rises again. however, if the load cur- rent is at the regulation limit of v cl / r sense for a period of t phlcb , the electronic circuit breaker trips, causing the max5949a/max5949b to turn off the external mosfet. after an overcurrent fault condition, the circuit breaker is reset by pulling the uv pin low and then pulling uv high or by cycling power to the max5949a/max5949b. unless power is cycled to the max5949a/max5949b, the device waits until t off has elapsed before turning on the gate of the external fet. overcurrent fault integrator the max5949_ features an overcurrent fault integrator. when an overcurrent condition exists, an internal digital counter increments its count. when the counter reaches 500? (the maximum current-limit duration) for the max5949_, an overcurrent fault is generated. if the overcurrent fault does not last 500?, then the counter begins decrementing at a rate 128 (maximum current- limit duty cycle) times slower than the counter was incrementing. repeated overcurrent conditions will gen- erate a fault if duty cycle of the overcurrent condition is greater than 1/128. load-current regulation the max5949_ accomplishes load-current regulation by pulling current from the gate pin whenever v sense - v ee > v cl (see the typical operating characteristics ). this decreases the gate-to-source voltage of the external mosfet, thereby reducing the load current. when v sense - v ee < v cl , the max5949a/max5949b pull the gate pin high by a 45? (i pu ) current. driving into a shorted load in the event of a permanent short-circuit condition, the max5949_ limits the current drawn by the load to v cl / r sense for a period of t phlcb , after which the circuit breaker trips. once the circuit breaker trips, the gate of the external fet is pulled low by 50ma (i pd ) turning off power to the load. immunity to input voltage steps the max5949_ guards against input voltage steps on the input supply. a rapid increase in the input supply voltage (v dd - v ee increasing) causes a current step equal to i = c l x ? v in / ? t. if the load current exceeds v cl / r sense during an input voltage step, the max5949a/max5949b current limit activates, pulling down the gate voltage and limiting the load current to v cl / r sense . the drain voltage (v drain ) then slews at a slower rate than the input voltage. as the drain voltage starts to slew down, the drain-to-gate feedback capacitor c2 pushes back on the gate, reducing the gate-to-source voltage (v gs ) and the current through the external mosfet. once the input supply reaches its final value, the drain slew rate (and therefore the inrush current) is limited by the capacitor c2 just as it is limited in the startup condition. to ensure correct operation, r sense must be chosen to provide a current limit larger than the sum of the load current and the dynamic current into the load capacitance in the slewing mode. if the load current plus the capacitive charging current is -48v hot-swap controllers with external r sense 10 ______________________________________________________________________________________ gate - v ee 10v/div v ee 50v/div drain 50v/div inrush current 1a/div 4ms/div contact bounce figure 7b. input inrush current
below the current limit, the circuit breaker does not trip. for c2 values less than 10nf, a positive voltage step on the input supply can result in q1 turning off momentarily, which can shut down the output. by adding an additional resistor and diode, q1 remains on during the voltage step. this is shown as d1 and r7 in figure 10. the pur- pose of d1 is to shunt current around r7 when the power pins first make contact and allow c1 to hold the gate low. the value of r7 should be sized to generate an r7 x c1 time constant of 33?. undervoltage and overvoltage protection the uv and ov pins can be used to detect undervoltage and overvoltage conditions. the uv and ov pins are internally connected to analog comparators with 130mv (uv) and 20mv (ov) of hysteresis. when the uv voltage falls below its threshold or the ov voltage rises above its threshold, the gate pin is immediately pulled low. the gate pin is held low until uv goes high and ov is low, indicating that the input supply voltage is within specifica- tion. the max5949_ includes an internal lockout (uvlo) that keeps the external mosfet off until the input supply voltage exceeds 15.4v, regardless of the uv input. max5949a/max5949b -48v hot-swap controllers with external r sense ______________________________________________________________________________________ 11 gate - v ee 10v/div i d (q1) 5a/div drain 50v/div 1ms/div figure 8. short-circuit protection waveform drain 20v/div i d (q1) 5a/div v ee 20v/div 400s/div figure 9. voltage step on input supply v ee sense gate drain v dd ov uv pwrgd max5949a -48v rtn -48v r4 549k? 1% r5 6.49k? 1% r6 10k? 1% r1 0.02? 5% r3 1k? 5% r2 10? 5% c1 150nf 25v q1 irf530 c2 3.3nf 100v * -48v rtn (short pin) r7 220? 5% d1 bat85 c4 22f 100v c3 0.1f 100v *diodes inc. smat70a. figure 10. circuit for input steps with small c1
max5949a/max5949b the uv pin is also used to reset the circuit breaker after a fault condition has occurred. the uv pin can be pulled below v uvl to reset the circuit breaker. figure 12 shows how to program the undervoltage and overvoltage trip thresholds using three resistors. with r4 = 549k? , r5 = 6.49k? , and r6 = 10k? , the undervoltage threshold is set to 38.5v (with a 43v release from under- voltage), and the overvoltage is set to 71v. the resistor- divider also increases the hysteresis of the overvoltage and overvoltage lockout, to 4.5v and 1.1v at the input supply, respectively. pwrgd /pwrgd output the pwrgd (pwrgd) output can be used directly to enable a power module after hot insertion. the max5949a (pwrgd) can be used to enable modules with an active-low enable input (figure 14), while the max5949b (pwrgd) is used to enable modules with an active-high enable input (figure 13). the pwrgd signal is referenced to the drain termi- nal, which is the negative supply of the power module. the pwrgd signal is referenced to v ee . -48v hot-swap controllers with external r sense 12 ______________________________________________________________________________________ gate 2v/div node2 50v/div 1s/div v ee sense gate drain v dd ov uv pwrgd max5949a -48v rtn -48v rtn (short pin) * -48v *diodes inc. smat70a. r4 549k? 1% r8 510k? 5% r5 10k? 1% r6 549k? 1% r7 1m? 5% r9 6.49k? 1% r1 0.02? 5% r3 1k? 5% r2 10? 5% c1 470nf 25v c4 1f 100v n q1 irf530 d1 1n4148 q2 2n2222 q3 zvn3310 c2 15nf 100v c3 100f 100v node2 figure 11. automatic restart after current fault v ee v dd ov uv max5949a max5949b -48v rtn -48v v uv = 1.255 r4 + r5 + r6 r5 + r6 r4 r5 r6 -48v rtn (short pin) 3 2 4 8 v ov = 1.255 r4 + r5 + r6 r6 figure 12. undervoltage and overvoltage sensing
max5949a/max5949b -48v hot-swap controllers with external r sense ______________________________________________________________________________________ 13 pwrgd gate i1 v ee v gh v dl ?v gate -48v r1 r2 c1 q1 r3 c2 max5949b v in+ v in- c3 n q2 q3 n v out+ v out- on/off active-high enable module drain gate sense v ee v dd r4 r5 r6 * *diodes inc. smat70a. -48v rtn -48v rtn (short pin) uv ov figure 13. active-high enable module pwrgd v ee v gh gate v dl ?v gate -48v r1 r2 c1 q1 r3 c2 max5949a v in+ v in- c3 v out+ v out- on/off active-low enable module drain gate sense v ee v dd r4 r5 r6 * *diodes inc. smat70a. -48v rtn -48v rtn (short pin) uv ov n q2 figure 14. active-low enable module
max5949a/max5949b when the drain voltage of the max5949a is high with respect to v ee or the gate voltage is low, the internal pulldown mosfet q2 is off and the pwrgd pin is in a high-impedance state (figure 14). the pwrgd pin is pulled high by the module? internal pullup current source, turning the module off. when the drain volt- age drops below v dl and the gate voltage is greater than ?v gate - v gh , q2 turns on and the pwrgd pin pulls low, enabling the module. the pwrgd signal can also be used to turn on an led or optoisolator to indicate that the power is good (figure 15) (see the component selection procedure section). when the drain voltage of the max5949b is high with respect to v ee (figure 13) or the gate voltage is low, the internal mosfet q3 is turned off so that i1 and the inter- nal mosfet q2 clamp the pwrgd pin to the drain pin. mosfet q2 sinks the module? pullup current, and the module turns off. when the drain voltage drops below v dl and the gate voltage is greater than ?v gate - v gh , mosfet q3 turns on, shorting i1 to v ee and turning q2 off. the pullup current in the module pulls the pwrgd pin high, enabling the module. gate pin voltage regulation the gate pin goes high when the following startup con- ditions are met: the uv pin is high, the ov pin is low, the supply voltage is above v uvloh , and (v sense - v ee ) is less than 50mv. the gate is pulled up with a 45? current source and is regulated at 13.5v above v ee . the max5949a/max5949b include an internal clamp that ensures the gate voltage of the external mosfet never exceeds 18v. during a fast-rising v dd , the clamp also keeps the gate and sense potentials as close as possi- ble to prevent the fet from accidentally turning on. when a fault condition is detected, the gate pin is pulled low with a 50ma current. applications information sense resistor the circuit-breaker current-limit threshold is set to 50mv (typically). select a sense resistor that causes a drop equal to or above the current-limit threshold at a current level above the maximum normal operating current. typically, set the overload current to 1.5 to 2.0 times the nominal load current plus the load-capacitance charging current during startup. choose the sense-resistor power rating to be greater than (v cl ) 2 / r sense . -48v hot-swap controllers with external r sense 14 ______________________________________________________________________________________ v ee sense gate drain v dd ov uv pwrgd max5949a -48v rtn -48v r4 549k? 1% r5 6.49k? 1% r6 10k? 1% r1 0.02? 5% r3 1k? 5% r2 10? 5% c1** 470nf 25v q1 irf530 c2 15nf 100v * -48v rtn (short pin) c3 100f 100v *diodes inc. smat70a. **optional. pwrgd moc207 r7** 51k? 5% figure 15. using pwrgd to drive an optoisolator
component selection procedure determine load capacitance: c l = c2 + c3 + module input capacitance determine load current, i load . select circuit-breaker current; for example: i cb = 2 x i load calculate r sense : realize that i cb varies ?0% due to trip-voltage tolerance. set allowable inrush current: determine value of c2: calculate value of c1: determine value of r3: set r2 = 10 ?. if an optocoupler is utilized as in figure 15, deter- mine the led series resistor: although the suggested optocoupler is not specified for operation below 5ma, its performance is adequate for 36v temporary low-line voltage where led current would then be 2.2ma to 3.7ma. if r7 is set as high as 51k? , optocoupler operation should be verified over the expected temperature and input voltage range to ensure suitable operation when led current 0.9ma for 48v input and 0.7ma for 36v input. if input transients are expected to momentarily raise the input voltage to >100v, select an input transient-volt- age-suppression diode (tvs) to limit maximum voltage on the max5949 to less than 100v. a suitable device is the diodes inc. smat70a telecom-specific tvs. select q1 to meet supply voltage, load current, efficien- cy, and q1 package power-dissipation requirements: bv dss 100v i d(on) 3x i load dpak, d 2 pak, or to-220ab the lowest practical r ds(on) , within budget constraints and with values from 14m? to 540m?, are available at 100v breakdown. ensure that the temperature rise of q1 junction is not excessive at normal load current for the package select- ed. ensure that i cb current during voltage transients does not exceed allowable transient-safe operating-area limitations. this is determined from the soa and tran- sient-thermal-resistance curves in the q1 manufacturer? data sheet. example 1: i load = 2.5a, efficiency = 98%, then v ds = 0.96v is acceptable, or r ds(on) 384m? at operating temper- ature is acceptable. an irl520ns 100v nmos with r ds(on) 180m? and i d(on) = 10a is available in d 2 pak. (a vishay siliconix sud40n10-25 100v nmos with r ds(on) 25m? and i d(on) = 40a is available in dpak, but may be more costly because of a larger die size.) using the irl520ns, v ds 0.625v even at +80? so efficiency 98.6% at 80?. p d 1.56w and junction temperature rise above case temperature would be 5? due to the package jc = 3.1?/w thermal resistance. of course, using the sud40n10-25 would yield an effi- ciency greater than 99.8% to compensate for the increased cost. r vv ma i ma in nominal led 7 2 35 () = ? ? r s c typically k 3 150 2 1 ( ) ? cccx vv v gd in max gs th gs th 12 =+ ? ? ? ? ? ? ? () () () () c axc i l inrush 2 45 = ix mv r ior ii xi inrush sense load inrush load cb min + ? 08 40 08 . . () r mv i sense cb = 50 max5949a/max5949b -48v hot-swap controllers with external r sense ______________________________________________________________________________________ 15
max5949a/max5949b if i cb is set to twice i load , or 5a, v ds momentarily dou- bles to 1.25v. if c out = 4000?, transient-line input voltage is ?36v, and the 5a charging-current pulse is: entering the data sheet transient-thermal-resistance curves at 1ms provides a jc = 0.9?/w. p d = 6.25w, so ? t jc = 5.6?. clearly, this is not a problem. example 2: i load = 10a, efficiency = 98%, allowing v ds = 0.96v but r ds(on) 96m? . an irf530 in a d 2 pak exhibits r ds(on) 90m? at +25? and 135m? at +80?. power dissipation is 9.6w at +25? or 14.4w at +80?. junction-to-case thermal resistance is 1.9w/?, so the junction-temperature rise would be approximately 5? above the +25? case temperature. for higher efficien- cy, consider irl540ns with r ds(on) 44m? . this allows = 99%, p d 4.4w, and t jc = +4? ( jc = 1.1?/w) at +25?. thermal calculations for the transient condition yield i cb = 20a, v ds = 1.8v, t = 0.5ms, transient jc = 0.12?/w, p d = 36w and ?t jc = 4.3?. t fx v a ms . == 4000 1 25 5 1 -48v hot-swap controllers with external r sense 16 ______________________________________________________________________________________ sense resistor high-current path max5949a max5949b sense v ee figure 16. recommended layout for kelvin-sensing current through sense resistor selector guide part pwrgd polarity fault management max5949aesa active low ( pwrgd) latched max5949besa active high (pwrgd) latched
max5949a/max5949b -48v hot-swap controllers with external r sense ______________________________________________________________________________________ 17 v ee sense gate drain v dd ov uv pwrgd max5949a -48v (input1) -48v (input2) input1 0.1f 10v c1 490nf 25v c3 0.1f 100v c4 100f 100v c2 15nf 100v r4 549k? 1% r5 649k? 1% r6 10k? 1% r2 10? 5% r1 0.02? 5% r3 1k? 5% input2 n lucent jw050a1-e v in+ v in- -48v rtn -48v rtn (short pin) backplane circuit card typical operating circuit chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 so s8+5 21-0041 90-0096
max5949a/max5949b -48v hot-swap controllers with external r sense maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 11/04 initial release 1 8/11 updated the electrical characteristics and figure 11. 3, 12

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