View LTC2704CGW-14PBF_3970451.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc2704 1 2704fc refm1 refg1 ref1 24 42 23 21 refm2 refg2 2704 bd ref2 43 44 2 v + 1 32 agnd 25 v + 2 v C 1,8,15,22,31,36 12 sro sdi 11 sck 13 ldac 9 clr 14 cs /ld 10 rflag 35 v dd 34 gnd 33 dac c dac d 26 29 28 27 30 20 17 18 19 16 agndc c1d rfbd outd agndd outc rfbc c1c vosc vosd dac a agnda outa rfba c1a vosa 3 6 5 4 7 dac b c1b rfbb outb agndb vosb 41 38 39 40 37 C1 C1 ltc2704-16 integral nonlinearity (inl) code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 16384 32768 2704 ta01b C0.6 0.6 0.8 0.2 49152 65535 v + /v C = 15v v ref = 5v 10v range all 4 dacs superimposed block diagram features applications description quad 12-, 14- and 16-bit voltage output softspan dacs with readback n six programmable output ranges: unipolar: 0v to 5v, 0v to 10v bipolar: 5v, 10v, 2.5v, ?2.5v to 7.5v n serial readback of all on-chip registers n 1lsb inl and dnl over the industrial temperature range (ltc2704-14/ltc2704-12) n force/sense outputs enable remote sensing n glitch impulse: < 2nv-sec n outputs drive 5ma n pin compatible 12-, 14- and 16-bit parts n power-on and clear to zero volts n 44-lead ssop package n process control and industrial automation n direct digital waveform generation n software controlled gain adjustment n automated test equipment the ltc ? 2704-16/ltc2704-14/ltc2704-12 are serial input, 12-, 14- or 16-bit, voltage output softspan? dacs that operate from 3v to 5v logic and 5v to 15v analog supplies. softspan offers six output spanstwo unipolar and four bipolarfully programmable through the 3-wire spi serial interface. inl is accurate to 1lsb (2lsb for the ltc2704-16). dnl is accurate to 1lsb for all versions. readback commands allow veri? cation of any on-chip register in just one 24- or 32- bit instruction cycle. all other commands produce a rolling readback response from the ltc2704, dramatically reducing the needed number of instruction cycles. a sleep command allows any combination of dacs to be powered down. there is also a reset ? ag and an offset adjustment pin for each channel. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
ltc2704 2 2704fc pin configuration absolute maximum ratings (note 1) total supply voltage v + 1 , v + 2 to v ? ........... ?0.3v to 36v v + 1 , v + 2 , ref1, ref2, refm1, refm2, outx, rfbx, v osx to gnd, agnd, agndx, c1x, refg1, refg2 .....................................18v gnd, agnd, agndx, c1x, refg1, refg2 to v + 1 , v + 2 , v ? , ref1, ref2, refm1, refm2, outx, rfbx, v osx ...............................................................18v outa, rfba, v osa , outb, rfbb, vosb, ref1, refm1 to gnd, agnd ............... v ? ? 0.3v to v + 1 + 0.3v outc, rfbc, v osc , outd, rfbd, v osd , ref2, refm2 to gnd, agnd ............................ v ? ? 0.3v to v + 2 + 0.3v v dd , digital inputs/outputs to gnd ............. ?0.3v to 7v digital inputs/outputs to v dd ..................................0.3v gnd, agndx, refg1, refg2 to agnd ..................0.3v c1x to agndx ........................................................0.3v v ? to any pin ...........................................................0.3v maximum junction temperature.......................... 150c operating temperature range ltc2704c ................................................ 0c to 70c ltc2704i .............................................? 40c to 85c storage temperature range ...................? 65c to 150c lead temperature (soldering, 10 sec) .................. 300c order information 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 top view gw package 44-lead plastic ssop 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 v ? refg1 agnda vosa c1a outa rfba v ? ldac cs/ld sdi sro sck clr v ? rfbd outd c1d vosd agndd refg2 v ? refm1 ref1 v + 1 agndb vosb c1b outb rfbb v ? rflag v dd gnd agnd v ? rfbc outc c1c vosc agndc v + 2 ref2 refm2 t jmax = 125c,
ltc2704 3 2704fc electrical characteristics symbol param eter conditions ltc2704-12 ltc2704-14 ltc2704-16 units min typ max min typ max min typ max accuracy resolution l 12 14 16 bits monotonicity l 12 14 16 bits inl integral nonlinearity v ref = 5v l 1 1 2 lsb dnl differential nonlinearity v ref = 5v l 1 1 1 lsb ge gain error v ref = 5v l 0.5 2 1 5 4 20 lsb gain temperature coef? cient gain/temperature l 2 2 2 ppm/c v os unipolar zero-scale error span = 0v to 5v, t a = 25c span = 0v to 10v, t a = 25c span = 0v to 5v span = 0v to 10v l l 80 100 140 150 200 300 400 600 80 100 140 150 200 300 400 600 80 100 140 150 200 300 400 600 v v v v v os temperature coef? cient 0v to 5v range 0v to 10v range l l 2 2 2 2 2 2 v/c v/c bze bipolar zero error all bipolar ranges l 0.25 1 2 0.5 2 2.5 2 8 12 lsb lsb psrr power supply rejection ratio v dd = 5v 10% (note 3) v dd = 3v 10% (note 3) 0v to 10v range, code = 0 v + /v C = 15v 10% (note 2) v + /v C = 5v 10%, v ref = 2v (note 2) l l 0.003 0.006 0.001 0.002 0.06 0.05 0.013 0.025 0.005 0.01 0.25 0.13 0.05 0.1 0.02 0.04 0.1 0.5 lsb/v lsb/v lsb/v lsb/v analog outputs (note 4) settling time 0v to 5v range, 5v step, to 1lsb 0v to 10v or 5v range, 10v step, to 1lsb 10v range, 20v step, to 1lsb 3 5 8 3.5 5.5 9 4 6 10 s s s output swing v + /v C = 15v, v ref = 7.25v, 0v to 10v range, i load = 3ma (note 2) l C14.3 14.3 C14.3 14.3 C14.3 14.3 v v + /v C = 5v, v ref = 2.25v, 0v to 10v range, i load = 2.5ma (note 2) l C4.5 4.5 C4.5 4.5 C4.5 4.5 v load current v + /v C = 10.8v to 16.5v, v ref = 5v, 0v to 10v range, v out = 10v (note 2) l 5 4 5 4 5 4 ma ma v + /v C = 4.5v to 16.5v, v ref = 2v, 0v to 10v range, v out = 4v (note 2) l 3 2.7 3 2.7 3 2.7 ma ma load regulation v + /v C = 15v, v ref = 5v, 0v to 10v range, code = 0, 5ma load (note 2) l 0.005 0.01 0.04 lsb/ma v + /v C = 5v, v ref = 2v, 0v to 10v range, code = 0, 3ma load (note 2) l 0.01 0.013 0.05 lsb/ma output impedance v ref = 5v, 0v to 10v range, code = 0, 5ma load l 0.015 0.006 0.006 i sc short-circuit current v + /v C = 16.5v, v ref = 5v, 10v range code = 0, v out shorted to v + (note 2) code = full scale, v out shorted to v C l l C36 38 C36 38 C36 38 ma ma v + /v C = 5.5v, v ref = 2v, 10v range code = 0, v out shorted to v + (note 2) code = full scale, v out shorted to v C l l C36 38 C36 38 C36 38 ma ma the l denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are t a = 25c, v + 1 = v + 2 = 15v, v ? = ?15v, v dd = 5v, ref1 = ref2 = 5v, agnd = agndx = refg1 = refg2 = gnd = 0v.
ltc2704 4 2704fc electrical characteristics the l denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are t a = 25c, v + 1 = v + 2 = 15v, v ? = ?15v, v dd = 5v, ref1 = ref2 = 5v, agnd = agndx = refg1 = refg2 = gnd = 0v. symbol param eter conditions ltc2704-12 ltc2704-14 ltc2704-16 units min typ max min typ max min typ max sr slew rate r l = 2k, v + /v C = 15v (note 2) r l = 2k, v + /v C = 5v (note 2) l l 2.2 2.0 3 2.8 2.2 2.0 3 2.8 2.2 2.0 3 2.8 v/s v/s capacitive load driving within maximum load current 1000 1000 1000 pf the l denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are t a = 25c, v + 1 = v + 2 = 15v, v ? = ?15v, v dd = 5v, ref1 = ref2 = 5v, agnd = agndx = refg1 = refg2 = gnd = 0v. symbol parameter conditions min typ max units reference inputs ref1, ref2 input voltage v + /v C = 15v, 0v to 5v span (note 2) l C14.5 14.5 v resistances r ref1, r ref2 reference input resistance l 57 k r fbx output feedback resistance l 710 k r vosx offset adjust input resistance l 700 1000 k ac performance (note 4) glitch impulse 0v to 5v range, midscale transition 2 nv-s crosstalk 10v step on v outa dac b: 0v to 5v range, full scale dac b: 0v to 10v range, full scale 2 3 nv-s nv-s digital feedthrough 10v range, midscale 0.2 nv-s multiplying feedthrough error 0v to 10v range, v ref = 5v, 10khz sine wave 0.35 mv p-p multiplying bandwidth span = 0v to 5v, full scale span = 0v to 10v, full scale 300 250 khz khz output noise voltage density 10khz span = 0v to 5v, midscale span = 0v to 10v, midscale 30 50 v/ hz v/ hz output noise voltage 0.1hz to 10hz span = 0v to 5v, midscale span = 0v to 10v, midscale 0.8 1.2 v rms v rms power supply i dd supply current, v dd digital inputs = 0v or v dd l 0.5 2 a i s supply current, v + /v C v + /v C = 15v, 10%; v ref = 5v, v out = 0v (note 2) v + /v C = 5v, 10%; v ref = 2v, v out = 0v (note 2) sleep modeall dacs (note 4) l l 17.5 17.0 20 18 1 ma ma ma v dd logic supply voltage l 2.7 5.5 v v + 1 /v + 2 positive analog supply voltage l 4.5 16.5 v v C negative analog supply voltage l C16.5 C4.5 v digital inputs/outputs v ih digital input high voltage v dd = 2.7v to 5.5v v dd = 2.7v to 3.3v l l 2.4 2.0 v v v il digital input low voltage v dd = 2.7v to 5.5v v dd = 4.5v to 5.5v l l 0.6 0.8 v v v oh digital output high voltage i oh = 200a l v cc C 0.4 v v ol digital output low voltage i ol = 200a l 0.4 v i in digital input current l 0.001 1 a
ltc2704 5 2704fc the l denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the notation v + is used to denote both v + 1 and v + 2 when the same voltage is applied to both pins. note 3: guaranteed by design, not subject to test. note 4: measured in unipolar 0v to 5v mode. note 5: when using sro, maximum sck frequency f max is limited by sro propagation delay as follows: f max = 1 2t 9 + t s ( ) , where t s is the setup time of the receiving device. symbol parameter conditions min typ max units c in digital input capacitance v in = 0v (note 3) l 5pf symbol parameter conditions min typ max units v dd = 4.5v to 5.5v t 1 sdi valid to sck setup l 7ns t 2 sdi valid to sck hold l 7ns t 3 sck high time l 11 ns t 4 sck low time l 11 ns t 5 cs /ld pulse width l 9ns t 6 lsb sck high to cs /ld high l 0ns t 7 cs /ld low to sck positive edge l 12 ns t 8 cs /ld high to sck positive edge l 12 ns t 9 sro propagation delay c load = 10pf l 18 ns t 10 clr pulse width l 50 ns t 11 ldac pulse width l 15 ns t 12 clr low to rflag low c load = 10pf (note 3) l 50 ns t 13 cs /ld high to rflag high c load = 10pf (note 3) l 40 ns sck frequency 50% duty cycle (note 5) l 40 mhz v dd = 2.7v to 3.3v t 1 sdi valid to sck setup l 9ns t 2 sdi valid to sck hold l 9ns t 3 sck high time l 15 ns t 4 sck low time l 15 ns t 5 cs /ld pulse width l 12 ns t 6 lsb sck high to cs /ld high l 0ns t 7 cs /ld low to sck positive edge l 12 ns t 8 cs /ld high to sck positive edge l 12 ns t 9 sro propagation delay c load = 10pf l 26 ns t 10 clr pulse width l 90 ns t 11 ldac pulse width l 20 ns t 12 clr low to rflag low c load = 10pf l 70 ns t 13 cs /ld high to rflag high c load = 10pf l 60 ns sck frequency 50% duty cycle (note 5) l 25 mhz timing characteristics electrical characteristics the l denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are t a = 25c, v + 1 = v + 2 = 15v, v ? = ?15v, v dd = 5v, ref1 = ref2 = 5v, agnd = agndx = refg1 = refg2 = gnd = 0v.
ltc2704 6 2704fc typical performance characteristics temperature (c) C50 lsb 4 90 2704 g07 C8 C30 C10 10 30 50 70 8 2 6 0 C4 C6 C2 v + /v C = 15v v ref = 5v 10v range temperature (c) C50 gain error (lsb) 12 16 C16 C12 30 2704 g08 0 4 C4 8 C8 C30 C10 10 50 70 90 v + /v C = 15v v ref = 5v 10v range temperature (c) C50 inl (lsb) 0.2 0.6 1.0 30 2704 g04 C0.2 Co.6 0 0.4 0.8 C0.4 C0.8 C1.0 C30 C10 10 50 70 90 v + /v C = 15v v ref = 5v 10v range max min temperature (c) C50 dnl (lsb) 0.2 0.6 1.0 30 2704 g05 C0.2 Co.6 0 0.4 0.8 C0.4 C0.8 C1.0 C30 C10 10 50 70 90 v + /v C = 15v v ref = 5v 10v range max min temperature (c) C50 offset (v) 200 400 600 30 2704 g06 C200 C600 0 C400 C30 C10 10 50 70 90 v + /v C = 15v v ref = 5v 0v to 10v range ltc2704-16 integral nonlinearity (inl) code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 16384 32768 2704 g01 C0.6 0.6 0.8 0.2 49152 65535 v + /v C = 15v v ref = 5v 10v range code 0 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 16384 32768 2704 g02 C0.6 0.6 0.8 0.2 49152 65535 v + /v C = 15v v ref = 5v 10v range v ref (v) C10 inl (lsb) 0.2 0.6 1.0 6 2704 g03 C0.2 C0.6 0 0.4 0.8 C0.4 C0.8 C1.0 C6 C8 C2 C4 24 8 0 10 v + /v C = 15v 5v range max max min min differential nonlinearity (dnl) inl vs v ref bipolar zero vs temperature gain error vs temperature inl vs temperature offset vs temperature dnl vs temperature
ltc2704 7 2704fc typical performance characteristics 2.5s/div v out 5v/div v out 1mv/div cs /ld 5v/div 2704 g18 settling 0v to 5v 2.5s/div v out 5v/div v out 1mv/div cs /ld 5v/div 2704 g19 2.5s/div v out 10v/div v out 1mv/div cs /ld 5v/div 2704 g20 settling 0v to 10v settling 10v ltc2704-14 integral nonlinearity (inl) differential nonlinearity (dnl) code 0 C1.0 lsb C0.8 C0.4 C0.2 0 1.0 0.4 4096 8192 2704 g09 C0.6 0.6 0.8 0.2 12288 16383 v + /v C = 15v v ref = 5v 10v range code 0 C1.0 lsb C0.8 C0.4 C0.2 0 1.0 0.4 4096 8192 2704 g10 C0.6 0.6 0.8 0.2 12288 16383 v + /v C = 15v v ref = 5v 10v range ltc2704-12 integral nonlinearity (inl) differential nonlinearity (dnl) code 0 C1.0 lsb C0.8 C0.4 C0.2 0 1.0 0.4 1536 2048 2704 g11 C0.6 0.6 0.8 0.2 3072 512 1024 2560 3584 4095 v + /v C = 15v v ref = 5v 10v range code 0 C1.0 lsb C0.8 C0.4 C0.2 0 1.0 0.4 1536 2048 2704 g12 C0.6 0.6 0.8 0.2 3072 512 1024 2560 3584 4095 v + /v C = 15v v ref = 5v 10v range ltc2704-16
ltc2704 8 2704fc typical performance characteristics v C (pins 1, 8, 15, 22, 31, 36): analog negative supply, typically C15v. C4.5v to C16.5v range. refg1 (pin 2): reference 1 ground. high impedance input, does not carry supply currents. tie to clean analog ground. agnda (pin 3): dac a signal ground. high impedance input, does not carry supply currents. tie to clean analog ground. vosa (pin 4): offset adjust for dac a. nominal input range is 5v. v os (dac a) = C0.01? v(vosa) [0v to 5v, 2.5v modes]. see operation section. c1a (pin 5): feedback capacitor connection for dac a output. this pin provides direct access to the negative input of the channel a output ampli? er. outa (pin 6): dac a voltage output pin. for best load regulation, this open-loop ampli? er output is connected to rfba as close to the load as possible. rfba (pin 7): dac a output feedback resistor pin. ldac (pin 9): asynchronous dac load input. when ldac is a logic low, all dacs are updated. 0.1hz to 10hz noise v cc supply current vs logic voltage 1s/div 1v/div 2704 g16 v + /v C = 15v v ref = 5v 0v to 5v range code = 0 logic voltage (v) 0 0 i cc (ma) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.5 2.5 3.5 2704 g17 2.0 4.5 5.0 1.0 1.5 3.0 4.0 v dd = 5v sck, sdi, cs /ld, ldac clr tied together pin functions ltc2704-16/ltc2704-14/ltc2704-12 positive slew negative slew 2.5s/div 5v/div 2704 g13 v + /v C = 15v v ref = 5v 10v range 20v step 2.5s/div 5v/div 2704 g14 v + /v C = 15v v ref = 5v 10v range 20v step 2.5s/div cs /ld 5v/div v out 2mv/div 2704 g15 midscale glitch
ltc2704 9 2704fc cs /ld (pin 10): synchronous chip select and load pin. sdi (pin 11): serial data input. data is clocked in on the rising edge of the serial clock when cs /ld is low. sro (pin 12): serial readback data output. data is clocked out on the falling edge of sck. readback data begins clocking out after the last address bit a0 is clocked in. sck (pin 13): serial clock. clr (pin 14): asynchronous clear pin. when this pin is low, all code and span b2 registers are cleared to zero. all dac outputs are cleared to zero volts. rfbd (pin 16): dac d voltage output feedback resis- tor pin. outd (pin 17): dac d voltage output pin. for best load regulation, this open-loop ampli? er output is connected to rfbd as close to the load as possible. c1d (pin 18): feedback capacitor connection for dac d output. this pin provides direct access to the negative input of the channel d output ampli? er. vosd (pin 19): offset adjust for dac d. nominal input range is 5v. v os (dac d) = C0.01? v(vosd) [0v to 5v, 2.5v modes]. see operation section. agndd (pin 20): dac d signal ground. high impedance input, does not carry supply currents. tie to clean analog ground. refg2 (pin 21): reference 2 ground. high impedance input, does not carry supply currents. tie to clean analog ground. refm2 (pin 23): reference 2 inverting amp output. the gain from ref2 to refm2 is C1. can swing to within 0.5v of the analog supplies v + /v C . ref2 (pin 24): dac c and dac d reference input. v + 2 (pin 25): analog positive supply for dacs c and d. typically 15v. 4.5v to 16.5v range. can be different from v + 1 . agndc (pin 26): dac c signal ground. high impedance input, does not carry supply currents. tie to clean analog ground. vosc (pin 27): offset adjust for dac c. nominal input range is 5v. v os (dac c) = C0.01? v(vosc) [0v to 5v, 2.5v modes]. see operation section. c1c (pin 28): feedback capacitor connection for dac c output. this pin provides direct access to the negative input of the channel c output ampli? er. outc (pin 29): dac c voltage output pin. for best load regulation, this open-loop ampli? er output is connected to rfbc as close to the load as possible. rfbc (pin 30): dac c output feedback resistor pin. agnd (pin 32): analog ground pin. tie to clean analog ground. gnd (pin 33): ground pin. tie to clean analog ground. v dd (pin 34): logic supply. 2.7v to 5.5v range. rflag (pin 35): reset flag pin. an active low output is asserted when there is a power on reset or a clear event. returns high when an update command is executed. rfbb (pin 37): dac b output feedback resistor pin. outb (pin 38): dac b voltage output pin. for best load regulation, this open-loop ampli? er output is connected to rfbb as close to the load as possible. c1b (pin 39): feedback capacitor connection for dac b output. this pin provides direct access to the negative input of the channel b output ampli? er. vosb (pin 40): offset adjust for dac b. nominal input range is 5v. v os (dac b) = C0.01 ? v(vosb) [0v to 5v, 2.5v modes]. see operation section. agndb (pin 41): dac b signal ground. high impedance input, does not carry supply currents. tie to clean analog ground. v + 1 (pin 42): analog positive supply for dacs a dnd b. typically 15v. 4.5v to 16.5v range. can be different from v + 2 . ref1 (pin 43): dac a and dac b reference input. refm1 (pin 44): reference 1 inverting amp output. the gain from ref1 to refm1 is C1. can swing to within 0.5v of the analog supplies v + /v C . pin functions
ltc2704 10 2704fc 42 12 sro 2704 bd 32 agnd 25 v + 2 v C 1,8,15,22,31,36 command decode input shift regs readback shift regs dac buffers sdi 11 sck 13 ldac 9 clr 14 cs /ld 10 rflag 35 v dd 34 gnd por 33 ref1 43 v + 1 agnda outa rfba c1a vosa 3 6 5 4 7 dac a + C agndb outb rfbb c1b vosb 41 refm1 44 refg1 agndc outc rfbc c1c vosc ref2 agndd outd rfbd c1d vosd refm2 refg2 2 38 39 40 37 26 29 28 24 27 30 20 23 21 17 18 19 16 dac b + C C + + C + C C + dac c dac d sdi sro hi-z cs /ld sck lsb 2704 td lsb t 2 t 9 t 8 t 5 t 7 1 2 31 32 t 6 t 1 ldac t 3 t 4 t 11 block diagram timing diagram
ltc2704 11 2704fc serial interface when the cs /ld pin is taken low, the data on the sdi pin is loaded into the shift register on the rising edge of the clock signal (sck pin). the minimum (24-bit wide) loading sequence required for the ltc2704 is a 4-bit command word (c3 c2 c1 c0), followed by a 4-bit address word (a3 a2 a1 a0) and 16 data (span or code) bits, msb ? rst. figure 1 shows the sdi input word syntax to use when writing a code or span. if a 32-bit input sequence is needed, the ? rst eight bits must be zeros, followed by the same sequence as for a 24-bit wide input. figure 2 shows the input and readback sequences for both 24-bit and 32-bit operations. when cs /ld is low, the serial readback output (sro) pin is an active output. the readback data begins after the command (c3-c0) and address (a3-a0) words have been shifted into sdi. for a 24-bit load sequence, the 16 readback bits are shifted out on the falling edges of clocks 8-23, suitable for shifting into a microprocessor on the rising edges of clocks 9-24. for a 32-bit load sequence, add 8 to these clock cycle counts; see figure 2b. when cs /ld is high, the sro pin presents a high impedance (three-state) output. at the beginning of a load sequence, when cs /ld is taken low, sro outputs a logic low until the readback data begins. when the asynchronous load pin, ldac , is taken low, all dacs are updated with code and span data (data in b1 buffers is copied into b2 buffers). cs /ld must be high during this operation. the use of ldac is functionally identical to the update b1 a b2 commands. the codes for the command word (c3-c0) are de? ned in table 1; table 2 de? nes the codes for the address word (a3-a0). readback each dac has two pairs of double-buffered digital regis- ters, one pair for dac code and the other for the output span (four buffers per dac). each double-buffered pair comprises two registers called buffer 1 (b1) and buffer 2 (b2). b1 is the holding buffer. when data is shifted into b1 via a write operation, dac outputs are not affected. the con- tents of b2 can only be changed by copying the contents of b1 into b2 via an update operation (b1 and b2 can be changed together, see commands 0110-1001 in table 1). the contents of b2 (dac code or dac span) directly control the dac output voltage or the dac output range. additionally each dac has one readback register associated with it. when a readback command is issued to a dac, the contents of one of its four buffers is copied into its readback register and serially shifted out onto the sro pin. figure 2 shows the loading and readback sequences. in the 16-bit data ? eld (d15-d0 for the ltc2704-16, see figure 2a) of any write or update command, the readback pin (sro) shifts out the contents of the buffer which was speci? ed in the preceding command. this rolling readback mode of operation can be used to reduce the number of operations, since any command can be veri? ed during succeeding commands with no additional overhead. table 1 shows the location (readback pointer) of the data which will be output from sro during the next instruction. for readback commands, the data is shifted out during the readback instruction itself (on the 16 falling sck edges im- mediately after the last address bit is shifted in on sdi). when programming the span of a dac, the span bits are the last four bits shifted in; and when checking the span of a dac using sro, the span bits are likewise the last four bits shifted out. table 3 shows the span codes. when span information is read back on sro, the sleep status of the addressed dac is also output. the sleep status bit, slp , occurs sequentially just before the four span bits. the sequence is shown in figures 2a and 2b. see table 4 for slp codes. note that slp is an output bit only; sleep is programmed by using command code 1110 along with the desired address. any update command, including the use of ldac , wakes the addressed dac(s). operation
ltc2704 12 2704fc output ranges the ltc2704 is a quad dac with software-programmable output ranges. softspan provides two unipolar output ranges (0v to 5v and 0v to 10v), and four bipolar ranges (2.5v, 5v, 10v and C 2.5v to 7.5v). these ranges are obtained when an external precision 5v reference and analog supplies of 12v to 15v are used. when a refer- ence voltage of 2v and analog supplies of 5v are used, the softspan ranges become: 0v to 2v, 0v to 4v, 1v, 2v, 4v and C1v to 3v. the output ranges are linearly scaled for references other than 2v and 5v (appropriate analog supplies should be used within the range 5v to 15v). each of the four dacs can be programmed to any one of the six output ranges. dac outputs can swing to 10v on 10.8v supplies (12v supplies with 10% tolerance) while sourcing or sinking 5ma of load current. operation table 1. command codes code readback pointer readback pointer c3 c2 c1 c0 command current input word w o next input word w +1 0 0 1 0 write to b1 span dac n set by previous command b1 span dac n 0 0 1 1 write to b1 code dac n set by previous command b1 code dac n 01 0 0 update b1 a b2 dac n set by previous command b2 span dac n 01 0 1 update b1 a b2 all dacs set by previous command b2 code dac n 0 1 1 0 write to b1 span dac n update b1 a b2 dac n set by previous command b2 span dac n 0 1 1 1 write to b1 code dac n update b1 a b2 dac n set by previous command b2 code dac n 1 0 0 0 write to b1 span dac n update b1 a b2 all dacs set by previous command b2 span dac n 1 0 0 1 write to b1 code dac n update b1 a b2 all dacs set by previous command b2 code dac n 1 0 1 0 read b1 span dac n b1 span dac n 1 0 1 1 read b1 code dac n b1 code dac n 1 1 0 0 read b2 span dac n b2 span dac n 1 1 0 1 read b2 code dac n b2 code dac n 1 1 1 0 sleep dac n (note 1) set by previous command b2 span dac n 1 1 1 1 no operation set by previous command b2 code dac n codes not shown are reserved and should not be used. note 1: normal operation can be resumed by issuing any update b1 a b2 command to the sleeping dac. table 2. address codes a3 a2 a1 a0 n readback pointer n 0 0 0 0 dac a dac a 0 0 1 0 dac b dac b 0 1 0 0 dac c dac c 0 1 1 0 dac d dac d 1 1 1 1 all dacs dac a codes not shown are reserved and should not be used. table 3. span codes s3 s2 s1 s0 span 0 0 0 0 unipolar 0v to 5v 0 0 0 1 unipolar 0v to 10v 0 0 1 0 bipolar C5v to 5v 0 0 1 1 bipolar C10v to 10v 0 1 0 0 bipolar C2.5v to 2.5v 0 1 0 1 bipolar C2.5v to 7.5v codes not shown are reserved and should not be used.
ltc2704 13 2704fc c2 c1 c0 a3 a2 a1 a0 d15 msb d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lsb c3 ltc2704-16 (write code) control word address word 16-bit code c2 c1 c0 a3 a2 a1 a0 d13 msb d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 lsb c3 ltc2704-14 (write code) control word sdi address word 14-bit code 2 zeros c2 c1 c0 a3 a2 a1 a0 d11 msb d10d9d8 d7d6d5d4d3d2d1d0 0 0 0 0 lsb c3 ltc2704-12 (write code) control word address word 12-bit code 4 zeros c2 c1 c0 a3 a2 a1 a0 0 0 0 0 0 0 0 0 0 0 0 0 s3 s2 s1 s0 c3 ltc2704-12 ltc2704-14 ltc2704-16 (write span) control word address word 12 zeros span 2704 f01 figure 1. input words operation
ltc2704 14 2704fc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 0 0 0 0 0 0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 cs /ld sck sdi sro hi-z hi-z control word readback code 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slp s3 s2 s1 s0 0 sro readback span address word dac code or dac span 24-bit data stream 2704 f02a sleep status span figure 2a. 24-bit load sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 0 0 0 0 0 0 0 0 cs /ld sck sdi control word address word dac code or dac span 32-bit data stream 0 0 0 0 0 0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 sro t 2 t 3 t 4 t 1 t 9 d15 17 sck sdi sro d14 d15 18 d14 8 zeros hi-z hi-z readback code 2704 f02b 000000 00000 0000000slps3s2s1s0 0 0 0 0 0 0 0 0 0 sro readback span sleep status span figure 2b. 32-bit load sequence operation
ltc2704 15 2704fc examples 1. using a 24-bit loading sequence, load dac a with the unipolar range of 0v to 10v, output at zero volts and all other dacs with the bipolar range of 10v, outputs at zero volts. note all dac outputs should change at the same time. a) cs /ld b) clock sdi = 0010 1111 0000 0000 0000 0011 c) cs /ld b b1-range of all dacs set to bipolar 10v. d) cs /ld clock sdi = 0010 0000 0000 0000 0000 0001 e) cs /ld b b1-range of dac a set to unipolar 0v to 10v. f) cs /ld clock sdi = 0011 1111 1000 0000 0000 0000 g) cs /ld b b1-code of all dacs set to midscale. h) cs /ld clock sdi = 0011 0000 0000 0000 0000 0000 i) cs /ld b b1-code of dac a set to zero code. j) cs /ld clock sdi = 0100 1111 xxxx xxxx xxxx xxxx k) cs /ld b update all dacs b1s into b2s for both code and range. l) alternatively steps j and k could be replaced with ldac . 2. using a 32-bit load sequence, load dac c with bipolar 2.5v and its output at zero volts. use readback to check b1 contents before updating the dac output (i.e., before copying b1 contents into b2). a) cs /ld (note that after power-on, the code in b1 is zero) b) clock sdi = 0000 0000 0011 0100 1000 0000 0000 0000 c) cs /ld b b1-code of dac c set to midscale setting. d) cs /ld clock sdi = 0000 0000 0010 0100 0000 0000 0000 0100 e) read data out on sro = 1000 0000 0000 0000 veri? es that b1-code dac c is at midscale setting. f) cs /ld b b1-range of dac c set to bipolar 2.5v range. g) cs /ld clock sdi = 0000 0000 1010 0100 xxxx xxxx xxxx xxxx data out on sro = 0000 0000 0000 0100 veri? es that b1-range of dac c set to bipolar 2.5v range. cs /ld b h) cs /ld clock sdi = 0000 0000 0100 0100 xxxx xxxx xxxx xxxx i) cs /ld b update dac c b1 into b2 for both code and range j) alternatively steps h and i could be replaced with ldac . system offset adjustment many systems require compensation for overall system offset, which may be an order of magnitude or more greater than the excellent offset of the ltc2704. the ltc2704 has individual offset adjust pins for each of the four dacs. vosa, vosb, vosc and vosd are referred to their corresponding signal grounds, agnda, agndb, agndc and agndd. for noise immunity and ease of adjustment, the control voltage is attenuated to the dac output: v os = C0.01 ? v(vosx) [0v to 5v, 2.5v spans] v os = C0.02 ? v(vosx) [0v to 10v, 5v, C2.5v to 7.5v spans] v os = C0.04 ? v(vosx) [10v span] the nominal input range of these pins is 5v; other refer- ence voltages of up to 15v may be used if needed. the vosx pins have an input impedance of 1m. to pre- serve the settling performance of the ltc2704, these pins operation
ltc2704 16 2704fc should be driven with a thevenin-equivalent impedance of 10k or less. if not used, they should be shorted to their respective signal grounds, agndx. power-on reset and clear when power is ? rst applied to the ltc2704, all dacs power-up in 5v unipolar mode (s3 s2 s1 s0 = 0000). all internal dac registers are reset to 0 and the dac outputs are zero volts. when the clr pin is taken low, a system clear results. the command and address shift registers, and the code and con? guration b2 buffers, are reset to 0; the dac outputs are all reset to zero volts. the b1 buffers are left intact, so that any subsequent update b1 a b2 command (including the use of ldac ) restores the addressed dacs to their respective previous states. if clr is asserted during an operation, i.e., when cs /ld is low, the operation is aborted. integrity of the relevant input (b1) buffers is not guaranteed under these condi- tions, therefore the contents should be checked using readback or replaced. the rflag pin is used as a ? ag to notify the system of a loss of data integrity. the rflag output is asserted low at power-up, system clear, or if the logic supply v dd dips below approximately 2v; and stays asserted until any valid update command is executed. sleep mode when a sleep command (c3 c2 c1 c0 = 1110) is issued, the addressed dac or dacs go into power-down mode. dacs a and b share a reference inverting ampli? er as do dacs c and d. if either dac a or dac b (similarly for dacs c and d) is powered down, its shared reference inverting ampli? er remains powered on. when both dac a and dac b are powered down together, their shared reference invert- ing ampli? er is also powered down (similarly for dacs c and d). to determine the sleep status of a particular dac, a direct read span command is performed by addressing the dac and reading its status on the readback pin sro. the ? fth lsb is the sleep status bit (see figures 2a and 2b). table 4 shows the sleep status bits functionality. table 4. readback sleep status bit slp status 0 dac n awake 1 dac n in sleep mode operation
ltc2704 17 2704fc applications information overview the ltc2704 is a highly integrated device, greatly sim- plifying design and layout as compared to a design using multiple current output dacs and separate ampli? ers. a similar design using four separate current output dacs would require six precision op amps, compensation capaci- tors, bypass capacitors for each ampli? er, several times as much pcb area and a more complicated serial interface. still, it is important to avoid some common mistakes in order to achieve full performance. dc752a is the evalu- ation board for the ltc2704. it is designed to meet all data sheet speci? cations, and to allow the ltc2704 to be integrated into other prototype circuitry. all force/sense lines are available to allow the addition of current booster stages or other output circuits. the dc752a design is presented as a tutorial on properly applying the ltc2704. this board shows how to properly return digital and analog ground currents, and how to compensate for small differences in ground potential between the two banks of two dacs. there are other ways to ground the ltc2704, but the one requirement is that analog and digital grounds be connected at the ltc2704 by a very low impedance path. it is not advisable to split the ground planes and connect them with a jumper or inductor. when in doubt, use a single solid ground plane rather than separate planes. the ltc2704 does allow the ground potential of the dacs to vary by 300mv with respect to analog ground, allowing compensation for ground return resistance. power supply grounding and noise ltc2704 v + and v C pins are the supplies to all of the output ampli? ers, ground sense ampli? ers and reference inversion ampli? ers. these ampli? ers have good power supply rejection, but the v + and v C supplies must be free from wideband noise. the best scheme is to pre? lter low noise regulators such as the lt ? 1761 (positive) and lt1964 (negative). refer to linear technology application note 101, minimizing switching regulator residue in linear regulator outputs. the ltc2704 v dd pin is the supply for the digital logic and analog dac switches and is very sensitive to noise. it must be treated as an analog supply. the evaluation board uses an lt1790 precision reference as the v dd supply to minimize noise. the gnd pin is the return for digital currents and the agnd pin is a bias point for internal analog circuitry. both of these pins must be tied to the same point on a quiet ground plane. each dac has a separate ground sense pin that can be used to compensate for small differences in ground potential within a system. since dacs a and b are associated with ref1 and dacs c and d are associated with ref2, the grounds must be grouped together as follows: agnda, agndb and refg1 tied together (gnd1 on dc752a) agndc, agndd and refg2 tied together (gnd2 on dc752a) this scheme allows compensation for ground return ir drops, as long as the resistance is shared by both dacs in a group. this implies that the ground return for dacs a and b must be as close as possible, and gnd1 must be connected to this point through a low current, low resistance trace. (similar for dacs c and d.) figure 3 shows the top layer of the evaluation board. the gnd1 trace connects refg1, agnda, agndb and the ground pin of the lt1236 precision reference (u4.) this point is the ground reference for dacs a and b. the gnd2 trace connects refg2, agndc, agndd and the ground pin of the other lt1236 precision reference (u5). this point is the ground reference for dacs c and d. voltage reference a high quality, low noise reference such as the lt1236 or lt1027 must be used to achieve full performance. the ground terminal of this reference must be connected directly to the common ground point. if gnd1 and gnd2 are separate, then two references must be used.
ltc2704 18 2704fc voltage output/feedback and compensation the ltc2704 provides separate voltage output and feedback pins for each dac. this allows compensation for resistance between the output and load, or a current boosting stage such as an lt1970 may be inserted without affecting ac- curacy. when outx is connected directly to rfbx and no gnd1 trace, separated from agnd under ltc2704 exposed ground plane around edge allows grounding to prototype circuits 2704 f03 gnd2 trace, separated from agnd under ltc2704 cutout prevents digital return currents from coupling into analog ground plane. note that there is a plane in this region on layer 3 2704 f04 figure 3. dc752 top layer figure 4. dc752 analog ground layer. no currents are returned to this plane, so it may be used as a reference point for precise voltage measurements additional capacitance is present, the internal frequency compensation is suf? cient for stability and is optimized for fast settling time. if a low bandwidth booster stage is used, then a compensation capacitor from outx to c1x may be required. similarly, extra compensation may be required to drive a heavy capacitive load. applications information
ltc2704 19 2704fc digital return currents flow in this region 2704 f05 v outa and v outb load return currents flow in this region when jp8 is set to tie v outc and v outd load return currents flow in this region when jp9 is set to tie power and load return currents flow in this region small ground pour allows low impedance bypassing of v + and v C 2704 f06 figure 5. dc752a load return, power return and digital return figure 6. dc752a routing, bypass applications information
ltc2704 20 2704fc package description gw package 44-lead plastic ssop (wide .300 inch) (reference ltc dwg # 05-08-1642) g44 ssop 0204 0 ? 8 typ 0.355 ref 0.231 ? 0.3175 (.0091 ? .0125) 0.40 ? 1.27 (.015 ? .050) 7.417 ? 7.595** (.292 ? .299) 45 0.254 ? 0.406 (.010 ? .016) 2.286 ? 2.388 (.090 ? .094) 0.1 ? 0.3 (.004 ? .0118) 2.44 ? 2.64 (.096 ? .104) 0.800 (.0315) bsc 0.28 ? 0.51 (.011 ? .02) typ 17.73 ? 17.93* (.698 ? .706) 1 2 3 4 5 6 7 8 9 101112131415161718192021 10.11 ? 10.55 (.398 ? .415) 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 dimension does not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side * dimension does not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side ** millimeters (inches) note: 1. controlling dimension: millimeters 2. dimensions are in 10.804 min recommended solder pad layout 7.75 ? 8.258 23 44 22 1 0.800 bsc 0.520 0.0635 1.40 0.127
ltc2704 21 2704fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 10/09 title change to block diagram electrical characteristics text changes to analog outputs section text and figure deletion in operation section 1 3 16 c 08/10 revised note 1 to remove power supply sequencing reference changed dac a to dac n in table 1 5 12 (revision history begins at rev b)
ltc2704 22 2704fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0810 rev c ? printed in usa related parts typical application part number description comments lt ? 1019 precision reference ultralow drift, 3ppm/c, 0.05% accuracy lt1236 precision reference ultralow drift, 10ppm/c, 0.05% accuracy ltc1588/ltc1589 ltc1592 12-/14-/16-bit, serial, softspan i out dacs software-selectable spans, 1lsb inl/dnl ltc1595 16-bit serial multiplying i out dac in so-8 1lsb max inl/dnl, low glitch, dac8043 16-bit upgrade ltc1596 16-bit serial multiplying i out dac 1lsb max inl/dnl, low glitch, ad7543/dac8143 16-bit upgrade ltc1597 16-bit parallel, multiplying dac 1lsb max inl/dnl, low glitch, 4 quadrant resistors ltc1650 16-bit serial v out dac low power, low gritch, 4-quadrant multiplication ltc1857/ltc1858 ltc1859 12-/14-/16-bit, serial 100ksps softspan adc software-selectable spans, 40mw, fault protected to 25v lt1970 500ma power op amp adjustable sink/source current limits evaluation board schematic. force/sense lines allow for remote sensing and optimal grounding ldac cs /ld sdi sro sck clr rflag refg1 ref1 refm1 refg2 ref2 refm2 v dd gnd agnd cs /ld sdi sro sck vosa c1a rfba outa agnda vosb c1b rfbb outb agndb vosc c1c rfbc outc agndc vosd c1d rfbd outd agndd 9 10 11 12 13 14 35 4 5 7 6 3 40 39 37 38 41 27 28 30 29 26 19 18 16 17 20 2 43 44 21 24 23 14 33 32 v + 1 25 42 1,8,15,22,31,36 v + 2 v C ltc2704 ldac vosa vosb gnd1 gnd1 gnd2 outa 1 2 3 bav99lt1 bav99lt1 bav99lt1 tie remote outsa outa outsb outb outsc outc 10k v dd 10k v dd v dd v dd bat54s 0.1f 1f 1f 15v C15v 1f 1f clr refm1 gnd1 gnd2 refm2 spi interface rflag 1k v dd 1 2 3 1 2 3 1 2 3 v dd 5v regulator ref ref2 ref1 remote vosx 5v remote 5v 5v ref2 5v ref1 1 12 12 v s 2 4.7f 0.1f 7v 15v 12 3 v in 6 4 v out lt1790acs6-5 gnd gnd vosc outb tie remote outc tie remote 1 2 3 1 2 3 gnd2 bav99lt1 outsd outd vosd outd tie remote 1 2 3 gnd2 tie remote bat54s gnd2 1 2 3 3 2 1 gnd1 tie remote bat54s gnd1 1 2 3 3 2 1 v in 6 5 4 2 v out trim lt1236acs8-5 gnd 0.1f 4.7f gnd1 v s 5v ref1 15v 15v C15v C15v 4.7f 25v 4.7f 25v v in 6 5 4 2 v out trim lt1236acs8-5 gnd 0.1f 4.7f gnd2 v s 5v ref2 refx offset adjustment for vosa, vosb, vosc, vosc 20k refmx 2704 ta01a

▲Up To Search▲

Price & Availability of LTC2704CGW-14PBF

	To Download LTC2704CGW-14PBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .