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xicor, inc. 2000 patents pending 7026 10/27/00 ep characteristics subject to change without notice. 1 of 14 block diagram serial e 2 prom data and address (sda) scl s 2 s 1 s 0 wp command decode and control logic device select logic write protect logic page decode logic data register y decode logic e 2 prom write voltage control array 8k x 8 64k x24641 8k x 8 bit 400 khz 2-wire serial e 2 prom features ? 1.8v to 3.6v, 2.5v to 5.5v and 4.5v to 5.5v power supply operation ? low power cmos active read current less than 1ma active write current less than 3ma standby current less than 1a ? 400khz fast mode 2-wire serial interface down to 1.8v schmitt trigger input noise suppression output slope control for ground bounce noise elimination ? internally organized 8k x 8 ? 32 byte page write mode minimizes total write time per byte ? hardware write protect ? bidirectional data transfer protocol ? self-timed write cycle typical write cycle time of 5ms ? high reliability endurance: 1,000,000 cycles data retention: 100 years ? 8-lead soic description the x24641 is a cmos serial e 2 prom memory, internally organized 8k x 8. the device features a serial interface and software protocol allowing opera- tion on a simple two wire bus. the bus operates at 400khz all the way down to 1.8v. three device select inputs (s 0 Cs 2 ) allow up to eight devices to share a common two wire bus. hardware write protection is provided through a write protect (wp) input pin on the x24641. when the wp pin is high, the upper quadrant of the serial e 2 prom array is protected against any nonvolatile write attempts. xicor serial e 2 prom memories are designed and tested for applications requiring extended endurance. inherent data retention is greater than 100 years.
x24641 characteristics subject to change without notice. 2 of 14 pin descriptions serial clock (scl) the scl input is used to cloc k all data into and out of the de vice . serial data (sda) sd a is a bidirectional pin used to tr ansf er data into and out of the de vice . it is an open dr ain output and ma y be wire-ored with an y n umber of open dr ain or open col- lector outputs . an open dr ain output requires the use of a pull-up resis- tor . f or selecting typical v alues , ref er to the pull-up resistor selection g r aph at the end of this data sheet. device select (s 0 , s 1 , s 2 ) the de vice select inputs (s 0 , s 1 , s 2 ) are used to set the ? rst three bits of the 8-bit sla v e address . this allo ws up to eight de vices to share a common b us . these inputs can be static or activ ely dr iv en. if used statically the y m ust be tied to v ss or v cc as appropr i- ate . if activ ely dr iv en, the y m ust be dr iv en with cmos le v els . write protect (wp) the wr ite protect input controls the hardw are wr ite protect f eature . when held lo w , hardw are wr ite pro- tection is disab led and the de vice can be wr itten nor- mally . when this input is held high, wr ite protection is enab led, and non v olatile wr ites are disab led to the upper quadr ant of the e 2 pr om arr a y . pin names pin configuration device operation the de vice suppor ts a bidirectional, b us or iented pro- tocol. the protocol de? nes an y de vice that sends data onto the b us as a tr ansmitter , and the receiving de vice as the receiv er . the de vice controlling the tr ansf er is a master and the de vice being controlled is the sla v e . the master will alw a ys initiate data tr ansf ers , and pro- vide the cloc k f or both tr ansmit and receiv e oper ations . theref ore , the de vice will be considered a sla v e in all applications . clock and data conventions data states on the sd a line can change only dur ing scl lo w . sd a state changes dur ing scl high are reser v ed f or indicating star t and stop conditions . ref er to figures 1 and 2. symbol description s 0 , s 1 , s 2 device select inputs sda serial data scl serial clock wp write protect v ss ground v cc supply voltage v cc wp scl sda s 0 s 1 s 2 v cc 1 2 3 4 8 7 6 5 x24641 8-lead soic figure 1. data validity scl sda data stable data change
x24641 characteristics subject to change without notice. 3 of 14 figure 2. definition of start and stop scl sda start bit stop bit start condition all commands are preceded b y the star t condition, which is a high to lo w tr ansition of sd a when scl is high. the de vice contin uously monitors the sd a and scl lines f or the star t condition and will not respond to an y command until this condition has been met. stop condition all comm unications m ust be ter minated b y a stop con- dition, which is a lo w to high tr ansition of sd a when scl is high. the stop condition is also used to place the de vice into the standb y po w er mode after a read sequence . a stop condition can only be issued after the tr ansmitting de vice has released the b us . acknowledge ac kno wledge is a softw are con v ention used to indicate successful data tr ansf er . the tr ansmitting de vice , either master or sla v e , will release the b us after tr ansmitting eight bits . dur ing the ninth cloc k cycle the receiv er will pull the sd a line lo w to ac kno wledge that it receiv ed the eight bits of data. ref er to figure 3. the de vice will respond with an ac kno wledge after rec- ognition of a star t condition and its sla v e address . if both the de vice and a wr ite oper ation ha v e been selected, the de vice will respond with an ac kno wledge after the receipt of each subsequent b yte . in the read mode the de vice will tr ansmit eight bits of data, release the sd a line and monitor the line f or an ac kno wledge . if an ac kno wledge is detected and no stop condition is gener ated b y the master , the de vice will contin ue to tr ansmit data. if an ac kno wledge is not detected, the de vice will ter minate fur ther data tr ans- missions . the master m ust then issue a stop condition to retur n the de vice to the standb y po w er mode and place the de vice into a kno wn state . figure 3. acknowledge response from receiver scl from master data output from transmitter 1 8 9 from receiver start acknowledge data output
x24641 characteristics subject to change without notice. 4 of 14 device addressing f ollo wing a star t condition, the master m ust output the address of the sla v e it is accessing. the ? rst f our bits of the sla v e address byte are the de vice type identi? er bits . these m ust equal 1010. the ne xt 3 bits are the de vice select bits s 0 , s 1 , and s 2 . this allo ws up to 8 de vices to share a single b us . these bits are compared to the s 0 , s 1 , and s 2 de vice select input pins . the last bit of the sla v e address byte de? nes the oper ation to be perf or med. when the r/ w bit is a one , then a read oper ation is selected. when it is z ero then a wr ite oper ation is selected. ref er to figure 4. after loading the sla v e address byte from the sd a b us , the de vice compares the de vice type bits with the v alue 1010 and the de vice select bits with the status of the de vice select input pins . if the compare is not successful, no ac kno wledge is output dur ing the ninth cloc k cycle and the de vice retur ns to the standb y mode . the b yte address is either supplied b y the master or obtained from an inter nal counter , depending on the oper ation. when required, the master m ust supply the tw o address bytes as sho wn in figure 4. the inter nal organization of the e 2 pr om arr a y is 256 pages b y 32 b ytes per page . the page address is par- tially contained in the address byte 1 and par tially in bits 7 through 5 of the address byte 0. the speci? c b yte address is contained in bits 4 through 0 of the address byte 0. ref er to figure 4. figure 4. device addressing 1 s 1 s 0 r / w device select 0 1 0 s 2 device type identifier slave address byte d7 d2 d1 d6 d5 d4 d3 data byte a2 a1 a0 a5 low order address a4 a3 address byte 0 0 a10 a9 a8 0 high order word address a11 address byte 1 0 a12 a7 a6 d0
x24641 characteristics subject to change without notice. 5 of 14 write operations byte write f or a byte wr ite oper ation, the de vice requires the sla v e address byte , the w ord address byte 1, and the w ord address byte 0, which giv es the master access to an y one of the b ytes in the arr a y . upon receipt of the w ord address byte 0, the de vice responds with an ac kno wledge , and w aits f or the ? rst eight bits of data. after receiving the 8 bits of the data b yte , the de vice again responds with an ac kno wledge . the master then ter minates the tr ansf er b y gener ating a stop condition, at which time the de vice begins the inter nal wr ite cycle to the non v olatile memor y . while the inter nal wr ite cycle is in prog ress the de vice inputs are disab led and the de vice will not respond to an y requests from the master . the sd a pin is at high impedance . see figure 4. page write operation the de vice e x ecutes a thir ty-tw o b yte p age wr ite oper ation. f or a p age wr ite oper ation, the de vice requires the sla v e address byte , address byte 1, and address byte 0. address byte 0 m ust contain the ? rst b yte of the page to be wr itten. upon receipt of address byte 0, the de vice responds with an ac kno wledge , and w aits f or the ? rst eight bits of data. after receiving the 8 bits of the ? rst data b yte , the de vice again responds with an ac kno wledge . the de vice will respond with an ac kno wledge after the receipt of each of 31 more b ytes . each time the b yte address is inter nally incre- mented b y one , while page address remains constant. when the counter reaches the end of the page , the master ter minates the data loading b y issuing a stop condition, which causes the de vice to begin the non v ol- atile wr ite cycle . all inputs are disab led until completion of the non v olatile wr ite cycle . the sd a pin is at high impedance . ref er to figure 5 f or the address , ac kno wl- edge , and data tr ansf er sequence . figure 5. byte write sequence figure 6. page write sequence signals from the master sda bus signals from s t a r t slave address s t o p a c k a c k a c k a c k word address byte 1 data 1 0 1 0 0 word address byte 0 s p the slave s t a r t slave address s t o p a c k a c k a c k a c k word address byte 1 word address byte 0 0 s p data signals from the master sda bus signals from the slave 1 0 0 1
x24641 characteristics subject to change without notice. 6 of 14 acknowledge polling the maxim um wr ite cycle time can be signi? cantly reduced using ac kno wledge p olling. t o initiate ac kno wledge p olling, the master issues a star t condi- tion f ollo w ed b y the sla v e address byte f or a wr ite or read oper ation. if the de vice is still b usy with the non- v olatile wr ite cycle , then no a ck will be retur ned. if the de vice has completed the non v olatile wr ite oper ation, an a ck will be retur ned and the host can then proceed with the read or wr ite oper ation. ref er to figure 7. figure 7. acknowledge polling sequence read operations read oper ations are initiated in the same manner as wr ite oper ations with the e xception that the r/ w bit of the sla v e address byte is set to one . there are three basic read oper ations: current address reads , ran- dom reads , and sequential reads . current address read inter nally , the de vice contains an address counter that maintains the address of the last b yte read or wr itten, incremented b y one . after a read oper ation from the last address in the arr a y , the counter will roll o v er to the ? rst address in the arr a y . after a wr ite oper ation to the last address in a giv en page , the counter will roll o v er to the ? rst address of the same page . upon receipt of the sla v e address byte with the r/ w bit set to one , the de vice issues an ac kno wledge and then tr ansmits the b yte at the current address . the master ter minates the read oper ation when it does not respond with an ac kno wledge dur ing the ninth cloc k and then issues a stop condition. ref er to figure 8 f or the address , ac kno wledge , and data tr ansf er sequence . it should be noted that the ninth cloc k cycle of the read oper ation is not a dont care . t o ter minate a read oper ation, the master m ust either issue a stop condi- tion dur ing the ninth cycle or hold sd a high dur ing the ninth cloc k cycle and then issue a stop condition. figure 8. current address read sequence byte load completed by issuing stop enter ack polling issue start issue slave address byte (read or write) ack returned? nonvolatile write cycle complete. continue sequence? continue normal read or write command sequence proceed issue stop no yes yes issue stop no s t a r t slave address s t o p a c k data 1 s p 0 1 0 1 signals from the master sda bus signals from the slave
x24641 characteristics subject to change without notice. 7 of 14 random read random read oper ation allo ws the master to access an y memor y location in the arr a y . pr ior to issuing the sla v e address byte with the r/ w bit set to one , the master m ust ? rst perf or m a dumm y wr ite oper ation. the master issues the star t condition and the sla v e address byte with the r/ w bit lo w , receiv es an ac kno wledge , then issues address byte 1, receiv es another ac kno wledge , then issues address byte 0 con- taining the address of the b yte to be read. after the de vice ac kno wledges receipt of address byte 0, the master issues another star t condition and the sla v e address byte with the r/ w bit set to one . this is f ol- lo w ed b y an ac kno wledge and then eight bits of data from the de vice . the master ter minates the read oper- ation b y not responding with an ac kno wledge and then issuing a stop condition. ref er to figure 9 f or the address , ac kno wledge , and data tr ansf er sequence . the de vice will perf or m a similar oper ation called set current address if a stop is issued instead of the sec- ond star t sho wn in figure 9. the de vice will go into standb y mode after the stop and all b us activity will be ignored until a star t is detected. the eff ect of this oper- ation is that the ne w address is loaded into the address counter , b ut no data is output b y the de vice . the ne xt current address read oper ation will read from the ne wly loaded address . sequential read sequential reads can be initiated as either a current address read or r andom read. the ? rst b yte is tr ansmit- ted as with the other modes; ho w e v er , the master no w responds with an ac kno wledge , indicating it requires additional data. the de vice contin ues to output data f or each ac kno wledge receiv ed. the master ter minates the read oper ation b y not responding with an ac kno wl- edge and then issuing a stop condition. the data output is sequential, with the data from address n f ollo w ed b y the data from address n + 1. the address counter f or read oper ations increments through all b yte addresses , allo wing the entire memor y contents to be read dur ing one oper ation. at the end of the address space the counter rolls o v er to address 0000h and the de vice contin ues to output data f or each ac kno wledge receiv ed. ref er to figure 9 f or the ac kno wledge and data tr ansf er sequence . figure 9. random read sequence figure 10. sequential read sequence s t a r t slave address s t o p a c k a c k a c k word address byte 1 slave address 0 words address byte 0 s t a r t 1 data a c k s p s 1 0 1 0 signals from the master sda bus signals from the slave slave address s s t o p a c k a c k a c k a c k data (1) data (2) data (nC1) data (n) 1 p signals from the master sda bus signals from the slave
x24641 characteristics subject to change without notice. 8 of 14 absolute maximum ratings t emper ature under bias x24641 ........... C65 to +135 c stor age temper ature ............................. C65 to +150 c v oltage on an y pin with respect to v ss ....... C1v to +7v d .c . output current ............................................... 5ma lead temper ature (solder ing, 10 seconds) ......... 300 c comment stresses abo v e those listed under absolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only; at these or an y other condi- tions abo v e those indicated in the oper ational sections of this speci? cation is not implied. exposure to abso- lute maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability . recommended operating conditions temperature min. max. commercial 0 c +70 c industrial C40 c +85 c supply voltage limits x24641 4.5v to 5.5v x24641C2.5 2.5v to 5.5v x24641C1.8 1.8v to 3.6v d.c. operating characteristics capacitance t a = +25c , f = 1mhz, v cc = 5v notes: (1) must perf or m a stop command pr ior to measurement. (2) v il min. and v ih max. are f or ref erence only and are not 100% tested. (3) this par ameter is per iodically sampled and not 100% tested. symbol parameter limits units test conditions min. max. i cc1 v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 400khz, sda = open, all other inputs = v ss or v cc C 0.3v i cc2 v cc supply current (write) 3 ma i sb1 (1) v cc standby current 3 m a scl = sda = v cc C 0.3v, all other inputs = v ss or v cc C 0.3v, v cc = 5v 10% i sb2 (1) v cc standby current 1 m a scl = sda = v cc C 0.1v, all other inputs = v ss or v cc C 0.1v, v cc = 1.8v i li input leakage current 10 m a v in = v ss to v cc i lo output leakage current 10 m a v out = v ss to v cc v ll (2) input low voltage C0.5 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma v hys (3) hysteresis of schmitt trigger inputs v cc x 0.05 v symbol parameter max. units test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (s 0 , s 1 , s 2 , scl,wp) 6 pf v in = 0v
x24641 characteristics subject to change without notice. 9 of 14 a.c. conditions of test equivalent a.c. load circuit input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 5v 1.53k w 100pf output a.c. operating characteristics (ov er the recommended oper ating conditions , unless otherwise speci? ed.) read & program cycle limits power-up timing (4) notes: (4) t pur and t puw are the dela ys required from the time v cc is stab le until the speci? ed oper ation can be initiated. these par ameters are per iodically sampled and not 100% tested. (5) c b = total capacitance of one b us line in pf (6) t aa = 1.1s max belo w v cc = 2.5v . symbol parameter min. max. units f scl scl clock frequency 0 400 khz t i noise suppression time constant at scl, sda inputs 50 ns t aa(6) scl low to sda data out valid 0.1 0.9 m s t buf time the bus must be free before a new transmission can start 1.2 m s t hd:sta start condition hold time 0.6 m s t low clock low period 1.2 m s t high clock high period 0.6 m s t su:sta start condition setup time (for a repeated start condition) 0.6 m s t hd:dat data in hold time 0 m s t su:dat data in setup time 100 ns t r sda and scl rise time 20+0.1xc b (5) 300 ns t f sda and scl fall time 20+0.1xc b (5) 300 ns t su:sto stop condition setup time 0.6 m s t dh data out hold time 50 ns t of output fall time 20 + 0.1c b (5) 250 ns symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 5 ms
x24641 characteristics subject to change without notice. 10 of 14 bus timing write cycle limits notes: (7) t ypical v alues are f or t a = 25c and nominal supply v oltage (5v). (8) t wr is the minim um cycle time to be allo w ed from the system perspectiv e unless polling techniques are used. it is the maxim um time the de vice requires to automatically complete the inter nal wr ite oper ation. the wr ite cycle time is the time from a v alid stop condition of a wr ite sequence to the end of the inter nal er ase/wr ite cycle . dur ing the wr ite cycle , the x24641 b us interf ace circuits are disab led, sd a is allo w ed to remain high, and the de vice does not respond to its sla v e address . bus timing symbol parameter min. typ. (6) max. units t wc (8) write cycle time 5 10 ms t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high scl sda 8th bit word n ack t wc stop condition start condition
x24641 characteristics subject to change without notice. 11 of 14 guidelines for calculating typical values of bus pull-up resistors symbol table 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k w ) bus capacitance (pf) min. resistance max. resistance rmax = cbus tr rmin = iol min vcc max =1.8k w waveform inputs outputs must be steady will be steady may change from lo w to high will change from lo w to high may change from high to low will change from high to low dont care: changes allo wed changing: state not kno wn n/a center line is high impedance
x24641 characteristics subject to change without notice. 12 of 14 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
x24641 characteristics subject to change without notice. 13 of 14 ordering information device x24641 x x -x v cc range blank = 5v 10% 2.5 = 2.5v to 5.5v temperature range blank = 0 c to +70 c i = C40 c to +85 c package x24641 s8= 8-lead soic 1.8 = 1.8v to 3.6v
x24641 characteristics subject to change without notice. 14 of 14 limited w arranty de vices sold b y xicor , inc. are co v ered b y the w arr anty and patent indemni? cation pro visions appear ing in its t er ms of sale only . xicor , inc. mak es no w arr anty , e xpress , statutor y , implied, or b y descr iption regarding the inf or mation set f or th herein or regarding the freedom of the descr ibed de vices from patent infr ingement. xicor , inc. mak es no w arr anty of merchantability or ? tness f or an y pur pose . xicor , inc. reser v es the r ight to discontin ue production and change speci? cations and pr ices at an y time and without notice . xicor , inc. assumes no responsibility f or the use of an y circuitr y other than circuitr y embodied in a xicor , inc. product. no other circuits , patents , or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered tr ademar ks of xicor , inc. a utostore , direct wr ite , bloc k loc k, ser ialflash, mps , and xdcp are also tr ademar ks of xicor , inc. all other s belong to their respectiv e o wners . u .s. p a tents xicor products are co v ered b y one or more of the f ollo wing u .s . p atents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. f oreign patents and additional patents pending. life rela ted policy in situations where semiconductor component f ailure ma y endanger lif e , system designers using this product should design the system with appropr iate error detection and correction, redundancy and bac k-up f eatures to pre v ent such an occurence . xicor s products are not author iz ed f or use in cr itical components in lif e suppor t de vices or systems . 1. lif e suppor t de vices or systems are de vices or systems which, (a) are intended f or surgical implant into the body , or (b) suppor t or sustain lif e , and whose f ailure to perf or m, when proper ly used in accordance with instr uctions f or use pro vided in the labeling, can be reasonab ly e xpected to result in a signi? cant injur y to the user . 2. a cr itical component is an y component of a lif e suppor t de vice or system whose f ailure to perf or m can be reasonab ly e xpected to cause the f ailure of the lif e suppor t de vice or system, or to aff ect its saf ety or eff ectiv eness . part mark convention x24641 x x blank = 8-lead soic blank = 4.5v to 5.5v, 0 c to +70 c i = 4.5v to 5.5v, C40 c to +85 c ae = 2.5v to 5.5v, 0 c to +70 c af = 2.5v to 5.5v, C40 c to +85 c ag = 1.8v to 3.6v, 0c to +70c ah = 1.8v to 3.6v, C40c to +85c

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