data sheet december 1997 revision 1.0 1 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh sob8uv6484-(67/84/100/125)t-s 64mbyte (8m x 64) cmos synchronous dram module general description the sob8uv6484-(67/84/100/125)t-s is a high performance, 64-megabtye synchronous, dynamic ram module organized as 8m words by 64 bits, in a 144-pin, small outline dual-in-line memory module (sodimm) package. the module utilizes eight fujitsu mb81164842a-(67/84/100/125) pftn cmos 8mx8 synchronous dynamic rams in surface mount package (tsop) on an epoxy laminated substrate. each device is accompanied by a decoupling capacitor for improved noise immunity. a 256 byte serial eeprom contains the module configuration information. features ? high density 64mbyte ? cycle time: 8ns (125 mhz), 10ns (100 mhz), 12ns (84 mhz), 15ns (67 mhz) ? low power: active 5.6w (125 mhz), 4.9w (100 mhz), 4.5w (84 mhz), 4.0w (67 mhz) ? lvttl-compatible inputs and outputs ? separate power and ground planes to improve noise immunity ? single power supply of 3.3v 0.3v ? height: 1.060 inch absolute maximum ratings recommended dc operating conditions (t a = 0 to +70 c) item symbol ratings unit voltage on any pin relative to v ss v t -0.5 to +4.6 v power dissipation p t 10.4 w operating temperature t opr 0 to +70 c storage temperate t stg -55 to +125 c short circuit output current i os 50 ma symbol parameter min typ max unit v cc supply voltage 3.0 3.3 3.6 v v ss ground 0 0 0 v v ih input high voltage 2.0 - v cc +0.5 v v il input low voltage -0.5 - 0.8 v
sob8uv6484-(67/84/100/125)t-s december 1997 revision 1.0 2 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh functional diagram notes: 1. a~a11 to all the devices. 2. clks are terminated using 10 ohm series resistors. 3. a0~a2 of serial pd eeprom are grounded. 4. each 8mx16 block comprises two 8mx8 sdrams. 5. dqms vs data i/os dqmb0 controls dq0 ~ dq7 dqmb1 controls dq8 ~ dq15 dqmb2 controls dq16 ~ dq23 dqmb3 controls dq24 ~ dq31 dqmb4 controls dq32 ~ dq39 dqmb5 controls dq40 ~ dq47 dqmb6 controls dq48 ~ dq55 dqmb7 controls dq56 ~ dq63 6. clock wiring dqmb7 dqmb6 dqmb5 dqmb4 dqmb3 dqmb2 dqmb1 dqmb0 ras* cas* clk0 dq0~dq15 dq48~dq63 dq32~dq47 dq16~dq31 dq0~dq63 scl scl sda eeprom sda v cc v ss decoupling capacitors to all devices (all specifications of the device are subject to change without notice.) 8m x 16 block 8m x 16 block 8m x 16 block 8m x 16 block cs0* cke0 0.01 m f we ba0 ba1 clk1 clk0,clk1 sdram1 sdram2 10 w sdram3 sdram4 10 w
december 1997 revision 1.0 sob8uv6484-(67/84/100/125)t-s 3 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh pin name a0~a11 row addresses dqmb0-dqmb7 dq mask enables a0~a8 column addresses cs0* chip select ba0, ba1 bank select address we* write enable dq0~dq63 data inputs/outputs scl serial clock clk0, clk1 clock inputs sda serial data input/output ras* row address strobes v cc power supply cas* column address strobes v ss ground cke0 clock enables nc no connection notes: 1. address a10 : initiates auto-precharge 2. address ba0,ba1 : bank select within the sdram devices. pin no. pin designation pin no. pin designation pin no. pin designation pin no. pin designation 1 v ss 2 v ss 73 nc 74 clk1 3 dq0 4 dq32 75 v ss 76 v ss 5 dq1 6 dq33 77 nc 78 nc 7 dq2 8 dq34 79 nc 80 nc 9 dq3 10 dq35 81 v cc 82 v cc 11 v cc 12 v cc 83 dq16 84 dq48 13 dq4 14 dq36 85 dq17 86 dq49 15 dq5 16 dq37 87 dq18 88 dq50 17 dq6 18 dq38 89 dq19 90 dq51 19 dq7 20 dq39 91 v ss 92 v ss 21 v ss 22 v ss 93 dq20 94 dq52 23 dqmb0 24 dqmb4 95 dq21 96 dq53 25 dqmb1 26 dqmb5 97 dq22 98 dq54 27 v cc 28 v cc 99 dq23 100 dq55 29 a0 30 a3 101 v cc 102 v cc 31 a1 32 a4 103 a6 104 a7 33 a2 34 a5 105 a8 106 ba0 (note) 35 v ss 36 v ss 107 v ss 108 v ss 37 dq8 38 dq40 109 a9 110 ba1 (note) 39 dq9 40 dq41 111 a10/ap (note) 112 a11 41 dq10 42 dq42 113 v cc 114 v cc 43 dq11 44 dq43 115 dqmb2 116 dqmb6 45 v cc 46 v cc 117 dqmb3 118 dqmb7 47 dq12 48 dq44 119 v ss 120 v ss 49 dq13 50 dq45 121 dq24 122 dq56 51 dq14 52 dq46 123 dq25 124 dq57 53 dq15 54 dq47 125 dq26 126 dq58 55 v ss 56 v ss 127 dq27 128 dq59 57 nc 58 nc 129 v cc 130 v cc 59 nc 60 nc 131 dq28 132 dq60 61 clk0 62 cke0 133 dq29 134 dq61 63 v cc 64 v cc 135 dq30 136 dq62 65 ras* 66 cas* 137 dq31 138 dq63 67 we* 68 nc 139 v ss 140 v ss 69 cs0* 70 nc 141 sda 142 scl 71 nc 72 nc 143 v cc 144 v cc
sob8uv6484-(67/84/100/125)t-s december 1997 revision 1.0 4 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh serial pd information byte# function described function supported hex value 0 # bytes written into serial memory at module mfr 128 bytes 80h 1 total # bytes of spd memory device 256 bytes 08h 2 fundamental memory type sdram 04h 3 # row address on this assembly 12 0ch 4 # column addresses on this assembly 9 09h 5 # module banks on this assembly 1 01h 6 data width of this assembly 64 bits 40h 7 data width of this assembly (continued) 00h 8 voltage interface standard of this assembly lvttl 01h 9 sdram cycle time at cl=3 (tclk) 8ns 80h 10ns a0h 12ns c0h 15ns f0h 10 sdram access from clock at cl=3 (tac) 7.5ns 75h 8.5ns 85h 8.5ns 85h 9.0ns 90h 11 dimm configuration type non-parity 00h 12 refresh rate/type s/r, normal 15.6 m s 80h 13 sdram width primary dram x8 08h 14 ecc sdram data width n/a 00h 15 min. clock delay, back to back random column addresses (iccd) 1clk 01h 16 burst length supported 1, 2, 4, 8 & full 8fh 17 # banks on each sdram device 4 04h 18 cas# latency 2, 3 06h 19 cs# latency 0 01h 20 write latency 0 01h 21 sdram module attribute non-buffered/registered 00h 22 sdram device attribute vcc, b/r, s/w, p/a, a/p 0eh 23 min clock cycle time at cl=2 (tclk) 12ns c0h 15ns f0h 17ns 20h 24 max. data access time from clock at cl=2 (tac) 9.0ns 90h 9.0ns 90h 10ns a0h 10ns a0h 25 min clock cycle time at cl=1 (tclk) n/a 00h 26 max. data access time from clock at cl=1 (tac) n/a 00h 27 min. row precharge time (trp) 29ns 1dh 30ns 1eh 35ns 23h 40ns 28h 28 min. row active delay (trrd) 16ns 10h 20ns 14h 20ns 14h 20ns 14h 29 min. ras to cas delay (trcd) 24ns 18h 30ns 1eh 30ns 1eh 30ns 1eh 30 min. ras pulse width (tras) 48ns 30h 60ns 3ch 65ns 41h 70ns 46h 31 module bank density 64mb 10h 32-61 superset information 00h 62 spd revision rev. 1 01h 63 checksum for bytes 0-62 64-127 manufacturer?s information 128+ unused storage locations
december 1997 revision 1.0 sob8uv6484-(67/84/100/125)t-s 5 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh dc characteristics (v cc = 3.3v 0.3v, v ss = 0v, t a = 0 to +70 ) ?cl = cas* latency notes: 1. i cc depends on output load condition when the device is selected i cc (max.) is specified at the output open condition. 2. an initial pulse of 200 m s is required after power-up followed by a minimum of eight auto-refresh-cycles. capacitance (ta =+25 c, vcc = 3.3v 0.3v) notes: 1. capacitance is measured with boonton meter or effective capacitance method. 2. cas* - v ih to disable d out . parameter symbol test condition 125 100 84 67 unit note min. max. min. max. min. max. min. max. operating current i cc1 no burst, t ck = min. t rc = min. - 720 - 640 - 600 - 560 ma 1, 2 no burst, t ck = min., t rc = min. all banks active - 1280 - 1120 - 1040 - 960 ma 1, 2 precharge standby current i cc2 cke -v il , t ck = min. all banks idle - 16 - 16 - 16 - 16 ma 1, 2 cke = v ih , t ck = min. all banks idle - 160 - 160 - 160 - 160 ma 1.2 active standby current i cc3 cke = v il , t ck = min. any bank active - 40 - 40 - 40 - 40 ma 1, 2 cke = v ih , t ck = min. any bank active - 200 - 200 - 200 - 200 ma 1, 2 burst mode current i cc4 t ck = min. - 1100 - 960 - 920 - 680 ma 1, 2 refresh current i cc5 t ck = min., t rc = min., t rrd = min. auto refresh - 1560 - 1360 - 1240 - 1120 ma 1, 2 self refresh current i cc6 cke - v il - 16 - 16 - 16 - 16 ma 1, 2 input leakage i li 0v v in v cc -180 180 -180 180 -180 180 -180 180 m a output leakage current i lo 0v v out v cc d out = disable -10 10 -10 10 -10 10 -10 10 m a output high voltage v oh high i out = -2ma 2.4 - 2.4 - 2.4 - 2.4 - v output low voltage v ol low i out = 2 ma - 0.4 - 0.4 - 0.4 - 0.4 v parameter symbol max. unit note input capacitance (address, we*, ras*, cas*) c i1 45 pf 1 input capacitance (dqmbs) c i2 10 pf 1 input capacitance (cs0*, cke0) c i3 45 pf 1 input capacitance (clk0,clk1) c i4 25 pf 1 input/output capacitance (dq0~dq63) c i/o 12 pf 1, 2
sob8uv6484-(67/84/100/125)t-s december 1997 revision 1.0 6 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh ac characteristics (ta = 0 to +70 c, v cc = 3.3v 0.3v, v ss = 0v ) notes: 1. an initial pulse of at least 200 m s is required after power-up followed by a minimum of eight auto refresh cycles. 2. ac characteristics assume t t = 1ns and 50pf capacitive load. if t t is longer than 1ms, reference level for measuring time of input signal is v ih (min.) and v il (max.). 3. 1.4v is the reference level for measuring timing of input signals. 4. t hz and t oh defines the time at which the outputs achieve 200mv. 5. actual clock output of t rc will be sum clock of t ras and t rp . 6. 20ns is not supported in spd. parameter symbol unit 125 100 84 67 notes clock period cl=3 t ck ns 8 - 10 - 12 - 15 - 1, 2, 3, 6 cl=2 12 - 15 - 17 - 20 - transition time t t ns 0.5 2 0.5 2 0.5 2 0.5 2 1, 2, 3 clock high time t ch ns 3.5 - 3.5 - 4 - 4 - 1, 2, 3 clock low time t cl ns 3.5 - 3.5 - 4 - 4 - 1, 2, 3 input setup time t si ns 2.5 - 3.0 - 3.0 - 3.0 - 1, 2, 3 input hold time t hi ns 1.0 - 1.0 - 1.0 - 1.0 - 1, 2, 3 output valid from clock cl=3 t ac ns - 7.5 - 8.5 - 8.5 - 9.0 1, 2, 3 cl=2 - 9 - 9 - 10 - 10 output in low-z t lz ns 2 - 3 - 3 - 3 - 1, 2, 3 output in high-z t hz ns 2 - 3 - 3 - 3 - 1, 2, 3, 4 output hold time t oh ns 2 - 3 - 3 - 3 - 1, 2, 3 time between refresh t ref ms - 65.6 - 65.6 - 65.6 - 65.6 1, 2, 3 ras cycle time t rc ns 77 - 90 - 100 - 110 - 1, 2, 3, 5 ras access time t rac ns - 45 - 54 - 56 - 60 1, 2, 3 cas access time t cac ns - 21 - 24 - 26 - 30 1, 2, 3 ras precharge time t rp ns 29 - 30 - 35 - 40 - 1, 2, 3 ras active time t ras ns 48 100000 60 100000 65 100000 70 100000 1, 2, 3 ras to cas delay time t rcd ns 24 - 30 - 30 - 30 - 1, 2, 3 write recovery time t wr ns 8 - 10 - 12 - 15 - 1, 2, 3 ras to ras delay time t rrd ns 16 - 20 - 20 - 20 - 1, 2, 3 power-down exit time t pde ns 3 - 3 - 4 - 5 - 1, 2, 3 cke to clock disable i cke cycle 1 1 1 1 dqm to output in high-z i dqz cycle 2 2 2 2 dqm to input data delay i dqd cycle 0 0 0 0 last output to write command delay i owd cycle 2 2 2 2 write command to input data delay i dwd cycle 0 0 0 0 precharge to output in high-z delay cl=3 i roh cycle 3 3 3 3 cl=2 2 2 2 2 burst stop command to output in high-z delay cl=3 i bsh cycle 3 3 3 3 cl=2 2 2 2 2 mode register access to bank active (min.) i mrd cycle 2 2 2 2 cas to cas delay i ccd cycle 1 1 1 1 cas bank delay i cbd cycle 1 1 1 1 write to precharge read delay cl=3 i rwl cycle 1 1 1 1 cl=2 1 1 1 1
december 1997 revision 1.0 sob8uv6484-(67/84/100/125)t-s 7 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh physical dimensions 144-pin (72x2) dimm 1 . 0 6 0 0 . 7 8 7 0.158x2 2.661 0.181 0.130 t.b.d. 0.040 0.004 front view 1 143 1.291 0.913 0.145 2 144 back view 2.503 d a t u m 0.098 0.083 0.031 ( all dimensions are in inches with 0.005" tolerance unless otherwise specified) ? 070x2 0 . 2 3 6 detail ?a? ?a? 0.157 0.100 0.024 0.010 0.098 0.031 0.157 0.059 t. b. d t. b. d
sob8uv6484-(67/84/100/125)t-s december 1997 revision 1.0 8 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh (1) memory type s : sdram g : sgram (2) module shape s : simm d : dimm o : small outline dimm (3) module pin count a : 72-pin b : 144-pin c : 168-pin d : 200-pin (4) word depth 1 : 1m 2 : 2m 4 : 4m 8 : 8m 256 : 256k 512 : 512k . (5) buffer type b : buffered u : unbuffered (6) operating voltage v : 3,3v (7) data width (ex. 64=x64, 72=x72 etc.) (8) device configuration 4 : x4 8 : x8 1 : x16 3 : x32 (8a) refresh 2 : 2krf 4 : 4krf s o b 8 u v 64 8 4 - 100 t - s (1) (2) (3) (4) (5) (6) (7) (8) (8a) (9) (10) (11) (12) (13) (14) (15) ordering information (9) interface level blank : lvttl s : sstl (10) module revision / applied ?standard? *1 blank : rev. 0 a : rev. 1 b : rev. 2 (etc.) *1 when dram device or pcb is revised, the revision is changed (11) power consumption blank : standard l : low power (12) clock frequency 67 : 67mhz 84 : 84mhz 100 : 100mhz 125 : 125mhz (13) package of component j : soj t : tsop (14) private brand name *2 blank : common products g : fmg brand *2 this column is applicable to custom modules, not applicable to jedec standard commodity products (15) assembly & test site s : smart modular technologies
december 1997 revision 1.0 sob8uv6484-(67/84/100/125)t-s 9 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh ? fujitsu limited 1997 printed in germany japan north and south america europe asia fujitsu microelectronics, inc. 3545 north first street san jose, ca 95134-1804, usa. tel: 408-922-9000 fax: 408-432-9044, 9045 fujitsu microelectronics asia pte limited #05-08, 151 lorong chuan newtechpark singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich?buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 fujitsu limited memory marketing dept. 4-1-1, kamikodanaka nakahara-ku, kawasaki 211-88, japan tel: (044)754-3767 fax: (044)754-3343 for further information please contact: fujitsu limited all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor appli- cations. complete information sufficient for construction purposes is not necessarily given. the information given in this document have been care- fully checked and is believed to be reliable. however, fujitsu assumes no responsibility for inaccuracies. the information contained in this document does not convey any licence under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifi- cations without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equip- ments, undersea repeaters, nuclear control systems or medical equipments for life support.
|
