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ltc2268-14/ ltc2267-14/ltc2266-14 1 22687614fa typical a pplica t ion descrip t ion 14-bit, 125msps/105msps/ 80msps low power dual adcs the ltc ? 2268-14/ltc2267-14/ltc2266-14 are 2-channel, simultaneous sampling 14-bit a/d converters designed for digitizing high frequency, wide dynamic range signals. they are perfect for demanding communications applica - tions with ac performance that includes 73.1db snr and 88db spurious free dynamic range (sfdr). ultralow jitter of 0.15ps rms allows undersampling of if frequencies with excellent noise performance. dc specs include 1lsb inl (typ), 0.3lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 1.2lsb rms . the digital outputs are serial lvds to minimize the num - ber of data lines. each channel outputs two bits at a time (2-lane mode). at lower sampling rates there is a one bit per channel option (1-lane mode). the lvds drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl, or cmos inputs. an internal clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. fea t ures a pplica t ions n 2-channel simultaneous sampling adc n 73.1db snr n 88db sfdr n low power: 299mw/243mw/203mw total n 150mw/121mw/101mw per channel n single 1.8v supply n serial lvds outputs: 1 or 2 bits per channel n selectable input ranges: 1v p-p to 2v p-p n 800mhz full power bandwidth s/h n shutdown and nap modes n serial spi port for confguration n pin compatible 14-bit and 12-bit versions n 40-pin (6mm 6mm) qfn package n communications n cellular base stations n software defned radios n portable medical imaging n multichannel data acquisition n nondestructive testing ltc2268-14, 125msps, 2-tone fft, f in = 70mhz and 75mhz l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. ch.1 analog input ch.2 analog input encode input 226814 ta01 gnd ognd 14-bit adc core 14-bit adc core pll data serializer serialized lvds outputs 1.8v 1.8v v dd ov dd out1a out1b out2a out2b data clock out frame s/h s/h frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 226814 ta01b
ltc2268-14/ ltc2267-14/ltc2266-14 2 22687614fa a bsolu t e maxi m u m r a t ings supply voltages v dd , ov dd ................................................ C0.3v to 2v analog input voltage (a in + , a in C , par/ ser, sense) (note 3) ............. C0.3v to (v dd +0.2v) digital input voltage (enc + , enc C , cs, sdi, sck) (note 4) .................................... C0.3v to 3.9v sdo (note 4) ............................................ C0.3v to 3.9v digital output voltage .................. C0.3v to (ov dd +0.3v) operating temperature range ltc2268c, 2267c, 2266c ........................ 0c to 70c ltc2268i, 2267i, 2266i ....................... C40c to 85c storage temperature range ................... C65c to 150c or d er in f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc2268cuj-14#pbf ltc2268cuj-14#trpbf ltc2268uj-14 40-lead (6mm 6mm) plastic qfn 0c to 70c ltc2268iuj-14#pbf ltc2268iuj-14#trpbf ltc2268uj-14 40-lead (6mm 6mm) plastic qfn C40c to 85c ltc2267cuj-14#pbf ltc2267cuj-14#trpbf ltc2267uj-14 40-lead (6mm 6mm) plastic qfn 0c to 70c ltc2267iuj-14#pbf ltc2267iuj-14#trpbf ltc2267uj-14 40-lead (6mm 6mm) plastic qfn C40c to 85c ltc2266cuj-14#pbf ltc2266cuj-14#trpbf ltc2266uj-14 40-lead (6mm 6mm) plastic qfn 0c to 70c ltc2266iuj-14#pbf ltc2266iuj-14#trpbf ltc2266uj-14 40-lead (6mm 6mm) plastic qfn C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ p in c on f igura t ion (note 1) 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 top view 41 gnd uj package 40-lead (6mm 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 a in1 + a in1 ? v cm1 refh refh refl refl v cm2 a in2 + a in2 ? out1b + out1b ? dco + dco ? ov dd ognd fr + fr ? out2a + out2a ? v dd v dd sense gnd v ref par/ ser sdo gnd out1a + out1a ? v dd v dd enc + enc ? cs sck sdi gnd out2b ? out2b + 21 30 10 1 t jmax = 150c, ja = 32c/w exposed pad (pin 41) is gnd, must be soldered to pcb
ltc2268-14/ ltc2267-14/ltc2266-14 3 22687614fa conver t er c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) parameter conditions ltc2268-14 ltc2267-14 ltc2266-14 units min typ max min typ max min typ max resolution (no missing codes) l 14 14 14 bits integral linearity error differential analog input (note 6) l C3.5 1 3.5 C3.5 1 3.5 C2.75 1 2.75 lsb differential linearity error differential analog input l C0.8 0.3 0.8 C0.8 0.3 0.8 C0.8 0.3 0.8 lsb offset error (note 7) l C12 3 12 C12 3 12 C12 3 2 mv gain error internal reference external reference l C2.3 C0.9 C0.9 0.5 C2.3 C0.9 C0.9 0.5 C2.3 C0.9 C0.9 0.5 %fs %fs offset drift 20 20 20 v/c full-scale drift internal reference external reference 30 10 30 10 30 10 ppm/c ppm/c gain matching external reference 0.2 0.2 0.2 %fs offset matching 3 3 3 mv transition noise external reference 1.2 1.2 1.2 lsb rms symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1 to 2 v pCp v in(cm) analog input common mode (a in + C a in C )/2 differential analog input (note 8) l v cm C 100mv v cm v cm +100mv v v sense external voltage reference applied to sense external reference mode l 0.625 1.25 1.3 v i incm analog input common mode current per pin, 125msps per pin, 105msps per pin, 80msps l 155 130 100 a a a i in1 analog input leakage current (no encode) 0 < a in + , a in C < v dd l C1 1 a i in2 par/ ser input leakage current 0 < par/ ser < v dd l C3 3 a i in3 sense input leakage current 0.625 < sense < 1.3v l C6 6 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter 0.15 ps rms cmrr analog input common mode rejection ratio 80 db bw-3b full power bandwidth figure 6 test circuit 800 mhz analog inpu t the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5)
ltc2268-14/ ltc2267-14/ltc2266-14 4 22687614fa d igi t al accuracy the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions ltc2268-14 ltc2267-14 ltc2266-14 units min typ max min typ max min typ max snr signal-to-noise ratio 5mhz input 70mhz input 140mhz input l 71.4 73.1 73 72.6 70.8 73 72.9 72.6 71 73 72.9 72.5 dbfs dbfs dbfs sfdr spurious free dynamic range 2 nd or 3 rd harmonic 5mhz input 70mhz input 140mhz input l 75 88 85 82 76 88 85 82 76 88 85 82 dbfs dbfs dbfs spurious free dynamic range 4 th harmonic or higher 5mhz input 70mhz input 140mhz input l 84 90 90 90 83 90 90 90 85 90 90 90 dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 5mhz input 70mhz input 140mhz input l 70.5 73 72.6 72 70.2 73 72.6 72 70.4 72.9 72.6 72 dbfs dbfs dbfs crosstalk 10mhz input C105 C105 C105 dbc parameter conditions min typ max units v cm output voltage i out = 0 0.5 ? v dd C 25mv 0.5 ? v dd 0.v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.25 1.275 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v in t ernal re f erence charac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 10) 10 k c in input capacitance 3.5 pf single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd =1.8v l 1.2 v v il low level input voltage v dd =1.8v l 0.6 v v in input voltage range enc + to gnd l 0 3.6 v r in input resistance (see figure 11) 30 k c in input capacitance 3.5 pf d igi t al inpu t s an d ou t pu t s the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5)
ltc2268-14/ ltc2267-14/ltc2266-14 5 22687614fa symbol parameter conditions min typ max units digital inputs ( cs, sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd =1.8v l 1.3 v v il low level input voltage v dd =1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance 3 pf sdo output (serial programming mode. open drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd =1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance 3 pf digital data outputs v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 247 125 350 175 454 250 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 1.125 1.125 1.25 1.25 1.375 1.375 v v r term on-chip termination resistance termination enabled, ov dd =1.8v 100 d igi t al inpu t s an d ou t pu t s the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) po w er re q uire m en t s the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 9) symbol parameter conditions ltc2268-14 ltc2267-14 ltc2266-14 units min typ max min typ max min typ max v dd analog supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v i vdd analog supply current sine wave input l 150 168 119 131 98 111 ma i ovdd digital supply current 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode l l 16 30 20 34 16 29 19 33 15 29 18 32 ma ma p diss power dissipation 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode l l 299 324 338 364 243 266 270 295 203 229 232 257 mw mw p sleep sleep mode power 1 1 1 mw p nap nap mode power 70 70 70 mw p diffclk power increase with differential encode mode enabled (no increase for sleep mode) 20 20 20 mw t i m ing charac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 5) symbol parameter conditions ltc2268-14 ltc2267-14 ltc2266-14 units min typ max min typ max min typ max f s sampling frequency (notes 10, 11) l 5 125 5 105 5 80 mhz t encl enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2 4 4 100 100 4.52 2 4.76 4.76 100 100 5.93 2 6.25 6.25 100 100 ns ns t ench analog supply current duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2 4 4 100 100 4.52 2 4.76 4.76 100 100 5.93 2 6.25 6.25 100 100 ns ns t ap sample-and-hold acquisition delay time 0 0 0 ns
ltc2268-14/ ltc2267-14/ltc2266-14 6 22687614fa e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 125mhz (ltc2268), 105mhz (ltc2267), or 80mhz (ltc2266), 2-lane output mode, differential enc + / enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. symbol parameter conditions min typ max units digital data outputs (r term = 100 differential, c l = 2pf to gnd on each output) t ser serial data bit period 2-lanes, 16-bit serialization 2-lanes, 14-bit serialization 2-lanes, 12-bit serialization 1-lane, 16-bit serialization 1-lane, 14-bit serialization 1-lane, 12-bit serialization 1/(8 ? f s ) 1/(7 ? f s ) 1/(6 ? f s ) 1/(16 ? f s ) 1/(14 ? f s ) 1/(12 ? f s ) s t frame fr to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser s t data data to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser s t pd propagation delay (note 8) l 0.7n + 2 ? t ser 1.1n + 2 ? t ser 1.5n + 2 ? t ser s t r output rise time data, dco, fr, 20% to 80% 0.17 ns t f output fall time data, dco, fr, 20% to 80% 0.17 ns dco cycle-cycle jitter t ser = 1ns 60 ps p-p pipeline latency 6 cycles spi port timing (note 8) t sck sck period write mode readback mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5 ns t h sck to cs setup time l 5 ns t ds sdi setup time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid readback mode, c sdo = 20pf, r pullup = 2k l 125 ns the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. note 6: integral nonlinearity is defned as the deviation of a code from a best ft straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5 lsb when the output code fickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = ov dd = 1.8v, f sample = 125mhz (ltc2268), 105mhz (ltc2267), or 80mhz (ltc2266), 2-lane output mode, enc + = single- ended 1.8v square wave, enc C = 0v, input range = 2v p-p with differential drive, unless otherwise noted. the supply current and power dissipation specifcations are totals for the entire chip, not per channel. note 10: recommended operating conditions. note 11: the maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. the maximum serial data rate is 1000mbps so t ser must be greater than or equal to 1ns.
ltc2268-14/ ltc2267-14/ltc2266-14 7 22687614fa t i m ing diagra m s 226814 td01 t ap n + 1 n analog input enc ? dco ? fr ? enc + dco + fr + out#a + sample n-6 *see the digital outputs section sample n-5 out#a ? out#b + out#b ? sample n-4 t frame t data t ser t ser t pd d5 d3 d1 0 d13 d11 d9 d7 d5 d3 d1 0 d13 d11 d9 d4 d2 d0 0 d12 d10 d8 d6 d4 d2 d0 0 d12 d10 d8 t ench t encl t ser 2-lane output mode, 16-bit serialization* 226814 td02 t ap n + 2 n + 1 n analog input enc ? dco ? fr ? enc + dco + fr + out#a + note that in this mode, fr + /fr ? has two times the period of enc + /enc ? sample n-6 sample n-5 out#a ? out#b + out#b ? sample n-3 sample n-4 t frame t data t ser t ser t pd d7 d5 d3 d1 d13 d11 d9 d7 d5 d3 d1 d13 d11 d9 d7 d5 d3 d1 d13 d11 d9 d6 d4 d2 d0 d12 d10 d8 d6 d4 d2 d0 d12 d10 d8 d6 d4 d2 d0 d12 d10 d8 t ench t encl t ser 2-lane output mode, 14-bit serialization
ltc2268-14/ ltc2267-14/ltc2266-14 8 22687614fa t i m ing diagra m s 226814 td03 t ap n + 1 n analog input enc ? dco ? fr + enc + dco + fr ? out#a + sample n-6 sample n-5 out#a ? out#b + out#b ? sample n-4 t frame t data t ser t ser t pd d9 d7 d5 d3 d13 d11 d9 d7 d5 d3 d13 d11 d9 d8 d6 d4 d2 d12 d10 d8 d6 d4 d2 d12 d10 d8 t ench t encl t ser 2-lane output mode, 12-bit serialization 226814 td04 t ap n + 1 n analog input enc ? dco ? fr ? enc + dco + fr + out#a + out#b + , out#b ? are disabled sample n-6 sample n-5 sample n-4 out#a ? t frame t data t ser t ser t pd d1 d0 0 0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 d13 d12 d11 d10 t ench t encl t ser 1-lane output mode, 16-bit serialization
ltc2268-14/ ltc2267-14/ltc2266-14 9 22687614fa t i m ing diagra m s 226814 td05 t ap n + 1 n analog input enc ? dco ? fr ? enc + dco + fr + out#a + out#b + , out#b ? are disabled sample n-6 sample n-5 sample n-4 out#a ? t frame t data t ser t ser t pd d3 d2 d1 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 d12 d11 d10 t ench t encl t ser 1-lane output mode, 14-bit serialization 226814 td06 t ap n + 1 n analog input enc ? dco ? fr ? enc + dco + fr + out#a + out#b + , out#b ? are disabled sample n-6 sample n-5 sample n-4 out#a ? t frame t data t ser t ser t pd d5 d4 d3 d2 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d13 d12 d11 t ench t encl t ser 1-lane output mode, 12-bit serialization
ltc2268-14/ ltc2267-14/ltc2266-14 10 22687614fa t i m ing diagra m s a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 226814 td07 cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 226814 td07 cs sck sdi r/w sdo high impedance
ltc2268-14/ ltc2267-14/ltc2266-14 11 22687614fa typical p er f or m ance c harac t eris t ics output code 0 ?2.0 ?0.5 ?1.0 ?1.5 inl error (lsb) 0 0.5 1.0 1.5 2.0 4096 8192 12288 16384 226814 g01 output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 4096 8192 12288 16384 226814 g02 frequency (mhz) ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 226814 g03 0 10 20 30 40 50 60 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 226814 g04 10 20 30 40 50 60 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 226814 g05 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 226814 g06 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 226814 g07 output code 8178 1000 0 3000 2000 count 4000 5000 6000 8180 8182 8184 8186 226814 g08 input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 226814 g09 ltc2268-14: 8k point fft, f in = 30mhz, ?1dbfs, 125msps ltc2268-14: 8k point fft, f in = 70mhz, ?1dbfs, 125msps ltc2268-14: 8k point fft, f in = 140mhz, ?1dbfs, 125msps ltc2268-14: 8k point 2-tone fft, f in = 70mhz, 75mhz, ?1dbfs, 125msps ltc2268-14: shorted input histogram ltc2268-14: snr vs input frequency, ?1db, 2v range, 125msps ltc2268-14: integral nonlinearity (inl) ltc2268-14: differential nonlinearity (dnl) ltc2268-14: 8k point fft, f in = 5mhz, ?1dbfs, 125msps
ltc2268-14/ ltc2267-14/ltc2266-14 12 22687614fa typical p er f or m ance c harac t eris t ics input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 226814 g10 input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 226814 g12 dbfs dbc sense pin (v) 0.6 71 68 69 70 67 66 72 73 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 226814 g15 output code 0 ?2.0 ?0.5 ?1.0 ?1.5 inl error (lsb) 0 0.5 1.0 1.5 2.0 4096 8192 12288 16384 226814 g21 io vdd vs sample rate, 5mhz sine wave input, C1db ltc2268-14: snr vs sense, f in = 5mhz, C1db ltc2267-14: integral nonlinearity (inl) ltc2268-14: sfdr vs input frequency, C1db, 2v range, 125msps ltc2268-14: sfdr vs input level, f in = 70mhz, 2v range, 125msps ltc2268-14: i vdd vs sample rate, 5mhz sine wave input, C1db output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 4096 8192 12288 16384 226814 g22 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 226814 g23 ltc2267-14: differential nonlinearity (dnl) ltc2267-14: 8k point fft, f in = 5mhz, C1dbfs, 105msps input level (dbfs) 60 50 40 30 20 10 0 80 70 snr (dbc and dbfs) ?60 ?50 ?40 ?30 ?20 ?10 0 226814 g50a dbfs dbc ltc2268-14: snr vs input level, f in = 70mhz, 2v range, 125msps sample rate (msps) 160 150 140 130 120 110 100 i vdd (ma) 0 25 50 75 100 125 226814 g53 sample rate (msps) 30 20 10 0 io vdd (ma) 0 25 50 75 100 125 226814 g51 1-lane, 1.75ma 2-lane, 3.5ma 2-lane, 1.75ma 1-lane, 3.5ma
ltc2268-14/ ltc2267-14/ltc2266-14 13 22687614fa frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 226814 g24 ltc2267-14: 8k point fft, f in = 30mhz, C1dbfs, 105msps input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 226814 g32 dbfs dbc ltc2267-14: sfdr vs input level, f in = 70mhz, 2v range, 105msps ltc2267-14: i vdd vs sample rate, 5mhz sine wave input, C1db typical p er f or m ance c harac t eris t ics frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 226814 g25 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 226814 g26 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 226814 g27 output code 8195 1000 0 3000 2000 count 4000 5000 6000 8197 8199 8201 8203 226814 g28 input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 226814 g29 input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 226814 g30 ltc2267-14: 8k point fft, f in = 70mhz, C1dbfs, 105msps ltc2267-14: 8k point fft, f in = 140mhz, C1dbfs, 105msps ltc2267-14: 8k point 2-tone fft, f in = 70mhz, 75mhz, C1dbfs, 105msps ltc2267-14: shorted input histogram ltc2267-14: snr vs input frequency, C1db, 2v range, 105msps ltc2267-14: sfdr vs input frequency, C1db, 2v range, 105msps sample rate (msps) 130 110 120 100 90 80 i vdd (ma) 0 25 50 75 100 226814 g54
ltc2268-14/ ltc2267-14/ltc2266-14 14 22687614fa t a = 25c, unless otherwise noted. typical p er f or m ance c harac t eris t ics output code 0 ?2.0 ?0.5 ?1.0 ?1.5 inl error (lsb) 0 0.5 1.0 1.5 2.0 4096 8192 12288 16384 226814 g41 output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 4096 8192 12288 16384 226814 g42 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 226814 g43 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 226814 g44 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 226814 g45 ltc2266-14: integral nonlinearity (inl) ltc2266-14: differential nonlinearity (dnl) ltc2266-14: 8k point fft, f in = 5mhz, C1dbfs, 80msps ltc2266-14: 8k point fft, f in = 30mhz, C1dbfs, 80msps ltc2266-14: 8k point fft, f in = 70mhz, C1dbfs, 80msps frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 226814 g46 ltc2266-14: 8k point fft, f in = 140mhz, C1dbfs, 80msps frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 226814 g47 output code 8184 1000 0 3000 2000 count 4000 5000 6000 8186 8188 8190 8192 226814 g48 ltc2266-14: 8k point 2-tone fft, f in = 70mhz, 75mhz, C1dbfs, 80msps ltc2266-14: shorted input histogram sense pin (v) 0.6 71 68 69 70 67 66 72 73 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 226814 g35 ltc2267-14: snr vs sense, f in = 5mhz, C1db
ltc2268-14/ ltc2267-14/ltc2266-14 15 22687614fa input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 226814 g49 ltc2266-14: snr vs input frequency, C1db, 2v range, 80msps typical p er f or m ance c harac t eris t ics input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 226814 g50 input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 226814 g52 dbfs dbc sense pin (v) 0.6 71 68 69 70 67 66 72 73 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 226814 g55 ltc2266-14: sfdr vs input frequency, C1db, 2v range, 80msps ltc2266-14: sfdr vs input frequency, C1db, 2v range, 80msps ltc2266-14: i vdd vs sample rate, 5mhz sine wave input, C1db ltc2266-14: snr vs sense, f in = 5mhz, C1db dco cycle-cycle jitter vs serial data rate sample rate (msps) 110 100 90 80 70 i vdd (ma) 0 20 40 60 80 226814 g55a serial data rate (mbps) 350 300 250 200 150 100 50 0 peak-to-peak jitter (ps) 0 200 400 600 800 1000 226814 g52a
ltc2268-14/ ltc2267-14/ltc2266-14 16 22687614fa p in func t ions a in1 + (pin 1): channel 1 positive differential analog input. a in1 C (pin 2): channel 1 negative differential analog input. v cm1 (pin 3): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channel 1. bypass to ground with a 0.1f ceramic capacitor. refh (pins 4,5): adc high reference. bypass to pins 6, 7 with a 2.2f ceramic capacitor and to ground with a 0.1f ceramic capacitor. refl (pins 6,7): adc low reference. bypass to pins 4, 5 with a 2.2f ceramic capacitor and to ground with a 0.1f ceramic capacitor. v cm2 (pin 8): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channel 2. bypass to ground with a 0.1f ceramic capacitor. a in2 + (pin 9): channel 2 positive differential analog input. a in2 C (pin 10): channel 2 negative differential analog input. v dd (pins 11, 12, 39, 40): 1.8v analog power supply. bypass to ground with 0.1f ceramic capacitors. adjacent pins can share a bypass capacitor. enc + (pin 13): encode input. conversion starts on the rising edge. enc C (pin 14): encode complement input. conversion starts on the falling edge. cs (pin 15): in serial programming mode, (par/ser=0v), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode (par/ ser = v dd ), cs selects 2-lane or 1-lane output mode. cs can be driven with 1.8v to 3.3v logic. sck (pin 16): in serial programming mode, (par/ser = 0v), sck is the serial interface clock input. in the parallel programming mode (par/ ser= v dd ), sck selects 3.5ma or 1.75ma lvds output currents. sck can be driven with 1.8v to 3.3v logic. sdi (pin 17): in serial programming mode, (par/ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel programming mode (par/ ser = v dd ), sdi can be used to power down the part. sdi can be driven with 1.8v to 3.3v logic. gnd (pins 18, 33, 37, exposed pad pin 41): adc power ground. the exposed pad must be soldered to the pcb ground. ognd (pin 25): output driver ground. must be shorted to the ground plane by a very low inductance path. use multiple vias close to the pin. ov dd (pin 26): output driver supply. bypass to ground with a 0.1f ceramic capacitor. sdo (pin 34): in serial programming mode, (par/ser = 0v), sdo is the optional serial interface data output. data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open-drain nmos output that requires an external 2k pull-up resistor to 1.8v C 3.3v. if read back from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. in the parallel programming mode (par/ ser = v dd ), sdo is an input that enables internal 100 termination resistors on the digital outputs. when used as an input, sdo can be driven with 1.8v to 3.3v logic through a 1k series resistor. par/ ser (pin 35): programming mode selection pin. connect to ground to enable the serial programming mode. cs , sck, sdi, sdo become a serial interface that control the a/d operating modes. connect to v dd to enable the parallel programming mode where cs , sck, sdi, sdo
ltc2268-14/ ltc2267-14/ltc2266-14 17 22687614fa become parallel logic inputs that control a reduced set of the a/d operating modes. par/ ser should be connected directly to ground or the v dd of the part and not be driven by a logic signal. v ref (pin 36): reference voltage output. bypass to ground with a 1f ceramic capacitor, nominally 1.25v. sense (pin 38): reference programming pin. connecting sense to v dd selects the internal reference and a 1v input range. connecting sense to ground selects the internal reference and a 0.5v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.8 ? v sense . lvds outputs all pins below are differential lvds outputs. the output current level is programmable. there is an optional internal 100 termination resistor between the pins of each lvds output pair. out2b C /out2b + , out2a C /out2a + (pins 19/20, 21/22): serial data outputs for channel 2. in 1-lane output mode only out2a C /out2a + are used. fr C /fr + (pins 23/24): frame start outputs. dco C /dco + (pins 27/28): data clock outputs. out1b C /out1b + , out1a C /out1a + (pins 29/30, 31/32): serial data outputs for channel 1. in 1-lane output mode only out1a C /out1a + are used. p in func t ions
ltc2268-14/ ltc2267-14/ltc2266-14 18 22687614fa b lock diagra m figure 1. functional block diagram pll sample- and-hold 14-bit adc core a in1 + a in1 ? 14-bit adc core a in2 + a in2 ? 1.8v 1.8v enc + enc ? ov dd v dd v dd /2 diff ref amp ref buf 2.2f 0.1f 0.1f 0.1f refh refl range select 1.25v reference refh refl out1a ? out1a + out1b ? out1b + out2a ? out2a + out2b ? out2b + dco + dco ? ognd v cm1 gnd v cm2 0.1f 0.1f sdo cs sense v ref 1f mode control registers sck par/ ser sdi 226814 f01 sample- and-hold data serializer fr + fr ?
ltc2268-14/ ltc2267-14/ltc2266-14 19 22687614fa converter operation the ltc2268-14/ltc2267-14/ltc2266-14 are low power, 2-channel, 14-bit, 125msps/105msps/80msps a/d con- verters that are powered by a single 1.8v supply. the analog inputs should be driven differentially. the encode input can be driven differentially for optimal jitter perfor- mance, or single-ended for lower power consumption. to minimize the number of data lines the digital outputs are serial lvds. each channel outputs two bits at a time (2-lane mode). at lower sampling rates there is a one bit per channel option (1-lane mode). many additional features can be chosen by programming the mode control registers through a serial spi port. a pplica t ions i n f or m a t ion analog input the analog inputs are differential cmos sample-and-hold circuits (figure 2). the inputs should be driven differentially around a common mode voltage set by the v cm1 or v cm2 output pins, which are nominally v dd /2. for the 2v input range, the inputs should swing from v cm C 0.5v to v cm + 0.5v. there should be 180 phase difference between the inputs. the two channels are simultaneously sampled by a shared encode circuit (figure 2). input drive circuits input fltering if possible, there should be an rc lowpass flter right at the analog inputs. this lowpass flter isolates the drive circuitry from the a/d sample-and-hold switching, and also limits wideband noise from the drive circuitry. figure 3 shows an example of an input rc flter. the rc component values should be chosen based on the applications input frequency. figure 2. equivalent input circuit. only one of the two analog channels is shown figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz c sample 3.5pf r on 25 r on 25 v dd v dd ltc2268-14 a in + 226814 f02 c sample 3.5pf v dd a in ? enc ? enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 25 25 25 25 50 0.1f a in + a in ? 12pf 0.1f v cm ltc2268-14 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 226814 f03
ltc2268-14/ ltc2267-14/ltc2266-14 20 22687614fa transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary. the center tap is biased with v cm , setting the a/d input at its optimal dc level. at higher input frequencies a transmission line balun transformer (figures 4 to 6) has better balance, resulting in lower a/d distortion. a pplica t ions i n f or m a t ion amplifer circuits figure 7 shows the analog input being driven by a high speed differential amplifer. the output of the amplifer is ac-coupled to the a/d so the amplifers output common mode voltage can be optimally set to minimize distor - tion. at very high frequencies an rf gain block will often have lower distortion than a differential amplifer. if the gain block is single-ended, then a transformer circuit (figures 4 to 6) should convert the signal to differential before driving the a/d. figure 5. recommended front end circuit for input frequencies from 170mhz to 300mhz figure 6. recommended front end circuit for input frequencies above 300mhz figure 4.recommended front end circuit for input frequencies from 70mhz to 170mhz figure 7. front end circuit using a high speed differential amplifer 25 25 50 0.1f a in + a in ? 4.7pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: ma/com mabaes0060 resistors, capacitors are 0402 package size 226814 f04 ltc2268-14 25 25 50 0.1f a in + a in ? 1.8pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1lb resistors, capacitors are 0402 package size 226814 f05 ltc2268-14 25 25 50 0.1f 2.7nh 2.7nh a in + a in ? 0.1f v cm analog input 0.1f 0.1f t1 t1: ma/com etc1-1-13 resistors, capacitors are 0402 package size 226814 f06 ltc2268-14 25 25 200 200 0.1f a in + a in ? 12pf 0.1f v cm ltc2268-14 226814 f07 ? ? + + analog input high speed differential amplifier 0.1f
ltc2268-14/ ltc2267-14/ltc2266-14 21 22687614fa reference the ltc2268-14/ltc2267-14/ltc2266-14 has an internal 1.25v voltage reference. for a 2v input range using the internal reference, connect sense to v dd . for a 1v input range using the internal reference, connect sense to ground. for a 2v input range with an external reference, apply a 1.25v reference voltage to sense (figure 9). the input range can be adjusted by applying a voltage to sense that is between 0.625v and 1.30v. the input range will then be 1.6 ? v sense . a pplica t ions i n f or m a t ion the reference is shared by both adc channels, so it is not possible to independently adjust the input range of individual channels. the v ref , refh and refl pins should be bypassed as shown in figure 8. the 0.1f capacitor between refh and refl should be as close to the pins as possible (not on the backside of the circuit board). encode input the signal quality of the encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signals do not route them next to digital traces on the circuit board. there are two modes of operation for the encode inputs: the differential encode mode (figure 10), and the single-ended encode mode (figure 11). figure 8. reference circuit figure 9. using an external 1.25v reference figure 10. equivalent encode input circuit for differential encode mode figure 11. equivalent encode input circuit for single-ended encode mode v ref refh sense tie to v dd for 2v range; tie to gnd for 1v range; range = 1.6 ? v sense for 0.65v < v sense < 1.300v 1.25v refl 0.1f 2.2f internal adc high reference buffer 226814 f08 ltc2268 -14 5 0.8x diff amp internal adc low reference 1.25v bandgap reference 0.625v range detect and control 1f 0.1f 0.1f sense 1.25v external reference 1f 1f v ref 226814 f09 ltc2268-14 v dd ltc2268-14 226814 f10 enc ? enc + 15k v dd differential comparator 30k 30k enc + enc ? 226814 f11 0v 1.8v to 3.3v ltc2268-14 cmos logic buffer
ltc2268-14/ ltc2267-14/ltc2266-14 22 22687614fa the differential encode mode is recommended for sinu- soidal, pecl, or lvds encode inputs (figures 12 and 13). the encode inputs are internally biased to 1.2v through 10k equivalent resistance. the encode inputs can be taken above v dd (up to 3.6v), and the common mode range is from 1.1v to 1.6v. in the differential encode mode, enc C should stay at least 200mv above ground to avoid falsely triggering the single-ended encode mode. for good jitter performance enc + should have fast rise and fall times. the single-ended encode mode should be used with cmos encode inputs. to select this mode, enc C is connected to ground and enc + is driven with a square wave encode input. enc + can be taken above v dd (up to 3.6v) so 1.8v to 3.3v cmos logic levels can be used. the enc + threshold is 0.9v. for good jitter performance enc + should have fast rise and fall times. a pplica t ions i n f or m a t ion clock pll and duty cycle stabilizer the encode clock is multiplied by an internal phase-locked loop (pll) to generate the serial digital output data. if the encode signal changes frequency or is turned off, the pll requires 25s to lock onto the input clock. a clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. in the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. in the parallel programming mode the duty cycle stabilizer is always enabled. digital outputs the digital outputs of the ltc2268-14/ltc2267-14/ ltc2266-14 are serialized lvds signals. each channel outputs two bits at a time (2-lane mode). at lower sam- pling rates there is a one bit per channel option (1-lane mode). the data can be serialized with 16-, 14-, or 12-bit serialization (see timing diagrams for details). note that with 12-bit serialization the two lsbs are not available this mode is included for compatibility with the 12-bit versions of these parts. the output data should be latched on the rising and falling edges of the data clock out (dco). a data frame output (fr) can be used to determine when the data from a new conversion result begins. in the 2-lane, 14-bit serialization mode, the frequency of the fr output is halved. the maximum serial data rate for the data outputs is 1gbps, so the maximum sample rate of the adc will depend on the serialization mode as well as the speed grade of the adc (see table 1). the minimum sample rate for all seri - alization modes is 5msps. figure 12. sinusoidal encode drive figure 13. pecl or lvds encode drive 50 100 0.1f 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 ltc2268-14 226814 f12 enc ? enc + enc + enc ? pecl or lvds clock 0.1f 0.1f 226814 f13 ltc2268-14
ltc2268-14/ ltc2267-14/ltc2266-14 23 22687614fa by default the outputs are standard lvds levels: 3.5ma output current and a 1.25v output common mode volt- age. an external 100? differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. programmable lvds output current the default output driver current is 3.5ma. this current can be adjusted by control register a2 in the serial pro- gramming mode. available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. in the parallel programming mode the sck pin can select either 3.5ma or 1.75ma. optional lvds driver internal termination in most cases using just an external 100? termination resistor will give excellent lvds signal integrity. in addi - tion, an optional internal 100? termination resistor can be enabled by serially programming mode control register a2. the internal termination helps absorb any refections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. in the parallel programming mode, the sdo pin enables internal termination. internal termination should only be used with 1.75ma, 2.1ma or 2.5ma lvds output current modes. a pplica t ions i n f or m a t ion data format table 2 shows the relationship between the analog input voltage and the digital data output bits. by default the output data format is offset binary. the 2s complement format can be selected by serially programming mode control register a1. table 2. output codes vs input voltage a in + C a in C (2v range) d13-d0 (offset binary) d13-d0 (2s complement) >1.000000v +0.999878v +0.999756v 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 +0.000122v +0.000000v C0.000122v C0.000244v 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 C0.999878v C1.000000v ?C1.000000v 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0000 10 0000 0000 0000 digital output randomizer interference from the a/d digital outputs is sometimes unavoidable. digital interference may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. table 1. maximum sampling frequency for all serialization modes. note that these limits are for the ltc2268-14. the sampling frequency for the slower speed grades cannot exceed 105mhz (ltc2267-14) or 80mhz (ltc2266-14). serialization mode maximum sampling frequency, f s (mhz) dco frequency fr frequency serial data rate 2-lane 16-bit serialization 125 4 ? f s f s 8 ? f s 2-lane 14-bit serialization 125 3.5 ? f s 0.5 ? f s 7 ? f s 2-lane 12-bit serialization 125 3 ? f s f s 6 ? f s 1-lane 16-bit serialization 62.5 8 ? f s f s 16 ? f s 1-lane 14-bit serialization 71.4 7 ? f s f s 14 ? f s 1-lane 12-bit serialization 83.3 6 ? f s f s 12 ? f s
ltc2268-14/ ltc2267-14/ltc2266-14 24 22687614fa the digital output is randomized by applying an exclu- sive-or logic operation between the lsb and all other data output bits. to decode, the reverse operation is appliedan exclusive-or operation is applied between the lsb and all other bits. the fr and dco outputs are not affected. the output randomizer is enabled by serially programming mode control register a1. digital output test pattern to allow in-circuit testing of the digital interface to the a/d, there is a test mode that forces the a/d data outputs (d13-d0) of both channels to known values. the digital output test patterns are enabled by serially programming mode control registers a3 and a4. when enabled, the test patterns override all other formatting modes: 2s comple - ment and randomizer. output disable the digital outputs may be disabled by serially program - ming mode control register a2. the current drive for all digital outputs including dco and fr are disabled to save power or enable in-circuit testing. when disabled the com - mon mode of each output pair becomes high impedance, but the differential impedance may remain low. sleep and nap modes the a/d may be placed in sleep or nap modes to conserve power. in sleep mode the entire chip is powered down, resulting in 1mw power consumption. sleep mode is enabled by mode control register a1 (serial program- ming mode), or by sdi (parallel programming mode). the amount of time required to recover from sleep mode depends on the size of the bypass capacitors on v ref , refh, and refl. for the suggested values in figure 8, the a/d will stabilize after 2ms. in nap mode any combination of a/d channels can be powered down while the internal reference circuits and the pll stay active, allowing faster wake-up than from sleep mode. recovering from nap mode requires at least 100 clock cycles. if the application demands very accurate dc settling then an additional 50s should be allowed so the on-chip references can settle from the slight temperature a pplica t ions i n f or m a t ion shift caused by the change in supply current as the a/d leaves nap mode. nap mode is enabled by mode control register a1 in the serial programming mode. device programming modes the operating modes of the ltc2268-14/ltc2267-14/ ltc2266-14 can be programmed by either a parallel interface or a simple serial interface. the serial interface has more fexibility and can program all available modes. the parallel interface is more limited and can only program some of the more commonly used modes. parallel programming mode to use the parallel programming mode, par/ ser should be tied to v dd . the cs , sck, sdi and sdo pins are binary logic inputs that set certain operating modes. these pins can be tied to v dd or ground, or driven by 1.8v, 2.5v, or 3.3v cmos logic. when used as an input, sdo should be driven through a 1k series resistor. table 3 shows the modes set by cs, sck, sdi and sdo. table 3. parallel programming mode control bits (par/ ser = v dd ) pin description cs 2-lane/1-lane selection bit 0 = 2-lane, 16-bit serialization output mode 1 = 1-lane, 14-bit serialization output mode sck lvds current selection bit 0 = 3.5ma lvds current mode 1 = 1.75ma lvds current mode sdi power down control bit 0 = normal operation 1 = sleep mode sdo internal 100 termination selection bit 0 = internal termination disabled 1 = internal termination enabled serial programming mode to use the serial programming mode, par/ ser should be tied to ground. the cs , sck, sdi and sdo pins become a serial interface that program the a/d mode control registers. data is written to a register with a 16-bit serial word. data can also be read back from a register to verify its contents.
ltc2268-14/ ltc2267-14/ltc2266-14 25 22687614fa serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the frst 16 rising edges of sck. any sck rising edges after the frst 16 are ignored. the data transfer ends when cs is taken high again. the frst bit of the 16-bit input word is the r/w bit. the next seven bits are the address of the register (a6:a0). the fnal eight bits are the register data (d7:d0). if the r/w bit is low, the serial data (d7:d0) will be written to the register set by the address bits (a6:a0). if the r/w bit is high, data in the register set by the address bits (a6: a0) will be read back on the sdo pin (see the timing dia - grams section). during a read back command the register is not updated and data on sdi is ignored. a pplica t ions i n f or m a t ion the sdo pin is an open-drain output that pulls to ground with a 200? impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and read back is not needed, then sdo can be left foating and no pull-up resistor is needed. table 4 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the frst serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit d7 in the reset register is written with a logic 1. after the reset spi write command is complete, bit d7 is automatically set back to zero. table 4. serial programming mode register map (par/ ser = gnd) register a0: reset register (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x bit 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h. the adc is momentarily placed in sleep mode. this bit is automatically set back to zero at the end of the spi write command. the reset register is write only. bits 6-0 unused, dont care bits. register a1: power-down register (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 dcsoff rand twoscomp sleep nap_2 x x nap_1 bit 7 dcsoff clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer on 1 = clock duty cycle stabilizer off. this is not recommended. bit 6 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 5 twoscomp twos complement mode control bit 0 = offset binar y data format 1 = twos complement data format bits 4,3,0 sleep:nap_2:nap_1 sleep/nap mode control bits 000 = normal operation 0x1 = channel 1 in nap mode 01x = channel 2 in nap mode 1xx = sleep mode. both channels are disabled note: any combination of channels can be placed in nap mode. bits 2,1 unused, dont care bits.
ltc2268-14/ ltc2267-14/ltc2266-14 26 22687614fa register a2: output mode register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 ilvds2 ilvds1 ilvds0 termon outoff outmode2 outmode1 outmode0 bits 7-5 ilvds2:ilvds0 lvds output current bits 000 = 3.5ma lvds output driver current 001 = 4.0ma l vds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 4 termon lvds internal termination bit 0 = internal t ermination off 1 = internal termination on. lvds output driver current is 2x the current set by ilvds2:ilvds0. internal termination should only be used with 1.75ma, 2.1ma or 2.5ma lvds output current modes. bit 3 outoff output disable bit 0 = digital outputs are enabled. 1 = digital outputs are disabled. bits 2-0 outmode2:outmode0 digital output mode control bits 000 = 2-lanes, 16-bit serialization 001 = 2-lanes, 14-bit serialization 010 = 2-lanes, 12-bit serialization 011 = not used 100 = not used 101 = 1-lane, 14-bit serialization 110 = 1-lane, 12-bit serialization 111 = 1-lane, 16-bit serialization register a3: test pattern msb register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 outtest x tp13 tp12 tp11 tp10 tp9 tp8 bit 7 outtest digital output test pattern control bit 0 = digital output test pattern off 1 = digital output t est pattern on bit 6 unused, dont care bit. bits 5-0 tp13:tp8 test pattern data bits (msb) tp13:tp8 set the test pattern for data bit 13 (msb) through data bit 8. register a4: test p attern lsb register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 bits 7-0 tp7:tp0 test pattern data bits (lsb) tp7:tp0 set the test pattern for data bit 7 through data bit 0 (lsb). a pplica t ions i n f or m a t ion
ltc2268-14/ ltc2267-14/ltc2266-14 27 22687614fa a pplica t ions i n f or m a t ion grounding and bypassing the ltc2268-14/ltc2267-14/ltc2266-14 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane in the frst layer beneath the adc is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , v ref , refh and refl pins. bypass capacitors must be located as close to the pins as possible. of particular importance is the 0.1f capacitor between refh and refl. this capacitor should be on the same side of the circuit board as the a/d, and as close to the device as possible (1.5mm or less). size 0402 ceramic capacitors are recommended. the larger 2.2f capacitor between refh and refl can be somewhat further away. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground fll and grounded vias should be used as barriers to isolate these signals from each other. heat transfer most of the heat generated by the ltc2268-14/ltc2267 - 14/ ltc2266-14 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. this pad should be con- nected to the internal ground planes by an array of vias. t ypical applica t ions silkscreen top top side
ltc2268-14/ ltc2267-14/ltc2266-14 28 22687614fa t ypical applica t ions inner layer 2 gnd inner layer 3 inner layer 4 inner layer 5 power bottom side silkscreen bottom
ltc2268-14/ ltc2267-14/ltc2266-14 29 22687614fa t ypical applica t ions ltc2268 schematic ltc2268 3 2 1 a in1 + a in1 ? v cm1 refh refh refl refl v cm2 a in2 + a in2 ? 8 9 10 v dd v dd sense gnd v ref par/ ser sdo gnd out1a + out1a ? 3940 38 37 36 sdo par/ ser sense v dd 35 34 33 32 31 c59 0.1f r92 100 c29 0.1f 6 5 4 7 c30 0.1f c1 2.2f c3 0.1f c2 0.1f ov dd r8 100 a in1 a in1 a in2 a in2 226814 ta02 digital outputs digital outputs out1b + out1b ? dco + dco ? ov dd ognd fr + fr ? out2a + out2a ? 23 24 25 26 27 28 29 30 22 21 c16 0.1f c4 1f c5 1f v dd v dd enc + enc ? cs sck sdi gnd out2b ? out2b + 1211 v dd 13 14 15 16 17 18 19 20 c7 0.1f spi bus c46 0.1f c47 0.1f encode clock encode clock
ltc2268-14/ ltc2267-14/ltc2266-14 30 22687614fa p ackage descrip t ion 6.00 0.10 (4 sides) note: 1. drawing is a jedec package outline variation of (wjjd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.45 or 0.35 45 chamfer 0.40 0.10 4039 1 2 bottom view?exposed pad 4.50 ref (4-sides) 4.42 0.10 4.42 0.10 4.42 0.05 4.42 0.05 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uj40) qfn rev ? 0406 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.50 0.05 (4 sides) 5.10 0.05 6.50 0.05 0.25 0.05 0.50 bsc package outline r = 0.10 typ uj package 40-lead plastic qfn (6mm 6mm) (reference ltc dwg # 05-08-1728 rev ?)
ltc2268-14/ ltc2267-14/ltc2266-14 31 22687614fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 6/11 revised a in + and a in C in pin functions section to match pin confguration revised software reset paragraph and table 4 in applications information section added v dd to ltc2268 schematic in typical applications section 16 25 29
ltc2268-14/ ltc2267-14/ltc2266-14 32 22687614fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0611 rev a ? printed in usa r ela t e d p ar t s part number description comments adcs ltc2170-14/ltc2171-14/ ltc2172-14 14-bit, 25msps/40msps/65msps 1.8v quad adcs, ultralow power 178mw/234mw/360mw, 73.4db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2170-12/ltc2171-12/ ltc2172-12 12-bit, 25msps/40msps/65msps 1.8v quad adcs, ultralow power 178mw/234mw/360mw, 70.5db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2173-12/ltc2174-12/ ltc2175-12 12-bit, 80msps/105msps/125msps 1.8v quad adcs, ultralow power 412mw/481mw/567mw, 70.5 db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2256-14/ltc2257-14/ ltc2258-14 14-bit, 25msps/40msps/65msps 1.8v adcs, ultralow power 35mw/49mw/81mw, 74db snr, 88db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-36 ltc2259-14/ltc2260-14/ ltc2261-14 14-bit, 80msps/105msps/125msps 1.8v adcs, ultralow power 89mw/106mw/127mw, 73.4db snr, 85db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-36 ltc2262-14 14-bit, 150msps 1.8v adc, ultralow power 149mw, 72.8db snr, 88db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-36 ltc2263-14/ltc2264-14/ ltc2265-14 14-bit, 25msps/40msps/65msps 1.8v dual adcs, ultralow power 99mw/126mw/191mw, 73.4db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-36 ltc2263-12/ltc2264-12/ ltc2265-12 12-bit, 25msps/40msps/65msps 1.8v dual adcs, ultralow power 99mw/126mw/191mw, 70.5db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-36 ltc2266-12/ltc2267-12/ ltc2268-12 12-bit, 80msps/105msps/125msps 1.8v dual adcs, ultralow power 216mw/250mw/293mw, 70.5db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-36 rf mixers/demodulators ltc5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator ltc5527 400mhz to 3.7ghz high linearity downconverting mixer 24.5dbm iip3 at 900mhz, 23.5dbm iip3 at 3.5ghz, nf = 12.5db, 50 single-ended rf and lo ports ltc5557 400mhz to 3.8ghz high linearity downconverting mixer 23.7dbm iip3 at 2.6ghz, 23.5dbm iip3 at 3.5ghz, nf = 13.2db, 3.3v supply operation, integrated transformer ltc5575 800mhz to 2.7ghz direct conversion quadrature demodulator high iip3: 28dbm at 900mhz, integrated lo quadrature generator, integrated rf and lo transformer amplifiers/filters ltc6412 800mhz, 31db range, analog-controlled variable gain amplifier continuously adjustable gain control, 35dbm oip3 at 240mhz, 10db noise figure, 4mm 4mm qfn-24 ltc6420-20 1.8ghz dual low noise, low distortion differential adc drivers for 300mhz if fixed gain 10v/v, 1n v/ hz total input noise, 80ma supply current per amplifier, 3mm 4mm qfn-20 ltc6421-20 1.3ghz dual low noise, low distortion differential adc drivers fixed gain 10v/v, 1nv/ hz total input noise, 40ma supply current per amplifier, 3mm 4mm qfn-20 ltc6605-7/ ltc6605-10/ ltc6605-14 dual matched 7mhz/10mhz/14mhz filters with adc drivers dual matched 2nd order lowpass filters with differential drivers, pin-programmable gain, 6mm 3mm dfn-22 receiver subsystems ltm9002 14-bit dual channel if/baseband receiver subsystem integrated high speed adc, passive filters and fixed gain differential amplifers

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