1 tm file number 3040.3 hs-82c08rh radiation hardened 8-bit bus transceiver the intersil hs-82c08rh is a radiation-hardened octal bus transceiver with three-state outputs. it is manufactured using a self-aligned, junction isolated cmos process and is designed for use with the hs-80c08rh radiation-hardened microprocessor. the hs-82c08rh allows asynchronous two-way communication between data buses. the direction of data ?w is determined by the logic level on the transmit/receive (t/ r) input. a logic high on the t/ r input speci?s data ?w from port a to port b of the device. conversely, a logic low on the t/ r input speci?s data ?w from port b to port a. the output enable input disables both ports by placing them in the high impedance state. the hs-82c08rh is ideally suited for a wide variety of buffering applications in radiation-hardened microcomputer systems. speci?ations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed here must be used when ordering. detailed electrical speci?ations for these devices are contained in smd 5962-95714. a ?ot-link?is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp functional diagram features electrically screened to smd # 5962-95714 qml quali?d per mil-prf-38535 requirements radiation performance - total dose. . . . . . . . . . . . . . . . . . . . . 100 krad(si) (max) - latch-up immune epi-cmos . . . . . >1 x 10 12 rad(si)/s bidirectional three-state input/outputs low propagation delay time low power consumption single power supply . . . . . . . . . . . . . . . . . . . . . . . . . +5v electrically equivalent to sandia sa2997 military temperature range . . . . . . . . . . . -55 o c to 125 o c a1 a2 a3 a4 a5 a6 a7 oe port a a0 b1 b2 b3 b4 b5 b6 b7 port b b0 t/ r ordering information ordering number internal mkt. number temp. range ( o c) 5962r9571401qrc HS1-82C08RH-8 -55 to 125 5962r9571401qxc hs9-82c08rh-8 -55 to 125 5962r9571401vrc hs1-82c08rh-q -55 to 125 5962r9571401vxc hs9-82c08rh-q -55 to 125 truth table inputs operation output enable transmit /receive port a port b 0 0 out in 0 1 in out 1 x high z high z x = don? care data sheet august 2000 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000
2 pinouts 20 lead ceramic dual-in-linemetal-seal package (sbdip) mil-std-1835, cdip2-t20 top view 20 lead ceramic metal sealflatpack package (flatpack) mil-std-1835, cdfp4-f20 top view 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 a0 a1 a2 a3 a4 a5 a7 a6 oe gnd v dd b1 b2 b3 b0 b4 b5 b6 b7 t/r 2 3 4 5 6 7 8 120 19 18 17 16 15 14 13 a0 a1 a2 a3 a4 a5 a6 a7 9 10 12 11 oe gnd v dd b0 b1 b2 b3 b4 b5 b6 b7 t/ r pin description pin description a0-a7 local bus data i/o pins t/ r transmit/receive input b0-b7 system bus data i/o pins oe active low output enable logic diagram note: an important caveat that is applicable to cmos devices in general is that unused inputs should never be left ?ating. this rule applies to inputs connected to a three-state bus. the need for external pull-up resistors during three-state bus conditions is eliminated by the presence of regenerative latches on the following hs-82c08rh pins. a0-7 and b0-7 the functional block diagram depicts one of these pins with the regenerative latch. when the cmos driver assumes the high impedance state, the latch holds the bus in whatever logic state (high or low) it was before the three- state condition. a transient drive current of 1.5ma at v dd /2 0.5v for 10ns is required to switch the latch. thus, cmos device inputs connected to the bus are not allowed to ?at during three-state conditions. 1 a0 tsb tsb b enable 19 b0 2 a1 tsb tsb 18 b1 3 a2 tsb tsb 17 b2 4 a3 tsb tsb 16 b3 5 a4 tsb tsb 15 b4 6 a5 tsb tsb 14 b5 7 a6 tsb tsb 13 b6 8 a7 tsb tsb 12 b7 a enable oe 9 t/r 11 hs-82c08rh
3 switching time waveforms figure 1. port to port note: c l includes stray and jig capacitance. figure 2. ac testing load circuit figure 3. oe to high-impedance, oe to port output input an or bn output bn or an v dd 0v v dd 0v 0.5v dd t plh t phl 0.5v dd t r t f 0.5v dd 0.5v dd t r = t f 20ns 10% to 90% device under test test points c l (note) 0.5v dd 0.5v dd 0.5v dd 0.5v dd t phz t plz 0.1v dd 0.1v dd v dd 0v v oh v ol input oe port output port output t r t f t pzh t pzl 0v v dd t r = t f 20ns 10% to 90% hs-82c08rh
4 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 die characteristics die dimensions: 76.0 mils x 89.4 mils x 14 mils 1 mil interface materials: glassivation: type: sio 2 thickness: 8k ? 1k ? top metallization: type: si - al thickness: 11k ? 2k ? metallization mask layout hs-82c08rh a1 (2) a2 (3) a3 (4) a4 (5) a5 (6) a6 (7) a7 (8) (12) b7 (13) b6 (14) b5 (15) b4 (16) b3 (17) b2 (18) b1 oe (9) gnd (10) t/ r (9) (19) b0 (20) v dd (1) a0 hs-82c08rh
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