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3 nv/hz, low power instrumentation amplifier data sheet ad8421 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2012 analog devices, inc. all rights reserved. features low power 2.3 ma maximum supply current low noise 3.2 nv/hz maximum input voltage noise at 1 khz 200 fa/hz current noise at 1 khz excellent ac specifications 10 mhz bandwidth (g = 1) 2 mhz bandwidth (g = 100) 0.6 s settling time to 0.001% (g = 10) 80 db cmrr at 20 khz (g = 1) 35 v/s slew rate high precision dc performance (ad8421brz) 94 db cmrr minimum (g = 1) 0.2 v/c maximum input offset voltage drift 1 ppm/c maximum gain drift (g = 1) 500 pa maximum input bias current inputs protected to 40 v from opposite supply 2.5 v to 18 v dual supply (5 v to 36 v single supply) gain set with a single resistor (g = 1 to 10,000) applications medical instrumentation precision data acquisition microphone preamplification vibration analysis multiplexed input applications adc driver pin connection diagram top view (not to scale) ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 ad8421 10123-001 figure 1. 10 1n 100 1m total noise density at 1khz (v/ hz) source resistance, r s ( ? ) 10123-078 1 100n 10n 1k 10k 100k g = 100 ad8421 best available 1ma low power in-amp best available 7ma low noise in-amp r s noise only figure 2. noise density vs. source resistance general description the ad8421 is a low cost, low power, extremely low noise, ultralow bias current, high speed instrumentation amplifier that is ideally suited for a broad spectrum of signal conditioning and data acquisition applications. this product features extremely high cmrr, allowing it to extract low level signals in the presence of high frequency common-mode noise over a wide temperature range. the 10 mhz bandwidth, 35 v/s slew rate, and 0.6 s settling time to 0.001% (g = 10) allow the ad8421 to amplify high speed signals and excel in applications that require high channel count, multiplexed systems. even at higher gains, the current feedback architecture maintains high performance; for example, at g = 100, the bandwidth is 2 mhz and the settling time is 0.8 s. the ad8421 has excellent distortion performance, making it suitable for use in demanding applications such as vibration analysis. the ad8421 delivers 3 nv/hz input voltage noise and 200 fa/hz current noise with only 2 ma quiescent current, making it an ideal choice for measuring low level signals. for applications with high source impedance, the ad8421 employs innovative process technology and design techniques to provide noise performance that is limited only by the sensor. the ad8421 uses unique protection methods to ensure robust inputs while still maintaining very low noise. this protection allows input voltages up to 40 v from the opposite supply rail without damage to the part. a single resistor sets the gain from 1 to 10,000. the reference pin can be used to apply a precise offset to the output voltage. the ad8421 is specified from ?40c to +85c and has typical performance curves to 125c. it is available in 8-lead msop and soic packages.
ad8421 data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? pin connection diagram ................................................................ 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? ar and br grades........................................................................ 3 ? arm and brm grades................................................................ 5 ? absolute maximum ratings............................................................ 8 ? thermal resistance ...................................................................... 8 ? esd caution.................................................................................. 8 ? pin configuration and function descriptions............................. 9 ? typical performance characteristics ........................................... 10 ? theory of operation ...................................................................... 20 ? architecture................................................................................. 20 ? gain selection............................................................................. 20 ? reference terminal .................................................................... 21 ? input voltage range................................................................... 21 ? layout .......................................................................................... 21 ? input bias current return path ............................................... 22 ? input voltages beyond the supply rails.................................. 22 ? radio frequency interference (rfi)........................................ 23 ? calculating the noise of the input stage................................. 23 ? applications information .............................................................. 25 ? differential output configuration .......................................... 25 ? driving an adc ......................................................................... 26 ? outline dimensions ....................................................................... 27 ? ordering guide .......................................................................... 27 ? revision history 5/12revision 0: initial version
data sheet ad8421 rev. 0 | page 3 of 28 specifications v s = 15 v, v ref = 0 v, t a = 25c, g = 1, r l = 2 k, unless otherwise noted. ar and br grades table 1. ar grade br grade parameter test conditions/ comments min typ max min typ max unit common-mode rejection ratio (cmrr) cmrr dc to 60 hz with 1 k source imbalance v cm = ?10 v to +10 v g = 1 86 94 db g = 10 106 114 db g = 100 126 134 db g = 1000 136 140 db over temperature, g = 1 t = ?40c to +85c 80 93 db cmrr at 20 khz v cm = ?10 v to +10 v g = 1 80 80 db g = 10 90 100 db g = 100 100 110 db g = 1000 110 120 db noise voltage noise, 1 khz 1 v in +, v in ? = 0 v input voltage noise, e ni 3 3.2 3 3.2 nv/hz output voltage noise, e no 60 60 nv/hz peak to peak, rti f = 0.1 hz to 10 hz g = 1 2 2 2.2 v p-p g = 10 0.5 0.5 v p-p g = 100 to 1000 0.07 0.07 0.09 v p-p current noise spectral density f = 1 khz 200 200 fa/hz peak to peak, rti f = 0.1 hz to 10 hz 18 18 pa p-p voltage offset 2 input offset voltage, v osi v s = 5 v to 15 v 60 25 v over temperature t a = ?40c to +85c 86 45 v average tc 0.4 0.2 v/c output offset voltage, v oso 350 250 v over temperature t a = ?40c to +85c 0.66 0.45 mv average tc 6 5 v/c offset rti vs. supply (psr) v s = 2.5 v to 18 v g = 1 90 120 100 120 db g = 10 110 120 120 140 db g = 100 124 130 140 150 db g = 1000 130 140 140 150 db input current input bias current 1 2 0.1 0.5 na over temperature t a = ?40c to +85c 8 6 na average tc 50 50 pa/c input offset current 0.5 2 0.1 0.5 na over temperature t a = ?40c to +85c 2.2 0.8 na average tc 1 1 pa/c
ad8421 data sheet rev. 0 | page 4 of 28 ar grade br grade parameter test conditions/ comments min typ max min typ max unit dynamic response small signal bandwidth ?3 db g = 1 10 10 mhz g = 10 10 10 mhz g = 100 2 2 mhz g = 1000 0.2 0.2 mhz settling time to 0.01% 10 v step g = 1 0.7 0.7 s g = 10 0.4 0.4 s g = 100 0.6 0.6 s g = 1000 5 5 s settling time to 0.001% 10 v step g = 1 1 1 s g = 10 0.6 0.6 s g = 100 0.8 0.8 s g = 1000 6 6 s slew rate g = 1 to 100 35 35 v/s gain 3 g = 1 + (9.9 k/r g ) gain range 1 10,000 1 10,000 v/v gain error v out = 10 v g = 1 0.02 0.01 % g = 10 to 1000 0.2 0.1 % gain nonlinearity v out = ?10 v to +10 v g = 1 r l 2 k 1 1 ppm r l = 600 1 3 1 3 ppm g = 10 to 1000 r l 600 30 50 30 50 ppm v out = ?5 v to +5 v 5 10 5 10 ppm gain vs. temperature 3 g = 1 5 0.1 1 ppm/c g > 1 ?50 ?50 ppm/c input input impedance differential 30||3 30||3 g||pf common mode 30||3 30||3 g||pf input operating voltage range 4 v s = 2.5 v to 18 v ?v s + 2.3 +v s ? 1.8 ?v s + 2.3 +v s ? 1.8 v over temperature t a = ?40c ?v s + 2.5 +v s ? 2.0 ?v s + 2.5 +v s ? 2.0 v t a = +85c ?v s + 2.1 +v s ? 1.8 ?v s + 2.1 +v s ? 1.8 v output r l = 2 k output swing v s = 2.5 v to 18 v ?v s + 1.2 +vs ? 1.6 ?v s + 1.2 +v s ? 1.6 v over temperature t a = ?40c to +85c ?v s + 1.2 +vs ? 1.6 ?v s + 1.2 +v s ? 1.6 v short-circuit current 65 65 ma reference input r in 20 20 k i in v in +, v in ? = 0 v 20 24 20 24 a voltage range ?v s +v s ?v s +v s v reference gain to output 1 0.0001 1 0.0001 v/v
data sheet ad8421 rev. 0 | page 5 of 28 ar grade br grade parameter test conditions/ comments min typ max min typ max unit power supply operating range dual supply 2.5 18 2.5 18 v single supply 5 36 5 36 v quiescent current 2 2.3 2 2.3 ma over temperature t a = ?40c to +85c 2.6 2.6 ma temperature range for specified performance ?40 +85 ?40 +85 c operational 5 ?40 +125 ?40 +125 c 1 total voltage noise = (e ni 2 + (e no /g) 2 + e rg 2 ). see the th section for more information. eory of operation 2 total rti v os = (v osi ) + (v oso /g). 3 these specifications do not include the tolerance of the external gain setting resistor, r g . for g > 1, add r g errors to the specifications given in this table. 4 input voltage range of the ad8421 input stage only. the input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. see the section for more details. input voltage range 5 see the section for expected operation between 85c and 125c. typical performance char acteristics arm and brm grades table 2. arm grade brm grade parameter test conditions/ comments min typ max min typ max unit common-mode rejection ratio (cmrr) cmrr dc to 60 hz with 1 k source imbalance v cm = ?10 v to +10 v g = 1 84 92 db g = 10 104 112 db g = 100 124 132 db g = 1000 134 140 db over temperature, g = 1 t a = ?40c to +85c 80 90 db cmrr at 20 khz v cm = ?10 v to +10 v g = 1 80 80 db g = 10 90 90 db g = 100 100 100 db g = 1000 100 100 db noise voltage noise, 1 khz 1 v in +, v in ? = 0 v input voltage noise, e ni 3 3.2 3 3.2 nv/hz output voltage noise, e no 60 60 nv/hz peak to peak, rti f = 0.1 hz to 10 hz g = 1 2 2 2.2 v p-p g = 10 0.5 0.5 v p-p g = 100 to 1000 0.07 0.07 0.09 v p-p current noise spectral density f = 1 khz 200 200 fa/hz peak to peak, rti f = 0.1 hz to 10 hz 18 18 pa p-p voltage offset 2 input offset voltage, v osi v s = 5 v to 15 v 70 50 v over temperature t a = ?40c to +85c 135 135 v average tc 0.9 0.9 v/c output offset voltage, v oso 600 400 v over temperature t a = ?40c to +85c 1 1 mv average tc 9 9 v/c
ad8421 data sheet rev. 0 | page 6 of 28 arm grade brm grade parameter test conditions/ comments min typ max min typ max unit offset rti vs. supply (psr) v s = 2.5 v to 18 v g = 1 90 120 100 120 db g = 10 110 120 120 140 db g = 100 124 130 140 150 db g = 1000 130 140 140 150 db input current input bias current 1 2 0.1 1 na over temperature t a = ?40c to +85c 8 6 na average tc 50 50 pa/c input offset current 0.5 2 0.1 1 na over temperature t a = ?40c to +85c 3 1.5 na average tc 1 1 pa/c dynamic response small signal bandwidth ?3 db g = 1 10 10 mhz g = 10 10 10 mhz g = 100 2 2 mhz g = 1000 0.2 0.2 mhz settling time 0.01% 10 v step g = 1 0.7 0.7 s g = 10 0.4 0.4 s g = 100 0.6 0.6 s g = 1000 5 5 s settling time 0.001% 10 v step g = 1 1 1 s g = 10 0.6 0.6 s g = 100 0.8 0.8 s g = 1000 6 6 s slew rate g = 1 to 100 35 35 v/s gain 3 g = 1 + (9.9 k/r g ) gain range 1 10,000 1 10,000 v/v gain error v out = 10 v g = 1 0.05 0.02 % g = 10 to 1000 0.3 0.2 % gain nonlinearity v out = ?10 v to +10 v g = 1 r l 2 k 1 1 ppm r l = 600 1 3 1 3 ppm g = 10 to 1000 r l 600 30 50 30 50 ppm v out = ?5 v to +5 v 5 10 5 10 ppm gain vs. temperature 3 g = 1 5 0.1 1 ppm/c g > 1 ?50 ?50 ppm/c input input impedance differential 30||3 30||3 g||pf common mode 30||3 30||3 g||pf input operating voltage range 4 v s = 2.5 v to 18 v ?v s + 2.3 +v s ? 1.8 ?v s + 2.3 +v s ? 1.8 v o ver temperature t a = ?40c ?v s + 2.5 +v s ? 2.0 ?v s + 2.5 +v s ? 2.0 v t a = +85c ?v s + 2.1 +v s ? 1.8 ?v s + 2.1 +v s ? 1.8 v
data sheet ad8421 rev. 0 | page 7 of 28 arm grade brm grade parameter test conditions/ comments min typ max min typ max unit output r l = 2 k output swing v s = 2.5 v to 18 v ?v s + 1.2 +v s ? 1.6 ?v s + 1.2 +vs ? 1.6 v over temperature t a = ?40c to +85c ?v s + 1.2 +v s ? 1.6 ?v s + 1.2 +vs ? 1.6 v short-circuit current 65 65 ma reference input r in 20 20 k i in v in +, v in ? = 0 v 20 24 20 24 a voltage range ?v s +v s ?v s +v s v reference gain to output 1 0.0001 1 0.0001 v/v power supply operating range dual supply 2.5 18 2.5 18 v single supply 5 36 5 36 v quiescent current 2 2.3 2 2.3 ma over temperature t a = ?40c to +85c 2.6 2.6 ma temperature range for specified performance ?40 +85 ?40 +85 c operational 5 ?40 +125 ?40 +125 c 1 total voltage noise = (e ni 2 + (e no /g) 2 + e rg 2 ). see the th section for more information. eory of operation 2 total rti v os = (v osi ) + (v oso /g). 3 these specifications do not include the tolerance of the external gain setting resistor, r g . for g > 1, add r g errors to the specifications given in this table. 4 input voltage range of the ad8421 input stage only. the input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. see the se ction for more information. input voltage range 5 see the section for expected operation between 85c and 125c. typical performance char acteristics
ad8421 data sheet rev. 0 | page 8 of 28 absolute maximum ratings table 3. parameter rating supply voltage 18 v output short-circuit current duration indefinite maximum voltage at ?in or +in 1 ?v s + 40 v minimum voltage at ?in or +in +v s ? 40 v maximum voltage at ref 2 +v s + 0.3 v minimum voltage at ref ?v s ? 0.3 v storage temperature range ?65c to +150c operating temperature range ?40c to +125c maximum junction temperature 150c esd human body model 2 kv charged device model 1.25 kv machine model 0.2 kv 1 for voltages beyond these limits, us e input protection resistors. see the theory of operation section for more information. 2 there are esd protection diodes from the reference input to each supply, so ref cannot be driven beyond the supplies in the same way that +in and ?in can. see the reference terminal section for more information. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for a device in free air using a 4-layer jedec printed circuit board (pcb). table 4. package ja unit 8-lead soic 107.8 c/w 8-lead msop 138.6 c/w esd caution
data sheet ad8421 rev. 0 | page 9 of 28 pin configuration and fu nction descriptions top view (not to scale) ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 ad8421 10123-002 figure 3. pin configuration table 5. pin function descriptions pin o. neonic description 1 ?in negative input terminal. 2, 3 r g gain setting terminals. place resistor across the r g pins to set the gain. g = 1 + (9.9 k/r g ). 4 +in positive input terminal. 5 ?v s negative power supply terminal. 6 ref reference voltage terminal. drive this terminal with a low impedance voltage source to level shift the output. 7 v out output terminal. 8 +v s positive power supply terminal.
ad8421 data sheet rev. 0 | page 10 of 28 typical performance characteristics t a = 25c, v s = 15 v, v ref = 0 v, r l = 2 k, unless otherwise noted. 600 0 100 200 300 400 500 ?60 ?40 ?20 20 40 06 units input offset voltage (v) 0 10123-003 figure 4. typical distributi on of input offset voltage 1800 0 300 600 900 1200 1500 ?2.0 ?1.5 1.5 1.0 ?1.0 ?0.5 0 0.5 2.0 units input bias current (na) 10123-004 figure 5. typical distributi on of input bias current 1400 0 200 400 600 800 1200 1000 ?20 ?15 15 10 ?10 ?5 0 5 20 units psrr (v/v) 10123-005 figure 6. typical distribution of psrr (g = 1) 600 0 100 200 300 400 500 ?400 ?300 300 200 ?200 ?100 0 100 400 units output offset voltage (v) 10123-006 figure 7. typical distribution of output offset voltage 800 1000 1200 600 0 200 400 ?2.0 ?1.5 ?1.0 ?0.5 0.5 1.0 1.5 02 units input offset current (na) 10123-007 . 0 figure 8. typical distribution of input offset current 600 800 1000 1200 1400 1600 0 200 400 ?120 120 906030 0 ?30 ?60 ?90 units cmrr (v/v) 10123-008 figure 9. typical distribution of cmrr (g = 1)
data sheet ad8421 rev. 0 | page 11 of 28 15 10 5 0 ?15 ?10 ?5 ?15 15 10 5 ?5 ?10 0 common-mode voltage (v) output voltage (v) v s = 15v v s = 12v 10123-009 g = 1 figure 10. input common-mode voltage vs. output voltage; v s = 12 v and 15 v (g = 1) 4 3 2 0 1 ?3 ?2 ?1 ?4 4 321 ?3 ?2 ?1 0 common-mode voltage (v) output voltage (v) v s = 5v v s = 2.5v 10123-010 g = 1 figure 11. input common-mode voltage vs. output voltage; v s = 2.5 v and 5 v (g = 1) 15 10 5 0 ?15 ?10 ?5 ?15 15 10 5 ?5 ?10 0 common-mode voltage (v) output voltage (v) v s = 15v v s = 12v 10123-011 g = 100 figure 12. input common-mode voltage vs. output voltage; v s = 12 v and 15 v (g = 100) 4 3 2 0 1 ?3 ?2 ?1 ?4 4 321 ?3 ?2 ?1 0 common-mode voltage (v) output voltage (v) v s = 5v v s = 2.5v 10123-012 g = 100 figure 13. input common-mode voltage vs. output voltage; v s = 2.5 v and 5 v (g = 100) 40 ?40 ?35 40 input current (ma) input voltage (v) ?30 ?20 ?10 0 10 20 30 ?30?25?20?15?10?5 0 5 101520253035 v s = 5v g = 1 10123-013 figure 14. input overvoltage performance; g = 1, +v s = 5 v, ?v s = 0 v 30 ?30 ?25 25 input current (ma) input voltage (v) ?20 ?10 0 10 20 ?20 ?15 ?10 ?5 0 5 10 15 20 v s = 15v g = 1 10123-014 figure 15. input overvoltage performance; g = 1, v s = 15 v
ad8421 data sheet rev. 0 | page 12 of 28 40 ?40 ?35 40 input current (ma) input voltage (v) ?30 ?20 ?10 0 10 20 30 ?30?25?20?15?10?5 0 5 101520253035 v s = 5v g = 100 10123-015 figure 16. input overvoltage performance; +v s = 5 v, ?v s = 0 v, g = 100 30 ?30 ?25 25 input current (ma) input voltage (v) ?20 ?10 0 10 20 ?20 ?15 ?10 ?5 0 5 10 15 20 v s = 15v g = 100 10123-016 figure 17. input overvoltage performance; v s = 15 v, g = 100 2.5 ?2.5 ?12 14 bias current (na) common-mode voltage (v) ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?10?8?6?4?2024681012 10123-017 figure 18. input bias current vs. common-mode voltage 160 140 120 100 80 60 40 20 0 0.1 1 10 100 1k 10k 100k 1m frequency (hz) positive psrr (db) gain = 100 gain = 10 gain = 1 gain = 1000 10123-018 figure 19. positive psrr vs. frequency 160 140 120 100 80 60 40 20 0 0.1 1 10 100 1k 10k 100k 1m frequency (hz) negative psrr (db) gain = 100 gain = 10 gain = 1 gain = 1000 10123-019 figure 20. negative psrr vs. frequency 70 ?30 100 1k 10k 100k 1m 10m gain (db) frequency (hz) ?20 ?10 0 10 20 30 40 50 60 gain = 100 gain = 10 gain = 1 gain = 1000 10123-020 figure 21. gain vs. frequency
data sheet ad8421 rev. 0 | page 13 of 28 40 60 80 100 cmrr (db) 120 140 160 0.1 1 10 100 1k 10k 100k frequency (hz) gain = 1000 gain = 100 gain = 10 gain = 1 10123-021 figure 22. cmrr vs. frequency 40 60 80 100 cmrr (db) 120 140 160 0.1 1 10 100 1k 10k 100k frequency (hz) gain = 1000 gain = 100 gain = 10 gain = 1 10123-022 figure 23. cmrr vs. frequency, 1 k source imbalance 2.0 1.5 0.5 0 1.0 ?0.5 05 change in input offset voltage (v) warm-up time (seconds) 5 1015202530354045 0 10123-023 figure 24. change in input offset voltage (v osi ) vs. warm-up time 6 ?8 ?40 125 bias current (na) temperature (c) ?6 ?4 ?2 0 2 4 ?25?105 203550658095110 representative samples 10123-024 figure 25. input bias current vs. temperature 100 ?80 ?40 125 gain error (v/v) temperature (c) ?60 ?40 ?20 0 20 40 60 80 ?25?105 203550658095110 representative samples gain = 1 10123-025 figure 26. gain vs. temperature (g = 1) 15 10 5 ?15 ?10 ?5 0 ?40 125 cmrr (v/v) temperature (c) ?25?105 203550658095110 representative samples gain = 1 10123-074 figure 27. cmrr vs. temperature (g = 1)
ad8421 data sheet rev. 0 | page 14 of 28 3.0 2.5 2.0 1.5 1.0 0.5 0 ?40 125 supply current (ma) temperature (c) ?25 ?10 5 20 35 50 65 80 95 110 v s = 15v v s = 5v 10123-026 figure 28. supply current vs. temperature (g = 1) 80 ?120 ?40 110 short-circuit current (ma) temperature (c) ?100 ?80 ?60 ?40 ?20 0 20 40 60 ?25 ?10 5 20 35 50 65 80 95 125 i short+ i short? 10123-027 figure 29. short-circuit current vs. temperature (g = 1) 40 0 ?40 125 slew rate (v/s) temperature (c) 5 10 15 20 25 30 35 ?25 ?10 5 20 35 50 65 80 95 110 ?sr +sr 10123-028 figure 30. slew rate vs. temperature, v s = 15 v (g = 1) 40 0 ?40 125 slew rate (v/s) temperature (c) 5 10 15 20 25 30 35 ?25 ?10 5 20 35 50 65 80 95 110 ?sr +sr 10123-029 figure 31. slew rate vs. temperature, v s = 5 v (g = 1) + v s ?v s 21 input voltage (v) referred to supply voltages supply voltage (v s ) 4 6 8 10121416 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 +0.5 +1.0 +1.5 +2.0 +2.5 8 ?40c +25c +85c +105c +125c 10123-030 figure 32. input voltage limit vs. supply voltage + v s ?v s 02 20 18 output voltage (v) referred to supply voltages supply voltage (v s ) 4 6 8 10 12 14 16 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 +0.5 +1.0 +1.5 +2.0 +2.5 ?40c +25c +85c +105c +125c 10123-031 figure 33. output voltage swing vs. supply voltage, r l = 10 k
data sheet ad8421 rev. 0 | page 15 of 28 + v s ?v s 02 20 18 output voltage (v) referred to supply voltages supply voltage (v s ) 4 6 8 10 12 14 16 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 +0.5 +1.0 +1.5 +2.0 +2.5 ?40c +25c +85c +105c +125c 10123-032 figure 34. output voltage swing vs. supply voltage, r l = 600 15 10 ?15 ?10 ?5 5 0 100 100k output voltage swing (v) load ( ? ) 1k 10k ?40c +25c +85c +105c +125c 10123-033 figure 35. output voltage swing vs. load resistance + v s ?v s 0 0.01 0.10 0.09 output voltage swing (v) referred to supply voltages output current (a) 0.02 0.03 0.04 0.05 0.06 0.07 0.08 ?2 ?4 ?6 ?8 +2 +4 +6 +8 ?40c +25c +85c +105c +125c 10123-034 figure 36. output voltage swing vs. output current 5 4 3 ?5 ?4 ?3 ?2 ?1 0 1 2 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 nonlinearity (ppm) output voltage (v) gain = 1 r l = 2k ? r l = 10k ? 10123-035 figure 37. gain nonlinearity (g = 1), r l = 10 k, 2 k 5 4 3 ?5 ?4 ?3 ?2 ?1 0 1 2 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 nonlinearity (ppm) output voltage (v) gain = 1 r l = 600 ? 10123-036 figure 38. gain nonlinearity (g = 1), r l = 600 100 80 60 ?100 ?80 ?60 ?40 ?20 0 20 40 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 nonlinearity (ppm) output voltage (v) gain = 1000 r l = 600 ? 10123-072 figure 39. gain nonlinearity (g = 1000), r l = 600 , v out = 10 v
ad8421 data sheet rev. 0 | page 16 of 28 100 80 60 ?100 ?80 ?60 ?40 ?20 0 20 40 ?5?4?3?2?1012345 nonlinearity (ppm) output voltage (v) gain = 1000 r l = 600 ? 10123-073 figure 40. gain nonlinearity (g = 1000), r l = 600 , v out = 5 v voltage noise spectral density (nv/ hz) 1 100 10 1k 1 10 100 1k 10k 100k frequency (hz) gain = 1 gain = 10 gain = 100 gain = 1000 10123-037 figure 41. rti voltage noise spectral density vs. frequency 1s/div g = 1000, 40nv/div g = 1, 1v/div 10123-038 figure 42. 0.1 hz to 10 hz rti voltage noise (g = 1, g = 1000) 10k 1k 100 10 0.1 1 10 100 1k 10k 100k current noise (fa/ hz) frequency (hz) 10123-039 figure 43. current noise spectral density vs. frequency 1s/div 5pa/div 10123-040 figure 44. 0.1 hz to 10 hz current noise 30 25 0 5 10 15 20 10 100 1k 10k 100k 1m 10m output voltage (v p-p) frequency (hz) 10123-045 figure 45. large signal frequency response
data sheet ad8421 rev. 0 | page 17 of 28 1s/div 5v/div 0.002%/div 720ns to 0.01% 1.12s to 0.001% 10123-041 figure 46. large signal pulse response and settling time (g = 1), 10 v step, v s = 15 v, r l = 2 k, c l = 100 pf 1s/div 5v/div 0.002%/div 420ns to 0.01% 604ns to 0.001% 10123-042 figure 47. large signal pulse response and settling time (g = 10), 10 v step, v s = 15 v, r l = 2 k, c l = 100 pf 1s/div 5v/div 0.002%/div 704ns to 0.01% 764ns to 0.001% 10123-043 figure 48. large signal pulse response and settling time (g = 100), 10 v step, v s = 15 v, r l = 2 k, c l = 100 pf 4s/div 5v/div 0.002%/div 3.8s to 0.01% 5.76s to 0.001% 10123-044 figure 49. large signal pulse response and settling time (g = 1000), 10 v step, v s = 15 v, r l = 2 k, c l = 100 pf 2500 0 22 settling time (ns) step size (v) 500 1000 1500 2000 4 6 8 10 12 14 16 18 0 settled to 0.01% settled to 0.001% 10123-054 gain = 1 figure 50. settling time vs. step size (g = 1), r l = 2 k, c l = 100 pf 50mv/div gain = 1 1s/div 10123-046 figure 51. small signal pulse response (g = 1), r l = 600 , c l = 100 pf
ad8421 data sheet rev. 0 | page 18 of 28 50mv/div gain = 10 1s/div 10123-047 figure 52. small signal pulse response (g = 10), r l = 600 , c l = 100 pf 20mv/div gain = 100 1s/div 10123-048 figure 53. small signal pulse response (g = 100), rl = 600 , cl = 100 pf 20mv/div gain = 1000 2s/div 10123-049 figure 54. small signal pulse response (g = 1000), r l = 600 , c l = 100 pf 10123-053 g = 1 no load 20pf 50pf 100pf 50mv/div 1s/div figure 55. small signal response with various capacitive loads (g = 1), r l = infinity ? 40 ?150 10 10k 1k 100 amplitude (dbc) frequency (hz) 10123-055 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 r l 600 ? v out = 10v p-p figure 56. second harmonic distortion vs. frequency (g = 1) ? 40 ?150 10 10k 1k 100 amplitude (dbc) frequency (hz) 10123-056 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 no load r l = 2k ? r l = 600 ? v out = 10v p-p figure 57. third harmonic distortion vs. frequency (g = 1)
data sheet ad8421 rev. 0 | page 19 of 28 ? 40 ?120 10 10k 1k 100 amplitude (dbc) frequency (hz) 10123-075 ?110 ?100 ?90 ?80 ?70 ?60 ?50 v out = 10v p-p no load r l = 2k ? r l = 600 ? figure 58. second harmonic distortion vs. frequency (g = 1000) ? 40 ?120 10 10k 1k 100 amplitude (dbc) frequency (hz) 10123-076 ?110 ?100 ?90 ?80 ?70 ?60 ?50 v out = 10v p-p r l 600 ? figure 59. third harmonic distortion vs. frequency (g = 1000) ? 20 ?140 10 10k 1k 100 amplitude (dbc) frequency (hz) 10123-077 ?110 ?120 ?130 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 g = 1 g = 10 g = 100 g = 1000 v out = 10v p-p r l = 2k ? figure 60. thd vs. frequency
ad8421 data sheet rev. 0 | page 20 of 28 theory of operation a3 a1 a2 q2 q1 c1 c2 +in ? in +v s ?v s 10k? 10k ? 10k ? +v s ?v s output ref node 1 node 2 i b compensation i b compensation r g v b ii +v s +v s + v s 10k ? r1 4.95k ? r2 4.95k ? difference amplifier stage gain stage i i esd and overvoltage protection esd and overvoltage protection super node 3 node 4 super ?v s 10123-057 figure 61. simpli fied schematic architecture the ad8421 is based on the classic 3-op-amp topology. this topology has two stages: a preamplifier to provide differential amplification, followed by a difference amplifier that removes the common-mode voltage. figure 61 shows a simplified schematic of the ad8421. topologically, q1, a1, r1 and q2, a2, r2 can be viewed as precision current feedback amplifiers. input transistors q1 and q2 are biased at a fixed current so that any input signal forces the output voltages of a1 and a2 to change accordingly. the differential signal applied to the inputs is replicated across the r g pins. any current through r g also flows through r1 and r2, creating a gained differential voltage between node 1 and node 2. the amplified differential and common-mode signals are applied to a difference amplifier that rejects the common-mode voltage but preserves the amplified differential voltage. the difference amplifier employs innovations that result in very low output errors such as offset voltage and drift, distortion at various loads, as well as output noise. laser-trimmed resistors allow for a highly accurate in-amp with gain error less than 0.01% and cmrr that exceeds 94 db (g = 1). the high performance pinout and special attention given to design and layout allow for high cmrr performance across a wide frequency and temperature range. using superbeta input transistors and bias current compensation, the ad8421 offers extremely high input impedance, low bias cur- rent, low offset current, low current noise, and extremely low voltage noise of 3 nv/hz. the current-limiting and overvoltage protection scheme allow the input to go 40 v from the opposite rail at all gains without compromising the noise performance. the transfer function of the ad8421 is v out = g ( v +in ? v ?in ) + v ref where g = 1 + g r k ? 9.9 users can easily and accurately set the gain using a single standard resistor. gain selection placing a resistor across the r g terminals sets the gain of the ad8421 . the gain can be calculated by referring to table 6 or by using the following gain equation: r g = 1 k ? 9.9 ? g the ad8421 defaults to g = 1 when no gain resistor is used. to determine the total gain accuracy of the system, add the tolerance and gain drift of the r g resistor to the specifications of the ad8421 . when the gain resistor is not used, gain error and gain drift are minimal. table 6. gains achieved using 1% resistors 1% standard table value of r g calculated gain 10 k 1.99 2.49 k 4.98 1.1 k 10.00 523 19.93 200 50.50 100 100.0 49.9 199.4 20 496.0 10 991.0 4.99 1985 r g power dissipation the ad8421 duplicates the differential voltage across its inputs onto the r g resistor. choose an r g resistor size that is sufficient to handle the expected power dissipation at ambient temperature.
data sheet ad8421 rev. 0 | page 21 of 28 reference terminal the output voltage of the ad8421 is developed with respect to the potential on the reference terminal. this can be used to sense the ground at the load, thereby taking advantage of the cmrr to reject ground noise or to introduce a precise offset to the signal at the output. for example, a voltage source can be tied to the ref pin to level shift the output, allowing the ad8421 to drive a single- supply adc. the ref pin is protected with esd diodes and should not exceed either +v s or ?v s by more than 0.3 v. for best performance, maintain a source impedance to the ref terminal that is below 1 . as shown in figure 61 , the reference terminal, ref, is at one end of a 10 k resistor. additional impedance at the ref terminal adds to this 10 k resistor and results in amplification of the signal connected to the positive input. the amplification from the additional r ref can be calculated as follows: 2(10 k + r ref )/(20 k + r ref ) only the positive signal path is amplified; the negative path is unaffected. this uneven amplification degrades cmrr. incorrect v correct ad8421 op1177 + ? v ref ad8421 ref 10123-058 figure 62. driving the reference pin input voltage range the 3-op-amp architecture of the ad8421 applies gain in the first stage before removing the common-mode voltage in the difference amplifier stage. internal nodes between the first and second stages (node 1 and node 2 in figure 61 ) experience a combination of a gained signal, a common-mode signal, and a diode drop. the voltage supplies can limit the combined signal, even when the individual input and output signals are not limited. figure 10 through figure 13 show this limitation in detail. layout to ensure optimum performance of the ad8421 at the pcb level, care must be taken in the design of the board layout. the pins of the ad8421 are arranged in a logical manner to aid in this task. 8 7 6 5 1 2 3 4 ?in r g r g +v s v out ref ?v s +in top view (not to scale) ad8421 10123-059 figure 63. pin configuration diagram common-mode reection ratio over frequency poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. such conversions occur when one input path has a frequency response that is different from the other. to maintain high cmrr over frequency, closely match the input source impedance and capacitance of each path. place additional source resistance in the input path (for example, input protection resistors) close to the in-amp inputs, to minimize the interaction of the resistance with parasitic capacitance from the pcb traces. parasitic capacitance at the gain setting pins (r g ) can also affect cmrr over frequency. if the board design has a component at the gain setting pins (for example, a switch or jumper), choose a component such that the parasitic capacitance is as small as possible. power supplies and grounding use a stable dc voltage to power the instrumentation amplifier. noise on the supply pins can adversely affect performance. place a 0.1 f capacitor as close as possible to each supply pin. because the length of the bypass capacitor leads is critical at high frequency, surface-mount capacitors are recommended. any parasitic inductance in the bypass ground trace works against the low impedance that is created by the bypass capacitor. as shown in figure 64 , a 10 f capacitor can be used farther away from the device. for these larger value capacitors, which are intended to be effective at lower frequencies, the current return path distance is less critical. in most cases, the 10 f capacitor can be shared by other local precision integrated circuits. ad8421 + v s +in ?in load r g ref 0.1f 10f 0.1f 10f ?v s v out 10123-060 figure 64. supply decoupling, ref, and output referred to local ground a ground plane layer helps to reduce parasitic inductances, which minimizes voltage drops with changes in current. the area of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the impedance of the path at high frequency. large changes in currents in an inductive decoupling path or ground return create unwanted effects due to the coupling of such changes into the amplifier inputs. because load currents flow from the supplies, the load should be connected at the same physical location as the bypass capacitor grounds.
ad8421 data sheet rev. 0 | page 22 of 28 reference pin the output voltage of the ad8421 is developed with respect to the potential on the reference terminal. ensure that ref is tied to the appropriate local ground. input bias current return path the input bias current of the ad8421 must have a return path to ground. when using a floating source without a current return path (such as a thermocouple), create a current return path as shown in figure 65 . thermocouple +v s ref ?v s ad8421 capacitively coupled +v s ref c c ?v s ad8421 transformer +v s ref ?v s ad8421 incorrect capacitively coupled +v s ref c r r c ?v s ad8421 1 f high-pass = 2 rc thermocouple +v s ref ?v s 10m ? ad8421 transformer +v s ref ?v s ad8421 correct 10123-061 figure 65. creating an input bias current return path input voltages beyond the supply rails the ad8421 has very robust inputs. it typically does not need additional input protection, as shown in figure 66 . most applications + v s ad8421 ?v s i v in+ + ? v in+ + ? 10123-062 figure 66. typical application; no input protection required the ad8421 inputs are current limited; therefore, input voltages can be up to 40 v from the opposite supply rail, with no input protection required at all gains. for example, if +v s = +5 v and ?v s = ?8 v, the part can safely withstand voltages from ?35 v to +32 v. the remaining ad8421 terminals should be kept within the supplies. all terminals of the ad8421 are protected against esd. input voltages beyond the maximum ratings for applications where the ad8421 encounters voltages beyond the limits in the absolute maximum ratings table, external protection is required. this external protection depends on the duration of the overvoltage event and the noise performance that is required. for short-lived events, transient protectors (such as metal oxide varistors (movs)), may be all that is required. + v s ad8421 ?v s v in+ + ? v in? + ? + v s ad8421 r protect r protect ?v s i v in+ + ? v in? + ? +v s +v s ad8421 r protect r protect ?v s ?v s i v in+ + ? v in? + ? +v s ?v s +v s ad8421 r protect r protect ?v s i v in+ + ? v in? + ? i simple continuous protection transient protection low noise continuous option 2 low noise continuous option 1 10123-063 figure 67. input protection options for input voltages beyond absolute maximum ratings for longer events, use resistors in series with the inputs, combined with diodes. to avoid degrading bias current performance, low leakage diodes such as the bav199 or fjh1100 are recommended. the diodes prevent the voltage at the input of the amplifier from exceeding the maximum ratings, and the resistors limit the current into the diodes. because most external diodes can easily handle 100 ma or more, resistor values do not need to be large and, therefore, have a minimal impact on noise performance. at the expense of some noise performance, another solution is to use series resistors. in the case of overvoltage, current into the ad8421 inputs is internally limited. although the ad8421 inputs must be kept within the limits defined in the absolute maximum ratings section, the i r drop across the protection resistor increases the maximum voltage that the system can withstand, as follows: for positive input signals v manew = (40 v + negative supply ) + i in r protect for negative input signals v minnew = ( positive supply ? 40 v) ? i out r protect
data sheet ad8421 rev. 0 | page 23 of 28 overvoltage performance is shown in figure 14 , figure 15, figure 16, and figure 17. the ad8421 inputs can withstand a current of 40 ma at room temperature for at least a day. this time is cumulative over the life of the device. if long periods of overvoltage are expected, the use of an external protection method is recommended. under extreme input conditions, the output of the amplifier may invert. radio frequency interference (rfi) rf rectification is often a problem when amplifiers are used in applications that have strong rf signals. the problem is intensified if long leads or pcb traces are required to connect the amplifier to the signal source. the disturbance can appear as a dc offset voltage or a train of pulses. high frequency signals can be filtered with a low-pass filter network at the input of the instrumentation amplifier, as shown in figure 68 . r r ad8421 + v s +in ?in 0.1f 10f 10f 0.1f ref v out ?v s c d 10nf c c 1nf c c 1nf 33? 33? 10123-067 l* l* *chip ferrite bead. figure 68. rfi suppression the choice of resistor and capacitor values depends on the desired trade-off between noise, input impedance at high frequencies, cmrr, signal bandwidth, and rfi immunity. an rc network limits both the differential and common-mode bandwidth, as shown in the following equations: )2(2 1 c d diff ccr uency filterfreq + = c cm rc uency filterfreq 2 1 = where c d 10 c c . c d affects the differential signal, and c c affects the common- mode signal. a mismatch between r c c at the positive input and r c c at the negative input degrades the cmrr of the ad8421 . by using a value of c d that is one order of magnitude larger than c c , the effect of the mismatch is reduced and cmrr performance is improved near the cutoff frequencies. to achieve low noise and sufficient rfi filtering, the use of chip ferrite beads is recommended. ferrite beads increase their impe- dance with frequency, thus leaving the signal of interest unaffected while preventing rf interference to reach the amplifier. they also help to eliminate the need for large resistor values in the filter, thus minimizing the systems input-referred noise. the selection of the appropriate ferrite bead and capacitor values is a function of the interference frequency, input lead length, and rf power. for best results, place the rfi filter network as close as possible to the amplifier. layout is critical to ensure that rf signals are not picked up on the traces after the filter. if rf interference is too strong to be filtered sufficiently, shielding is recommended. the resistors used for the rfi filter can be the same as those used for input protection. calculating the noise of the input stage the total noise of the amplifier front end depends on much more than the 3.2 nv/hz specification of this data sheet. the three main contributors to noise are: the source resistance, the voltage noise of the instrumentation amplifier, and the current noise of the instrumentation amplifier. in the following calculations, noise is referred to the input (rti). in other words, all sources of noise are calculated as if the source appeared at the amplifier input. to calculate the noise referred to the amplifier output (rto), multiply the rti noise by the gain of the instru-mentation amplifier. source resistance noise any sensor connected to the ad8421 has some output resistance. there may also be resistance placed in series with inputs for pro- tection from either overvoltage or radio frequency interference. this combined resistance is labeled r1 and r2 in figure 69 . any resistor, no matter how well made, has an intrinsic level of noise. this noise is proportional to the square root of the resistor value. at room temperature, the value is approximately equal to 4 nv/hz (resistor value in k). r2 r g r1 senso r ad8421 10123-065 figure 69. source resistance from sensor and protection resistors for example, assume that the combined sensor and protection resistance is 4 k on the positive input and 1 k on the negative input. then the total noise from the input resistance is ( ) ( ) =+=+ 16641444 2 2 8.9 nv/hz
ad8421 data sheet rev. 0 | page 24 of 28 voltage noise of the instrumentation amplifier the voltage noise of the instrumentation amplifier is calculated using three parameters: the device output noise, the input noise, and the r g resistor noise. it is calculated as follows: total voltage noise = ( ) ( ) ( ) 2 2 2 / resistorrofnoise noiseinputgnoise output g + + for example, for a gain of 100, the gain resistor is 100 . therefore, the voltage noise of the in-amp is () () 2 2 2 1.042.3100/60 + + = 3.5 nv/hz current noise of the instrumentation amplifier current noise is converted to a voltage by the source resistance. the effect of current noise can be calculated by multiplying the specified current noise of the in-amp by the value of the source resistance. for example, if the r1 source resistance in figure 69 is 4 k, and the r2 source resistance is 1 k, the total effect from the current noise is calculated as follows: ()() 2 2 2.012.04 + = 0.8 nv/hz total noise density calculation to determine the total noise of the in-amp, referred to input, combine the source resistance noise, voltage noise, and current noise contribution by the sum of squares method. for example, if the r1 source resistance in figure 69 is 4 k, the r2 source resistance is 1 k, and the gain of the in-amp is 100, the total noise, referred to input, is 222 8.05.39.8 ++ = 9.6 nv/hz
data sheet ad8421 rev. 0 | page 25 of 28 applications information differential output configuration although the dc performance and resistor matching of the op amp affect the dc common-mode output accuracy, such errors are likely to be rejected by the next device in the signal chain and, therefore, typically have little effect on overall system accuracy. figure 70 shows an example of how to configure the ad8421 for differential output. +in ?in ref ad8421 v bias + ? op amp +out ?out 10123-066 12pf 10k ? 10k ? because this circuit is susceptible to instability, a capacitor is included to limit the effective op amp bandwidth. this capacitor can be omitted if the amplifier pairing is stable. the open-loop gain and phase of any amplifier may vary with process variation and temperature. additional phase lag can be introduced by resistive or capacitive loading. to guarantee stability, the value of the capacitor in figure 70 should be determined with a sample of circuits by evaluating the small signal pulse response of the circuit with load at the extremes of the output dynamic range. figure 70. differential output configuration with op amp the ambient temperature should also be varied over the expected range to evaluate its effect on stability. the voltage at +out may still have some overshoot after the circuit is tuned because the ad8421 output amplifier responds faster than the op amp. a 12 pf capacitor is a good starting point. the differential output voltage is set by the following equation: v diff_out = v +out ? v ?out = gain (v +in ? v ?in ) the common-mode output is set by the following equation: v cm_out = ( v +out + v ?out )/2 = v bias for best large signal ac performance, use an op amp with a high slew rate to match the ad8421 performance of 35 v/s. high bandwidth is not essential because the system bandwidth is limited by the rc feedback. some good choices for op amps are the ad8610 , ada4627-1 , ad8510 , and the ada4898-1 . the advantage of this circuit is that the dc differential accuracy depends on the ad8421 , not on the op amp or the resistors. in addition, this circuit takes advantage of the precise control that the ad8421 has of its output voltage relative to the reference voltage.
ad8421 data sheet rev. 0 | page 26 of 28 driving an adc the class ab output stage, low noise and distortion, and high bandwidth and slew rate make the ad8421 a good choice for driving an adc in a data acquisition system that requires front- end gain, high cmrr, and dc precision. figure 71 shows the ad8421 , in a gain-of-10 configuration, driving the ad7685, a 16-bit, 250 ksps pseudodifferential sar adc. the rc low-pass filter that is shown between the ad8421 and the ad7685 has several purposes. it isolates the amplifier output from excessive loading from the dynamic adc inputs, reduces the noise bandwidth of the amplifier, and provides overload protection for the ad7685 analog inputs. the filter cutoff can be determined empirically. to achieve the best ac performance, keep the impe- dance magnitude greater than 1 k at the maximum input signal frequency, and set the filter cutoff to settle to ? lsb in one sampling period for a full-scale step. for additional considerations, refer to the data sheet of the adc in use. in a gain-of-10 configuration, the ad8421 has approximately 8 nv/hz voltage noise rti (see the calculating the noise of the input stage section.) the front-end gain makes the system ten times more sensitive to input signals, with only a 7.5 db reduction of snr. the high current output and load regulation of the adr435 allow the ad7685 to be powered directly from the reference without the need to provide another analog supply rail. the reference pin buffer may be any low power, unity-gain stable, dc precision op amp with less than approximately 25 nv/hz of wideband noise, such as the op1177 . not all proper decoupling is shown in figure 71 . take care to follow decoupling guidelines for both amplifiers and the adr435 . ad7685 ref gnd vdd in? in+ vio sdi sck sdo cnv 3- or 4-wire interface 0.1f +12v adr435 3nf +in ?in ad8421 g = 10 +12v ?12v 1.1k ? 250mv +5 v 1f 2.5v 2.5v 10k ? 10k ? 10 ? ref 10f 5k ? 10123-070 100 ? figure 71. ad8421 driving an adc 0 ?20 ?40 ?160 ?140 ?120 ?100 ?80 ?60 0 25 50 75 100 125 amplitude (db of full scale) frequency (khz) 10123-071 snr 81.12db thd ?100.91db sfdr 90.71db figure 72. typical spectrum of the ad8421 (g = 10) driving the ad7685
data sheet ad8421 rev. 0 | page 27 of 28 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 73. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 74. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ad8421arz ?40c to +85c 8-lead soic_n, standard grade r-8 ad8421arz-r7 ?40c to +85c 8-lead soic_n, standard grade, 7 tape and reel, r-8 ad8421arz-rl ?40c to +85c 8-lead soic_n, standard grade, 13 tape and reel r-8 ad8421brz ?40c to +85c 8-lead soic_n, high performance grade r-8 AD8421BRZ-R7 ?40c to +85c 8-lead soic_n, high performance grade, 7 tape and reel r-8 ad8421brz-rl ?40c to +85c 8-lead soic_n, high performance grade, 13 tape and reel r-8 ad8421armz ?40c to +85c 8-lead msop, standard grade rm-8 y49 ad8421armz-r7 ?40c to +85c 8-lead msop, stan dard grade, 7 tape and reel rm-8 y49 ad8421armz-rl ?40c to +85c 8-lead msop, stan dard grade, 13 tape and reel rm-8 y49 ad8421brmz ?40c to +85c 8-lead msop, high performance grade rm-8 y4a ad8421brmz-r7 ?40c to +85c 8-lead msop, high pe rformance grade, 7 tape and reel rm-8 y4a ad8421brmz-rl ?40c to +85c 8-lead msop, high pe rformance grade, 13 tape and reel rm-8 y4a 1 z = rohs compliant part.
ad8421 data sheet rev. 0 | page 28 of 28 notes ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10123-0-5/12(0)

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