 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 78p2341jat e3/ds3/sts-1 liu with jitter attenuator preliminary datasheet - 1 - august 2003 description the 78p2341jat is a low-power, single channel ds3/e3/sts1 transceiver ic with integrated jitter attenuator (jat). it includes clock recovery and transmitter pulse shaping functions for applications using 75-ohm coaxial cable at distances up to 1350 feet. these applications include dslams, t1,3/e1,3 digital multiplexers, sonet add/drop multiplexers, pdh equipment, ds3 to fiber optic and microwave modems, and atm wan access for routers and switches. the receiver recovers clock and data from a b3zs or hdb3 coded ami signal. it can compensate for over 12db of cable and 6db of flat loss. the transmitter generates a signal that meets the standard pulse shape requirements. it has an integrated b3zs/hdb3 ende c with a receive line code violation detector, a loop-back mode, a clock polarity selection mode, and the ability to receive a dsx3 monitor signal. standards ? jitter tolerance: telcordia gr-499-core [ds3] and gr-253-core [sts1], itu-t g.823 [e3] and g.824 [ds3] ? loss of signal: itu-t g.775 ? jitter transfer: etsi tbr-24 1997 [e3]; telcordia gr-499-core [ds3] and gr-253- core [ds3/sts1] features ? transmit and receive interface for e3, ds3 and sts-1 applications ? designed for use with 75 ohm coaxial cable up to 1350 ft long end-to-end or up to 900 ft long from a ds3 cross-connect ? receive ds3-high and dsx3 monitor signals ? local and remote loopback ? selectable b3zs/hdb3 endec with line code violation detector ? standards-based los function ? optional serial-port based mode selection and channel status monitoring ? receiver agc corrects for up to 6db of flat loss ? adaptive digital clock recovery (uses line-rate reference clock input) ? receive output clock maintains nominal line-rate frequency at all times ? fully integrated jitter attenuator (no external vcxo required) confi gurable for transmit or receive path ? transmit line fault monitor ? requires no external current-setting resistor or loop filter components ? single 3.3v supply operation ? available in 28-pin plcc or 48-pin tqfp block diagram loutn loutp tpos tneg tclk rclk rpos rneg ds3 txen llbk rlbk pdtx endec txnw control registers sck sdio e3 lbo master bias generator ckref ckref los attenuator power distribution b3zs / hdb3 encoder data detector b3zs / hdb3 decoder adaptive equalizer signal detector transmit monitor pulse shaper controls jitter attenuator flags tclkp rclkp clock recovery pdrx linn linp mon agc
78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 2 - functional description the 78p2341jat contains all the necessary transmit and receive circuitry for connection between e3, ds3, or sts-1 interfaces and framer/mapper ics. operating rate the master control register (mscr) determines which mode the device operates in according to the table below. the msl0 pin is also provided for mode selection in applications without a serial control interface. upon power-up or reset, the state of the msl0 pin is sensed and mapped into the ds3 and e3 register bits representing the appropriate mode of operation. after pow er-up/reset, the state of the msl0 pin is ignored. standard msl0 pin ds3 bit e3 bit e3 l 0 1 ds3 h 1 0 sts-1 z 0 0 sts-1 z 1 1 receiver operation the receiver inputs li np and linn are either transformer-coupled or capacitor-coupled to the line signal. in applications where the highest performance and isolation are required, a 1:1 transformer is used in the receive path. in applications where isolation is provided elsewhere in the circuit, capacitor coupling can be used. the receiver inputs should be line terminated externally with a termination resistor. the ami signal first enters an agc, which has a selectable gain range setting. in normal operation, the agc can compensate for signals with up to 6db of flat loss. when receiver monitor mode is enabled, the agc can compensate for a dsx3 monitor signal with 16 to 20 db of flat loss. the signal then enters a high performance adaptive equalizer. the equalizer is designed to overcome inter-symbol interference caused by long cable lengths. because the equalizer is adaptive, the circuit will work with all square-shaped signals such as ds3-high or 34.368 mbit/s e3. the variable gain differential amplifier automat ically controls the gain to maintain a constant voltage level output regardless of the input voltage level. the jitter tolerance of 78p2341jat meets the requirements of itu-t g.823 for e3 rates; the requirements of itu-t g.824, gr-499 (cat i and ii) for ds3 rates; and the requirements of gr-253 for sts1 rates. when the jitter attenuator is disabled, the jitter transfer function meets the requirements of gr-499 for category ii ds3 interfaces. when the jitter attenuator is enabled, the 78p2341jat meets the requirements of gr-499 and gr-253 for all categories of ds3/sts1 equipment and the etsi tbr-24 requirements for e3 rates. to check conformance with other standards, please refer to the jitter attenuator transfer function section for more detailed info. reference clock the clock recovery system employs a digital pll, which uses a line-rate reference clock frequency. this reference frequency can be input to the ckref pin or it can utilize the transmitter clock input tclk when ckref is left floating or pulled high. receiver monitor mode when the mon pin is high, 20db of flat gain is applied to the incoming signal before it is fed to the receive equalizer. alternately, the mon bit in the mode control register can be used if the register control bit, regen, is enabled. signal detect when the received signal is below a minimum threshold, the los signal (bit) in the status monitor register is asserted. a ti me delay is provided before this output is active so t hat transient interruptions do not cause false indications. by default, the los signal is also used to trigger an interrupt on the los pin. note that the erro r events that control the assertion of the los pin can be configured in the interrupt control register (intc). note: in ds3 or sts-1 mode, when lbo is not enabled, the transmitters have to be properly terminated to ensure reliable los detection. if a transmitter is not terminated, the resultant 2x signal is large enough to couple to the neighboring receivers through the esd diodes, causing false signal detect indication. 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 3 - loopback modes the lpbk pin is used to activate common loopback modes as shown in the table below. the llbk and rlbk bits in the mode control register can also control these modes when the register control bit, regen, is enabled. lpbk pin loopback mode l local (analog) loopback same as llbk = ?1? z remote (digital) loopback same as rlbk = ?1? h normal operation same as llbk, rlbk = ?0? when in local (analog) loopback, the transmit output signals, loutp,n are internally routed to the receiver inputs. any incoming signals on linp,n will be ignored when in local loopback. for proper operation in this mode, the transmitter needs to be properly terminated with no hanging cables. loutn loutp tpos tneg tclk rclk rpos rneg ds3 txen llbk rlbk pdtx endec txnw control registers sck sdio e3 lbo master bias generator ckref ckref los attenuator power distribution b3zs / hdb3 encoder data detector b3zs / hdb3 decoder adaptive equalizer signal detector transmit monitor pulse shaper controls jitter attenuator flags tclkp rclkp clock recovery pdrx linn linp mon agc local (analog) loopback tx jat off tx jat on rx jat on rx jat off when in remote (digital) loopback, the received signals and clock data, rpos/rneg/rclk, are internally routed to the transmitter input signals. any incoming data on tpos, tneg, or tclk will be ignored when in remote loopback. loutn loutp tpos tneg tclk rclk rpos rneg ds3 txen llbk rlbk pdtx endec txnw control registers sck sdio e3 lbo master bias generator ckref ckref los attenuator power distribution b3zs / hdb3 encoder data detector b3zs / hdb3 decoder adaptive equalizer signal detector transmit monitor pulse shaper controls jitter attenuator flags tclkp rclkp clock recovery pdrx linn linp mon agc remote (digital) loopback a third loopback mode is also available when using the serial control interface. local (digital) loopback mode is controlled by the jitter attenuator control register and only passes through the jitter attenuator, bypassing all analog blocks in the ic. loutn loutp tpos tneg tclk rclk rpos rneg ds3 txen llbk rlbk pdtx endec txnw control registers sck sdio e3 lbo master bias generator ckref ckref los attenuator power distribution b3zs / hdb3 encoder data detector b3zs / hdb3 decoder adaptive equalizer signal detector transmit monitor pulse shaper controls jitter attenuator flags tclkp rclkp clock recovery pdrx linn linp mon agc local (digital) loopback b3zs/hdb3 endec with line code violation detect the 78p2341jat includes a selectable b3zs/hdb3 encoder/decoder (endec). when the endec pin is low, the endec is selected and the decoder generates a composite nrz logic data stream following the b3zs (for ds3/sts-1) or hdb3 (for e3) substitution codes via the rpos pin as shown below. endec rpos rneg 1 positive ami negative ami 0 nrz data receive line code violation indicator the decoder also detects receive line code violations (rlcv) and outputs a pulse via the rneg pin. three different classes of line code violations are detected. ? too many zeros: more than two (three) consecutive zeros in b3zs (hdb3) mode. ? not enough zeros between bipolar pulse (b) and bipolar violation pulse (v): (b,v) for b3zs. (b,v) or (b,0,v) for hdb3. ? code violation: even number of bipolar pulses (b) detected between bipolar violation pulses (v). 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 4 - on the transmit side, when the endec pin is low, nrz input data is encoded to positive and negative logic data following the b3zs (for ds3/sts-1) or hdb3 (for e3) substitution codes. the nrz data is input to the tpos pin as shown below. endec tpos tneg 1 positive ami negative ami 0 nrz data ?don?t care? the endec bit in the mode control register can also control the endec. the register control bit (regen) must be enabled if using the register settings to avoid conflict with external setting pins. transmitter operation the transmitter accepts either nrz coded data or positive and negative ami signals and generates current pulses on the loutp and loutn pins. when properly connected to a 1:2ct center-tapped transformer, an ami pulse is generated which can drive a 75 ? coaxial cable. when the recommended transformer is used and when ds3 mode is selected, the transmitted pulse shape at the end of the 75 ? terminated cable of 0 to 450 feet will fit the ds3 template in ansi t1.102- 1993 and telcordia gr-499-core standard documents. for sts-1 applications, the transmitted pulse for a short cable meets the requirements of telcordia gr-253-core. for e3 applications, the transmitted pulse for a short cable meets the requirements of itu-t g.703. line build-out the line build-out (lbo) function controls the transmit amplitude and pulse shape in ds3 and sts-1 modes. the selection of lbo depends on the amount of cable the transmitter is connected to. when less than 225 ft of cable is used, the lbo pin (or lbo bit) should be high. when 225ft or more cable is used, the lbo pin (or lbo bit) should be low. lbo settings can be controlled either from pins or from register settings, depending on the status of the register control bit, regen. note that lbo settings are ignored when in e3 mode. transmit enable the txen pin controls the transmitter output. when low, the transmitter output is disabled. alternately, the txen bit in the mode control register can control the transmitter if the register control bit is enabled. transmit monitor the transmit monitor function detects activity on the transmitter output at the loutp and loutn pins. when there is a transmitter fault, as in an open or short on the chip, the transformer, or the circuit board, the transmit signal amplitude will be altered. the transmit monitor detects the amplitude of the driven signal. the txok pin goes low when the amplitude of the transmit signal is outside a valid amplitude range for longer than a specified durat ion. alternately, the txnw bit in the status monitor register can be used to monitor the transmit amlitude. note that the txnw signal can also be used to trigger an event on the los pin. this is done by setting the txer bit in the interrupt control register (intc). jitter attenuator jitter attenuation function is provided on-chip. the jitter attenuator can be configured to be in the transmit or the receive path. when configured in the transmit path, the input clo ck at tclk pin is passed through a very low bandwidth digital pll. the corresponding transmit data is buffered into a fifo and clocked out using the de-jittered output clock of the pll. when configured in the receive path, the recovered clock is passed through the low bandwidth digital pll, and the corresponding receive data is buffered into the fifo and clocked out using the de-jittered clock. the jitter attenuator can be configured by writing to the jitter attenuator contro l register (jacr) as follows: jaen bit jasl bit jitter attenuator mode 0 x jitter attenuator disabled 1 0 jitter attenuator configured to be in the receive path 1 1 jitter attenuator configured to be in the transmit path 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 5 - when serial interface contro l is not available, the txen and mon pins are provided for jitter attenuator mode selection. upon power-up or reset, the states of the txen and mon pins are sensed and mapped into the jaen and jasl register bits representing the appropriate mode of operation. after power-up/reset, the states of the txen and mon pins are ignored for jat controls (transmit enable/disable and rx monitor modes can still be controlled). the states of the txen and mon pins, and the corresponding jitter a ttenuator configuration are shown below. txen pin jitter attenuator mode/transmit driver mode l jitter attenuator disabled (upon reset) disable transmit driver z jitter attenuator enabled in transmit path (upon reset) enable transmit driver h jitter attenuator disabled (upon reset) enable transmit driver mon pin jitter attenuator mode/receive monitor mode l jitter attenuator disabled (upon reset) disable monitor mode z jitter attenuator enabled in receive path (upon reset) disable monitor mode h jitter attenuator disabled (upon reset) enable monitor mode pll bandwidth a pll response with effectively one pole below 27 hz is adequate to meet the etsi tbr24 e3 standards. a pll response with one pole below 40 hz is adequate to meet the gr-499 (cat i) ds3 standards. either of the two bandwidths can be selected via register setting. in either high or low bandwidth mode, the pll bandwidth is proportional to the data rate as follows: line rate jabw bit pll bandwidth (hz) 0 13 e3 1 188 0 17 ds3 1 245 0 20 sts1 1 283 the default state of the jabw bit depends on which line-rate is selected through the msl0 pin. if e3 or ds3 mode is selected, the default state is ?0?. if sts1 mode is selected, the default state is ?1?. elastic store depth to optimize the trade-off between data latency and clock wander tolerance, the fifo elastic store depth can be selected through the serial port by writing to the jitter attenuator contro l register (jacr) as follows: esp[1:0] bits elastic store depth 00 pass-through mode 01 16 ui 10 32 ui 11 64 ui (default) the elastic store depth selects the nominal fifo read pointer address. the total or maximum elastic store depth is set to be twice as deep as the nominal pointer address. the circular buffer length is always twice as long as the nominal pointer address. 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 6 - rclk/tclk polarity reversal to simplify the interface with various framer circuitries, clock polarities can be set with the ickp pin as described in the table below. alternately, tclk polarity can be internally inverted by setting the tclkp bit, and rclk polarity can be inverted by setting the rclkp bit. both bits are located in the master control register (mscr) and are only active when the register control enable (regen) bit is enabled. ickp rclk/tclk polarity l update on falling edge of rclk sample on rising edge of tclk z update on rising edge of rclk sample on falling edge of tclk h update on falling edge of rclk sample on falling edge of tclk power-down function power-down controls are provided to allow the transceiver to be shut off. transmit and receive power-down can be set independently via the pdtx and pdrx bits in the mode control register. the serial control interface and configuration registers are not affected by power-down. internal power-on reset the 78p2341jat includes on-chip power-on reset (por) function to ensure the serial-port registers are initialized to known default states upon power-up. this reset signal also sets all state machines within the transceiver to nominal operational states. the internal reset signal is also brought out to the por pin. this pin is a multi-function pin which allows for the following: 1) override the internal po r signal by driving in an external active-low reset signal; 2) monitor the state of t he internal por signal (for test and debug only); 3) add external capacitor to delay the release of the internal power-on reset signal to allow the msl0 pin to stabilize prior to release of reset (approximately 8 s per nf added). the internal resistance of the por pin is approximately 5k ? . this pin is not available in the 28-pin plcc version. serial control interface the serial port controlled register allows a generic controller to interface with the 78p2341jat. it is used for mode settings, diagnostics and test, and the retrieval of status and performance information. the serial interface consists of two pins: serial clock (sck) and serial data in and out (sdio). serial data in (sdi) and serial data out (sdo) are connected together internally to simplify the operation. sck is the clo ck input that times the data on sdio. data on sdi is latched in on the rising- edge of sck, and data on sdo is clocked out using the falling edge of sck. sdi is used to insert mode, address, and register data into the chip. address and data information are input least significant bit (lsb) first. the mode and address bit assignment and register table are shown in the following section. sdo is a tristate capable out put. it is used to output register data during a read operation. sdo output is normally high impedance, and is enabled only during the duration when register data is being clocked out. read data is clocked out significant bit (lsb) first. the maximum clock frequency for register access is 20mhz, while the minimum is 5mhz. there must be at least 10us between clock bursts. 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 7 - register description register addressing address bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port address sub-address read/ write assignment pa[3] pa[2] pa[1] pa[ 0] sa[2] sa[1] sa[0] r/w* register table a) pa[3:0] = 0 : global registers sub addr reg. name description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 mscr (r/w) master control regen <0> ds3 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 8 - register description (continued) legend type description type description r/o read only r/w read or write global registers address 0-0: master control register bit name type dflt value description 7 regen r/w 0 register control enable: 0 : pin selection overrides register settings. 1 : device is controlled via register set. 6 ds3 r/w x 5 e3 r/w x line speed selection: selects the li ne speed as well as the input clock frequency at the ckref pin. [ds3 e3] = 00 : sts-1 (51.840mhz) 01 : e3 (34.368mhz) 10 : ds3 (44.736mhz) 11 : sts-1 (51.840mhz) note: the default values of these register bits depend on the state of the msl0 pin upon power-up or reset. 4 endec r/w 0 encoder/decoder disable: 0 : selects nrz digital data interface 1 : selects ami digital data interface note: relevant only when the regen bit is set. otherwise, endec pin selection prevails. 3 rclkp r/w 0 rclk polarity selection: 0 : receive data clocked out on the falling-edge of rclk 1 : receive data clocked out on the rising-edge of rclk 2 tclkp r/w 0 tclk polarity selection: 0 : transmit data clocked in on the rising-edge of tclk 1 : transmit data clocked in on the falling-edge of tclk 1 rsvd r/o x reserved 0 srst r/w 0 register soft-reset: when this bit is set, all registers are reset to their default values. also resets jitter a ttenuator to ?centered? states. this register bit is self-clearing. 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 9 - register description (continued) address 0-1: interrupt control register this register selects the events that would cause the los pin to be activated. user may set as many bits as required. bit name type dflt value description 7 inpol r/w 0 interrupt pin polarity selection: 0 : interrupt output is active-low 1 : interrupt output is active-high 6:4 rsvd r/o x reserved 3 jaflg r/w 0 reserved for test only. must be set to ?0?. 2 jaer r/w 0 jitter attenuator error event: when set, jat fifo overflow or underfl ow (as indicated by the ferr bit) will cause an interrupt to be flagged. 1 rxer r/w 1 receiver error event: when set, loss of receive signal (as i ndicated by the los bit) will cause an interrupt to be flagged. 0 txer r/w 0 transmitter error event: when set, transmitter fault (as indicated by the txnw bit) will cause an interrupt to be flagged. 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 10 - register description (continued) specific registers for pa[3:0] = 1 only. accessing a register with port address greater than 1 constitutes an invalid command, and the read/write operation will be ignored. address 1-0: mode control register bit name type dflt value description 7 pdtx r/w 0 transmitter power-down: 0 : normal operation 1 : power-down 6 pdrx r/w 0 receiver power-down: 0 : normal operation 1 : power-down 5 lbo r/w 1 transmitter line build-out (ds3 and sts-1 only): 0 : 225ft of cable attached to the cross-connect 1 : < 225ft of cable attached to the cross-connect (note this bit is inactive when regen bit is ?0? ) 4 rsvd r/w 0 reserved 3 llbk r/w 0 local (analog) loopback mode enable: 0 : normal operation 1 : loops loutp and loutn back onto linp and linn (note this bit is inactive when regen bit is ?0? ) 2 rlbk r/w 0 remote (digital) loopback enable: 0 : normal operation 1 : loops rclk, rpos, and rneg back onto tclk, tpos, and tneg (note this bit is inactive when regen bit is ?0? ) 1 mon r/w 0 monitor mode enable: used for recepti on of split-off signals that are flat- attenuated by at least 16db but no more than 20db. 0 : disable 1 : enable (note this bit is inactive when regen bit is ?0? ) 0 txen r/w 1 transmitter output enable: 0 : transmit driver is disabled 1 : normal operation (note this bit is inactive when regen bit is ?0? ) 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 11 - register description (continued) address 1-1: status monitor register bit name type dflt value description 7 ferr r/o x jitter attenuator fifo error flag: this bit is set whenever a fifo overflow or underflow occurred. it is reset after a read operation to this register. 0 : proper operation 1 : fifo overflow/underflow 6:4 jaf[2:0] r/o x jitter attenuat or monitor flags: used for internal test only. ignore during normal operation. 3 los r/o x loss-of-signal indication: 0 : signal detector detecting a valid receive input signal 1 : standards-based loss-of-signal indication note: rposx and rnegx are forced low when los=?1? ; rclk will continue to output a line rate clock 2 txnw r/o x transmitter not-working indication: 0 : transmitter ok 1 : transmitter not working 1 sghi r/o x signal high indication: used for inter nal test only. ignore during normal operation 0 sglo r/o x signal low indication: 0 : receive signal level ok 1 : receive signal level too low / loss of signal 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 12 - register description (continued) address 1-3: jitter attenuator control register bit name type dflt value description 7 jaen r/w x jitter attenuator enable: 0 : disables jitter attenuation function 1 : enables jitter attenuation function note: the default value of this regi ster bit depends on the state of the txen and mon pins upon power up or a reset. 6 jasl r/w x jitter attenuation selection: 0 : jitter attenuator on the receive path 1 : jitter attenuator on the transmit path note: the default value of this regi ster bit depends on the state of the txen and mon pins upon power up or a reset. 5 jlbk r/w 0 jitter attenuator local loopback enable: 0 : normal operation 1 : tclkx, tposx, tnegx connect ed to jat input and rclkx, rposx, rnegx connected to jat output note: if both rlbk and jlbk bits are set, rlbk mode takes priority. 4 rsvd r/w 0 reserved. must be set to zero. 3:2 esp [1:0] r/w 11 fifo elastic store pointer selection: 00 : pass-through 01 : 8 ui 10 : 16 ui 11 : 32 ui 1 rsvd r/w 0 reserved. must be set to zero. 0 jabw r/w x jitter attenuator bandwidth selection: 0 : low bandwidth 1 : high bandwidth (see jat bandwidth selection table on page 5) note that the default value of this register bit depends on the power-up state of the msl0 pin. if the state of the msl0 pin selects e3 or ds3 mode, the default value of jabw is ?0?. if the state of the msl0 pin selects sts1 mode, the default value of jabw is ?1?. 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 13 - pin description legend type description type description a analog pin cis cmos schmitt trigger input ci cmos digital input co cmos digital output ciu cmos digital input w/ pull-up co z cmos tristate digital output cid cmos digital input w/ pull-down s supply transmitter pins name pin tqfp pin plcc type description tpos 16 14 ci transmit positive data/transmit nrz: when endec =?1?, a logic one on this pin generates a positive ami pulse on the coax. this pin should not be high at the same time that corresponding tneg is high. when endec =?0?, data on this pin is encoded and converted into positive and negative ami pulses. tneg 17 15 ci transmit negative data: when endec bit =?1?, a logic one on this pin generates a negative ami pulse on the coax. this pin should not be high at the same time that corresponding tpos is high. when endec bit =?0?, this pin is ignored. tclk 18 16 cis transmitter clock input: this clock signal is used to latch the respective tpos and tneg signals into the 78p2341jat. the frequency should correspond to the line-rate frequency as follows: e3 : 34.368 mhz ds3: 44.736 mhz sts-1: 51.840 mhz if ckref pin pulled high or left floating, tclk is also used as the reference clock for the 78p2341jat. loutp loutn 9 11 9 11 a line out: differential ami outputs. require s a 1:2ct center-tapped transformer and a shunt termination resistor. see application information section for more info. 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 14 - pin description (continued) receiver pins name pin tqfp pin plcc type description ckref 26 19 ciu reference clock input: this clock should be from a clean source ( 20 ppm) and represents the line-rate frequency as follows: e3 : 34.368 mhz ds3: 44.736 mhz sts-1: 51.840 mhz tying this pin high or leaving it floating forces the 78p2341jat to use the clock applied to the transmitter clock input (tclk) as the reference source. rclk 33 23 co receive clock: recovered receive clock. note: when loss of signal (los) occurs, rclk will output the reference clock applied at ckref (or tclk if ckref is pulled high or left floating). rneg 34 24 co receive negative data: when endec =?1?, this pin indicates reception of a negative ami pulse on the coax. when endec =?0?, this pin outputs a one when a receive line code violation is detected. rpos 35 25 co receive positive data/nrz data: when endec =?1?, this pin indicates reception of a positive ami pulse on the coax cable. when endec =?0?, it outputs decoded nrz data. linp linn 42 44 1 3 a line in: differential ami inputs. should be 1:1 transformer-coupled and terminated with a shunt resistor. see application information section for more info. 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 15 - pin description (continued) control and status pins name pin tqfp pin plcc type description msl0 15 13 a data-rate mode selection: low = e3 mode high = ds3 mode float = sts-1 mode note: this pin is only sensed upon power up or a reset. mon 28 21 a receive monitor and jitter attenuator mode selection: low = disable monitor mode and disable rx jitter attenuation high = enable monitor mode and disable rx jitter attenuation float = disable monitor mode and enable rx jitter attenuation (note this pin is inactive w hen regen register bit is ?1? ) por 12 xx a power-on reset: see power-on reset description on use of this pin. lbo 13 12 cid line build-out: logic low used with 225ft or more of cable. logic high used with less than 225ft of cable. (note this pin is inactive w hen regen register bit is ?1? ) lpbk 40 28 a loopback enable: low = local loopback. transmitter looped back to receiver high = normal operation float = remote loopback. receiver looped back to transmitter (note this pin is inactive w hen regen register bit is ?1? ) txen 22 18 a transmit tri-state and jitter attenuator mode selection: low = disable transmit output driver and disable tx jitter attenuation high = enable transmit output driver and disable tx jitter attenuation float = enable transmit output driv er and enable tx jitter attenuation ickp 10 10 a invert clock polarity selection: low=update on falling edge of rclk, sample on rising edge of tclk high=update on falling edge of rclk, sample on falling edge of tclk float=update on rising edge of rclk, sample on falling edge of tclk (note this pin is inactive w hen regen register bit is ?1? ) endec 27 20 a endec enable (active-low): when lo w, activates b3zs/hdb3 endec on receiver and transmitter logic signals. (note this pin is inactive w hen regen register bit is ?1? ) jaerr 36 xx co jitter attenuator error: logic high indicates fifo over/underflow. same as the ferr bit in the status monitor register. los 39 27 a loss of signal (active low): when lo w, indicates the receive signal (linp,n) is below the threshold leve l for 128 periods (default setting). can be configured to represent any combination of los, txnw, and ferr error events through the in terrupt control register txok 30 xx co transmitter ok: logic high when transmitter amplitude within valid ranges. inversed logic of the txnw bit in the status monitor register. 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 16 - pin description (continued) serial-port pins name pin tqfp pin plcc type description sck 47 4 cis serial clock: controls the timing of sdi and sdo. sdio 2 5 ci coz serial data input and output: i nputs mode and address information. also inputs register data during a wri te operation. both address and data are input least significant bit first. outputs register information during a read operation. data is output least significant bit first power and ground pins it is recommended that all supply pins be connected to a single power supply plane and all ground pins be connected to a single ground plane. name pin tqfp pin plcc type description vcc 5, 6, 20, 21 7, 17 s analog power supply gnd 3, 4, 7, 8, 43, 45, 46 2, 6, 8 s analog ground vccd 37, 38 26 s digital power supply gndd 31, 32 22 s digital ground 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 17 - electrical specifications absolute maximum ratings operation beyond these limits ma y permanently damage the device. parameter rating supply voltage (vcc/vccd) -0.5 to 4.0 v storage temperature -65 to 150 c junction temperature -40 to 125 c pin voltage (loutp, loutn) vcc + 1.5 vdc pin voltage (all other pins) -0.3 to (vcc+0.6) vdc pin current 100 ma recommended operating conditions unless otherwise noted all specifications are valid over these temperatur es and supply voltage ranges. parameter rating dc voltage supply (vcc/vccd) 3.0 to 3.6 v ambient operating temperature -40 to 85c dc characteristics: parameter symbol conditions min nom max unit supply current idd vcc = 3.3v ds3 mode max. cable length jat enabled: jat disabled: 99 83 ma ma supply current iddr vcc = 3.3v transmitter disabled ds3 mode max. cable length jat enabled: jat disabled: 46 30 ma ma 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 18 - electrical specifications (continued) analog pins characteristics: the following table is provided for informat ive purpose only. not tested in production. parameter symbol conditions min nom max unit linp and linn common-mode bias voltage vblin ground reference 1.9 2.6 v linp and linn differential input impedance rilin 10 k ? por input impedance ripor 5 k ? digital i/o characteristics: pins of type ci, ciu, cid: parameter symbol conditions min nom max unit input voltage low vil 0.8 v input voltage high vih 2.0 v input current iil, iih -1 1 a pull-up resistance rpu type ciu only 53 70 113 k ? pull-down resistance rpd type cid only 43 58 118 k ? input capacitance cin 10 pf pins of type cis: parameter symbol conditions min nom max unit low-to-high threshold vt+ 1.45 1.55 v high-to-low threshold vt- 0.85 0.95 v input current iil, iih -1 1 a input capacitance cin 10 pf pins of type co and coz: parameter symbol conditions min nom max unit output voltage low vol iol = 8ma 0.4 v output voltage high voh ioh = -8ma 2.4 v output transition time tt c l = 20pf; (20-80%) 3 ns tristate output leakage current iz type coz only -1 1 a 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 19 - electrical specifications (continued) serial-port timing characteristics: parameter symbol condition min typ max unit sdio to sck setup time t su 2 ns sdio to sck hold time t h 2 ns sck to sdio propagation delay t prop 3 ns 1 sa0 sa1 sa2 pa0 pa1 pa2 pa3 sck sdio sdo t su t h d0 d1 d2 d3 d4 d5 d6 d7 z t prop sdi read operation 0 sa0 sa1 sa2 pa0 pa1 pa2 pa3 d0 d1 d2 d3 d4 d5 d6 d7 sck sdio t su t h x x sdi write operation 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 20 - electrical specifications (continued) transmitter timing characteristics: parameter symbol conditions min nom max unit clock duty cycle ttcf/ttc 40 60 % transition time ttct 1 5 ns setup time ttdps 2.5 ns hold time ttdph 2.5 ns timing diagram: transmitter waveforms (e3/ds3/sts-1) tclk tclkp=low tclk tclkp=high tpos tneg ttc ttct ttct ttdps ttdph ttdns ttdnh ttcf 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 21 - electrical specifications (continued) receiver timing characteristics: parameter symbol conditions min nom max unit ckref duty cycle -- 40 60 % ckref frequency stability -- w.r.t. line-rate frequency -20 +20 ppm transition time trct 1 5 ns rclk duty cycle trcf/trc 40 60 % data setup time trdps 7 ns data hold time trdph 7 ns timing diagram: receive waveforms (e3/ds3/sts-1) rclk rclkp=low rclk rclkp=high rpos rneg receive line input (ref) (linp,linn) trc trcf trct trct trdps trdph trdns trdnh 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 22 - electrical specifications (continued) ds3 transmitter parameter condition min typ max unit transmitter amplitude measured at loutp/loutn pins w/ 37.5 ? load and lbo pin held high. 700 800 850 mvpk transmitter amplitude mismatch ratio of amplitudes of positive and negative pulses measured at pulse peaks. 0.9 1.1 transmitter power at 22.368 mhz all ones pattern, 3khz bandwidth -1.8 +5.7 dbm harmonic power at 44.736 mhz all ones pattern power below fundamental at 22.368mhz -20 dbm sts-1 transmitter parameter condition min typ max unit transmitter amplitude measured at loutp/loutn pins w/ 37.5 ? effective load and lbo pin held high. 700 825 950 mvpk transmitter amplitude mismatch rati o of amplitudes of positive and negative pulses measured at pulse peaks. 0.9 1.1 transmitter power prbs15 pattern band-limited to 207.36mhz. -2.7 +4.7 dbm e3 ? transmitter parameter condition (see timing diagram) min typ max unit transmitter amplitude measured at loutp/loutn pins w/ 37.5 ? load. 900 1000 1100 mvpk transmitter amplitude mismatch ratio of amplitudes of positive and negative pulses measured at pulse centers 0.95 1.05 transmitter pulsewidth mismatch ratio of widths of positive and negative pulses measured at pulse half amplitude 0.95 1.05 transmitter pulsewidth measured at loutp/loutn pins 14.8 ns 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 23 - electrical specifications (continued) e3 transmit pulse template 17 ns 8.65 ns 14.55 ns 12.1 ns 24.5 ns 29.1 ns 0.1 0.1 0.1 0.1 0.1 0.1 0.2 0.2 0 0.5 1.0 0.2 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 24 - electrical specifications (continued) ds3 transmit pulse template time axis range (ui) normalized amplitude equation upper curve -0.85 < t < -0.68 0.03 -0.68 < t < 0.36 0.03 + 0.5{1+sin[(pi/2)(1+t/0.34)]} 0.36 < t < 1.4 0.08+0.407 e -1.84(t-0.36) lower curve -0.85 < t < -0.36 -0.03 -0.36 < t < 0.36 -0.03 + 0.5{1+sin[(pi/2)(1 + t/0.18)]} 0.36 < t < 1.4 -0.03 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.5 0 0.5 1 1.5 time, unit intervals normalized amplitude 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 25 - electrical specifications (continued) sts-1 transmit pulse template sts-1 (transmit template specs) time axis range (t) normalized amplitude equation (a) upper curve -0.85 < t < -0.68 0.03 -0.68 < t < 0.26 0.03 + 0.5{1+sin[(pi/2)(1+t/0.34)]} 0.26 < t < 1.4 0.1+0.61 e -2.4(t-0.26) lower curve -0.85 < t < -0.38 -0.03 -0.38 < t < 0.36 -0.03 + 0.5{1+sin[(pi/2)(1 + t/0.18)]} 0.36 < t < 1.4 -0.03 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.5 0 0.5 1 1.5 time, unit intervals normalized amplitude 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 26 - electrical specifications (continued) transmitter output jitter the transmit jitter specification ens ures compliance with itu-t g.823 and g.824, telcordia gr-499 core(i) and gr-253-core, and ansi t1.102-1993 for all supported ra tes. transmit output jitter is guaranteed only if a clean sonet quality transmit clock source is used. transmitter output jitter detector measured jitter a mplitude f1 f2 20db/decade parameter condition min nom max unit 10 hz to 800 khz 0.15 uipp transmitter output jitter 10 khz to 800 khz 0.08 uipp note: filters defined by standards are used for all testing 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 27 - electrical specifications (continued) transmit monitor the transmit monitor function looks at the signals on the loutp and loutn pins and checks for the existence of a valid signal. the monitor detects the peak of the transmitted signal at the loutp and loutn pins and checks that it is between v under and v over at all times. if the peak level is within the voltage threshold window, the txok signal is high (txnw bit is low). if the peak level falls outside of the threshold limits for more than approximately 32 bit times, the txok signal goes low (txnw bit goes high). v tpos - v tneg v peak v over v under time parameter condition min typ max unit v under ds3 mode with lbo=1 sts-1 mode 320 mvpk v under e3 mode ds3 mode with lbo=0 400 mvpk v over ds3 mode with lbo=1 sts-1 mode 1280 mvpk v over e3 mode ds3 mode with lbo=0 1600 mvpk 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 28 - electrical specifications (continued) ds3/sts-1 receiver (transformer-coupled) parameter condition min typ max unit mon=0. signal at dsx is 360-850 mvpk. see notes 2, 3 90 850 mvpk mon=1 25 80 mvpk peak differential input amplitude, linpx and linnx mon=0. ds3-high 90 1200 mvpk flat-loss tolerance mon=0. all valid cable lengths. 0 6 db receive clock jitter ds3 mode with 10 hz ? 400 khz a) normal receive mode b) remote loopback mode 0.1 0.06 uipp uipp interfering tone tolerance (see note 5) maximum ratio of interference power to signal power for ber < 10 -8 a) with 0ft cable from dsx b) with 450ft cable from dsx -9 -10 db db note 1: signal source should meet ds3 template of ansi-t102.1993 figure 4 and sts-1 template of ansi- t102.1993 figure 5. loss characteristics of the we728a or rg59b cable should be better than figure c2 of ansi-t102.1993. note 2: min spec corresponds to minimum dsx amp litude, 5.5db of cable loss (450ft) and 6db of flat attenuation. error-free receiver performance is guaranteed for up to 600ft of cable from dsx cross- connect. typical part can handle up to 900ft. note 3: min spec corresponds to amplitude of 425mvpk at dsx, 5.5db of cable lo ss (450ft) and 20db of flat attenuation. in monitor mode, interfer ing tone performance is not guaranteed. note 4: in this mode, no noise, jitter, or interfering tone im pairments should be added for guaranteed receiver performance. note 5: interfering signal is a non-synchronous sinusoi dal tone of 22.368mhz for ds 3 or 25.92mhz for sts-1. data is a prbs15 (2 15 -1) pattern. 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 29 - electrical specifications (continued) e3 ? receiver (transformer-coupled) parameter condition min typ max unit mon=0 (see note 1) 120 1200 mvpk peak differential input amplitude, linpx and linnx mon=1 (see note 2) 25 100 mvpk flat-loss tolerance mon=0. all valid cable lengths. 0 6 db receive clock jitter with 100hz-800khz filter: a) normal receive mode b) remote loopback mode 0.1 0.06 uipp uipp interfering tone tolerance (see note 3) maximum ratio of interference power to signal power for ber < 10 -8 a) with 0ft cable b) with 900ft cable -9 -10 db db note 1: min spec corresponds to signal amplitude of 950mvpk at source, 12db of cable loss (1100ft) and 6db of flat attenuation. error-free receiver performance is guaranteed for all cable less than 1100ft. typical part can handle up to 1350ft. note 2: min spec corresponds to signal amplitude of 1000mvpk at source, 12db of cable loss (1100ft) and 20db of flat attenuation. in monitor mode, interfering tone performance is not guaranteed. note 3: interfering signal is a non-synchronous e3 si gnal of the specified power level below the desired e3 signal. both data and interfering signals are prbs23 (2 23 -1) pattern. 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 30 - electrical specifications (continued) receiver jitter tolerance the 78p2341jat receive jitter tolerance exceeds all specifications as show n on the graph below. parameter condition min nom max unit receiver high frequency jitter tolerance > 60 khz 0.75 uipp 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 10 1 10 2 10 3 10 4 10 5 10 6 10 7 jitter tolerance: 78p234x vs. standards 78p234x core(i) [ds3] core(ii) [ds3] core(ii) [sts1] jitter frequency (hz) jat enabled gr-253- itu - t g.823 [e3] itu - t g.824 [ds3] gr-499- gr-499- jitter tolerance (uip-p) 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 31 - electrical specifications (continued) receiver jitter transfer function the receiver clock recovery loop charac teristics are such that the receiver has the following transfer function. when the jitter attenuator (jat) is enabled in the receiv e or transmit path, the receiver or transmitter will exhibit a jitter transfer as shown in the graph and tabl e below. jitter attenuator operation is guaranteed through digital scan testing. the actual jitter transfer is guaranteed by logic design and is not tested during production testing. parameter condition min nom max unit receiver jitter transfer function below fc 0.1 db receiver jitter bandwidth, fc at ?3db point jabw= 0, e3 mode (default) jabw= 1, e3 mode jabw= 0, ds3 mode (default) jabw= 1, ds3 mode jabw= 0, sts1 mode jabw= 1, sts1 mode (default) jaen= 0, jat disabled 13 188 17 245 20 283 55 hz jitter transfer function roll-off after fc 20 db per decade -50 -40 -30 -20 -10 0 10 jitter frequency jitter transfer (db) 10 100 1k 10k 100k 1m etsi tbr 24 (e3) g r - 2 5 3 c a t i ( d s 3 ) e3 jat ds3 jat sts1 jat jat disabled g r - 4 9 9 c a t i ( d s 3 ) g r - 2 5 3 c a t i i ( s t s 1 ) g r - 4 9 9 c a t i i ( d s 3 ) 40hz 1khz 27hz 40khz 59.6khz 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 32 - application information external components: component pin(s) value units tolerance receiver termination resistor linp linn 75 ? 1% transmitter termination resistor loutp loutn 402 ? 1% transformer specifications: component value units tolerance turns ratio for the receiver 1:1 turns ratio for the transmitter (center-tapped) 1:2ct suggested manufacturer: pulse, tdk, halo schematics for the latest typical application sc hematics, please check tdk semiconducto r's website or contact your local sales representative for the latest app lication note(s) and/or demo board manuals. 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 33 - package information mechanical specifications 28-pin plcc mechanical specification 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 34 - package information mechanical specifications 48-pin tqfp (jedec lqfp) mechanical specification 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 35 - package information pin-out (top view) 5 6 7 8 9 10 11 4 3 2 1 28 27 26 12 13 14 15 16 17 18 25 24 23 22 21 20 19 sck linn gnd linp lpbk los vccd lbo msl0 tpos tneg tclk vcc txen sdio gnd vcc gnd loutp ickp loutn rpos rneg rclk gndd mon endec ckref 78p2341 28-pin plcc 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 36 - package information pin-out (top view) rneg 1 n/c 3 rclk 2 sdio 4 gnd 5 gnd 6 vcc 7 gnd 8 m s l 0 1 7 t p o s 1 8 t n e g 1 9 t c l k 2 0 n / c 2 1 v c c 2 2 v c c 2 3 t x e n 2 4 4 7 s c k 4 8 n / c 4 6 g n d 4 5 g n d 4 4 l i n n 4 3 g n d 4 2 l i n p 4 1 n / c 4 0 l p b k 3 8 v c c d 3 7 v c c d 36 jaerr ckref 34 35 rpos 33 gndd 32 gndd 31 txok 30 n/c 29 mon 78p2341 loutn 1 3 por 1 4 l b o 1 5 n / c 1 6 gnd 9 10 loutp 11 ickp 12 n / c 28 27 n/c 26 n / c 25 endec 3 9 l o s vcc ordering information part description o rder number package mark 48-pin jedec lqfp 78p2341jat-igt 78p2341j-igt 28-pin plcc 78p2341jat-ih 78p2341j-ih tape & reel option append ?r? n/a lead-free option append ?/f? append ?/f 78p2341jat e3/ds3/sts-1 liu with jitter attenuator - 37 - revision history revision date: revision description: june 24, 2002 changes to 48-tqfp pinout (pins 14, 19, 23) additions to ckref pin description corrected lpbk pin description and intrinsic transmit jitter spec. marketing number change august 06, 2003 changed to preliminary status updated receive jitter tolerance and jitter transfer graphs removed sghi bit definition updated internal power on reset description updated timing diagrams & e-spec table values changed recommended rx / tx termination resist or values to 75 / 402 ohm respectively preliminary data sheet: this preliminary data sheet describes a product not co mpletely released to production. the specifications are based on preliminary evaluations and may not be accurate. samp les of the described product are available and limited quantities can be purchased. tdk semiconductor corporation s hould be consulted contacted fo r contacted to obtain the most current up-to-date inf ormation about the product. if and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of ord er acknowledgment, including those per taining to warranty, patent infringement and lim itation of liability. tdk semiconductor co rporation (tsc) reserves the right to make changes in specifications at any time without notic e. accordingly, the reader is cautioned to verify that a data sheet is current before plac ing orders. tsc assumes no liab ility for applications assistance. tdk semiconductor corp., 6440 oak canyon rd., irvine, ca 92618 tel (714) 508-8800, fax (714) 508-8877, http:// www.tdksemiconductor.com ? 2003 ? tdk semiconductor corporation 08/06/03 ? rev 1.3 |
Price & Availability of 78P2341JAT-IGTR
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |