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rev 1.2 11/28/00 characteristics subject to change without notice. 1 of 15 www.xicor.com preliminary information recommended system management alternative: x4643 for a more integrated solution use xicor system management products 64k x24645 8192 x 8 bit advanced 2-wire serial eeprom with block lock protection features 2.7v to 5.5v power supply low power cmos active read current less than 1ma active write current less than 3ma standby current less than 1? internally organized 8192 x 8 new programmable block lock protection software write protection programmable hardware write protect block lock (0, 1/4, 1/2, or all of the eeprom array) 2-wire serial interface bidirectional data transfer protocol 32-byte page write mode minimizes total write time per byte self timed write cycle typical write cycle time of 5ms high reliability endurance: 1,000,000 cycles data retention: 100 years available packages 8-lead soic (jedec) description the x24645 is a cmos 65,536-bit serial eeprom, internally organized 8192 x 8. the x24645 features a serial interface and software protocol allowing opera- tion on a simple two wire bus. two device select inputs (s 1 , s 2 ) allow up to four devices to share a common two wire bus. a write protect register at the highest address loca- tion, 1fffh, provides three new write protection fea- tures: software write protect, block write protect, and hardware write protect. the software write protect feature prevents any nonvolatile writes to the x24645 until the wel bit in the write protect register is set. the block write protect feature allows the user to individu- ally write protect four blocks of the array by program- ming two bits in the write protect register. the programmable hardware write protect feature allows the user to install the x24645 with wp tied to v cc , pro- gram the entire memory array in place, and then enable the hardware write protection by programming a wpen bit in the write protect register. after this, selected blocks of the array, including the write protect register itself, are permanently write protected, as long as wp remains high. xicor eeproms are designed and tested for applica- tions requiring extended endurance. inherent data retention is greater than 100 years.
x24645 ?preliminary information characteristics subject to change without notice. 2 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products block diagram start stop logic control logic slave address register +comparator h.v. generation timing & control word address counter xdec ydec d out ack eeprom 256 x 256 data register start cycle v cc r/w pin v ss sda scl s 2 s 1 d out load inc ck wp 8 write protect register & logic pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open col- lector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the pull-up resistor selection graph at the end of this data sheet. device select (s 1 , s 2 ) the device select inputs (s 1 , s 2 ) are used to set the ?st and second bits of the 8-bit slave address. this allows up to four x24645 devices to share a common bus. these inputs can be static or actively driven. if used statically, they must be tied to v ss or v cc as appropriate. if actively driven, they must be driven with cmos levels (driven to v cc or v ss ). write protect (wp) the write protect input controls the hardware write pro- tect feature. when held low, hardware write protec- tion is disabled, and the x24645 can be written normally. when this input is held high, and the wpen bit in the write protect register is set high, write pro- tection is enabled, and nonvolatile writes are disabled to the selected blocks, as well as the write protect reg- ister itself.
x24645 ?preliminary information characteristics subject to change without notice. 3 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products pin names pin configurations device operation the x24645 supports a bidirectional bus oriented pro- tocol. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers, and pro- vide the clock for both transmit and receive operations. therefore, the x24645 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the x24645 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. symbol description s 1 , s 2 device select inputs sda serial data scl serial clock wp write protect v ss ground v cc supply voltage nc no connect 8-lead soic nc s 1 s 2 v ss 1 2 3 4 v cc wp scl sda 8 7 6 5 x24645 figure 1. data validity figure 2. definition of start and stop scl sda data stable data change scl sda start bit stop bit
x24645 ?preliminary information characteristics subject to change without notice. 4 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 3. the x24645 will respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the x24645 will respond with an acknowl- edge after the receipt of each subsequent 8-bit word. in the read mode the x24645 will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the x24645 will continue to transmit data. if an acknowledge is not detected, the x24645 will terminate further data trans- missions. the master must then issue a stop condition to return the x24645 to the standby power mode and place the device into a known state. figure 3. acknowledge response from receiver scl from master data output from transmitter 1 89 from receiver start acknowledge data output device addressing following a start condition, the master must output the address of the slave it is accessing (see figure 4). the next two bits are the device select bits. a system could have up to four x24645s on the bus. the four addresses are de?ed by the state of the s 1 and s 2 inputs. s 2 of the slave address must be the inverse of the s 2 input pin. figure 4. slave addressing the next ?e bits of the slave address are an extension of the arrays address, and are concatenated with the eight bits of address in the byte address ?ld, providing direct access to the whole 8192 x 8 array. the last bit of the slave address de?es the operation to be performed. when set high a read operation is selected, when set low, a write operation is selected. following the start condition, the x24645 monitors the sda bus, comparing the slave address being transmit- ted with its slave address device type identi?r. upon a correct compare, the x24645 outputs an acknowledge on the sda line. depending on the state of the r/w bit, the x24645 will execute a read or write operation. write operations byte write for a write operation, the x24645 requires a second address ?ld. this address ?ld is the byte address, comprised of eight bits, providing access to any one of 8192 words in the array. upon receipt of the byte address, the x24645 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time s 2 r/w address bits s 1 a12 a11 a10 device select high order a9 a8
x24645 ?preliminary information characteristics subject to change without notice. 5 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products the x24645 begins the internal write cycle to the non- volatile memory. while the internal write cycle is in progress the x24645 inputs are disabled, and the device will not respond to any requests from the master. refer to figure 5 for the address, acknowledge and data transfer sequence. figure 5. byte write bus activity: master sda bus bus activity: x24645 s t a r t slave address s t o p a c k a c k a c k word address data p s page write the x24645 is capable of a 32-byte page write operation. it is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the ?st data word is transferred, the master can transmit up to thirty-one more bytes. after the receipt of each byte, the x24645 will respond with an acknowledge. after the receipt of each byte, the ?e low order address bits are internally incremented by one. the high order eight bits of the address remain constant. if the master should transmit more than 32 bytes prior to generating the stop condition, the address counter will ?oll over and the previously written data will be over- written. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 6 for the address, acknowledge, and data transfer sequence. figure 6. page write s t a r t slave address s t o p a c k a c k a c k a c k a c k data n + 1 byte address (n) data n s p data n + 31 bus activity: master sda line bus activity: x24645 acknowledge polling the max write cycle time can be signi?antly reduced using acknowledge polling. to initiate acknowledge polling, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the high voltage cycle, then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. refer to flow 1.
x24645 ?preliminary information characteristics subject to change without notice. 6 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products flow 1. ack polling sequence read operations read operations are initiated in the same manner as write operations with the exception that the r/ w bit of the slave address is set high. there are three basic read operations: current address read, random read and sequential read. it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. current address read internally the x24645 contains an address counter that maintains the address of the last byte read, incre- mented by one or the exact address of the last byte written. therefore, if the last access read was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with the r/w set high, the x24645 issues an acknowledge and transmits the byte. the read opera- tion is terminated by the master by not responding with an acknowledge and then issuing a stop condition. refer to figure 7 for the sequence of address, acknowledge and data transfer. figure 7. current address read random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set high, the master must ?st perform a ?ummy write opera- tion. the master issues the start condition, and the slave address with the r/w bit set low, followed by the byte address it is to read. after the word address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set high. this will be followed by an acknowledge from the x24645 and then by the data byte. the read operation is terminated by the master by not respond- ing with an acknowledge and then issuing a stop condi- tion. refer to figure 8 for the address, acknowledge and data transfer sequence. write operation completed enter ack polling issue start issue slave address and r/w = 0 ack returned? next operation a write? issue byte address proceed issue stop no yes yes proceed issue stop no s t a r t slave address a c k s bus activity: master sda line bus activity: x24645 data s t o p p
x24645 ?preliminary information characteristics subject to change without notice. 7 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products figure 8. random read s t a r t slave address a c k a c k s s t a r t slave address word address n s a c k data n s t o p p bus activity: master sda line bus activity: x24c16 sequential read sequential reads can be initiated as either a current address read or random access read. the ?st byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. the x24645 continues to output data for each acknowledge received. the read operation is terminated by the master by not responding with an acknowledge, and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address space (address 8191), the counter ?olls over to 0 and the x24645 continues to output data for each acknowledge received. refer to figure 9 for the address, acknowl- edge and data transfer sequence. figure 9. sequenctial read figure 10. typical system configuration slave address s t o p a c k a c k a c k a c k data n data n+1 data n+2 data n+x p bus activity: master sda line bus activity: x24645 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver pull-up resistors sda scl v cc
x24645 ?preliminary information characteristics subject to change without notice. 8 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products write protect register the write protect register (wpr) is located at the high- est address, 1fffh. write protect register wpr (addr = fffh) wpr.1 = wel ?rite enable latch (volatile) 0 = write enable latch reset, writes disabled 1 = write enable latch set, writes enabled if wel = ? then ?o ack after ?st byte of input data. wpr.2 = rwel ?egister write enable latch (volatile) 0 = register write enable latch reset, writes disabled 1 = register write enable latch set, writes enabled wpr.3, wpr.4 = bp0, bp1 block protect bits (nonvolatile) (see block protect section for de?ition) wpr.7 = wpen write protect enable bit (nonvolatile) (see hardware write protect section for de?ition) writing to the write protect register the write protect register is written by performing a random write of one byte directly to address, 1fffh. if a page write is performed starting with any address other than 1fff, the byte in the array at address 1fffh will be written instead of the write protect regis- ter (assuming writes are not disabled by the block pro- tect register). the state of the write protect register can be read by performing a random read at address 1fffh at any time. if a sequential read starting at any other address than 1fffh is performed, the contents of the byte in the array at 1fffh is read out instead of the write pro- tect register. wel and rwel are volatile latches that power-up in the low (disabled) state. a write to any address other than 1fffh, where the write protect register is located, will be ignored (no ack) until the wel bit is set high. the wel bit is set by writing 0000001x to address 1fffh. once set, wel remains high until either reset (by writing 00000000 to 1fffh) or until the part powers-up again. the rwel bit controls writes to the block protect bits. rwel is set by ?st setting wel to ? and then writing 0000011x to address 1fffh. rwel must be set in order to change the block protect bits, bp0 and bp1, or the wpen bit. rwel is reset when the block protect or wpen bits are changed, or when the part powers-up again. programming the bp or wpen bits a three step sequence is required to change the non- volatile block protect or write protect enable: 1) set wel = 1 (write 00000010 to address 1fffh, volatile write cycle) (start) 2) set rwel = 1 (write 00000110 to address 1fffh, volatile write cycle) (start) 3) set bp1, bp0, and/or wpen bits (write w00yz010 to address 1fffh) w = wpen, y = bp1, z = bp0, (stop) step 3 is a nonvolatile write cycle, requiring 10ms to complete. rwel is reset to ? by this write cycle, requiring another write cycle to set rwel again before the block protect bits can be changed. rwel must be ? in step 3; if w00yz110 is written to address 1fffh, rwel is set but wpen, bp1 and bp0 are not changed (the device remains at step 2). block protect bits the block protect bits bp0 and bp1 determine which blocks of the memory are write-protected: programmable hardware write protect the write protect (wp) pin and the write protect enable (wpen) bit in the write protect register con- trol the programmable hardware write protect feature. hardware write protection is enabled when the wp pin and the wpen bit are both high, and disabled when either the wp pin is low or the wpen bit is low. when the chip is hardware write-protected, nonvolatile writes are disabled to the write protect register, including the bp bits and the wpen bit itself, as well as to block protected sections in the memory array. only the sec- tions of the memory array that are not block-protected can be written. note that since the wpen bit is write- protected, it cannot be changed back to a low state, 7 6543 2 10 wpen 0 0 bp1 bp0 rwel wel 0
x24645 ?preliminary information characteristics subject to change without notice. 9 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products and write protection is disabled as long as the the wp pin is held high. table 2 de?es the write protection status for each state of wpen and wp. block protect bits the block protect bits bp0 and bp1 determine which blocks of the memory are write-protected: table 1. block protect bits programmable hardware write protect the write protect (wp) pin and the write protect enable (wpen) bit in the write protect register control the programmable hardware write protect feature. hardware write protection is enabled when the wp pin is high and the wpen bit is ?? and disabled when either the wp pin is low or the wpen bit is ?? when the chip is hardware write-protected, nonvolatile writes are disabled to the write protect register, including the bp bits and the wpen bit itself, as well as to block-pro- tected sections in the memory array. only the sections of the memory array that are not block-protected can be written. note that since the wpen bit is write-pro- tected, it cannot be changed back to a low state, and write protection is disabled as long as the the wp pin is held high. table 2 de?es the write protection status for each state of wpen and wp. bp1 bp0 protected addresses 0 0 none 0 1 1800h?fffh upper 1/4 1 0 1000h?fffh upper 1/2 1 1 0000h?fffh full array (wpr not included) table 2. write protect status table wp wpen memory array (not block protected) memory array (block protected) bp bits wpen bit l x writable protected writable writable x 0 writable protected writable writable h 1 writable protected protected protected
x24645 ?preliminary information characteristics subject to change without notice. 10 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products absolute maximum ratings temperature under bias x24645 ...........?5 to +135? storage temperature .............................?5 to +150? voltage on any pin with respect to v ss ....... ?v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds).........300? comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0 c +70 c industrial ?0 c +85 c supply voltage limits x24645-2.7 2.7v to 5.5v d.c. operating characteristics capacitance t a = +25?, f = 1mhz, v cc = 5v notes: (1) must perform a stop command prior to measurement. (2) v il min. and v ih max. are for reference only and are not 100% tested. (3) this parameter is periodically sampled and not 100% tested. symbol parameter limits unit test conditions min. max. i cc1 v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 100khz, sda = open, all other inputs = v ss or v cc ?0.3v i cc2 v cc supply current (write) 3 ma i sb1 (1) v cc standby current 50 ? scl = sda = v cc , all other inputs = v ss or v cc ?0.3v, v cc = 5v 10% i sb2 (1) v cc standby current 1 a scl = sda = v cc , all other inputs = v ss or v cc ?0.3v, v cc = 2.7v i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc v ll (2) input low voltage ? v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma, v cc = 4.5v symbol parameter max. unit test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (s 1 , s 2 , scl) 6 pf v in = 0v
x24645 ?preliminary information characteristics subject to change without notice. 11 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products a.c. conditions of test equivalent a.c. load circuit input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 5v 1.53 ? 100pf output a.c. operating characteristics (over the recommended operating conditions, unless otherwise speci?d.) read & write cycle limits power-up timing (4) note: (4) t pur and t puw are the delays required from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. symbol parameter min. max. unit f scl scl clock frequency 0 400 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 ? t buf time the bus must be free before a new transmission can start 4.7 ? t hd:sta start condition hold time 4 s t low clock low period 4.7 ? t high clock high period 4 s t su:sta start condition setup time (for a repeated start condition) 4.7 ? t hd:dat data in hold time 0 s t su:dat data in setup time 250 ns t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 ? t dh data out hold time 300 ns symbol parameter max. unit t pur power-up to read operation 1 ms t puw power-up to write operation 5 ms
x24645 ?preliminary information characteristics subject to change without notice. 12 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products bus timing write cycle limits notes: (5) typical values are for t a = 25? and nominal supply voltage (5v). (6) t wr is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal write operation. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. during the write cycle, the x24645 bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. bus timing symbol parameter min. typ. (5) max. unit t wc (6) write cycle time 5 10 ms t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high scl sda 8 th bit word n ack t wc stop condition start condition
x24645 ?preliminary information characteristics subject to change without notice. 13 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products guidelines for calculating typical values of bus pull-up resistors symbol table 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k ? ) bus capacitance (pf) min. resistance max. resistance r max. = c bus t r r min. = i ol min. v cc max. =1.8k ? waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
x24645 ?preliminary information characteristics subject to change without notice. 14 of 15 rev 1.2 11/28/00 www.xicor.com for a more integrated solution use xicor system management products packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0?- 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint
for a more integrated solution use xicor system management products x24645 ?preliminary information characteristics subject to change without notice. 15 of 15 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2000 patents pending rev 1.2 11/28/00 www.xicor.com ordering information part mark convention device x24645 x x -x v cc range 2.7 = 2.7v to 5.5v temperature range blank = 0 c to +70 c i = ?0 c to +85 c package s8 = 8-lead soic (jedec) f = 2.7v to 5.5v, 0 c to +70 c g = 2.7v to 5.5v, ?0 c to +85 c x24645 x x blank = 8-lead soic (jedec)
xicor product change notice 02/04/00 page 1 of 9 file://f:\export\projects\bitting2\imaging\bitting\mail_pdf\recode\pcn_000204.html 1/15/01 product change notice : pcn february 4, 2000 february 4, 2000 ref: pcn-00-01 dear xicor customer, at xicor, we continuously strive to improve the performance and efficiency of our operations, and the quality of our products. consistent with this effort, we are currently adding additional wafer fabrication capacity for various iic and spi serial products. this added wafer fabrication capacity will complement current operations and will expand xicor ? s capabilities to accommodate future growth. in addition, several of the iic and spi serial products are undergoing a die revision change. the new die revision is functionally and pin to pin compatable with the existing die revision. see the detailed product number list below for the implementation date and description of the change. samples for qualification will be available approximately 4 weeks before the implementation date. qualification data is available upon request. if you have any further questions, please contact your regional xicor sales office. sincerely, xicor marketing department xicor part number implement date description of change iic serial products x24164p 2/28/00 foundry change x24164p-3 2/28/00 foundry change x24164pi 2/28/00 foundry change x24164pi-3 2/28/00 foundry change x24164s 2/28/00 foundry change x24164s-2.7 2/28/00 foundry change x24164s-3 2/28/00 foundry change x24164si 2/28/00 foundry change x24164si-2.7 2/28/00 foundry change x24c04p 5/31/00 die rev / foundry change x24c04p-2.7 5/31/00 die rev / foundry change x24c04p-3 5/31/00 die rev / foundry change x24c04p-3.5 5/31/00 die rev / foundry change x24c04pi 5/31/00 die rev / foundry change x24c04pi-2.7 5/31/00 die rev / foundry change
xicor product change notice 02/04/00 page 2 of 9 file://f:\export\projects\bitting2\imaging\bitting\mail_pdf\recode\pcn_000204.html 1/15/01 x24c04pi-2.7 5/31/00 die rev / foundry change x24c04pi-3 5/31/00 die rev / foundry change x24c04pi-3.5 5/31/00 die rev / foundry change x24c04pm 5/31/00 die rev / foundry change x24c04pm-3 5/31/00 die rev / foundry change x24c04pm-3.5 5/31/00 die rev / foundry change x24c04s14 5/31/00 die rev / foundry change x24c04s14-3 5/31/00 die rev / foundry change x24c04s14-3.5 5/31/00 die rev / foundry change x24c04s14i 5/31/00 die rev / foundry change x24c04s14i-3 5/31/00 die rev / foundry change x24c04s14i-3.5 5/31/00 die rev / foundry change x24c04s14m 5/31/00 die rev / foundry change x24c04s14m-3 5/31/00 die rev / foundry change x24c04s14m-3.5 5/31/00 die rev / foundry change x24c04s8 5/31/00 die rev / foundry change x24c04s8-2.7 5/31/00 die rev / foundry change x24c04s8-3 5/31/00 die rev / foundry change x24c04s8-3.5 5/31/00 die rev / foundry change x24c04s8i 5/31/00 die rev / foundry change x24c04s8i-2.7 5/31/00 die rev / foundry change x24c04s8i-3 5/31/00 die rev / foundry change x24c04s8i-3.5 5/31/00 die rev / foundry change x24c04s8m 5/31/00 die rev / foundry change x24c04s8m-3 5/31/00 die rev / foundry change x24c04s8m-3.5 5/31/00 die rev / foundry change x24c08p 8/31/00 die rev / foundry change x24c08p-2.7 8/31/00 die rev / foundry change x24c08p-3 8/31/00 die rev / foundry change x24c08p-3.5 8/31/00 die rev / foundry change x24c08pi 8/31/00 die rev / foundry change x24c08pi-2.7 8/31/00 die rev / foundry change x24c08pi-3 8/31/00 die rev / foundry change x24c08pi-3.5 8/31/00 die rev / foundry change x24c08pm 8/31/00 die rev / foundry change x24c08pm-3 8/31/00 die rev / foundry change x24c08pm-3.5 8/31/00 die rev / foundry change x24c08s 8/31/00 die rev / foundry change x24c08s-3 8/31/00 die rev / foundry change x24c08s-3.5 8/31/00 die rev / foundry change x24c08s8 8/31/00 die rev / foundry change x24c08s8-2.7 8/31/00 die rev / foundry change x24c08s8-3 8/31/00 die rev / foundry change x24c08s8i 8/31/00 die rev / foundry change x24c08s8i-2.7 8/31/00 die rev / foundry change
xicor product change notice 02/04/00 page 3 of 9 file://f:\export\projects\bitting2\imaging\bitting\mail_pdf\recode\pcn_000204.html 1/15/01 x24c08s8i-3 8/31/00 die rev / foundry change x24c08s8m 8/31/00 die rev / foundry change x24c08si 8/31/00 die rev / foundry change x24c08si-3 8/31/00 die rev / foundry change x24c08si-3.5 8/31/00 die rev / foundry change x24c08sm 8/31/00 die rev / foundry change x24c08sm-3 8/31/00 die rev / foundry change x24c08sm-3.5 8/31/00 die rev / foundry change spi serial products x25020p 7/31/00 die rev / foundry change x25020p-2.7 7/31/00 die rev / foundry change x25020pi 7/31/00 die rev / foundry change x25020pi-2.7 7/31/00 die rev / foundry change x25020s 7/31/00 die rev / foundry change x25020s-2.7 7/31/00 die rev / foundry change x25020s-3 7/31/00 die rev / foundry change x25020si 7/31/00 die rev / foundry change x25020si-2.7 7/31/00 die rev / foundry change x25020si-3 7/31/00 die rev / foundry change x25040p 7/31/00 die rev / foundry change x25040p-2.7 7/31/00 die rev / foundry change x25040pi 7/31/00 die rev / foundry change x25040pi-2.7 7/31/00 die rev / foundry change x25040s 7/31/00 die rev / foundry change x25040s-2.7 7/31/00 die rev / foundry change x25040si 7/31/00 die rev / foundry change x25040si-2.7 7/31/00 die rev / foundry change x25040sm 7/31/00 die rev / foundry change x25160s 8/31/00 foundry change x25160s-2.7 8/31/00 foundry change x25160si 8/31/00 foundry change x25160si-2.7 8/31/00 foundry change x25320p 8/31/00 foundry change x25320s 8/31/00 foundry change x25320s-2.7 8/31/00 foundry change x25320si 8/31/00 foundry change x25320si-2.7 8/31/00 foundry change
xicor product change notice 02/04/00 page 4 of 9 file://f:\export\projects\bitting2\imaging\bitting\mail_pdf\recode\pcn_000204.html 1/15/01 ? february 4, 2000 dear xicor customer, at xicor, we continuously strive to improve the performance and efficiency of our operations, and the quality of our products. consistent with this effort, we are revising the tape and reel "t" codes to eliminate partial reel quantities. see the detailed tape and reel "t" codes definitions list and definitions matrix below . the implementation date for the new tape and reel "t" codes is march 1, 2000. all existing orders with shipment dates on or after march 1, 2000 will be converted to the new tape and reel "t" codes. all new orders on or after march 1, 2000 must use the new tape and reel "t" codes. if you have any further questions, please contact your regional xicor sales office. sincerely, xicor marketing department ? tape and reel "t" code definitions code package qty requirements reel size t1 soic (150 mil soic) "s" =2500 tape and reel 13" t1 soic (300 mil soic) "s" =1000 tape and reel 13" t1 eiaj (wide soic) "a" =2000 tape and reel 13" t1 tsop (thin soic) "t" =1000 tape and reel 13" t1 plcc "j" =750 tape and reel 13" t1 msop "m" =2500 tape and reel 13" t1 gull wing "r" =500 tape and reel 13" t1 tssop "v" =2500 tape and reel 13" t1 xbga "b" or "z" =10000 tape and reel 13" t2 soic (150 mil soic) "s" =1000 tape and reel 7" t2 soic (300 mil soic) "s" =500 tape and reel 13" t2 eiaj (wide soic) "a" =1000 tape and reel 7"
xicor product change notice 02/04/00 page 5 of 9 file://f:\export\projects\bitting2\imaging\bitting\mail_pdf\recode\pcn_000204.html 1/15/01 t2 tsop (thin soic) "t" =500 tape and reel 13" t2 plcc "j" =500 tape and reel 13" t2 msop "m" =1000 tape and reel 7" t2 gull wing "r" =250 tape and reel 13" t2 tssop "v" =1000 tape and reel 7" t2 xbga "b" or "z" =5000 tape and reel 13" t3 soic (150 mil soic) "s" =2500 tape and reel & dry pack 13" t3 soic (300 mil soic) "s" =1000 tape and reel & dry pack 13" t3 eiaj (wide soic) "a" =2000 tape and reel & dry pack 13" t3 tsop (thin soic) "t" =1000 tape and reel & dry pack 13" t3 plcc "j" =750 tape and reel & dry pack 13" t3 msop "m" =2500 tape and reel & dry pack 13" t3 gull wing "r" =500 tape and reel & dry pack 13" t3 tssop "v" =2500 tape and reel & dry pack 13" t3 xbga "b" or "z" =10000 tape and reel & dry pack 13" t4 soic (150 mil soic) "s" =1000 tape and reel & dry pack 7" t4 soic (300 mil soic) "s" =500 tape and reel & dry pack 13" t4 eiaj (wide soic) "a" =1000 tape and reel & dry pack 7" t4 tsop (thin soic) "t" =500 tape and reel & dry pack 13" t4 plcc "j" =500 tape and reel & dry pack 13" t4 msop "m" =1000 tape and reel & dry pack 7" t4 gull wing "r" =250 tape and reel & dry pack 13" t4 tssop "v" =1000 tape and reel & dry pack 7" t4 xbga "b" or "z" =5000 tape and reel & dry pack 13" t5 msop "m" =3500 tape and reel 13" t5 tssop "v" =3500 tape and reel 13" t5 xbga "b" or "z" =2500 tape and reel 13" t6 msop "m" =3500 tape and reel & dry pack 13" t6 tssop "v" =3500 tape and reel & dry pack 13" t6 xbga "b" or "z" =2500 tape and reel & dry pack 13"
xicor product change notice 02/04/00 page 6 of 9 file://f:\export\projects\bitting2\imaging\bitting\mail_pdf\recode\pcn_000204.html 1/15/01 ? tape and reel "t" code definition matrix *note: dry pack only ? *note: dry pack only t6 xbga "b" or "z" =2500 tape and reel & dry pack 13" t7 all packages all qtys. dry pack n/a 150 mil soic "s" (8l, 14l,16l) code 2500 1000 dry pack t1 x x x t2 x x x t3 x ? x t4 x x x t7* x x x tsop thin soic "t" code 1000 500 dry pack t1 x x x t2 x x x t3 x x x t4 x x x t7* x x x gull wing "r" code 500 250 dry pack t1 x x x t2 x x x t3 x x x t4 x x x t7* x x x
xicor product change notice 02/04/00 page 7 of 9 file://f:\export\projects\bitting2\imaging\bitting\mail_pdf\recode\pcn_000204.html 1/15/01 *note: dry pack only *note: dry pack only ? *note: dry pack only *note: dry pack only 300 mil soic "s" (20l, 24l, 28l) code 1000 500 dry pack t1 x x x t2 x x x t3 x x x t4 x x x t7* x x x xbga "b" or "z" code 10000 5000 2500 dry pack t1 x x x x t2 x x x x t3 x x x x t4 x x x x t5 x x x x t6 x x x x t7* x x x x eiaj "a" code 2000 1000 dry pack t1 x x x t2 x x x t3 x x x t4 x x x t7* x x x
xicor product change notice 02/04/00 page 8 of 9 file://f:\export\projects\bitting2\imaging\bitting\mail_pdf\recode\pcn_000204.html 1/15/01 ? *note: dry pack only *note: dry pack only ? plcc "j" code 750 500 dry pack t1 x x x t2 x x x t3 x x x t4 x x x t7* x x x tssop "v" code 2500 1000 3500 dry pack t1 x x x x t2 x x x x t3 x x x x t4 x x x x t5 x x x x t6 x x x x t7* x x x x msop "m" code 2500 1000 3500 dry pack t1 x x x x t2 x x x x t3 x x x x t4 x x x x t5 x x x x t6 x x x x
xicor product change notice 02/04/00 page 9 of 9 file://f:\export\projects\bitting2\imaging\bitting\mail_pdf\recode\pcn_000204.html 1/15/01 *note: dry pack only t7* x x x x our web site makes extensive use adobe acrobat (pdf) documents to provide you with the highest quality in electronic publishing. if you do not have the adobe acrobat reader , click this hyperlink for a free copy. home | products | corporate | support | reps & disti's | what's new cool jobs | contact info | datasheets | search | site map copyright ? 2000 xicor inc.

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