View MT18HVF12872DY-667E1_3902822.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm features pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 1 ?2007 micron technology, inc. all rights reserved. ddr2 sdram dual-rank vlp rdimm mt18hvf12872(p)d ? 1gb mt18hvf25672(p)d ? 2gb for component data sheets, refer to micron?s web site: www.micron.com features ? fits with atca form factor ? 240-pin, very low profile registered dual in-line memory module (vlp rdimm) ? fast data transfer rates: pc2-3200, pc2-4200, pc2-5300, or pc2-6400 ? 1gb (128 meg x 72) or 2gb (256 meg x 72) ? supports ecc error detection and correction ?v dd = v dd q = +1.8v ?v ddspd = +1.7v to +3.6v ? jedec-standard 1.8v i/ o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ?4 n -bit prefetch architecture ? multiple internal device banks for concurrent operation ? programmable cas# latency (cl) ? posted cas# additive latency (al) ? write latency = read latency - 1 t ck ? programmable burst lengths: 4 or 8 ? adjustable data-output drive strength ? 64ms, 8,192-cycle refresh ? on-die termination (odt) ? serial presence-det ect (spd) with eeprom ? gold edge contacts ?dual rank figure 1: 240-pin vlp rdimm (atca form factor) notes: 1. contact micron for industrial temperature module offerings. 2. cl = cas (read) latency; registered mode will add one clock cycle to cl. options marking ?parity p ? operating temperature 1 ? commercial (0c t a +70c) d ? industrial (?40c t a +85c) t ?package ? 240-pin dimm (pb-free) y ? frequency/cas latency 2 ? 2.5ns @ cl = 5 (ddr2-800) -80e ? 2.5ns @ cl = 6 (ddr2-800) -800 ? 3.0ns @ cl = 5 (ddr2-667) -667 ? 3.75ns @ cl = 4 (ddr2-533) -53e ? 5.0ns @ cl = 3 (ddr2-400) -40e ?pcb height ? 17.9mm (0.70in) pcb height 17.9mm (0.70in) table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 6 cl = 5 cl = 4 cl = 3 -80e pc2-6400 ? 800 533 ? 12.5 12.5 55 -800 pc2-6400 800 667 533 ? 15 15 55 -667 pc2-5300 ? 667 533 400 15 15 55 -53e pc2-4200 ? ? 533 400 15 15 55 -40e pc2-3200 ? ? 400 400 15 15 55
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 2 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm features notes: 1. data sheets for the base device pa rts can be found on micron?s web site. 2. all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory fo r current revision codes. ex ample: mt18hvf12872(p)dy-667e1 . table 2: addressing parameter 1gb 2gb refresh count 8k 8k row address 16k (a0?a13) 16k (a0?a13) device bank address 4 (ba0, ba1) 8 (ba0?ba2) device page size per bank 1kb 1kb device configuration 512mb (64 meg x 8) 1gb (128 meg x 8) column address 1k (a0?a9) 1k (a0?a9) module rank address 2 (s0#, s1#) 2 (s0#, s1#) table 3: part numbers and timing parameters ? 1gb modules base device: mt47h64m8 1 , 512mb ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate latency (cl- t rcd- t rp) mt18hvf12872(p)d-80e__ 1gb 128 meg x 72 6.4 gb/s 2.5ns/800 mt/s 5-5-5 mt18hvf12872(p)d-800__ 1gb 128 meg x 72 6.4 gb/s 2.5ns/800 mt/s 6-6-6 mt18hvf12872(p)d-667__ 1gb 128 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 mt18hvf12872(p)d-53e__ 1gb 128 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt18hvf12872(p)d-40e__ 1gb 128 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 table 4: part numbers and timing parameters ? 2gb modules base device: mt47h128m8 1 , 1gb ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate latency (cl- t rcd- t rp) mt18hvf25672(p)d-80e__ 2gb 256 meg x 72 6.4 gb/s 2.5ns/800 mt/s 5-5-5 mt18hvf25672(p)d-800__ 2gb 256 meg x 72 6.4 gb/s 2.5ns/800 mt/s 6-6-6 mt18hvf25672(p)d-667__ 2gb 256 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 mt18hvf25672(p)d-53e__ 2gb 256 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt18hvf25672(p)d-40e__ 2gb 256 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 3 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm pin assignments and descriptions pin assignments and descriptions table 5: pin assignments 240-pin vlp rdimm front 240-pin vlp rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ref 31 dq19 61 a4 91 v ss 121 v ss 151 v ss 181 v dd q211dm5/ dqs14 2v ss 32 v ss 62 v dd q 92 dqs5# 122 dq4 152 dq28 182 a3 212 nc/ dqs14# 3 dq0 33 dq24 63 a2 93 dqs5 123 dq5 153 dq29 183 a1 213 v ss 4 dq1 34 dq25 64 v dd 94 v ss 124 v ss 154 v ss 184 v dd 214 dq46 5v ss 35 v ss 65 v ss 95 dq42 125 dm0/ dqs9 155 dm3/ dqs12 185 ck0 215 dq47 6dqs0#36dqs3#66 v ss 96 dq43 126 nc/ dqs9# 156 nc/ dqs12# 186ck0#216 v ss 7 dqs037dqs367 v dd 97 v ss 127 v ss 157 v ss 187 v dd 217 dq52 8v ss 38 v ss 68 p ar _i n 98 dq48 128 dq6 158 dq30 188 a0 218 dq53 9 dq2 39 dq26 69 v dd 99 dq49 129 dq7 159 dq31 189 v dd 219 v ss 10 dq3 40dq2770 a10 100 v ss 130 v ss 160 v ss 190 ba1 220 rfu 11 v ss 41 v ss 71 ba0 101 sa2 131 dq12 161 cb4 191 v dd q221 rfu 12 dq8 42 cb0 72 v dd q 102 nc 132 dq13 162 cb5 192 ras# 222 v ss 13 dq9 43 cb1 73 we# 103 v ss 133 v ss 163 v ss 193 s0# 223 dm6/ dqs15 14 v ss 44 v ss 74 cas# 104 dqs6# 134 dm1/ dqs10 164 dm8/ dqs17 194 v dd q224 nc/ dqs15# 15 dqs1# 45 dqs8# 75 v dd q105dqs6 135 nc/ dqs10# 165 nc/ dqs17# 195 odt0 225 v ss 16 dqs1 46 dqs8 76 s1# 106 v ss 136 v ss 166 v ss 196 a13 226 dq54 17 v ss 47 v ss 77 odt1 107 dq50 137 rfu 167 cb6 197 v dd 227 dq55 18 reset# 48 cb2 78 v dd q 108 dq51 138 rfu 168 cb7 198 v ss 228 v ss 19 nc 49 cb3 79 v ss 109 v ss 139 v ss 169 v ss 199 dq36 229 dq60 20 v ss 50 v ss 80 dq32 110 dq56 140 dq14 170 v dd q 200 dq37 230 dq61 21 dq10 51 v dd q 81 dq33 111 dq57 141 dq15 171 cke1 201 v ss 231 v ss 22 dq11 52 cke0 82 v ss 112 v ss 142 v ss 172 v dd 202 dm4/ dqs13 232 dm7/ dqs16 23 v ss 53 v dd 83 dqs4# 113 dqs7# 143 dq20 173 a15 203 nc/ dqs13# 233 nc/ dqs16# 24 dq16 54 ba2 84 dqs4 114 dqs7 144 dq21 174 a14 204 v ss 234 v ss 25 dq17 55 e rr _o ut 85 v ss 115 v ss 145 v ss 175 v dd q 205 dq38 235 dq62 26 v ss 56 v dd q 86 dq34 116 dq58 146 dm2/ dqs11 176 a12 206 dq39 236 dq63 27 dqs2# 57 a11 87 dq35 117 dq59 147 nc/ dqs11# 177 a9 207 v ss 237 v ss 28 dqs2 58 a7 88 v ss 118 v ss 148 v ss 178 v dd 208 dq44 238 v ddspd 29 v ss 59 v dd 89 dq40 119 sda 149 dq22 179 a8 209 dq45 239 sa0 30 dq18 60 a5 90 dq41 120 scl 150 dq23 180 a6 210 v ss 240 sa1
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 4 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm pin assignments and descriptions table 6: pin descriptions symbol type description odt0, odt1 input (sstl_18) on-die termination: odt1 (registered high) enables term ination resistance internal to the ddr2 sdram. when enabled, odt is only applied to the following pins: dq, dqs, dqs#, and cb. the odt input will be ignored if disa bled via the lo ad mode command. ck0, ck0# input (sstl_18) clock: ck and ck# are differential clock inputs. all address an d control input signals are sampled on the crossing of th e positive edge of ck and ne gative edge of ck#. output data (dqs and dqs/dqs#) is referenc ed to the crossings of ck and ck#. cke0, cke1 input (sstl_18) clock enable: cke (registered high) activates an d cke (registered low) deactivates clocking circuitry on the ddr2 sdram. s0#, s1# input (sstl_18) chip select: s# enables (registered low) and di sables (registered high) the command decoder. ras#, cas#, we# input (sstl_18) command inputs: ras#, cas#, and we# (along with s#) define the command being entered. ba0?ba2 input (sstl_18) bank address inputs: ba0?ba2 define the device bank to which an active, read, write, or precharge command is being applied. ba0?ba 2 define which mode register, including mr, emr, emr(2), and emr(3), is loaded duri ng the load mode command. ba0?ba1 (1gb), ba0?ba2 (2gb). a0?a15 input (sstl_18) address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank . a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0?ba2) or all device banks (a10 high). the ad dress inputs also provide the op-code during a load mode command . a14, a15 connected for parity. p ar _i n input (sstl_18) parity bit for the address and control bus. scl input (sstl_18) serial clock for presence-detect: scl is used to synchroniz e the presence-detect data transfer to and from the module. sa0?sa2 input (sstl_18) presence-detect address inputs: these pins are used to configure the presence-detect devices. reset# input (lvcmos) asynchronously forces all regi stered outputs low when reset# is low. this signal can be used during power-up to ensure that cke is low and dqs are high-z. dqs0?dqs8, dqs0#?dqs17# i/o (sstl_18) data strobe: output with read data, input with write data for source-synchronous operation. edge-aligned with read data, center-ali gned with write data. dqs# is only used when differential data strobe mode is enabled via the load mode command. dm0?dm8 (dqs9?dqs17) i/o (sstl_18) data input mask: dm is an input mask signal for wr ite data. input data is masked when dm is sampled high, along with that input data, during a wr ite access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading is designed to match that of dq and dqs pins. if rdqs is disabled, dqs9?dqs17 become dm0?dm8 and dqs9#?dqs17# are not used. dq0?dq63 i/o (sstl_18) data input/output: bidirectional data bus. cb0?cb7 i/o (sstl_18) check bits. sda i/o (sstl_18) serial presence-detect data: sda is a bidirectional pin us ed to transfer addresses and data into and out of the presence-detect portion of the module. e rr _o ut output (open drain) parity error found on the address and control bus. v dd /v dd q supply power supply: 1.8v 0.1v. v ref supply sstl_18 reference voltage. vss supply ground. v ddspd supply serial eeprom positive power supply: +1.7v to +3.6v.
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 5 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm pin assignments and descriptions nc ? no connect: these pins should be left unconnected. rfu ? reserved for future use. table 6: pin descriptions (continued) symbol type description
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 6 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm functional block diagram functional block diagram figure 2: functional block diagram dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm/ nu/ cs# dqs dqs# rdqs rdqs# u1 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u22 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dm/ nu/ cs# dqs dqs# rdqs rdqs# u9 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u16 dqs0 dqs0# dm0/dqs9 nc/dqs9# dqs4 dqs4# dm4/dqs13 nc/dqs13# dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm/ nu/ cs# dqs dqs# rdqs rdqs# u2 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u21 dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dm/ nu/ cs# dqs dqs# rdqs rdqs# u10 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u15 dqs1 dqs1# dm1/dqs10 nc/dqs10# dqs5 dqs5# dm5/dqs14 nc/dqs14# dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dm/ nu/ cs# dqs dqs# rdqs rdqs# u3 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u20 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dm/ nu/ cs# dqs dqs# rdqs rdqs# u11 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u14 dqs2 dqs2# dm2/dqs11 nc/dqs11# dqs6 dqs6# dm6/dqs15 nc/dqs15# dq dq dq dq dq dq dq dq dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm/ nu/ cs# dqs dqs# rdqs rdqs# u4 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u19 dq dq dq dq dq dq dq dq dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dm/ nu/ cs# dqs dqs# rdqs rdqs# u12 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u13 dqs3 dqs3# dm3/dqs12 nc/dqs12# dqs7 dqs7# dm7/dqs16 nc/dqs16# dq dq dq dq dq dq dq dq cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dm/ nu/ cs# dqs dqs# rdqs rdqs# u5 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u18 dqs8 dqs8# dm8/dqs17 nc/dqs17# a0 spd eeprom a1 a2 sa0 sa1 sa2 sda scl wp r e g i s t e r s pll s0# s1# ba0?ba2 a0?a15 ras# cas# we# cke0 cke1 odt0 odt1 p ar _i n reset# rs0#: rank0 rs1#: rank1 rba0?rba1/rba2: ddr2 sdram ra0?ra13: ddr2 sdram rras#: ddr2 sdram rcas#: ddr2 sdram rwe#: ddr2 sdram rcke0: rank0 rcke1: rank1 rodt0: rank0 rodt1: rank1 e rr _o ut ck0 ck0# ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 register x 2 reset# u7 v ref v ss ddr2 sdram ddr2 sdram v dd /v dd q v ddspd spd eeprom ddr2 sdram u6, u17 u8 rs1# rs0# rank0: u1?u5, u9?u12 rank1: u13?u16, u18?u22 v ss
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 7 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm general description general description the mt18hvf12872(p)d and mt18hvf25 672(p)d ddr2 sdram modules are high- speed, cmos, dynamic random-access 1gb and 2gb memory modules organized in a x72 configuration. these ddr2 sdram modules use internally configured 4-bank (512mb) or 8-bank (1gb) ddr2 sdram devices. ddr2 sdram modules use double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially a 4 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr2 sdram module effectively consists of a single 4 n -bit-wide, one-clock-cycle data transfer at the internal dram core and four corre- sponding n -bit-wide, one-half-clock-cycle da ta transfers at the i/o pins. a bidirectional data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram device during reads and by the memory controller during writes. dqs is edge- aligned with data for reads and center-aligned with data for writes. ddr2 sdram modules operate fr om a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. register and pll operation ddr2 sdram modules operate in registered mode, where the command/address input signals are latched in the registers on the ri sing clock edge and sent to the ddr2 sdram devices on the following rising clock edge (data access is delayed by one clock cycle). a phase-lock loop (pll) on the module receives and re-drives the differential clock signals (ck, ck#) to the ddr2 sdram devices. the register(s) and pll reduce address, command, control, and clock signal loading by isolating dram from the system controller. pll clock timing is defined by jedec specifications and ensured by use of the jedec clock reference board. registered mode will add one clock cycle to cl. serial presence-d etect operation ddr2 sdram modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bi t eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes are programmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa (2:0), which provide eight unique dimm/eeprom addresse s. write protect (wp) is tied to v ss on the module, permanently disabling hardware write protect.
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 8 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm electrical specifications electrical specifications stresses greater than those listed in ta ble 7 may cause perman ent damage to the module. this is a stress rating only, and func tional operation of the module at these or any other conditions above those indicated in each device?s data sheet is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. notes: 1. refresh rate is requir ed to double when 85c < t c 95c. 2. for further information, refer to technical note tn-00-08: thermal applications , available on micron?s web site. input capacitance micron encourages designers to simulate the performance of the module to achieve optimum values. simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. jedec modules are currently designed using simulations to close timing budgets. component ac timing an d operating conditions recommended ac operating conditions are given in the ddr2 component data sheets. component specifications are available on micron?s web site. module speed grades correlate with component speed grades, as shown in table 8. table 7: absolute maximum ratings symbol parameter min max units v dd /v dd q v dd /v dd q supply voltage relative to v ss ?0.5 +2.3 v v in , v out voltage on any pin relative to v ss ?0.5 +2.3 v i i input leakage curren t; any input 0v v in v dd ; v ref input 0v v in 0.95v (all other pins not under test = 0v) address inputs ras#, cas#, we#, s#, cke, odt, ba ?5 +5 a ck, ck# ?250 +250 dm ?10 +10 i oz output leakage current; 0v v out v dd q; dqs and odt are disabled dq, dqs, dqs# ?10 +10 a i vref v ref leakage current; v ref = valid v ref level ?36 +36 a t a module ambient operating temperature commercial 0+70c industrial ?40 +85 c t c 1 ddr2 sdram component case operating commercial 0+85c temperature 2 industrial ?40 +95 c table 8: module and component speed grades module speed grade component speed grade -80e -25e -800 -25 -667 -3 -53e -37e -40e -5e
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 9 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm electrical specifications i dd specifications notes: 1. value calculated as one mo dule rank in this op erating condition; all other module ranks in i dd 2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition. ta bl e 9 : dd r2 i dd specifications and conditions ? 1gb values shown for mt47h64m8 ddr2 sdram only an d are computed from valu es specified in the 512mb (64 meg x 8) component data sheet parameter/condition symbol -80e -800 -667 -53e -40e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switch ing; data bus inpu ts are switching i dd 0 1 963 873 783 783 ma operating one bank active-read-precharge current: i out =0ma; bl=4, cl=cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high be tween valid commands; address bus inputs are switching; da ta pattern is same as i dd 4w i dd 1 1 1,098 1,008 918 873 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd 2p 2 126 126 126 126 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other cont rol and address bus inputs are stable; data bus inputs are floating i dd 2q 2 900 810 720 630 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other co ntrol and address bus inpu ts are switching; data bus inputs are switching i dd 2n 2 990 900 810 720 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd 3p 2 720 630 540 450 ma slow pdn exit mr[12] = 1 216 216 216 216 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control an d address bus inputs ar e switching; data bus inputs are switching i dd 3n 2 1,260 1,170 990 810 ma operating burst write current: all device banks open; continuous burst writes; bl=4, cl=cl(i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4w 1 1,818 1,593 1,323 1,098 ma operating burst read current: all device banks open; continuous burst reads; i out =0ma; bl=4, cl=cl(i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switch ing; data bus inpu ts are switching i dd 4r 1 1,908 1,683 1,368 1,098 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are swit ching; data bus inputs are switching i dd 5 2 4,140 3,240 3,060 2,970 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating ; data bus inputs are floating i dd 6 2 126 126 126 126 ma operating bank interleave read current: all device banks interleaving reads; i out =0ma; bl=4, cl=cl(i dd ), al = t rcd (i dd )-1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid command s; address bus inputs are stable during deselects; data bus inputs are switching i dd 7 1 2,763 2,223 2,088 2,043 ma
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 10 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm electrical specifications notes: 1. value calculated as one mo dule rank in this op erating condition; all other module ranks in i dd 2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition. table 10: ddr2 i dd specifications and conditions ? 2gb values shown for mt47h128m8 ddr2 sdram only an d are computed from values specified in the 1gb (128 meg x 8) component data sheet parameter/condition symbol -80e -800 -667 -53e -40e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switch ing; data bus inpu ts are switching i dd 0 1 873 828 693 693 ma operating one bank active-read-precharge current: i out =0ma; bl=4, cl=cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd 4w i dd 1 1 1,053 963 918 873 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and addr ess bus inputs are stable; data bus inputs are floating i dd 2p 2 126 126 126 126 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other cont rol and address bus inputs are stable; data bus inputs are floating i dd 2q 2 900 720 720 630 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other co ntrol and address bus inpu ts are switching; data bus inputs are switching i dd 2n 2 900 720 720 630 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; othe r control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd 3p 2 720 540 540 540 ma slow pdn exit mr[12] = 1 180 180 180 180 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and addr ess bus inputs are switching; data bus inputs are switching i dd 3n 2 1,080 990 810 720 ma operating burst write current: all device banks open; continuous burst writes; bl=4, cl=cl(i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4w 1 1,503 1,278 1,188 1,008 ma operating burst read current: all device banks open; continuous burst reads; i out =0ma; bl=4, cl=cl(i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4r 1 1,503 1,278 1,188 1,008 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are swit ching; data bus inputs are switching i dd 5 2 4,230 3,870 3,780 3,690 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating ; data bus inputs are floating i dd 6 2 126 126 126 126 ma operating bank interleave read current: all device banks interleaving reads; i out =0ma; bl=4, cl=cl(i dd ), al = t rcd (i dd )-1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid command s; address bus inputs are stable during deselects; data bus inputs are switching i dd 7 1 3,078 2,583 2,493 2,403 ma
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 11 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm register and pll specifications register and pll specifications notes: 1. timing and switching specifications for the register listed above are cr itical for proper oper- ation of the ddr2 sdram regist ered dimms. these are meant to be a subset of the param- eters for the specific device us ed on the module. detailed in formation for this register is available in jedec standard jesd82. table 11: register specifications sstu32866 devices or equivalent jesd82-16 parameter symbol pins condition min max units dc high-level input voltage v ih ( dc ) address, control, command sstl_18 v ref ( dc ) + 125 v dd q + 250 mv dc low-level input voltage v il ( dc ) address, control, command sstl_18 0 v ref ( dc ) - 125 mv ac high-level input voltage v ih ( ac ) address, control, command sstl_18 v ref ( dc ) + 250 v dd mv ac low-level input voltage v il ( ac ) address, control, command sstl_18 0 v ref ( dc ) - 250 mv output high voltage v oh parity output lvcmos 1.2 ? v output low voltage v ol parity output lvcmos ? 0.5 v input current i i all pins v i = v dd q or v ss q?5 +5a static standby i dd all pins reset# = v ss q (i o = 0) ? 100 a static operating i dd all pins reset# = v ss q; v i = v ih ( ac ) or v il ( dc ) i o = 0 ?40ma dynamic operating (clock tree) i ddd n/a reset# = v dd , v i = v ih ( ac ) or v il ( ac ), i o = 0; ck and ck# switching 50% duty cycle ?varies by manufacturer a dynamic operating (per each input) i ddd n/a reset# = v dd , v i = v ih ( ac ) or v il ( ac ), i o = 0; ck and ck# switching 50% duty cycle; one data input switching at t ck/2, 50% duty cycle ?varies by manufacturer a input capacitance (per device, per pin) c i data v i = v ref 250mv; v dd q = 1.8v 2.5 3.5 pf input capacitance (per device, per pin) c i reset# v i = v dd q or v ss q?varies by manufacturer pf
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 12 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm register and pll specifications notes: 1. pll timing and swit ching specifications are critical for proper operation of the ddr2 dimm. this is a subset of parameters for the specific pll used. detailed pll in formation is available in jedec standard jesd82-8.01. table 12: pll specifications cu877 device or equivalent jesd82-8.18 parameter symbol pins condition min max units dc high-level input voltage v ih reset# lvcmos 0.65 v dd ?v dc low-level input voltage v il reset# lvcmos ? 0.35 v dd v input voltage (limits) v in reset#, ck, ck# ?0.3 v dd q + 0.3 v dc high-level input voltage v ih ck, ck# differential input 0.65 v dd ?v dc low-level input voltage v il ck, ck# differential input ? 0.35 v dd v input differential-pair cross voltage v ix ck, ck# differential input (v dd q/2) - 0.15 (v dd q/2) + 0.15 v input differential voltage v id ( dc ) ck, ck# differential input 0.3 v dd q + 0.4 v input differential voltage v id ( ac ) ck, ck# differential input 0.6 v dd q + 0.4 v input current i i reset# v i = v dd q or v ss q ?10 +10 a ck, ck# v i = v dd q or v ss q?250 +250a output disabled current i odl reset# = v ss q; v i = v ih ( ac ) or v il ( dc ) 100 ? a static supply current i ddld ck = ck# = low ? 500 a dynamic supply i dd n/a ck, ck# = 410 mhz, all outputs open (not connected to pcb) ?300ma input capacitance c in each input v i = v dd q or v ss q2 3pf table 13: pll clock driver timing requirements and switching characteristics parameter symbol min max units stabilization time t l? 15s input clock slew rate slr(i) i 1.0 4 v/ns ssc modulation frequency 30 33 khz ssc clock input frequency deviation 0.0 ?0.50 % pll loop bandwidth (?3db from unity gain) 2.0 ? mhz
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 13 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm serial presence-detect serial presence-detect notes: 1. to avoid spurious start and stop conditio ns, a minimum delay is pl aced between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a vali d stop condition of a write sequence to the end of the eeprom intern al erase/program cycl e. during the write cycle, the eeprom bus interface circuit is disabled, sda rema ins high due to pull-up resis- tance, and the eeprom does not respond to its slave address. table 14: serial presence-detec t eeprom dc operating conditions all voltages referenced to v ss parameter/condition symbol min max units supply voltage v ddspd 1.7 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il ?0.6 v ddspd 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li 0.10 3 a output leakage current: v out = gnd to v dd i lo 0.05 3 a standby current i sb 1.6 4 a power supply curren t, read: scl clock frequency = 100 khz i cc r 0.4 1 ma power supply current, write: scl clock frequency = 100 khz i cc w 23ma table 15: serial presence-detec t eeprom ac operating conditions all voltages referenced to v ss parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 ? s data-out hold time t dh 200 ? ns sda and scl fall time t f ? 300 ns 2 data-in hold time t hd:dat 0 ? s start condition hold time t hd:sta 0.6 ? s clock high period t high 0.6 ? s noise suppression time con stant at scl, sda inputs t i?50ns clock low period t low 1.3 ? s sda and scl rise time t r?0.3s2 scl clock frequency f scl ? 400 khz data-in setup time t su:dat 100 ? ns start condition setup time t su:sta 0.6 ? s 3 stop condition setup time t su:sto 0.6 ? s write cycle time t wrc ? 10 ms 4
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 14 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm serial presence-detect table 16: serial presence-detect matrix byte description entry (version) 1gb 2gb 0 number of spd bytes used by micron 128 80 80 1 total number of bytes in spd device 256 08 08 2 fundamental memory type ddr2 sdram 08 08 3 number of row addresses on sdram 14 0e 0e 4 number of column addresses on sdram 10 0a 0a 5 dimm height and module ranks 17.9mm, dual rank 11 11 6 module data width 72 48 48 7 reserved 00000 8 module voltage in terface levels sstl 1.8v 05 05 9 sdram cycle time, t ck (cl = max value, see byte 18) -80e/-800 -667 -53e -40e 25 30 3d 50 25 30 3d 50 10 sdram access from clock, t ac (cl = max value, see byte 18) -80e/-800 -667 -53e -40e 40 45 50 60 40 45 50 60 11 module configuration type ecc ecc and parity 02 06 02 06 12 refresh rate/type 7.81s/self 82 82 13 sdram device width (primary sdram) 80808 14 error-checking sdram data width 80808 15 reserved 00000 16 burst lengths supported 4, 8 0c 0c 17 number of banks on sdram device 4 or 8 04 08 18 cas latencies supported -80e (5, 4) -800 (6, 5, 4) -667 (5, 4, 3) -53e/-40e (4, 3) 30 70 38 18 30 70 38 18 19 module thickness 01 01 20 ddr2 dimm type registered dimm 01 01 21 sdram module attributes 1 pll, 2 reg 05 05 22 sdram device attributes: weak driver (01), or weak driver and 50 odt (03) -80e/-800/-667 -53e/-40e 03 01 03 01 23 sdram cycle time, t ck, max cl - 1 -80e/-667 -800 -53e/-40e 3d 30 50 3d 30 50 24 sdram access from ck, t ac, max cl - 1 -80e/-800 -667 -53e -40e 40 45 50 60 40 45 50 60 25 sdram cycle time, t ck, max cl - 2 -80e/-800 -667 -53e/-40e 00/3d 50 00 00/3d 50 00 26 sdram access from ck, t ac, max cl - 2 -80e/-800 -667 -53e/-40e 00/40 45 00 00/40 45 00 27 min row precharge time, t rp -80e -800/-667/-53e/-40e 32 3c 32 3c 28 min row active-t o-row active, t rrd 1e 1e
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 15 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm serial presence-detect 29 min ras#-to-cas# delay, t rcd -80e -800/-667/-53e/-40e 32 3c 32 3c 30 min active-to-precharge time, t ras -80e/-800/-667/-53e -40e 2d 28 2d 28 31 module rank density 512mb, 1gb 80 01 32 address and comma nd setup time, t is b -80e/-800 -667 -53e -40e 17 20 25 35 17 20 25 35 33 address and comma nd hold time, t ih b -80e/-800 -667 -53e -40e 25 27 37 47 25 27 37 47 34 data/data mask input setup time, t ds b -80e/-800 -667/-53e -40e 05 10 15 05 10 15 35 data/data mask input hold time, t dh b -80e/-800 -667 -53e -40e 12 17 22 27 12 17 22 27 36 write recovery time, t wr 3c 3c 37 write-to-read command delay, t wtr -80e/-667/-53e -800/-40e 1e 28 1e 28 38 read-to-precharge command delay, t rtp 1e 1e 39 memory analysis probe 00 00 40 extension for bytes 41 and 42 -80e -800/-667/-53e/-40e 30 00 36 06 41 min active-to-active/refresh time, t rc 1 -80e -800/-667/-53e -40e 39 3c 37 39 3c 37 42 min auto refresh-to-active/auto refresh command period, t rfc 69 7f 43 sdram device max cycle time, t ck (max) 80 80 44 sdram device max dqs?dq skew time, t dqsq -80e/-800 -667 -53e -40e 14 18 1e 23 14 18 1e 23 45 sdram device max read data hold skew factor, t qhs -80e/-800 -667 -53e -40e 1e 22 28 2d 1e 22 28 2d 46 pll relock time 15s 0f 0f 47?61 optional features, not supported 00 00 62 spd revision release 1.2 12 12 63 checksum for bytes 0? 62 ecc/ecc and parity -80e -800 -667 -53e -40e 65/69 06/0a 21/25 cc/d0 33/37 06/0a a7/ab c2/c6 6d/71 d4/d8 64 manufacturer?s jedec id code micron 2c 2c 65?71 manufacturer?s jedec id code (continued) ff ff table 16: serial presence-detect matrix (continued) byte description entry (version) 1gb 2gb
pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 16 ?2007 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm serial presence-detect notes: 1. the t rc spd values shown are jede c ddr2 device specification values. the actual micron ddr2 device specification is t rc = 55ns for all speed grades. 72 manufacturing location 1?12 01?0c 01?0c 73?90 module part number (ascii) ? variable data variable data 91 pcb identification code 1?9 01?09 01?09 92 identification co de (continued) 00000 93 year of manufacture in bcd ? variable data variable data 94 week of manufacture in bcd ? variable data variable data 95?98 module serial number ? variable data variable data 99?127 reserved for manufacturer-specific data 00 00 128?255 reserved for customer-specific data ff ff table 16: serial presence-detect matrix (continued) byte description entry (version) 1gb 2gb
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. 1gb, 2gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm module dimensions pdf: 09005aef8286b286/source: 09005aef8286b2d2 micron technology, inc., reserves the right to change products or specifications without notice. hvf18c128_256x72d.fm - rev. a 4/07 en 17 ?2007 micron technology, inc. all rights reserved. module dimensions figure 3: 240-pin ddr2 vlp rdimm notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference on ly. refer to the jedec mo document for com- plete design dimensions. 18.00 (0.710) 17.80 (0.701) pin 1 2.50 (0.098) d (2x) 3.30 (0.130) typ 5.0 (0.250) typ 123.0 (4.84) typ 1.0 (0.039) typ 2.20 (0.087) typ 0.80 (0.040) typ. 2.0 (0.079) r (4x) 0.75 (0.029) r pin 120 front view 133.50 (5.256) 133.20 (5.244) 63.0 (2.48) typ 55.0 (2.16) typ 10.0 (0.394) typ back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) 4.0 (0.157) max 1.0 (0.039) typ 3.05 (0.012) typ 70.68 (2.78) typ u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 u21 u22

▲Up To Search▲

Price & Availability of MT18HVF12872DY-667E1

	To Download MT18HVF12872DY-667E1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .