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is71vpcf16 x s04 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 copyright ? 2002 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 3.0 volt-only flash & sram combo with stacked multi-chip package (mcp) ? 16 mbit simultaneous operation flash memory and 4 mbit static ram mcp features ? power supply voltage 2.7v to 3.3v high performance: flash: 85ns maximum access time sram: 85ns maximum access time package: 69-ball bga operating temperature: -25c to +85c flash features power dissipation: read current at 1 mhz: 7 ma maximum read current at 5 mhz: 18 ma maximum sleep mode: 5 a maximum simultaneous read and write operations: zero latency between read and write operations; data can be programmed or erased in one bank while data is simultaneously being read from the other bank low-power mode: a period of no activity causes flash to enter a low- power state erase suspend/resume: suspends of erase activity to allow a read in the same bank. sector erase architecture: 8 words of 4k size and 31 words of 32k size (16 mbit) any combination of sectors, or the entire flash can be simultaneously erased erase algorithms: automatically preprograms/erases the flash memory entirely, or by sector program algorithms: automatically writes and verifies data at specified address hidden rom region: 64kb with a factory-serialized secure electronic serial number (esn), which is accessible through a command sequence data polling and toggle bit: allow for detection of program or erase cycle completion ready-busy output (ry/ by ): detection of program or erase cycle completion over 100,000 write/erase cycles low supply voltage (vccf 2.5v) inhibits writes wp /acc input pin: if v il , allows protection of boot sectors if v ih , allows removal of boot sector protection if vacc, program time is reduced by 40% boot sector: top or bottom sram features (4 mb density) power dissipation: operating: 40 ma maximum standby: 7 a maximum chip selects: ce1 s, ce2s power down feature using ce1s , or ce2s data retention supply voltage: 1.5 to 3.3 volt byte data control: lb s (dq0?dq7), ub s (dq8?dq15) ? in x16 mode general description the flash and sram mcp is available in 16 mbit flash/4 mbit sram having a data bus of either x8 or x16. the 16 mbit flash is composed of 1,048,576 words of 16 bits or 2,097,152 bytes of 8 bits. the 4mb sram has 262,144 words of 16 bits or 524,288 bytes of 8 bits. data lines dq0- dq7 handle the x8 format, while lines dq0-dq15 handle the x16 format. the package uses a 3.0v power supply for all operations. no other source is required for program and erase opera- tions. the flash can be programmed in system using this 3.0v supply, or can be programmed in a standard eprom programmer. the 16 mbit flash/4 mbit sram is offered in a 69-ball bga package. the flash is compatible with the jedec flash command set standard . the flash access time is 85ns and the sram access time is 85ns. the flash architecture is composed of two banks which allows simultaneous operation on each. optimized per- formance can be achieved by first initializing a program or erase function in one bank, then immediately starting a read from the other bank. both operations would then be operating simultaneously, with zero latency. preliminary information june 2002
is71vpcf16 x s04 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 logic symbol mcp block diagram a0-a19, a-1 sa ce f ce1 s ce2s oe we wp /acc reset ub s lb s i/of i/os dq0-dq15 21 16 or 8 ry/ by gnd gnd v ccf ry/ by 4-mbit static ram 16-mbit flash memory dq0-dq15/a-1 a0-a19 a0-a19 a-1 wp /acc reset ce f i/of sa lb s ub s we oe ce1 s ce2s i/os dq0-dq15/a-1 a0-a17 v ccs
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 preliminary information rev. 00c 06/14/02 state control & command register reset we ce byte wp /acc dq0-dq15 a0-a19 a0-a19 a0-a19 a0-a19 a0-a19 lower bank address upper bank address y -decoder latches and control logic lower bank upper bank x-decoder y -decoder latches and control logic x-decoder status control dq0-dq15 dq0-dq15 dq0-dq15 oe byte oe byte v cc gnd ry/ by flash memory block diagram flash bank organization note : for device part number, see part number logic diagram or ordering information organization type bank 1 size bank 2 size boot block type h 0.5mb 15.5mb top type j 2mb 14mb top type k 4mb 12mb top type l 8mb 8mb top type m 0.5mb 15.5mb bottom type n 2mb 14mb bottom type p 4mb 12mb bottom type q 8mb 8mb bottom
is71vpcf16 x s04 4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 pin descriptions a0-a17 address inputs, common a18-a19, a-1 address inputs, flash dq0-dq15/a-1 data inputs/outputs reset reset ce1 s, ce2s chip selects, sram i/of i/o configuration, flash ce f chip enable input, flash oe output enable input we write enable input i/os i/o configuration, sram lb s lower-byte control(dq0-dq7), sram ub s upper-byte control (dq8-dq15), sram wp /acc write protect/acceleration pin, flash ry/ by ready/busy output sa high order address pin, sram (x8) nc no connection vccf power, flash vccs power, sram gnd ground 1234 1 23 4 1 23 4 1234 shared flash only sram only 1234567890123 1 23456789012 3 1 23456789012 3 1 23456789012 3 1 23456789012 3 1234567890123 123456789012345 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 123456789012345 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 123456789012345 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 123456789012345 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 pin configuration (16 mb flash and 4 mb sram) 69 ball fbga (top view) 12345678910 ancncncnc bnc a7 lb wp /acc we a8 a11 ca3a6 ub reset ce2s a19 a12 a15 d a2 a5 a18 ry/ by nc a9 a13 nc e nc a1 a4 a17 a10 a14 nc nc f nc a0 gnd dq1 dq6 sa a16 nc g ce f oe dq9 dq3 dq4 dq13 dq15/a-1 i/of h ce1 s dq0 dq10 v cc fv cc s dq12 dq7 gnd j dq8 dq2 dq11 i/os dq5 dq14 kncncncnc
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 preliminary information rev. 00c 06/14/02 operation (1,3) f 1s ce2s sa (6) s sdq 0- dq 7 dq 8 -dq 15
/acc (5) full standby h h x x x x x x high-z high-z h x h x l x x x x x high-z high-z h x output disable h l h h h x x x high-z high-z h x h l h x x x h h high-z high-z h x l h x h h x x x high-z high-z h x l x l h h x x x high-z high-z h x read from flash (2) lhxlhxxx d out d out hx lxl lhxxx d out d out hx write to flash l h x h l x x x d in d in hx lxlhlxxx d in d in hx read from sram h l h l h x l l d out d out hx h l h l h x h l high-z d out hx hlhlhxlhd out high-z h x write to sram h l h x l x l l d in d in hx h l h x l x h l high-z d in hx hlhxlxlh d in high-z h x temporary sector xxxxxxxx x x v id (8) x group unprotection (4) flash hardware x h x x x x x x high-z high-z l x reset x x l x x x x x high-z high-z l x boot block sector xxxxxxxx x x x l write protection notes: 1. any operations not indicated this column are inhibited. 2. we can be vil if oe is vil, oe at vih initiates the write operations. 3. do not apply ce f = vil, ce 1s = vil and ce2s = vih all at once. 4. it is also used for the extended sector group protections. 5. wp /acc = vil: protection of boot sectors. wp /acc = vih: removal of boot sectors protection. wp /acc = vacc (9v): program time will reduce by 40%. 6. sa: don?t care or open. 7. l = vil, h = vih, x = vil or vih. 8. see dc characteristics. device bus operations user bus operations (flash=word mode: i/of = vccf, sram= word mode: i/os = vccs)
is71vpcf16 x s04 6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 notes: 1. any operations not indicated this column are inhibited.. 2. we can be vil if oe is vil, oe at vih initiates the write operations. 3. do not apply ce f = vil, ce 1s = vil and ce2s = vih all at once. 4. it is also used for the extended sector group protections. 5. wp /acc = vil: protection of boot sectors. wp /acc = vih: removal of boot sectors protection. wp /acc = vacc (9v): program time will reduce by 40%. 6. sa: don?t care or open. 7. l = vil, h = vih, x = vil or vih. 8. see dc characteristics. device bus operations operation ( ce2s dq 15 /a-1 sa (6) dq 0- dq 7 dq 8 -dq 15
wp/acc (5) full standby h h x x x x x x x high-z high-z h x h x l x x x x x x high-z high-z h x output disable h l h x h h x x x high-z high-z h x h l h x x x x h h high-z high-z h x l h x a-1 h h x x x high-z high-z h x l x l a-1 h h x x x high-z high-z h x read from flash (2) l h x a-1 l h x x x d out d out hx l x l a-1 l h x x x d out d out hx write to flash l h x a-1 h l x x x d in d in hx l x l a-1 h l x x x d in d in hx read from sram h l h x l h x l l d out d out hx h l h x l h x h l high-z d out hx hl h x lhxlhd out high-z h x write to sram h l h x x l x l l d in d in hx h l h x x l x h l high-z d in hx hl h x xlxlh d in high-z h x temporary sector x x x x x x x x x x x v id (8) x group unprotection (4) flash hardware x h x x x x x x x high-z high-z l x reset x x l x x x x x x high-z high-z l x boot block sector x x x x x x x x x x x x l write protection user bus operations (flash=byte mode: i/of = gnd, sram= word mode: i/os = vccs)
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 preliminary information rev. 00c 06/14/02 device bus operations user bus operations (flash=word mode: i/of = vccf, sram= byte mode: i/os = gnd notes: 1. any operations not indicated this column are inhibited.. 2. we can be vil if oe is vil, oe at vih initiates the write operations. 3. do not apply ce f = vil, ce 1s = vil and ce2s = vih all at once. 4. it is also used for the extended sector group protections. 5. wp /acc = vil: protection of boot sectors. wp /acc = vih: removal of boot sectors protection. wp /acc = vacc (9v): program time will reduce by 40%. 6. lb s, ub s: don?t care or open. 7. l = vil, h = vih, x = vil or vih. 8. see dc characteristics. operation (1,3) f 1s ce2s sa s (6) s (6) dq 0- dq 7 dq 8 -dq 15
/acc (5) full standby h h x x x x x x high-z high-z h x h x l x x x x x high-z high-z h x output disable h l h h h x x x high-z high-z h x h l h x x x h h high-z high-z h x l h x h h x x x high-z high-z h x l x l h h x x x high-z high-z h x read from flash (2) lhxlhxxx d out d out hx lxl lhxxx d out d out hx write to flash l h x h l x x x d in d in hx lxlhlxxx d in d in hx read from sram h l h l h sa x x d out high-z h x write to sram h l h x l sa x x d in high-z h x temporary sector xxxxxxxx x x v id (8) x group unprotection (4) flash hardware x h x x x x x x high-z high-z l x reset x x l x x x x x high-z high-z l x boot block sector xxxxxxxx x x x l write protection
is71vpcf16 x s04 8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 notes: 1. any operations not indicated this column are inhibited. 2. we can be vil if oe is vil, oe at vih initiates the write operations. 3. do not apply ce f = vil, ce 1s = vil and ce2s = vih all at once. 4. it is also used for the extended sector group protections. 5. wp /acc = vil: protection of boot sectors. wp /acc = vih: removal of boot sectors protection. wp /acc = vacc (9v): program time will reduce by 40%. 6. lb s, ub s: don?t care or open. 7. l = vil, h = vih, x = vil or vih. 8. see dc characteristics. device bus operations user bus operations (flash=byte mode: i/of = gnd, sram= byte mode: i/os = gnd) operation ( ce2s dq 15 /a-1 sa (6) (6) dq 0- dq 7 dq 8 -dq 15
wp/acc (5) full standby h h x x x x x x x high-z high-z h x h x l x x x x x x high-z high-z h x output disable h l h x h h x x x high-z high-z h x h l h x x x x h h high-z high-z h x l h x a-1 h h x x x high-z high-z h x l x l a-1 h h x x x high-z high-z h x read from flash (2) l h x a-1 l h x x x d out d out hx l x l a-1 l h x x x d out d out hx write to flash l h x a-1 h l x x x d in d in hx l x l a-1 h l x x x d in d in hx read from sram h l h x l h sa x x d out high-z h x write to sram h l h x x l sa x x d in high-z h x temporary sector x x x x x x x x x x x v id (8) x group unprotection (4) flash hardware x h x x x x x x x high-z high-z l x reset x x l x x x x x x high-z high-z l x boot block sector x x x x x x x x x x x x l write protection
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 preliminary information rev. 00c 06/14/02 flash - top boot sector address sector sector type t ype type type sector address size (x8) (x16) l k j h a19-a12 kb/kw address range address range bank2 bank2 bank2 bank2 sa0 00000xxx 64/32 000000h?00ffffh 000000h?007fffh bank2 bank2 bank2 bank2 sa1 00001xxx 64/32 010000h?01ffffh 008000h?00ffffh bank2 bank2 bank2 bank2 sa2 00010xxx 64/32 020000h?02ffffh 010000h?017fffh bank2 bank2 bank2 bank2 sa3 00011xxx 64/32 030000h?03ffffh 018000h?01ffffh bank2 bank2 bank2 bank2 sa4 00100xxx 64/32 040000h?04ffffh 020000h?027fffh bank2 bank2 bank2 bank2 sa5 00101xxx 64/32 050000h?05ffffh 028000h?02ffffh bank2 bank2 bank2 bank2 sa6 00110xxx 64/32 060000h?06ffffh 030000h?037fffh bank2 bank2 bank2 bank2 sa7 00111xxx 64/32 070000h?07ffffh 038000h?03ffffh bank2 bank2 bank2 bank2 sa8 01000xxx 64/32 080000h?08ffffh 040000h?047fffh bank2 bank2 bank2 bank2 sa9 01001xxx 64/32 090000h?09ffffh 048000h?04ffffh bank2 bank2 bank2 bank2 sa10 01010xxx 64/32 0a0000h?0affffh 050000h?057fffh bank2 bank2 bank2 bank2 sa11 01011xxx 64/32 0b0000h?0bffffh 058000h?05ffffh bank2 bank2 bank2 bank2 sa12 01100xxx 64/32 0c0000h?0cffffh 060000h?067fffh bank2 bank2 bank2 bank2 sa13 01101xxx 64/32 0d0000h?0dffffh 068000h?06ffffh bank2 bank2 bank2 bank2 sa14 01110xxx 64/32 0e0000h?0effffh 070000h?077fffh bank2 bank2 bank2 bank2 sa15 01111xxx 64/32 0f0000h?0fffffh 078000h?07ffffh bank1 bank2 bank2 bank2 sa16 10000xxx 64/32 100000h?10ffffh 080000h?087fffh bank1 bank2 bank2 bank2 sa17 10001xxx 64/32 110000h?11ffffh 088000h?08ffffh bank1 bank2 bank2 bank2 sa18 10010xxx 64/32 120000h?12ffffh 090000h?097fffh bank1 bank2 bank2 bank2 sa19 10011xxx 64/32 130000h?13ffffh 098000h?09ffffh bank1 bank2 bank2 bank2 sa20 10100xxx 64/32 140000h?14ffffh 0a0000h?0a7fffh bank1 bank2 bank2 bank2 sa21 10101xxx 64/32 150000h?15ffffh 0a8000h?0affffh bank1 bank2 bank2 bank2 sa22 10110xxx 64/32 160000h?16ffffh 0b0000h?0b7fffh bank1 bank2 bank2 bank2 sa23 10111xxx 64/32 170000h?17ffffh 0b8000h?0bffffh bank1 bank1 bank2 bank2 sa24 11000xxx 64/32 180000h?18ffffh 0c0000h?0c7fffh bank1 bank1 bank2 bank2 sa25 11001xxx 64/32 190000h?19ffffh 0c8000h?0cffffh bank1 bank1 bank2 bank2 sa26 11010xxx 64/32 1a0000h?1affffh 0d0000h?0d7fffh bank1 bank1 bank2 bank2 sa27 11011xxx 64/32 1b0000h-1bffffh 0d8000h-0dffffh bank1 bank1 bank1 bank2 sa28 11100xxx 64/32 1c0000h?1cffffh 0e0000h?0e7fffh bank1 bank1 bank1 bank2 sa29 11101xxx 64/32 1d0000h?1dffffh 0e8000h?0effffh
is71vpcf16 x s04 10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 flash - top boot sector address (continued) note: the address range is a19:a-1 in byte mode (i/of=vil ) or a19:a0 in word mode (i/of=vih ). the bank address bits are a19?a15 for type h, a19 - a17 for type j, and a19 and a18 for type k, and a19 for type l. device sector address size (x8) (x16) a19-a12 kb/kw address range address range types h, j, k, l 11111xxx 64/32 1f0000h-1fffffh f8000h-fffffh flash - top boot security sector addresses (hidden-rom) sector sector type t ype type type sector address size (x8) (x16) l k j h a19-a12 kb/kw address range address range bank1 bank1 bank1 bank2 sa30 11110xxx 64/32 1e0000h?1effffh f0000h?f7fffh bank1 bank1 bank1 bank1 sa31 11111000 8/4 1f0000h?1f1fffh f8000h?f8fffh bank1 bank1 bank1 bank1 sa32 11111001 8/4 1f2000h?1f3fffh f9000h?f9fffh bank1 bank1 bank1 bank1 sa33 11111010 8/4 1f4000h?1f6fffh fa000h?fafffh bank1 bank1 bank1 bank1 sa34 11111011 8/4 1f6000h?1f7fffh fb000h?fbfffh bank1 bank1 bank1 bank1 sa35 11111100 8/4 1f8000h?1f9fffh fc000h?fcfffh bank1 bank1 bank1 bank1 sa36 11111101 8/4 1fa000h?1fbfffh fd000h?fdfffh bank1 bank1 bank1 bank1 sa37 11111110 8/4 1fc000h?1fdfffh fe000h?fefffh bank1 bank1 bank1 bank1 sa38 11111111 8/4 1fe000h?1fffffh ff000h?fffffh
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 preliminary information rev. 00c 06/14/02 flash - bottom boot sector address sector sector type t ype type type sector address size (x8) (x16) q p n m a19-a12 kb/kw address range address range bank 1 bank1 bank1 bank1 sa0 00000000 8/4 000000h?001fffh 000000h?000fffh bank1 bank1 bank1 bank1 sa1 00000001 8/4 002000h?003fffh 001000h?001fffh bank1 bank1 bank1 bank1 sa2 00000010 8/4 004000h?005fffh 002000h?002fffh bank1 bank1 bank1 bank1 sa3 00000011 8/4 006000h?007fffh 003000h?003fffh bank1 bank1 bank1 bank1 sa4 00000100 8/4 008000h?009fffh 004000h?004fffh bank1 bank1 bank1 bank1 sa5 00000101 8/4 00a000h?00bfffh 005000h?005fffh bank1 bank1 bank1 bank1 sa6 00000110 8/4 00c000h?00dfffh 006000h?006fffh bank1 bank1 bank1 bank1 sa7 00000111 8/4 00e000h?00ffffh 007000h?007fffh bank1 bank1 bank1 bank2 sa8 00001xxx 64/32 010000h?01ffffh 008000h?00ffffh bank1 bank1 bank1 bank2 sa9 00010xxx 64/32 020000h?02ffffh 010000h?017fffh bank1 bank1 bank1 bank2 sa10 00011xxx 64/32 030000h?03ffffh 018000h?01ffffh bank1 bank1 bank2 bank2 sa11 00100xxx 64/32 040000h?04ffffh 020000h?027fffh bank1 bank1 bank2 bank2 sa12 00101xxx 64/32 050000h?05ffffh 028000h?02ffffh bank1 bank1 bank2 bank2 sa13 00110xxx 64/32 060000h?06ffffh 030000h?037fffh bank1 bank1 bank2 bank2 sa14 00111xxx 64/32 070000h?07ffffh 038000h?03ffffh bank1 bank2 bank2 bank2 sa15 01000xxx 64/32 080000h?08ffffh 040000h?047fffh bank1 bank2 bank2 bank2 sa16 01001xxx 64/32 090000h?09ffffh 048000h?04ffffh bank1 bank2 bank2 bank2 sa17 01010xxx 64/32 0a0000h?0affffh 050000h?057fffh bank1 bank2 bank2 bank2 sa18 01011xxx 64/32 0b0000h?0bffffh 058000h?05ffffh bank1 bank2 bank2 bank2 sa19 01100xxx 64/32 0c0000h?0cffffh 060000h?067fffh bank1 bank2 bank2 bank2 sa20 01101xxx 64/32 0d0000h?0dffffh 068000h?06ffffh bank1 bank2 bank2 bank2 sa21 01110xxx 64/32 0e0000h?0effffh 070000h?077fffh bank1 bank2 bank2 bank2 sa22 01111xxx 64/32 0f0000h?0fffffh 078000h?07ffffh bank2 bank2 bank2 bank2 sa23 10000xxx 64/32 100000h?10ffffh 080000h?087fffh bank2 bank2 bank2 bank2 sa24 10001xxx 64/32 110000h?11ffffh 088000h?08ffffh bank2 bank2 bank2 bank2 sa25 10010xxx 64/32 120000h?12ffffh 090000h?097fffh bank2 bank2 bank2 bank2 sa26 10011xxx 64/32 130000h?13ffffh 098000h?09ffffh bank2 bank2 bank2 bank2 sa27 10100xxx 64/32 140000h?14ffffh 0a0000h?0a7fffh bank2 bank2 bank1 bank2 sa28 10101xxx 64/32 150000h?15ffffh 0a8000h?0affffh bank2 bank2 bank1 bank2 sa29 10110xxx 64/32 160000h?16ffffh 0b0000h?0b7fffh
is71vpcf16 x s04 12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 flash - bottom boot sector address (continued) flash - bottom boot security sector addresses (hidden-rom) sector sector type t ype type type sector address size (x8) (x16) q p n m a19-a12 kb/kw address range address range bank2 bank2 bank2 bank2 sa30 10111xxx 64/32 170000h?17ffffh 0b8000h?0bffffh bank2 bank2 bank2 bank2 sa31 11000xxx 64/32 180000h?18ffffh 0c0000h?0c7fffh bank2 bank2 bank2 bank2 sa32 11001xxx 64/32 190000h?19ffffh 0c8000h?0cffffh bank2 bank2 bank2 bank2 sa33 11010xxx 64/32 1a0000h?1affffh 0d0000h?0d7fffh bank2 bank2 bank2 bank2 sa34 11011xxx 64/32 1b0000h?1bffffh 0d8000h?0dffffh bank2 bank2 bank2 bank2 sa35 11100xxx 64/32 1c0000h?1cffffh 0e0000h?0e7fffh bank2 bank2 bank2 bank2 sa36 11101xxx 64/32 1d0000h?1dffffh 0e8000h?0effffh bank2 bank2 bank2 bank2 sa37 11110xxx 64/32 1d0000h?1dffffh 0e8000h?0effffh bank2 bank2 bank2 bank2 sa38 11111xxx 64/32 1f0000h?1fffffh 0f8000h?0fffffh note: the address range is a19:a-1 in byte mode (i/of=vil ) or a19:a0 in word mode (i/of=vih ). the bank address bits are a19?a15 for type m, a19 - a17 for type n, and a19 - a18 for type p, and a19 for type q. device sector address size (x8) (x16) a19-a12 kb/kw address range address range types m,n,p,q 00000xxx 64/32 000000h-00ffffh 00000h-07fffh
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 preliminary information rev. 00c 06/14/02 sector group a19 a18 a17 a16 a15 a14 a13 a12 sectors sga0 00000xxx sa0 01 sga1 00010xxx sa1 to sa3 11 sga2 0 0 1 xxxxx sa4 to sa7 sga3 0 1 0 xxxxx sa8 to sa11 sga4 0 1 1 xxxxx sa12 to sa15 sga5 1 0 0 xxxxx sa16 to sa19 sga6 1 0 1 xxxxx sa20 to sa23 sga7 1 1 0 xxxxx sa24 to sa27 00 sga8 11101xxx sa28 to sa30 10 sga9 11111000 sa31 sga10 11111001 sa32 sga11 11111010 sa33 sga12 11111011 sa34 sga13 11111100 sa35 sga14 11111101 sa36 sga15 11111110 sa37 sga16 11111111 sa38 sector group address (type h, type j, type k, type l) (top boot block)
is71vpcf16 x s04 14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 sector group a19 a18 a17 a16 a15 a14 a13 a12 sectors sga0 00000000 sa0 sga1 00000001 sa1 sga2 00000010 sa2 sga3 00000011 sa3 sga4 00000100 sa4 sga5 00000101 sa5 sga6 00000110 sa6 sga7 00000111 sa7 01 sga8 00010xxx sa8 to sa10 11 sga9 001x xxxx sa11 to sa14 sga10 0 1 0 xxxxx sa15 to sa18 sga11 0 1 1 xxxxx sa19 to sa22 sga12 1 0 0 xxxxx sa23 to sa26 sga13 1 0 1 xxxxx sa27 to sa30 sga14 1 1 0 xxxxx sa31 to sa34 00 sga15 11101xxx sa35 to sa37 10 sga16 11111xxx sa38 sector group address (type m, type n, type p, type q) ( bottom boot block)
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 preliminary information rev. 00c 06/14/02 type a 12 to a 19 a 6 a 1 a 0 a ?1(1) code (hex) manufacturer?s code x vil vil vil vil 04h type h device id byte x vil vil vih vil 36h word x vil vil vih x 2236h type m device id byte x vil vil vih vil 39h word x vil vil vih x 2239h type j device id byte x vil vil vih vil 2dh word x vil vil vih x 222dh type n device id byte x vil vil vih vil 2eh word x vil vil vih x 222eh type k device id byte x vil vil vih vil 28h word x vil vil vih x 2228h type p device id byte x vil vil vih vil 2bh word x vil vil vih x 222bh type l device id byte x vil vil vih vil 33h word x vil vil vih x 2233h type q device id byte x vil vil vih vil 35h word x vil vil vih x 2235h sector group protect sector vil vih vil vil 01h (2) group address flash memory autoselect codes note: 1. a?1 is only used for byte mode. 2. output 01h at protected sector address and output 00h at unprotected sector address.
is71vpcf16 x s04 16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 flash memory command definitions note: *1: both read/reset commands are functionally equivalent, resetting the device to the read mode. *2: this command is valid during fast mode. *3: this command is valid while reset=vid. *4: the valid address is a0 to a6. *5: this command is valid during hi-rom mode. *6: the data ?00h? is also acceptable. command sequence bus 6 1 1 3 2 2 4 1 3 4 6 4 bus write cycle req'd first bus second bus third bus fourth bus fifth bus sixth bus cycle write cycle write cycle read/write cycle cycle ? pa data read / reset * 1 hidden-rom exit * 5 extended sector group protection * 3 set to fast mode fast program * 2 data data 2aah 555h ? addr. addr. xxxh ba ba 555h aah ? addr. addr. data ? addr. data ? addr. ? ? ? data read / reset ? pa spa xxxh ? 60h f0h*6 ? spa ? ? pa ? ? spa ? ? ? ? ? ? ra ? ? ? ? ? ? ? ? ? ? 55h ? ? ? ? ? ? ? ? ? ? ? ? hra 555h aaah sa ? ? ? ? ? ? ? ? ? 30h 10h ? ? ? 30h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 55h 55h 55h 55h 55h ? ? 55h pd f0h aah aah aah aah f0h ? ? rd ? aah pd aah ? ? ? ? ? sd ? ? pd aah 00h a0h 80h 80h ? ? 20h ? ? 40h ? 88h a0h 80h 90h aah b0h 30h ? 555h aaah ? ? xxxh ba xxxh aah a0h 90h 60h 98h aah aah aah aah 55h 55h 55h 55h word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte 55h aah 555h aaah 555h aaah 555h aaah 555h aaah 2aah 555h 2aah 555h 2aah 555h 2aah 555h 2aah 555h 2aah 555h 2aah 555h 2aah 555h 2aah 555h 555h 555h aaah 555h aaah 555h aaah 555h aaah 555h aaah 555h aaah 555h (hrba) 2aah 555h 2aah 555h 2aah 555h 555h aaah 555h aaah 555h aaah xxxh reset from fast mode * 2 555h aaah 555h aaah 555h aaah 555h aaah 555h aaah autoselect program chip erase sector erase sector erase suspend sector erase resume query * 4 hidden-rom entry hidden-rom program * 5 hidden-rom erase * 5 90h ? ? 55h 55h ? (ba) aaah (hrba) aaah 555h aaah 1 3 3 4 (ba)
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 preliminary information rev. 00c 06/14/02 mcp absolute maximum ratings (1,2,3) symbol parameter value unit t bias temperature under bias ?25 to +85 c t stg storage temperature ?55 to +125 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for data, ?0.3 to v cc f + 0.4 v address and control pins ?0.3 to v cc s + 0.4 v v in reset (5) -0.5 to +13.0 v v in wp /acc (6) -0.5 to +10.5 v v cc f/v cc s voltage on vcc supply relative to gnd (4) ?0.3 to 4.0 v notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 4. minimum dc voltage on input or i/o pins is ?0.3 v. during voltage transitions, input or i/o pins may undershoot vss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc f+0.3 v or v cc s+0.3 v. during voltage transitions, input or i/o pins may overshoot to v cc f+2.0 v or v cc s+2.0 v for periods of up to 20 ns. 5. minimum dc input voltage on reset pin is ?0.5 v. during voltage transitions, reset pin may undershoot vss to ?2.0 v for per iods of up to 20 ns. voltage difference between input and supply voltage (v in -v cc f or v cc s) does not exceed 9.0 v. maximum dc input voltage on reset pin is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. 6. minimum dc input voltage on wp /acc pin is ?0.5 v. during voltage transitions, wp /acc pin may undershoot vss to ?2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +12.0v for periods of up to 20 ns, when v cc f is applied. type m, type n, type p, type q (bottom boot type) word mode: 000000h to 007fffh byte mode: 000000h to 00ffffh hrba = bank address of the hidden-rom area type h, type j, type k, type l (top boot type) : a15 = a16 = a17 = a18 = a19 = 1 type m, type n, type p, type q (bottom boot type) : a15 = a16 = a17 = a18 = a19 = 0 rd = data read from location ra during read operation. pd = data to be programmed at location pa. sd = sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. the system should generate the following address patterns; word mode : 555h or 2aah to addresses a0 to a10 byte mode : aaah or 555h to addresses a?1 and a0 to a10 ddress bits a12 to a19 = x = ?h? or ?l? for all address commands except for program address (pa), sector address (sa),and bank address (ba). bus operations are defined in ?device bus operations?. ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a19 , a18 , a17 , a16 , a15 , a14 , a13 , and a12 will uniquely select any sector. ba = bank address (a15 to a19 ) spa = sector group address to be protected. set sector group address (sga) and (a6 , a1 , a0 ) = (0, 1, 0) for protect; or sga and (a6, a1, a0) = (1,1,0) for unprotect. hra= address of the hidden-rom area type h, type j, type k, type l (top boot type) word mode: 0f8000h to 0fffffh byte mode: 1f0000h to 1fffffh
is71vpcf16 x s04 18 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 mcp operating range range ambient temperature v ccf ,v ccs industrial ?25c to +85c 2.7?3.3v capacitance (1) symbol parameter conditions typ. max. unit c in input capacitance v in = 0v 11 14 pf c out output capacitance v out = 0v 12 16 pf c in 2 control pin capacitance v in = 0v 14 16 pf c in 3 wp /acc pin capacitance v in = 0v 17 20 pf notes: 1. test conditions: t a = 25c, f = 1 mhz standard voltage range v cc = 2.7-3.3 v f lash m emory sram u nits max access time 70 85 70 85 ns ce access 70 85 70 85 ns oe access 30 40 35 45 ns
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 19 preliminary information rev. 00c 06/14/02 symbol parameter test conditions min. max. unit i li input leakage v in =v ss to v cc f, v cc s -1.0 1.0 a i lo output leakage v out =v ss to v cc f, v cc s -1.0 1.0 a v il input low level -0.2 0.5 v v ih input high level 2.4 v cc + 0.3 (2) v v id voltage for sector 11.5 12.5 v protection, and temporary sector unprotection ( reset ) (1) v acc voltage for program 8.5 9.5 v acceleration ( wp /a cc ) (1) v ol output low level v cc f = v cc f min., v ccs =v ccs min. ? 0.45 v i ol = 1.0ma v oh output high level v cc f = v cc f min., v ccs =v ccs min. 2.4 ? v i oh = -0.5ma v lko flash low vccf 2.3 2.5 v mcp dc characteristics notes: 1. applicable for only v cc f applying. 2. v cc indicates lower of v cc f or v cc s .
is71vpcf16 x s04 20 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 flash dc characteristics symbol parameter test conditions min. max. unit i lit reset inputs v cc f=v cc f max., v cc s=v cc s max. ? 35 a leakage current reset = 12.5v i lia acc inputs v cc f=v cc f max., v cc s=v cc s max. ? 20 a leakage current wp /acc = vacc max. i cc 1f flash vcc (1) ce f=v il tcycle = 5mhz byte ? 13 ma active current (read) oe =v ih tcycle = 5mhz word ? 15 tcycle = 1mhz byte ? 7 tcycle = 1mhz word ? 7 i cc 2f flash vcc active (2) ce f=v il ?35ma current(program/erase) oe =v ih i cc 3f flash vcc active (4) ce f=v il byte ? 48 ma current oe =v ih word 50 (read-while-program) i cc 4f flash vcc active (4) ce f=v il byte ? 48 ma current oe =v ih word 50 (read-while-erase) i cc 5f flash vcc active ce f=v il ?35ma current oe =v ih (erase-suspend-program) i sb 1f flash vcc v cc f = vcc max, ce f= v cc f = + 0.3v ? 5 a standby current reset, ce f, wp /acc = v cc f = + 0.3v i sb 2f flash vcc v cc f = vcc max, reset = v ss = + 0.3v ? 5 a standby current wp /acc = v cc f = + 0.3v ( reset ) i sb 3f flash vcc (3) v cc f = vcc max. ce f, = v ss = + 0.3v ? 5 a standby current reset, wp /acc = v cc f = + 0.3v (auto sleep mode) v in = v cc f + 0.3v or v ss + 0.3v notes: 1. the icc current listed includes both the dc operating current and the frequency dependent component. 2. icc active while embedded algorithm (program or erase) is in progress. 3. automatic sleep mode enables the low power mode when address remain stable for 150 ns.. 4. embedded algorithm (program or erase) is in progress. (@5 mhz)
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 21 preliminary information rev. 00c 06/14/02 jedec standard parameter symbol symbol condition min unit ce recover time ? t ccr ?0ns ce hold time ? t chold ?3ns ac characteristics - timing timing diagram for alternating sram to flash cef ce1 s ce2s t ccr t ccr t ccr t ccr t chold t chold we
is71vpcf16 x s04 22 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 flash read only switching characteristics (over operating range) symbol parameter min. max. min. max. unit t rc cycle time 70 85 ? ns t acc address to output delay ? 70 ? 85 ns t ce chip enable to output delay ? 70 ? 85 ns t oe output enable to output delay ? 30 ? 35 ns t df chip enable to output high-z ? 25 ? 30 ns t df output enable to output high-z ? 25 ? 30 ns t oh output hold time from addresses, 0 ? 0 ? ns ce f or oe , whichever occurs first t ready reset pin low to read mode ? 20 ? 20 s flash ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 5 ns input and output timing 1.5v and reference level output load 1 ttl gate and 30pf
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 23 preliminary information rev. 00c 06/14/02 flash read cycle address dq cef oe we address stable output valid high-z high-z t oeh t rc t oe t df t ce t acc t oh
is71vpcf16 x s04 24 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 flash hardware / read operation timing diagram address dq cef reset address stable output valid high-z t rc t acc t rh t ce t rh t rp t oh
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 25 preliminary information rev. 00c 06/14/02 flash erase/program operation characteristics (over operating range) -70 ns -85ns symbol parameter min. max. min. max. unit t wc write cycle time 70 - 85 - ns t as address setup time ( we to addr.) 0 - 0 - ns t aso address setup time to ce f low during 12 - 15 - ns toggle bit polling t ah address hold time ( we to addr.) 45 - 45 - ns t aht address hold time from ce f or 0 - 0 - ns oe high during toggle bit polling t ds data setup time 30 - 35 - ns t dh data hold time 0 - 0 - ns t oes output enable setup time 0 - 0 - ns t oeh output enable hold time read 0 - 0 - ns t oeh output enable hold time 10 - 10 - ns toggle and data polling t ceph ce f high during toggle bit polling 20 - 20 - ns t oeph oe high during toggle bit polling 20 - 20 - ns t ghel read recover time before write ( oe to ce f) 0 - 0 - ns t ghwl read recover time before write ( oe to we )0-0-ns t ws we setup time (cef to we) 0 - 0 - ns t cs ce f setup time (we to cef) 0 - 0 - ns t wh we hold time (cef to we) 0 - 0 - ns t ch ce f hold time (we to cef) 0 - 0 - ns t wp write pulse width 30 - 35 - ns t cp ce f pulse width 30 - 35 - ns t wph write pulse width high 25 - 30 - ns t cph ce f pulse width high 25 - 30 - ns t whwh 1 byte programming operation - 12 - 15 s t whwh 1 word programming operation - 15 - 20 s t whwh 2 sector erase operation (1) - 0.7 - 1 s t vcs v cc f setup time 50 - 50 - s note : 1. this does not include the preprogramming time.
is71vpcf16 x s04 26 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 -70 ns -85ns symbol parameter min. max. min. max. unit t vlht voltage transition time (2) 4- 4 - s t vidr rise time to v id (2) 500 - 500 - ns t vacca rise time to v acc 500 - 500 - ns t rb recovery time from ry/ by 0- 0 - ns t rp reset pulse width 500 - 500 - ns t eoe delay time from embedded output enable - 70 - 85 ns t rh reset high level period before read 200 - 200 - ns t busy program/erase valid to ry/b y delay - 90 - 90 ns t tow erase time-out time (3) 50 - 50 - s t spd erase suspend transition time (4) - 20 -20 s note: 2. this timing is for sector protection operation. 3. the time between writes must be less than ?ttow ? otherwise that command will not be accepted and erasure will start. a time-out or ?ttow ? from the rising edge of last ce f or we whichever happens first will initiate the execution of the sector erase command(s). 4. when the erase suspend command is written during the sector erase operation, the device will take a maximum of ?tspd ? to suspend the erase operation. flash erase/program operation characteristics (continued) (over operating range)
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 27 preliminary information rev. 00c 06/14/02 flash write cycle ( we control) notes: 1 . pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode (the addresses differ from 8 mode, i.e. aaah). address dq cef oe we a0h dq 7 dout pa 555h pa data p pd dt t as 3rd bus cycle t sh t wc t rc t oe t ce t oh t df t ds t dh t whwh1 t cs t ch t ghwl t wp t wph
is71vpcf16 x s04 28 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 flash write cycle ( ce f control) notes: 1 . pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode (the addresses differ from 8 mode, i.e. aaah). address dq cef oe we a0h dq 7 dout pa 555h pa data p pd t as 3rd bus cycle t ah t wc t ds t dh t whwh1 t ws t wh t ghel t cp t cph
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 29 preliminary information rev. 00c 06/14/02 flash ac waveforms chip/sector erase operations *sa is the sector address for sector erase. address = 555h for chip erase. note: these waveforms are for the 16 mode (the addresses differ from 8 mode: aaah, 555h, aaah, aaah, 555h, sa*). address dq cef oe we 55h 10h/ 30h vccf 55h aah 80h aah 555h 2aah 555h 555h 2aah sa* 30h for sector erase t wc t as t ah t cs t ch t wp t wph t vcs t ghwl t ds t dh
is71vpcf16 x s04 30 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 flash ac waveforms for data polling during embedded alogrithm operations *dq7 = valid data (the device has completed the embedded operation.) data in dq 0 /dq 6 cef oe we ry/ by dq data in dq 7 dq0 to dq6 = output flag dq0 to dq6 valid data dq7 = valid data t df t busy t whwh1 or 2 t oe t eoe t oeh t cef t ch high - z high - z
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 31 preliminary information rev. 00c 06/14/02 flash ac waveforms for toggle bit during embedded algorithm operations * dq6 stops toggling (the device has completed the embedded operation). toggle toggle toggle toggle outpu t data data data data valid data address dq 6 /dq 2 cef oe we t dh t busy t oeh t oe ry/ by t cef * t oeh t oeph t ceph t aht t aso t aht t as
is71vpcf16 x s04 32 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 flash back-to-back read/write timing diagram note: this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address of bank 1. ba2: address of bank 2. address dq cef oe we ba1 ba1 ba1 t rc t as t ah t acc t ce ba2 (555h) ba2 (pa) ba2 (pa) read command read command read read valid valid valid valid valid output input output input output status t wc t rc t wc t rc t rc t ds t dh t df t df t oeh (pd) t ghwl t wp (a0h) t oe t ceph t aht t as
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 33 preliminary information rev. 00c 06/14/02 flash ry/ timing diagram during write/erase operations flash ry/ timing diagram we cef ry/ by the rising edge of the last we signal entire programming or erase operations t busy we reset ry/ by t ready t rp t rb
is71vpcf16 x s04 34 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 flash temporary sector group unprotection reset v ccf v id v ih cef we ry /by program or erase command sequence unprotection period vidr t vcs t vlht t vlht t vlht
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 35 preliminary information rev. 00c 06/14/02 flash accelerated program wp/ acc vccf vacc vih cef we ry /by acceleration period t vaccr t vcs t vlht t vlht t vlht program command sequence
is71vpcf16 x s04 36 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 flash extended sector group protection sgax: sector group address to be protected. sgay: next group sector address to be protected unprotection: implement with a6 = 1, a1 = 1, a0 = 0. time-out approximately 15 ms. time-out : time-out window = 250 s (min.) reset address a0 a1 a6 cef oe we data vccf 60h 60h 40h 01h 60h sgax sgay sgax time-out t vcs vidr vlht t wc t wp t oe t wc
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 37 preliminary information rev. 00c 06/14/02 sram read cycle switching characteristics (1) (over operating range) 70 ns 85ns symbol parameter min. max. min. max. unit t rc read cycle time 70 ? 85 ? ns t aa address access time ? 70 ? 85 ns t oha output hold time 10 ? 10 ? ns t ace1 ce1 s access time ? 70 ? 85 ns t doe oe access time ? 35 ? 45 ns t hzoe (2) oe to high-z output ? 25 ? 35 ns t lzoe (2) oe to low-z output 5 ? 5 ? ns t hzce1 (2) ce1 s to high-z output 0 25 0 35 ns t lzce1 (2) ce1 s to low-z output 10 ? 10 ? ns t ba lb s , ub s access time ? 70 ? 85 ns t hzb lb s , ub s to high-z output 0 25 0 50 ns t lzb lb s , ub s to low-z output 0 ? 0 ? ns notes: 1. see sram ac test conditions. 2. transition is measured 500 mv from steady-state voltage. not 100% tested. sram power supply characteristics (1) (over operating range) symbol parameter test conditions min. max. unit i cc vcc dynamic operating v ccs = max., ? 40 ma supply current i out = 0 ma, f = f max i cc 1 operating supply v ccs = max., ? 8 ma current i out = 0 ma, f = 0 i sb cmos standby v ccs = max., ? 7 a current (cmos inputs) ce1 s v ccs ? 0.2v, ce2 s 0.2v, v in v ccs ? 0.2v, or v in 0.2v, f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
is71vpcf16 x s04 38 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 ac waveforms sram read cycle no. 1 (1,2) (address controlled) ( ce1 s = oe = v il , s or s = v il ) data valid previous data valid t aa t oha t oha t rc dout address sram ac test conditions parameter unit input pulse level 0.4v to 3.0v input rise and fall times 5 ns input and output timing 1.5v and reference level output load 1 ttl gate and 30pf
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 39 preliminary information rev. 00c 06/14/02 ac waveforms sram read cycle no. 2 (1,3) ( ce1 s , oe , and ub s / lb s controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce1 , ub s , or lb s = v il . 3. address is valid prior to or coincident with ce1 low transition. t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzce1 address oe ce1 s ce2 s dout lb s , ub s t hzb t ba t lzb
is71vpcf16 x s04 40 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 write cycle switching characteristics (1,2) (over operating range) 70ns 85ns symbol parameter min. max. min. max. unit t wc write cycle time 70 ? 85 ? ns t sce1 ce1 s to write end 60 ? 70 ? ns t aw address setup time to write end 60 ? 70 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup time 0 ? 0 ? ns t pwb lb s , ub s valid to end of write 60 ? 70 ? ns t pwe we pulse width 50 ? 60 ? ns t sd data setup to write end 30 ? 35 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe (3) we low to high-z output ? 25 ? 35 ns t lzwe (3) we high to low-z output 0 ? 0 ? ns notes: 1. see sram ac test conditions. 2. the internal write time is defined by the overlap of ce1 low and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that termi nates the write. 3. transition is measured 500 mv from steady-state voltage. not 100% tested.
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 41 preliminary information rev. 00c 06/14/02 notes: 1. write is an internally generated signal asserted during an overlap of the low states on the ce1 s and we inputs and at least one of the lb s and ub s inputs being in the low state. 2. write = ( ce1 s ) [ ( lb s ) = ( ub s ) ] ( we ). ac waveforms sram write cycle no. 1 (1,2) ( ce1 s controlled, oe = high or low) data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe (4) t hzwe high-z t lzwe t sa t sd t hd address ce1 s ce2 s we dout din lb s , ub s
is71vpcf16 x s04 42 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 ac waveforms sram write cycle no. 2 ( we controlled: oe is high during write cycle) data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe1, 2 t hzwe high-z t lzwe t sa t sd t hd address oe ce1s ce2s we lbs , ubs dout din
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 43 preliminary information rev. 00c 06/14/02 ac waveforms sram write cycle no. 3 ( we controlled: oe is low during write cycle) data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe1, 2 t hzwe high-z t lzwe t sa t sd t hd address oe ce1s ce2s we lbs , ubs dout din
is71vpcf16 x s04 44 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 write cycle no. 4 ( ub s / lb s controlled, ce1 s is low, ce2s is high) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 word 2 t hd t sa t hzwe address ubs , lbs we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha ub_cswr4.eps
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 45 preliminary information rev. 00c 06/14/02 sram data retention switching characteristics symbol parameter test condition min. max. unit v dr vcc for data retention see data retention waveform 1.5 3.3 v i dr data retention current vcc = 1.5v, cs1 vcc ? 0.2v ? 7 a t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns sram data retention waveform ( ce1 controlled) v cc ce1 s v cc - 0.2v t sdr t rdr v dr ce1 s gnd 2.7v 2.5v data retention mode
is71vpcf16 x s04 46 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 symbol min. typ. max. units a? ?1.40mm a1 0.28 0.38 0.48 mm d 11.50 11.00 11.10 mm d1 ? 7.20 ? mm e 7.90 8.00 8.10 mm e1 ? 7.20 ? mm e ? 0.80 ? mm mini ball grid array ? 69-ball bga package code: f - 8.0 mm x 11.0 mm body, 0.8 mm ball pitch 10987654321 12345678910 a b c d e f g h j k a b c d e f g h j k ? 0.45 + 0.10/-0.05 (73x) e e a1 seating plane e1 a e d1 d
is71vpcf16 x s04 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 47 preliminary information rev. 00c 06/14/02 part number logic is 71 x xx f xx x s xx ? xxxx x x flash organization : a = type a - top boot block (bank1: 4mbit, bank2: 28mbit) b = type b - top boot block (bank1: 8mbit, bank2: 24mbit) c = type c - top boot block (bank1: 16mbit, bank2: 16mbit) d = type d - bottom boot block (bank1: 4mbit, bank2: 28mbit) e = type e - bottom boot block (bank1: 8mbit, bank2: 24mbit) f = type f - bottom boot block (bank1: 16mbit, bank2: 16mbit) g = user configurable bank grouping h = type h - top boot block (bank1: 0.5mbit, bank2: 15.5mbit) j = type j - top boot block (bank1: 2mbit, bank2: 14mbit) k = type k - top boot block (bank1: 4mbit, bank2: 12mbit) l = type l - top boot block (bank1: 8mbit, bank2: 8mbit) m = type m - bottom boot block (bank1: 0.5mbit, bank2: 15.5mbit) n = type n - bottom boot block (bank1: 2mbit, bank2: 14mbit) p = type p - bottom boot block (bank1: 4mbit, bank2: 12mbit) q = type q - bottom boot block (bank1: 8mbit, bank2: 8mbit) temperature grade: blank = commercial i = industrial package: a = 101-ball bga b = 73-ball bga f = 69-ball bga speed : 8570 = 85ns flash, 70ns sram 7070 = 70ns flash, 70ns sram 8585 = 85ns flash, 85ns sram 7085 = 70ns flash, 85ns sram sram density (mbit) sram label issi prefix product family: flash/sram mcp voltage : v = 3.0 center voltage sram data bus width: 08, 16, or pc (pin configurable) flash label flash density (mbit)
is71vpcf16 x s04 48 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 06/14/02 ordering information industrial range: -25oc to +85oc sram data boot flash bank flash speed sram speed order part no. bus section organization (ns) (ns) package is71vpcf16hs04-8585fi 8/16 top 0.5mb, 15.5mb 85 85 69-ball bga is71vpcf16js04-8585fi 8/16 top 2mb, 14mb 85 85 69-ball bga is71vpcf16ks04-8585fi 8/16 top 4mb, 12mb 85 85 69-ball bga is71vpcf16ls04-8585fi 8/16 top 8mb, 8mb 85 85 69-ball bga is71vpcf16ms04-8585fi 8/16 bottom 0.5mb, 15.5mb 85 85 69-ball bga is71vpcf16ns04-8585fi 8/16 bottom 2mb, 14mb 85 85 69-ball bga IS71VPCF16PS04-8585FI 8/16 bottom 4mb, 12mb 85 85 69-ball bga is71vpcf16qs04-8585fi 8/16 bottom 8mb, 8mb 85 85 69-ball bga

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