128k x 16 static ram cy62136v mobl? cy62136v18 mobl2? cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 january 20, 2000 features low voltage range: ? cy62136v18: 1.65v ? 1.95v ? cy62136v: 2.7v ? 3.6v ultra-low active, standby power easy memory expansion with ce and oe features ttl-compatible inputs and outputs automatic power-down when deselected cmos for optimum speed/power functional description the cy62136v and cy62136v18 are high-performance cmos static rams organized as 131,072 words by 16 bits. this device features advanced circuit design to provide ul- tra-low active current. this is ideal for providing more battery life? (mobl?) in portable applications such as cellular tele- phones. the device also has an automatic power-down fea- ture that significantly reduces power consumption by 99% when addresses are not toggling. the device can also be put into standby mode when deselected (ce high). the in- put/output pins (i/o 0 through i/o 15 ) are placed in a high-im- pedance state when: deselected (ce high), outputs are dis- abled (oe high), bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 16 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip en- able (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete de- scription of read and write modes. the cy62136v and cy62136v18 are available in 48-ball fbga and standard 44-pin tsop type ii (forward pinout) packaging. more battery life and mobl are trademarks of cypress semiconductor corporation. logic block diagram pin configurations we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view 12 13 41 44 43 42 16 15 29 30 v cc a 16 a 15 a 14 a 13 nc a 4 a 3 oe v ss a 5 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe nc a 1 a 0 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 v ss i/o 6 i/o 4 i/o 5 i/o 7 a 6 a 7 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 8 a 9 a 10 a 11 62136v?2 tsop ii (forward) 128k x 16 ram array i/o 0 ?i/o 7 row decoder a 9 a 7 a 6 a 3 a 0 column decoder a 11 a 12 a 13 a 14 a 15 1024 x 2048 sense amps data in drivers oe a 2 a 1 i/o 8 ?i/o 15 ce we ble bhe a 10 62136v?1 a 16 a 12
2 cy62136v mobl ? cy62136v18 mobl2 ? maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage to ground potential ..................? 0.5v to +4.6v dc voltage applied to outputs in high z state [1] ....................................... ? 0.5v to v cc + 0.5v dc input voltage [1] .................................... ? 0.5v to v cc + 0.5v output current into outputs (low) ............................. 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma notes: 1. v il (min) = ? 2.0v for pulse durations less than 20 ns. 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc typ, t a = 25 c. pin configuration (continued) we v cc a 11 a 10 nc a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe nc nc a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 62136v ? 3 3 26 5 4 1 d e b a c f g h fbga a 16 top view operating range device range ambient temperature v cc cy62136v18 industrial ? 40 c to +85 c 1.65v to 1.95v cy62136v industrial ? 40 c to +85 c 2.7v to 3.6v product portfolio product v cc range speed power dissipation (industrial) operating (i cc ) standby (i sb2 ) v cc(min) v cc(typ) [2] v cc(max) typ. [2] maximum typ. [2] maximum cy62136v 2.7v 3.0v 3.6v 70 ns 7 ma 15 ma 1 a 15 a cy62136v18 1.65 1.80 1.95 70 ns 3 ma 7 ma 1 a 15 shaded areas contain preliminary information.
3 cy62136v mobl ? cy62136v18 mobl2 ? electrical characteristics over the operating range cy62136v parameter description test conditions min. typ. [2] max. unit v oh output high voltage i oh = ? 1.0 ma v cc = 2.7v 2.4 v v ol output low voltage i ol = 2.1 ma v cc = 2.7v 0.4 v v ih input high voltage v cc = 3.6v 2.2 v cc + 0.5v v v il input low voltage v cc = 2.7v ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 1 + 1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ? 1 +1 +1 a i cc v cc operating supply current i out = 0 ma, f = f max = 1/t rc, cmos levels v cc = 3.6v 7 15 ma i out = 0 ma, f = 1 mhz, cmos levels 1 2 ma i sb1 automatic ce power-down current ? cmos inputs ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f = f max 100 a i sb2 automatic ce power-down current ? cmos inputs ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v, f = 0 v cc = 3.6v ll 1 15 a cy62136v18 parameter description test conditions min. typ. [2] max. unit v oh output high voltage i oh = ? 0.1 ma v cc = 1.65v 1.5 v v ol output low voltage i ol = 0.1 ma v cc = 1.65v 0.2 v v ih input high voltage v cc = 1.95v 1.4 v cc + 0.3v v v il input low voltage v cc = 1.65v ? 0.5 0.4 v i ix input load current gnd < v i < v cc ? 1+ 1+1a i oz output leakage current gnd < v o < v cc , output disabled ? 1+1 +1a i cc v cc operating supply current i out = 0 ma, f = f max = 1/t rc, cmos levels v cc = 1.95v 3 7 ma i out = 0 ma, f = 1 mhz, cmos levels 12ma i sb1 automatic ce power-down current ? cmos inputs ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f = f max 100 a i sb2 automatic ce power-down current ? cmos inputs ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v, f = 0 v cc = 1.95v ll 1 15 a capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 6 pf c out output capacitance 8 pf note: 3. tested initially and after any design or process changes that may affect these parameters.
4 cy62136v mobl ? cy62136v18 mobl2 ? notes: 4. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. 5. test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to v cc typ., and output loading of the specified i ol /i oh and 30 pf load capacitance. ac test loads and waveforms v cc typ v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% <5ns <5 ns output v equivalent to: th venin equivalent all input pulses 62136v ? 4 62136v ? 5 rth r1 parameters 3.0v 1.8v unit r1 1105 15294 ohms r2 1550 11300 ohms r th 645 6500 ohms v th 1.75v 0.85v volts shaded areas contain preliminary information. data retention characteristics (over the operating range) parameter description conditions [5] min. typ. [2] max. unit v dr v cc for data retention (cy62136v18) 1.0 1.95 v v dr v cc for data retention (cy62136v) 1.0 3.6 v i ccdr data retention current v cc = 1.0v ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v no input may exceed v cc +0.3v ll 0.1 5 a t cdr [3] chip deselect to data retention time 0 ns t r [4] operation recovery time 100 s data retention waveform 62136v ? 6 v cc(min.) v cc(min.) t cdr v dr > 1.0 v data retention mode t r ce v cc
5 cy62136v mobl ? cy62136v18 mobl2 ? switching characteristics over the operating range [5] 70 ns parameter description min. max. unit read cycle t rc read cycle time 70 ns t aa address to data valid 70 ns t oha data hold from address change 10 ns t ace ce low to data valid 70 ns t doe oe low to data valid 35 ns t lzoe oe low to low z [6] 5 ns t hzoe oe high to high z [6, 7] 25 ns t lzce ce low to low z [6] 10 ns t hzce ce high to high z [6, 7] 25 ns t pu ce low to power-up 0 ns t pd ce high to power-down 70 ns t dbe ble / bhe low to data valid 35 ns t lzbe ble / bhe low to low z [6, 7] 5 ns t hzbe ble / bhe high to high z [8] 25 ns write cycle [8, 9] t wc write cycle time 70 ns t sce ce low to write end 60 ns t aw address set-up to write end 60 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 50 ns t bw ble / bhe low to write end 60 ns t sd data set-up to write end 30 ns t hd data hold from write end 0 ns t hzwe we low to high z [6, 7] 25 ns t lzwe we high to low z [6] 10 ns switching waveforms notes: 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. t hzoe , t hzce , and t hzwe are specified with c l = 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 8. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal that termina tes the write. 9. the minimum write cycle time for write cycle #3 (we controlled, oe low) is the sum of t hzwe and t sd . 10. device is continuously selected. oe , ce = v il . 11. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha 62136v-7 read cycle no. 1 [10, 11]
6 cy62136v mobl ? cy62136v18 mobl2 ? notes: 12. address valid prior to or coincident with ce transition low. 13. data i/o is high impedance if oe = v ih . 14. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 15. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) 62136v-8 read cycle no. 2 [11, 12] 50% 50% data valid t rc t ace t dbe t lzbe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current t hzbe bhe /ble t doe t lzoe t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe 62146v ? 9 data in valid note write cycle no. 1 (we controlled) [8, 13, 14] 15 bhe /ble t bw
7 cy62136v mobl ? cy62136v18 mobl2 ? switching waveforms (continued) 62136v-10 write cycle no. 2 (ce controlled) [8, 13, 14] t wc t aw t sa t ha t hd t sd t sce we data i/o address ce data in valid bhe /ble t bw t pwe 62136v ? 11 write cycle no. 3 (we controlled, oe low) [9, 14] data i/o address t hd t sd t lzwe t sa t ha t aw t wc ce we t hzwe data in valid note 15 bhe /ble t bw
8 cy62136v mobl ? cy62136v18 mobl2 ? typical dc and ac characteristics ? 55 25 105 2.5 2.0 1.5 current vs. ambient temperature ambient temperature ( c) 1.0 0.5 0.0 ? 0.5 i sb 3.0 standby v cc =v cc typ. v in =v cc typ. i sb2 a 1.50 1.00 0.50 1 15 normalized cycle frequency (mhz) normalized i cc vs. cycle time 0.10 v cc =3.6v t a =25 c 10 5 1.2 1.4 1.0 0.6 0.4 0.2 1.0 1.9 2.8 3.7 supply voltage (v) normalized standby current vs. supply voltage 0.0 0.8 normalized i sb i sb2 v in =v cc typ. t a =25 c 1.2 1.4 1.0 0.6 0.4 0.2 1.7 2.2 2.7 3.2 3.7 supply voltage (v) normalized supply current vs. supply voltage 0.0 0.8 normalized i cc i cc v in =v cc typ. t a =25 c i cc truth table ce we oe bhe ble inputs/outputs mode power h x x x x high z deselect/power-down standby (i sb ) l h l l l data out (i/o o ? i/o 15 ) read active (i cc ) l h l h l data out (i/o o ? i/o 7 ); i/o 8 ? i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ? i/o 15 ); i/o 0 ? i/o 7 in high z read active (i cc ) l h h l l high z deselect/output disabled active (i cc ) l h h h l high z deselect/output disabled active (i cc ) l h h l h high z deselect/output disabled active (i cc ) l l x l l data in (i/o o ? i/o 15 ) write active (i cc ) l l x h l data in (i/o o ? i/o 7 ); i/o 8 ? i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ? i/o 15 ); i/o 0 ? i/o 7 in high z write active (i cc )
9 cy62136v mobl ? cy62136v18 mobl2 ? shaded areas contain preliminary information. document #: 38 ? 00728 ? *b ordering information speed (ns) ordering code package name package type operating range 70 cy62136vll-70zi z44 44-pin tsop ii industrial cy62136vll-70bai ba48 48-ball fine pitch bga CY62136V18LL-70BAI ba48 48-ball fine pitch bga package diagrams 48-ball (7.00 mm x 7.00 mm) fbga ba48 51-85096-a
cy62136v mobl ? cy62136v18 mobl2 ? ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 44-pin tsop ii z44 51-85087-a
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