ddr2-400, 533 single rank, x8 registered sdram dimms ddr2_rdimm_1 rank_x8_spec rev. 1.0 - december, 04 wintec industries, inc., reserves the right to cha nge datasheets and/or products without any notice. ? 2004 wintec industries, inc. 1 256mb - w1d32m72r8 512mb - w1d64m72r8 1gb - w1d128m72r8 2gb - w1d256m72r8 (preliminary*) figure 1: available layouts layout a: 1.181" layout b: 1.0" front view of double-sided dimm (see detail physical dimensions at the back) features: ? 240-pin registered ecc ddr2 sdram dual-in- line memory module for ddr2-400 and ddr2-533 ? jedec standard vdd=1.8v (+/- 0.1v) power supply ? one rank 256mb, 512mb, 1gb, and 2gb ? modules are built with 18 x8 ddr2 sdram devices in a 60-ball fbga package ? ecc error detection and correction ? programmable cas latency of 3 and 4; burst length of 4 and 8 ? auto refresh and self refresh mode ? ocd (off-chip driver impedance adjustment) and odt (on-die termination) ? spd (serial presence detect) with eeprom ? all input/output are sstl_18 compatible ? all contacts are gold plated ? one clock delay for register speed grades: speed grade -5 -3.75 units module speed grade pc2-3200 pc2-4200 speed @ cl3 400 - mhz speed @ cl4 400 533 mhz speed @ cl5 - 533 mhz note: see product ordering for full naming guide description: the following specification covers the w1d32m72r8, w1d64m72r8, w1d128m72r8, and w1d256m72r8 family of single-rank registered ecc ddr2 modules using x8 fbga sdrams. please reference figure 1 for available layout configurations and the product ordering guide on the final page of this specification for available options including speed grade and silicon manufacturer. address summary table: 256mb 512mb 1gb 2gb module configuration 32m x 72 64m x 72 128m x 72 256m x 72 refresh 8k 8k 8k 8k device configuration 32m x 8 (9 components) 64m x 8 (9 components) 128m x 8 (9 components) 256m x 8 (9 components) row addressing a0-a13 a0-a13 a0-a14 a0-a14 column addressing a0-a9 a0-a9 a0-a9 a0-a9 module rank 1 1 1 1 *specifications are for reference purposes only and are subject to change by wintec without notice.
ddr2-400, 533 single rank, x8 registered sdram dimms ddr2_rdimm_1 rank_x8_spec rev. 1.0 - december, 04 wintec industries, inc., reserves the right to cha nge datasheets and/or products without any notice. ? 2004 wintec industries, inc. 2 pin configuration: pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 vref 31 dq19 61 a4 91 vss 121 vss 151 vss 181 vddq 211 dm5/dqs14 2 vss 32 vss 62 vddq 92 dqs5# 122 dq4 152 dq28 182 a3 212 nc/dqs14# 3 dq0 33 dq24 63 a2 93 dqs5 123 dq5 153 dq29 183 a1 213 vss 4 dq1 34 dq25 64 vdd 94 vss 124 vss 154 vss 184 vdd 214 dq46 5 vss 35 vss key 95 dq42 125 dm0/dqs9 155 dm3/dqs12 key 215 dq47 6 dqs0# 36 dqs3# 65 vss 96 dq43 126 nc/dqs9# 156 nc/dqs12# 185 ck0 216 vss 7 dqs0 37 dqs3 66 vss 97 vss 127 vss 157 vss 186 ck0# 217 dq52 8 vss 38 vss 67 vdd 98 dq48 128 dq6 158 dq30 187 vdd 218 dq53 9 dq2 39 dq26 68 nc 99 dq49 129 dq7 159 dq31 188 a0 219 vss 10 dq3 40 dq27 69 vdd 100 vss 130 vss 160 vss 189 vdd 220 rfu 11 vss 41 vss 70 a10/ap 101 sa2 131 dq12 161 cb4 190 ba1 221 rfu 12 dq8 42 cb0 71 ba0 102 nc,test 1 132 dq13 162 cb5 191 vddq 222 vss 13 dq9 43 cb1 72 vddq 103 vss 133 vss 163 vss 192 ras# 223 dm6/dqs15 14 vss 44 vss 73 we# 104 dqs6# 134 dm1/dqs10 164 dm8/dqs17 193 s0# 224 nc/dqs15# 15 dqs1# 45 dqs8# 74 cas# 105 dqs6 135 nc/dqs10# 165 nc/dqs17# 194 vddq 225 vss 16 dqs1 46 dqs8 75 vddq 106 vss 136 vss 166 vss 195 odt0 226 dq54 17 vss 47 vss 76 s1# 107 dq50 137 rfu 167 cb6 196 a13 227 dq55 18 reset# 48 cb2 77 odt1 108 dq51 138 rfu 168 cb7 197 vdd 228 vss 19 nc 49 cb3 78 vddq 109 vss 139 vss 169 vss 198 vss 229 dq60 20 vss 50 vss 79 vss 110 dq56 140 dq14 170 vddq 199 dq36 230 dq61 21 dq10 51 vddq 80 dq32 111 dq57 141 dq15 171 cke1 200 dq37 231 vss 22 dq11 52 cke0 81 dq33 112 vss 142 vss 172 vdd 201 vss 232 dm7/dqs16 23 vss 53 vdd 82 vss 113 dqs7# 143 dq20 173 a15 202 dm4/dqs13 233 nc/dqs16# 24 dq16 54 a16,ba2 83 dqs4# 114 dqs7 144 dq21 174 a14 203 nc/dqs13# 234 vss 25 dq17 55 nc 84 dqs4 115 vss 145 vss 175 vddq 204 vss 235 dq62 26 vss 56 vddq 85 vss 116 dq58 146 dm2/dqs11 176 a12 205 dq38 236 dq63 27 dqs2# 57 a11 86 dq34 117 dq59 147 nc/dqs11# 177 a9 206 dq39 237 vss 28 dqs2 58 a7 87 dq35 118 vss 148 vss 178 vdd 207 vss 238 vddspd 29 vss 59 vdd 88 vss 119 sda 149 dq22 179 a8 208 dq44 239 sa0 30 dq18 60 a5 89 dq40 120 scl 150 dq23 180 a6 209 dq45 240 sa1 90 dq41 210 vss nc - no connect, rfu - reserved for future use 1. the test pin (pin 102) is reserved for bus anal ysis and is not connected on normal memory modules 2. cke1 and s1# pin are used for dual-rank registered dimm 3. a13 (pin 196) is for 512mb and above dimm. pin locations: front view pin 1 120 back view pin 240 121 64 65 185 184 240-pin dimm
ddr2-400, 533 single rank, x8 registered sdram dimms ddr2_rdimm_1 rank_x8_spec rev. 1.0 - december, 04 wintec industries, inc., reserves the right to cha nge datasheets and/or products without any notice. ? 2004 wintec industries, inc. 3 functional block diagram: single rank 32m x 72 (256mb), 64m x 72 (512mb), 128m x 72 (1gb), and 256m x 72 (2gb) ddr2 registered sdram dimm (x8 organization) note: 1. *) cs0# connects to dcs# of register 1 and csr# of register 2; csr# of register 1 and dcs# of register 2 connects to vdd 2. dq/dm/dqs, address and control resistor values are 22 ohms. a0 a1 a2 scl sda serial pd sa0 sa2 sa1 dq[0:7] rcs0# dqs0# dm0/dqs9 8 dqs0 dqs1# dm1/dqs10 dqs1 dqs2# dm2/dqs11 dqs2 dqs3# dm3/dqs12 dqs3 dqs8# dm8/dqs17 dqs8 dqs4# dm4/dqs13 dqs4 dqs5# dm5/dqs14 dqs5 dqs6# dm6/dqs15 dqs6 dqs7# dm7/dqs16 dqs7 dqs9# u0 dm/ cs# dqs# dqs rdqs nu/ rdqs# dq[8:15] 8 dqs10# u1 dm/ cs# dqs# dqs rdqs nu/ rdqs# dq[16:23] 8 dqs11# u2 dm/ cs# dqs# dqs rdqs nu/ rdqs# dq[24:31] 8 dqs12# u3 dm/ cs# dqs# dqs rdqs nu/ rdqs# cb[0:7] 8 dqs17# u8 dm/ cs# dqs# dqs rdqs nu/ rdqs# dq[32:39] 8 dqs13# u4 dm/ cs# dqs# dqs rdqs nu/ rdqs# dq[40:47] 8 dqs14# u5 dm/ cs# dqs# dqs rdqs nu/ rdqs# dq[48:55] 8 dqs15# u6 dm/ cs# dqs# dqs rdqs nu/ rdqs# dq[56:63] 8 dqs16# u7 dm/ cs# dqs# dqs rdqs nu/ rdqs# ck0 ck to u0 - u8 ck# to u0 - u8 ck to all registers ck# to all registers ck0# reset# p l l v ddspd v dd /v ddq v ref vss to spd to u0 - u8 to u0 - u8 to u0 - u8 ba0-ba1 a0-a13 ras# cas# we# cke0 odt0 cs0#* reset# rba0-rba1 -> ba0-ba1 to u0 - u8 ra0-ra13 -> a0-a13 to u0 - u8 rras# -> ras# to u0 - u8 rcas# -> cas# to u0 - u8 rwe# -> we# to u0 - u8 rcke0 -> cke0 to u0 - u8 rodt0 -> odt0 to u0 - u8 rs0# -> cs0# to u0 - u8 r e g i s t e r rst#
ddr2-400, 533 single rank, x8 registered sdram dimms ddr2_rdimm_1 rank_x8_spec rev. 1.0 - december, 04 wintec industries, inc., reserves the right to cha nge datasheets and/or products without any notice. ? 2004 wintec industries, inc. 4 absolute maximum ratings: exposure to stresses greater than these absolute maxi mum rating conditions for extended periods may affect reliability of the module. symbol parameter min max units v dd v dd supply voltage relative to v ss -1.0 2.3 v v dd q v dd q supply voltage relative to v ss -0.5 2.3 v v dd l v dd l supply voltage relative to v ss -0.5 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature (t case ) -55 +100 c t opr operating temperature (ambient) 0 +55 c i il input leakage current; any input 0v a i ol output leakage current; 0v v out a dc operating conditions: parameter symbol min nom max units notes supply voltage v dd 1.7 1.8 1.9 v 1 v dd l supply voltage v dd l 1.7 1.8 1.9 v 4 i/o supply voltage v dd q 1.7 1.8 1.9 v 4 i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51 x v dd q v 2 i/o termination voltage (system) v tt v ref - 40 v ref v ref + 40 mv 3 note: 1. v dd and v dd q must keep track of each other. v dd q cannot exceed the value of v dd 2. v ref is expected to equal v dd q/2 of the transmitting device and to track variations in the dc level of the same 3. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref 4. v dd q must tracks v dd ; and v dd l tracks v dd input/output capacitance: v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v ref = v ss , f =100mhz, 0c ddr2-400, 533 single rank, x8 registered sdram dimms ddr2_rdimm_1 rank_x8_spec rev. 1.0 - december, 04 wintec industries, inc., reserves the right to cha nge datasheets and/or products without any notice. ? 2004 wintec industries, inc. 5 idd specifications and conditions (256mb - 32mx8, 9 components): symbol parameter dram ic manufacturer* -5 ddr2-400 -3.75 ddr2-533 units mt 675 720 ma inf n/a n/a ma idd0 operating current sam 1265 1420 ma mt 765 810 ma inf n/a n/a ma idd1 operating current sam 1330 1540 ma mt 32 45 ma inf n/a n/a ma idd2p precharge power-down current sam 495 535 ma mt 189 225 ma inf n/a n/a ma idd2q precharge quiet standby current sam 665 715 ma mt 225 270 ma inf n/a n/a ma idd2n precharge standby current sam 670 730 ma mt 135 171 ma inf n/a n/a ma active power-down standby current mrs(12) = 0 sam 720 750 ma mt 63 81 ma inf n/a n/a ma idd3p active power-down standby current mrs(12) = 1 sam 365 375 ma mt 288 351 ma inf n/a n/a ma idd3n active standby current sam 1065 1180 ma mt 1125 1440 ma inf n/a n/a ma idd4w operating current burst write sam 1635 2115 ma mt 990 1260 ma inf n/a n/a ma idd4r operating current burst read sam 1520 1840 ma mt 1485 1530 ma inf n/a n/a ma idd5b burst auto-refresh current sam 1900 2005 ma mt 27 27 ma inf n/a n/a ma idd6 self refresh current sam 485 555 ma mt 2070 2160 ma inf n/a n/a ma idd7 operating current sam 2885 2975 ma note: dram ic manufacturer* - mt = micron, inf = infineon, sam=samsung
ddr2-400, 533 single rank, x8 registered sdram dimms ddr2_rdimm_1 rank_x8_spec rev. 1.0 - december, 04 wintec industries, inc., reserves the right to cha nge datasheets and/or products without any notice. ? 2004 wintec industries, inc. 6 idd specifications and conditions (512mb - 64mx8, 9 components): symbol parameter dram ic manufacturer* -5 ddr2-400 -3.75 ddr2-533 units mt tbd tbd ma inf 745 918 ma idd0 operating current sam 1265 1420 ma mt tbd tbd ma inf 790 1008 ma idd1 operating current sam 1330 1540 ma mt tbd tbd ma inf 286 369 ma idd2p precharge power-down current sam 495 535 ma mt tbd tbd ma inf 475 603 ma idd2q precharge quiet standby current sam 665 715 ma mt tbd tbd ma inf 538 639 ma idd2n precharge standby current sam 670 730 ma mt tbd tbd ma inf 367 477 ma active power-down standby current mrs(12) = 0 sam 720 750 ma mt tbd tbd ma inf 295 378 ma idd3p active power-down standby current mrs(12) = 1 sam 365 375 ma mt tbd tbd ma inf 565 693 ma idd3n active standby current sam 1065 1180 ma mt tbd tbd ma inf 925 1188 ma idd4w operating current burst write sam 1725 2340 ma mt tbd tbd ma inf 880 1143 ma idd4r operating current burst read sam 1655 2020 ma mt tbd tbd ma inf 1330 1503 ma idd5b burst auto-refresh current sam 2125 2275 ma mt tbd tbd ma inf 36 36 ma idd6 self refresh current sam 490 560 ma mt tbd tbd ma inf 1420 1593 ma idd7 operating current sam 3020 3155 ma note: dram ic manufacturer* - mt = micron, inf = infineon, sam=samsung
ddr2-400, 533 single rank, x8 registered sdram dimms ddr2_rdimm_1 rank_x8_spec rev. 1.0 - december, 04 wintec industries, inc., reserves the right to cha nge datasheets and/or products without any notice. ? 2004 wintec industries, inc. 7 electrical characterist ics and ac timings: v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v ref = v ss , f =100mhz, 0c ddr2-400, 533 single rank, x8 registered sdram dimms ddr2_rdimm_1 rank_x8_spec rev. 1.0 - december, 04 wintec industries, inc., reserves the right to cha nge datasheets and/or products without any notice. ? 2004 wintec industries, inc. 8 v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v ref = v ss , f =100mhz, 0c ddr2-400, 533 single rank, x8 registered sdram dimms ddr2_rdimm_1 rank_x8_spec rev. 1.0 - december, 04 wintec industries, inc., reserves the right to cha nge datasheets and/or products without any notice. ? 2004 wintec industries, inc. 9 physical dimensions ? layout a: note: 1. dimensions are in inches/(mm) 2. outline dimensions and tolerances are in accordance with the jedec standard (mo-237) layout a: ddr2 registered dimm raw card a one physical rank, 9 components x8 organised front back 5.171/(131.35) 5.250/(133.350.15) 5.014/(127.35) 1.181/(30.0) 0.10/(2.54) 0.118/(3.0) 2.55/(64.77) 1.95/(49.5) 0.25/(6.35) 0.039/ (1.0) 0.05/ (1.27) 0.1575/(4.0) pin 121 240 pin 1 120 register pll 184 185 64 65 0.0500.004/ (1.270.1) side 0.106/(2.7) max
ddr2-400, 533 single rank, x8 registered sdram dimms ddr2_rdimm_1 rank_x8_spec rev. 1.0 - december, 04 wintec industries, inc., reserves the right to cha nge datasheets and/or products without any notice. ? 2004 wintec industries, inc. 10 physical dimensions ? layout b: note: 1. dimensions are in inches/(mm) 2. outline dimensions and tolerances are in accordance with the jedec standard (mo-237) layout b: 1" height ddr2 registered dimm raw card a one physical rank, 9 components x8 organised front back 5.171/(131.35) 5.250/(133.350.15) 5.014/(127.35) 1.0/(25.4) 0.10/(2.54) 0.118/(3.0) 2.55/(64.77) 1.95/(49.5) 0.25/(6.35) 0.039/ (1.0) 0.05/ (1.27) 0.1575/(4.0) pin 121 240 pin 1 120 register pll 184 185 64 65 0.0500.004/ (1.270.1) side 0.106/(2.7) max
ddr2-400, 533 single rank, x8 registered sdram dimms ddr2_rdimm_1 rank_x8_spec rev. 1.0 - december, 04 wintec industries, inc., reserves the right to cha nge datasheets and/or products without any notice. ? 2004 wintec industries, inc. 11 product ordering guide: 256mb - w1d32m72r8 512mb - w1d64m72r8 1gb - w1d128m72r8 2gb - w1d256m72r8 (preliminary*) contact us: wintec industries oem & industrial solutions 4280 technology drive fremont, ca 94538 ph: 510-360-6246 fx: 510-770-9338 oemsales@wintecind.com http://www.wintecind.com/oem dram ic vendor psamsung q infineon hmicron fpromos/vitelic jnanya w 1 d 32 m 72 r 8 a - 5a e - p a 1 pcb layout see front page/module dimension for details component speed grade data rate mo dule bandwidth 5a 400-333 pc2-3200 3.75a 533-444 pc2-4200 modul e s pe e d options e industrial t emp lcustom labeling plow power r reduced sp d p rogram die rev. control aa die bb die ddr ii product ordering guide pcb rev. control blank initial release 1 1st revision 2 2nd revision
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