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the mark shows major revised points. the revised points can be easily searched by copying an "" in the pdf file and specifying it in the "find what:" field. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd44325084, 44325094, 44325184, 44325364 36m-bit qdr tm ii sram 4-word burst operation document no. m16784ej4v0ds00 (4th edition) date published march 2007 ns cp(n) printed in japan data sheet 2003 description the pd44325084 is a 4,194,304-word by 8-bit, the pd44325094 is a 4,194,304-word by 9-bit, the pd44325184 is a 2,097,152-word by 18-bit and the pd44325364 is a 1,048,576-word by 36-bit synchronous quad data rate static ram fabricated with advanced cmos technology using full cmos six-transistor memory cell. the pd44325084, pd44325094, pd44325184 and pd44325364 integrate unique synchronous peripheral circuitry and a burst counter. all input registers controlled by an input clock pair (k and k#) are latched on the positive edge of k and k#. these products are suitable for application which require sync hronous operation, high speed, low voltage, high density and wide bit configuration. these products are packaged in 165-pin plastic bga. features ? 1.8 0.1 v power supply ? 165-pin plastic bga (13 x 15) ? hstl interface ? pll circuitry for wide output data valid window and future frequency scaling ? separate independent read and write data ports with concurrent transactions ? 100% bus utilization ddr read and write operation ? four-tick burst for reduced address frequency ? two input clocks (k and k#) for precise ddr timing at clock rising edges only ? two output clocks (c and c#) for precise flight time and clock skew matching-clock and data delivered together to receiving device ? internally self-timed write control ? clock-stop capability. normal operation is restor ed in 1,024 cycles after clock is resumed. ? user programmable impedance output ? fast clock cycle time : 3.7 ns (270 mhz), 4.0 ns (250 mhz), 5.0 ns (200 mhz) ? simple control logic for easy depth expansion ? jtag boundary scan ? operating ambient temperature: commercial t a = 0 to +70c (-e37, -e40, -e50) industrial t a = ?40 to +85c (-e40y, -e50y)
2 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 ordering information (1) operating ambient temperature t a = 0 to +70c part number cycle clock organization package operating time frequency (word x bit) ambient ns mhz temperature pd44325084f5-e37-eq2 3.7 270 4m x 8-bit 165-pin plastic commercial pd44325084f5-e40-eq2 4.0 250 bga (13 x 15) (t a = 0 to +70c) pd44325084f5-e50-eq2 5.0 200 pd44325094f5-e37-eq2 3.7 270 4m x 9-bit pd44325094f5-e40-eq2 4.0 250 pd44325094f5-e50-eq2 5.0 200 pd44325184f5-e37-eq2 3.7 270 2m x 18-bit pd44325184f5-e40-eq2 4.0 250 pd44325184f5-e50-eq2 5.0 200 pd44325364f5-e37-eq2 3.7 270 1m x 36-bit pd44325364f5-e40-eq2 4.0 250 pd44325364f5-e50-eq2 5.0 200 pd44325084f5-e37-eq2-a 3.7 270 4m x 8-bit 165-pin plastic pd44325084f5-e40-eq2-a 4.0 250 bga (13 x 15) pd44325084f5-e50-eq2-a 5.0 200 pd44325094f5-e37-eq2-a 3.7 270 4m x 9-bit lead-free pd44325094f5-e40-eq2-a 4.0 250 pd44325094f5-e50-eq2-a 5.0 200 pd44325184f5-e37-eq2-a 3.7 270 2m x 18-bit pd44325184f5-e40-eq2-a 4.0 250 pd44325184f5-e50-eq2-a 5.0 200 pd44325364f5-e37-eq2-a 3.7 270 1m x 36-bit pd44325364f5-e40-eq2-a 4.0 250 pd44325364f5-e50-eq2-a 5.0 200 remarks 1. qdr consortium standard package size is 13 x 15 and 15 x 17. the footprint is commonly used. 2. products with -a at the end of t he part number are lead-free products.
3 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 (2) operating ambient temperature t a = ?40 to +85c part number cycle clock organization package operating time frequency (word x bit) ambient ns mhz temperature pd44325084f5-e40y-eq2 4.0 250 4m x 8-bit 165-pin plastic industrial pd44325084f5-e50y-eq2 5.0 200 bga (13 x 15) (t a = ?40 to +85c) pd44325094f5-e40y-eq2 4.0 250 4m x 9-bit pd44325094f5-e50y-eq2 5.0 200 pd44325184f5-e40y-eq2 4.0 250 2m x 18-bit pd44325184f5-e50y-eq2 5.0 200 pd44325084f5-e40y-eq2-a 4.0 250 4m x 8-bit 165-pin plastic pd44325084f5-e50y-eq2-a 5.0 200 bga (13 x 15) pd44325094f5-e40y-eq2-a 4.0 250 4m x 9-bit pd44325094f5-e50y-eq2-a 5.0 200 lead-free pd44325184f5-e40y-eq2-a 4.0 250 2m x 18-bit pd44325184f5-e50y-eq2-a 5.0 200 remarks 1. qdr consortium standard package size is 13 x 15 and 15 x 17. the footprint is commonly used. 2. products with -a at the end of t he part number are lead-free products.
4 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 pin configurations 165-pin plastic bga (13 x 15) (top view) [ pd44325084] 4m x 8-bit 1 2 3 4 5 6 7 8 9 10 11 a cq# v ss a w# nw1# k# nc r# a a cq b nc nc nc a nc k nw0# a nc nc q3 c nc nc nc v ss a nc a v ss nc nc d3 d nc d4 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q4 v dd q v ss v ss v ss v dd q nc d2 q2 f nc nc nc v dd q v dd v ss v dd v dd q nc nc nc g nc d5 q5 v dd q v dd v ss v dd v dd q nc nc nc h dll# v ref v dd q v dd q v dd v ss v dd v dd q v dd q v ref zq j nc nc nc v dd q v dd v ss v dd v dd q nc q1 d1 k nc nc nc v dd q v dd v ss v dd v dd q nc nc nc l nc q6 d6 v dd q v ss v ss v ss v dd q nc nc q0 m nc nc nc v ss v ss v ss v ss v ss nc nc d0 n nc d7 nc v ss a a a v ss nc nc nc p nc nc q7 a a c a a nc nc nc r tdo tck a a a c# a a a tms tdi a : address inputs tms : ieee 1149.1 test input d0 to d7 : data inputs tdi : ieee 1149.1 test input q0 to q7 : data outputs tck : ieee 1149.1 clock input r# : read input tdo : ieee 1149.1 test output w# : write input v ref : hstl input reference input nw0#, nw1# : nibble write data select v dd : power supply k, k# : input clock v dd q : power supply c, c# : output clock v ss : ground cq, cq# : echo clock nc : no connection zq : output impedance matching dll# : dll/pll disable remarks 1. # indicates active low signal. 2. refer to package drawing for the index mark. 3 . 2a and 7a are expansion addresses: 2a for 72mb and 7a for 144mb. 2a of this product can also be used as nc.
5 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 165-pin plastic bga (13 x 15) (top view) [ pd44325094] 4m x 9-bit 1 2 3 4 5 6 7 8 9 10 11 a cq# v ss a w# nc k# nc r# a a cq b nc nc nc a nc k bw0# a nc nc q4 c nc nc nc v ss a nc a v ss nc nc d4 d nc d5 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q5 v dd q v ss v ss v ss v dd q nc d3 q3 f nc nc nc v dd q v dd v ss v dd v dd q nc nc nc g nc d6 q6 v dd q v dd v ss v dd v dd q nc nc nc h dll# v ref v dd q v dd q v dd v ss v dd v dd q v dd q v ref zq j nc nc nc v dd q v dd v ss v dd v dd q nc q2 d2 k nc nc nc v dd q v dd v ss v dd v dd q nc nc nc l nc q7 d7 v dd q v ss v ss v ss v dd q nc nc q1 m nc nc nc v ss v ss v ss v ss v ss nc nc d1 n nc d8 nc v ss a a a v ss nc nc nc p nc nc q8 a a c a a nc d0 q0 r tdo tck a a a c# a a a tms tdi a : address inputs tms : ieee 1149.1 test input d0 to d8 : data inputs tdi : ieee 1149.1 test input q0 to q8 : data outputs tck : ieee 1149.1 clock input r# : read input tdo : ieee 1149.1 test output w# : write input v ref : hstl input reference input bw0# : byte write data select v dd : power supply k, k# : input clock v dd q : power supply c, c# : output clock v ss : ground cq, cq# : echo clock nc : no connection zq : output impedance matching dll# : dll/pll disable remarks 1. # indicates active low signal. 2. refer to package drawing for the index mark. 3 . 2a and 7a are expansion addresses: 2a for 72mb and 7a for 144mb. 2a of this product can also be used as nc.
6 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 165-pin plastic bga (13 x 15) (top view) [ pd44325184] 2m x 18-bit 1 2 3 4 5 6 7 8 9 10 11 a cq# v ss a w# bw1# k# nc r# a v ss cq b nc q9 d9 a nc k bw0# a nc nc q8 c nc nc d10 v ss a nc a v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v dd q v ss v ss v ss v dd q nc d6 q6 f nc q12 d12 v dd q v dd v ss v dd v dd q nc nc q5 g nc d13 q13 v dd q v dd v ss v dd v dd q nc nc d5 h dll# v ref v dd q v dd q v dd v ss v dd v dd q v dd q v ref zq j nc nc d14 v dd q v dd v ss v dd v dd q nc q4 d4 k nc nc q14 v dd q v dd v ss v dd v dd q nc d3 q3 l nc q15 d15 v dd q v ss v ss v ss v dd q nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss a a a v ss nc nc d1 p nc nc q17 a a c a a nc d0 q0 r tdo tck a a a c# a a a tms tdi a : address inputs tms : ieee 1149.1 test input d0 to d17 : data inputs tdi : ieee 1149.1 test input q0 to q17 : data outputs tck : ieee 1149.1 clock input r# : read input tdo : ieee 1149.1 test output w# : write input v ref : hstl input reference input bw0#, bw1# : byte write data select v dd : power supply k, k# : input clock v dd q : power supply c, c# : output clock v ss : ground cq, cq# : echo clock nc : no connection zq : output impedance matching dll# : dll/pll disable remarks 1. # indicates active low signal. 2. refer to package drawing for the index mark. 3. 2a and 10a are expansion addresses: 10a for 72mb and 2a for 144mb. 2a and 10a of this product can also be used as nc.
7 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 165-pin plastic bga (13 x 15) (top view) [ pd44325364] 1m x 36-bit 1 2 3 4 5 6 7 8 9 10 11 a cq# v ss nc w# bw2# k# bw1# r# a v ss cq b q27 q18 d18 a bw3# k bw0# a d17 q17 q8 c d27 q28 d19 v ss a nc a v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v dd q v ss v ss v ss v dd q q15 d6 q6 f q30 q21 d21 v dd q v dd v ss v dd v dd q d14 q14 q5 g d30 d22 q22 v dd q v dd v ss v dd v dd q q13 d13 d5 h dll# v ref v dd q v dd q v dd v ss v dd v dd q v dd q v ref zq j d31 q31 d23 v dd q v dd v ss v dd v dd q d12 q4 d4 k q32 d32 q23 v dd q v dd v ss v dd v dd q q12 d3 q3 l q33 q24 d24 v dd q v ss v ss v ss v dd q d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss a a a v ss q10 d9 d1 p q35 d35 q26 a a c a a q9 d0 q0 r tdo tck a a a c# a a a tms tdi a : address inputs tms : ieee 1149.1 test input d0 to d35 : data inputs tdi : ieee 1149.1 test input q0 to q35 : data outputs tck : ieee 1149.1 clock input r# : read input tdo : ieee 1149.1 test output w# : write input v ref : hstl input reference input bw0# to bw3# : byte write data select v dd : power supply k, k# : input clock v dd q : power supply c, c# : output clock v ss : ground cq, cq# : echo clock nc : no connection zq : output impedance matching dll# : dll/pll disable remarks 1. # indicates active low signal. 2. refer to package drawing for the index mark. 3. 3a and 10a are expansion addresses: 3a for 72mb and 10a for 144mb. 2a and 10a of this product can also be used as nc.
8 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 pin identification (1/2) symbol description a synchronous address inputs: these inputs are regist ered and must meet the setup and hold times around the rising edge of k. all transactions operate on a burst of four words (two clock periods of bus activity). these inputs are ignored when device is deselec ted, i.e., nop (r# = w# = high). d0 to dxx synchronous data inputs: input data must m eet setup and hold times around the rising edges of k and k# during write operations. see pin configurations for ball site location of individual signals. x8 device uses d0 to d7. x9 device uses d0 to d8. x18 device uses d0 to d17. x36 device uses d0 to d35. q0 to qxx synchronous data outputs: output data is synchron ized to the respective c and c# or to k and k# rising edges if c and c# are tied high. data is output in synchronization with c and c# (or k and k#), depending on the r# command. see pin configurations for ball site location of individual signals. x8 device uses q0 to q7. x9 device uses q0 to q8. x18 device uses q0 to q17. x36 device uses q0 to q35. r# synchronous read: when low this input causes the address inputs to be registered and a read cycle to be initiated. this input must meet setup and hold times around the rising edge of k. if a read command (r# = low) is input, an input of r# on t he subsequent rising edge of k is ignored. w# synchronous write: when low this input causes the address inputs to be registered and a write cycle to be initiated. this input must meet setup and hold times around the rising edge of k. if a write command (w# = low) is input, an input of w# on t he subsequent rising edge of k is ignored. bwx# nwx# synchronous byte writes (nibble writ es on x8): when low these inputs caus e their respective byte or nibble to be registered and written during write cycles. t hese signals must meet setup and hold times around the rising edges of k and k# for each of the two ri sing edges comprising the write cycle. see pin configurations for signal to data relationships. x8 device uses nw0#, nw1#. x9 device uses bw0#. x18 device uses bw0#, bw1#. x36 device uses bw0# to bw3#. see byte write operation for relation between bwx#, nwx# and dxx. k, k# input clock: this input clock pair registers addre ss and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of k#. k# is ideally 180 degrees out of phase with k. all synchronous inputs must meet setup and hold times around the clock rising edges. c, c# output clock: this clock pair provides a user c ontrolled means of tuning device output data. the rising edge of c# is used as the output timing refe rence for first and third output data. the rising edge of c is used as the output reference for second and fourth output data. ideally , c# is 180 degrees out of phase with c. when use of k and k# as the reference instead of c and c#, then fixed c and c# to high. operation cannot be guaranteed unless c and c# are fixed to high (i.e. toggle of c and c#).
9 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 (2/2) symbol description cq, cq# synchronous echo clock outputs. the rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indicati on. these signals run freely and do not stop when q tristates. if c and c# are stopped (if k and k# are stopped in the single clock mode), cq and cq# will also stop. zq output impedance matching input: this input is us ed to tune the device outputs to the system data bus impedance. q, cq and cq# output impedance are set to 0.2 x rq, where rq is a resistor from this bump to ground. the output impedance can be minimi zed by directly connect zq to v dd q. this pin cannot be connected directly to gnd or left unconnected. the output impedanc e is adjusted every 1,024 cycles upon power-up to account for drifts in supply voltage and temperature. a fter replacement for a resistor, the new output impedance is reset by implementing power-on sequence. dll# dll/pll disable: when debugging the system or boar d, the operation can be performed at a clock frequency slower than tkhkh (max.) without the dll/pll circuit bei ng used, if dll# = low. the ac/dc characteristics cannot be guaranteed. for normal operation, dll# must be high and it can be connected to v dd q through a 10 k or less resistor. tms tdi ieee 1149.1 test inputs: 1.8 v i/o level. these balls ma y be left not connected if the jtag function is not used in the circuit. tck ieee 1149.1 clock input: 1.8 v i/o level. this pin must be tied to v ss if the jtag function is not used in the circuit. tdo ieee 1149.1 test output: 1.8 v i/o level. v ref hstl input reference voltage: nominally v dd q/2. provides a reference voltage for the input buffers. v dd power supply: 1.8 v nominal. see recommended dc operating conditions and dc characteristics for range. v dd q power supply: isolated output buffer supply. nominally 1.5 v. 1.8 v is also permissible. see recommended dc operating conditions and dc characteristics for range. v ss power supply: ground nc no connect: these signals are not connected internally. < r > < r > < r >
10 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 block diagram [ pd44325084] data registry & logic output register w# nw0# nw1# r# k k# k k r# w# k address 20 20 d0 to d7 8 output select output buffer 8 16 16 16 32 16 mux mux address registry & logic 2 20 x 32 memory array write driver sense amps write register q0 to q7 c, c# or k, k# cq, cq# 2 [ pd44325094] data registry & logic output register w# bw0# r# k k# k k r# w# k address 20 20 d0 to d8 9 output select output buffer 9 18 18 18 36 18 mux mux address registry & logic 2 20 x 36 memory array write driver sense amps write register q0 to q8 c, c# or k, k# cq, cq# 2 [ pd44325184] data registry & logic output register w# bw0# bw1# r# k k# k k r# w# k address 19 19 d0 to d17 18 output select output buffer 18 36 36 36 72 36 mux mux address registry & logic 2 19 x 72 memory array write driver sense amps write register q0 to q17 c, c# or k, k# cq, cq# 2
11 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 [ pd44325364] data registry & logic output register w# bw0# bw1# r# k k# k k r# w# k address 18 18 d0 to d35 36 output select output buffer 36 72 72 72 144 72 mux mux address registry & logic 2 18 x 144 memory array write driver sense amps write register q0 to q35 c, c# or k, k# cq, cq# 2 bw2# bw3#
12 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 power-on sequence the following timing charts show the recommended powe r-on sequence, i.e., when starting the clock after v dd /v dd q stable and when starting the clock before v dd /v dd q stable. 1. clock starts after v dd /v dd q stable the clock is supplied from a controller. (a) v dd /v dd q v dd /v dd q stable (< 0.1 v dc per 50 ns) dll# clock start normal operation start clock fix high (or tied to v dd q) 20 ns (min.) 1,024 cycles or more stable clock note note input a stable clock from the start . (b) v dd /v dd q dll# switched to high after clock is stable. unstable clock (level, frequency) v dd /v dd q stable (< 0.1 v dc per 50 ns) clock clock start normal operation start 1,024 cycles or more stable clock (c) v dd /v dd q dll# 30 ns. (min.) clock stop v dd /v dd q stable (< 0.1 v dc per 50 ns) fix high (or tied to v dd q) unstable clock (level, frequency) clock clock start normal operation start 1,024 cycles or more stable clock
13 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 2. clock starts before v dd /v dd q stable the clock is supplied from a clock generator. (a) v dd /v dd q dll# 30 ns. (min.) clock stop v dd /v dd q stable (< 0.1 v dc per 50 ns) fix high (or tied to v dd q) unstable clock (level, frequency) clock clock start normal operation start 1,024 cycles or more stable clock (b) v dd /v dd q dll# clock keep running switched to high after clock is stable. high or low 30 ns (min.) dll# low v dd /v dd q stable (< 0.1 v dc per 50 ns) normal operation start 1,024 cycles or more stable clock unstable clock (level, frequency) clock clock start
14 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 truth table operation clk r# w# d or q write cycle l h h l data in load address, input write data on two input data d a (a+0) d a (a+1) d a (a+2) d a (a+3) consecutive k and k# rising edge input clock k(t+1) k#(t+1) k(t+2) k#(t+2) read cycle l h l x data out load address, read data on two output data q a (a+0) q a (a+1) q a (a+2) q a (a+3) consecutive c and c# rising edge output clock c#(t+1) c(t+2) c#(t+2) c(t+3) nop (no operation) l h h h d = x, q = high-z clock stop stopped x x previous state remarks 1. h : high, l : low, : don?t care, : rising edge. 2. data inputs are registered at k and k# rising edges . data outputs are delivered at c and c# rising edges except if c and c# are high then data out puts are delivered at k and k# rising edges. 3. r# and w# must meet setup/hold times around the rising edge (low to high) of k and are registered at the rising edge of k. 4. this device contains circuitry that ensure th e outputs to be in high impedance during power-up. 5. refer to state diagram and timing diagrams for clarification. 6. it is recommended that k = k# = c = c# when clock is stopped. this is not essential but permits most rapid restart by overcoming transmission line charging symmetrically. 7. if r# was low to initiate the previous cycle, th is signal becomes a don't care for this write operation however it is strongly recommended that this signal is brought high as shown in the truth table. 8. w# during write cycle and r# during read cycle were high on previous k clock rising edge. initiating consecutive read or write operat ions on consecutive k clock risi ng edges is not permitted. the device will ignore the second request.
15 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 byte write operation [ pd44325084] operation k k# nw0# nw1# write d0 to d7 l h ? 0 0 ? l h 0 0 write d0 to d3 l h ? 0 1 ? l h 0 1 write d4 to d7 l h ? 1 0 ? l h 1 0 write nothing l h ? 1 1 ? l h 1 1 remarks 1. h : high, l : low, : rising edge. 2. assumes a write cycle was initiated. nw0# and nw1# can be altered for any portion of the burst write operation provided that the set up and hold requirements are satisfied. [ pd44325094] operation k k# bw0# write d0 to d8 l h ? 0 ? l h 0 write nothing l h ? 1 ? l h 1 remarks 1. h : high, l : low, : rising edge. 2. assumes a write cycle was initiated. bw0# can be altered for any portion of the burst write operation provided that t he setup and hold requirements are satisfied. [ pd44325184] operation k k# bw0# bw1# write d0 to d17 l h ? 0 0 ? l h 0 0 write d0 to d8 l h ? 0 1 ? l h 0 1 write d9 to d17 l h ? 1 0 ? l h 1 0 write nothing l h ? 1 1 ? l h 1 1 remarks 1. h : high, l : low, : rising edge. 2. assumes a write cycle was initiated. bw0# and bw1# can be altered for any portion of the burst write operation provided that the set up and hold requirements are satisfied.
16 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 [ pd44325364] operation k k# bw0# bw1# bw2# bw3# write d0 to d35 l h ? 0 0 0 0 ? l h 0 0 0 0 write d0 to d8 l h ? 0 1 1 1 ? l h 0 1 1 1 write d9 to d17 l h ? 1 0 1 1 ? l h 1 0 1 1 write d18 to d26 l h ? 1 1 0 1 ? l h 1 1 0 1 write d27 to d35 l h ? 1 1 1 0 ? l h 1 1 1 0 write nothing l h ? 1 1 1 1 ? l h 1 1 1 1 remarks 1. h : high, l : low, : rising edge. 2. assumes a write cycle was initiated. bw0# to bw3# can be altered for any portion of the burst write operation provided that the set up and hold requirements are satisfied.
17 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 bus cycle state diagram read double; r_count = r_count+2 write double; w_count = w_count+2 power up always r# = high supply voltage provided load new read address; r_count = 0; r_init = 1 read port nop r_init = 0 r# = low & r_count = 4 w# = high write port nop load new write address; w_count = 0 always w# = low & w_count = 4 w# = low r_init = 0 r# = low supply voltage provided increment read address by two r_init = 0 increment write address by two w_count = 2 r_count = 2 always always w# = high & w_count = 4 r# = high & r_count = 4 remarks 1. the address is concatenated with two additional in ternal lsbs to facilitate burst operation. the address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3. bus cycle is terminated at the end of this sequence (burst count = 4). 2. read and write state machines can be active simultaneously. read and write cannot be simultaneously initiated. read takes precedence. 3. state machine control timing is controlled by k.
18 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 electrical specifications absolute maximum ratings parameter symbol conditions min. typ. max. unit supply voltage v dd ?0.5 +2.5 v output supply voltage v dd q ?0.5 v dd v input voltage v in ?0.5 v dd + 0.5 (2.5 v max.) v input / output voltage v i/o ?0.5 v dd q + 0.5 (2.5 v max.) v operating ambient temperature t a commercial 0 +70 c industrial ?40 +85 storage temperature t stg ?55 +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this sp ecification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions parameter symbol conditions min. typ. max. unit note supply voltage v dd 1.7 1.9 v output supply voltage v dd q 1.4 v dd v 1 input high voltage v ih (dc) v ref + 0.1 v dd q + 0.3 v 1, 2 input low voltage v il (dc) ?0.3 v ref ? 0.1 v 1, 2 clock input voltage v in ?0.3 v dd q + 0.3 v 1, 2 reference voltage v ref 0.68 0.95 v notes 1. during normal operation, v dd q must not exceed v dd . 2. power-up: v ih v dd q + 0.3 v and v dd 1.7 v and v dd q 1.4 v for t 200 ms recommended ac operating conditions parameter symbol conditions min. typ. max. unit note input high voltage v ih (ac) v ref + 0.2 ? v 1 input low voltage v il (ac) ? v ref ? 0.2 v 1 note 1. overshoot: v ih (ac) v dd + 0.7 v (2.5 v max.) for t tkhkh/2 undershoot: v il (ac) ? 0.5 v for t tkhkh/2 control input signals may not have pulse widths less than tkhkl (min.) or operate at cycle rates less than tkhkh (min.). < r > < r >
19 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 dc characteristics (v dd = 1.8 0.1 v) parameter symbol test condition min. typ. max. unit note x8, x9 x18 x36 input leakage current i li ?2 ? +2 a i/o leakage current i lo ?2 ? +2 a operating supply i dd note1 commercial -e37 740 1,020 1,140 ma current (t a = 0 to +70c) -e40 700 950 1,050 (read cycle / -e50 600 800 900 write cycle) industrial -e40y 800 1,090 ? (t a = ?40 to +85c) -e50y 690 920 ? standby supply i sb1 note1 commercial -e37 420 420 420 ma current (t a = 0 to +70c) -e40 400 400 400 (nop) -e50 350 350 350 industrial -e40y 450 450 ? (t a = ?40 to +85c) -e50y 400 400 ? output high voltage v oh(low) |i oh | 0.1 ma v dd q ? 0.2 ? v dd q v 4, 5 v oh note2 v dd q/2?0.12 ? v dd q/2+0.12 v 4, 5 output low voltage v ol(low) i ol 0.1 ma v ss ? 0.2 v 4, 5 v ol note3 v dd q/2?0.12 ? v dd q/2+0.12 v 4, 5 notes 1. v in v il or v in v ih , i i/o = 0 ma, cycle = max. 2. outputs are impedance-controlled. | i oh | = (v dd q/2)/(rq/5) 15% for values of 175 rq 350 . 3. outputs are impedance-controlled. i ol = (v dd q/2)/(rq/5) 15% for values of 175 rq 350 . 4. ac load current is higher than the shown dc values. 5. hstl outputs meet jedec hstl class i standards. capacitance (t a = 25 c, f = 1 mhz) parameter symbol test conditions min. typ. max. unit input capacitance (address, control) c in v in = 0 v 4 5 pf input / output capacitance c i/o v i/o = 0 v 6 7 pf (d, q, cq, cq#) clock input capacitance c clk v clk = 0 v 5 6 pf remark these parameters are periodically sampled and not 100% tested. thermal resistance parameter symbol test conditions min. typ. max. unit thermal resistance j-a 22.6 c/w (junction ? ambient) thermal resistance j-c 2.0 c/w (junction ? case) remark these parameters are simulated under the condition of air flow velocity = 1 m/s.
20 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 ac characteristics (v dd = 1.8 0.1 v) ac test conditions (v dd = 1.8 0.1 v, v dd q = 1.4 v to v dd ) input waveform (rise / fall time 0.3 ns) 0.75 v 0.75 v test points 1.25 v 0.25 v output waveform v dd q / 2 v dd q / 2 test points output load condition figure 1. external load at test v dd q / 2 0.75 v 50 z o = 50 250 sram v ref zq
21 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 read and write cycle parameter symbol -e37 -e40, -e40y -e50, -e50y unit note (270 mhz) (250 mhz) (200 mhz) min. max. min. max. min. max. clock average clock cycle time (k, k#, c, c#) tkhkh 3.7 8.4 4.0 8.4 5.0 8.4 ns 1 clock phase jitter (k, k#, c, c#) tkc var ? 0.2 ? 0.2 ? 0.2 ns 2 clock high time (k, k#, c, c#) tkhkl 1.5 ? 1.6 ? 2.0 ? ns clock low time (k, k#, c, c#) tklkh 1.5 ? 1.6 ? 2.0 ? ns clock high to clock# high tkhk#h 1.7 ? 1.8 ? 2.2 ? ns (k k#, c c#) clock# high to clock high tk#hkh 1.7 ? 1.8 ? 2.2 ? ns (k# k, c# c) clock to data clock 250 to 270 mhz tkhch 0 1.65 ? ? ? ? ns (k c, k# c#) 200 to 250 mhz 0 1.8 0 1.8 ? ? 167 to 200 mhz 0 2.3 0 2.3 0 2.3 133 to 167 mhz 0 2.8 0 2.8 0 2.8 < 133 mhz 0 3.55 0 3.55 0 3.55 dll/pll lock time (k, c) tkc lock 1,024 ? 1,024 ? 1,024 ? cycle 3 k static to dll/pll reset tkc reset 30 ? 30 ? 30 ? ns 4 output times c, c# high to output valid tchqv ? 0.45 ? 0.45 ? 0.45 ns c, c# high to output hold tchqx ? 0.45 ? ? 0.45 ? ? 0.45 ? ns c, c# high to echo clock valid tchcqv ? 0.45 ? 0.45 ? 0.45 ns c, c# high to echo clock hold tchcqx ? 0.45 ? ? 0.45 ? ? 0.45 ? ns cq, cq# high to output valid tcqhqv ? 0.3 ? 0.3 ? 0.35 ns 5 cq, cq# high to output hold tcqhqx ? 0.3 ? ? 0.3 ? ? 0.35 ? ns 5 c high to output high-z tchqz ? 0.45 ? 0.45 ? 0.45 ns c high to output low-z tchqx1 ? 0.45 ? ? 0.45 ? ? 0.45 ? ns setup times address valid to k rising edge tavkh 0.5 ? 0.5 ? 0.6 ? ns 6 control inputs (r#, w#) valid to k rising edge tivkh 0.5 ? 0.5 ? 0.6 ? ns 6 data inputs and write data select tdvkh 0.35 ? 0.35 ? 0.4 ? ns 6 inputs (bwx#, nwx#) valid to k, k# rising edge hold times k rising edge to address hold tkhax 0.5 ? 0.5 ? 0.6 ? ns 6 k rising edge to control inputs (r#, w#) hold tkhix 0.5 ? 0.5 ? 0.6 ? ns 6 k, k# rising edge to data inputs and tkhdx 0.35 ? 0.35 ? 0.4 ? ns 6 write data select inputs (bwx#, nwx#) hold
22 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 notes 1. when debugging the system or board, these products can operate at a cl ock frequency slower than tkhkh (max.) without the dll/pll circuit being used, if dll# = low. read latency (rl) is changed to 1.5 clock in this operation. the ac/dc characteri stics cannot be guaranteed, however. 2. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. tkc var (max.) indicates a peak-to-peak value. 3. v dd slew rate must be less than 0.1 v dc per 50 ns for dll/pll lock retention. dll/pll lock time begins once v dd and input clock are stable. it is recommended that the device is kept nop (r# = w# = high) during these cycles. 4. k input is monitored for this o peration. see below for the timing. k k tkc reset or tkc reset 5. echo clock is very tightly controlled to data valid / data hold. by design, there is a 0.1 ns variation from echo clock to data. the data s heet parameters reflect tester guardba nds and test setup variations. 6. this is a synchronous device. all addresses, dat a and control lines must meet the specified setup and hold times for all latching clock edges. remarks 1. this parameter is sampled. 2. test conditions as specified with the output loading as shown in ac test conditions unless otherwise noted. 3. control input signals may not be operated with pulse widths less than tkhkl (min.). 4. if c, c# are tied high, k, k# become the references for c, c# timing parameters. 5. v dd q is 1.5 v dc. < r > < r >
23 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 read and write timing k address data in k# 246 13 5 7 tkhk#h tk#hkh c c# tkhch nop read read tkhkl tklkh q00 q02 data out q01 q03 r# w# tkhkl tklkh tchqx1 tchqx tchqz d10 d12 d11 d13 tdvkh tkhdx tdvkh tkhdx tkhkh tivkh tkhix tavkh tkhax cq cq# tchqv tchcqx tchcqv tchcqx tchcqv write nop qx3 tchqx tchqv write tivkh tkhix a0 a1 a2 a3 d30 d32 d31 d33 q20 q22 q21 q23 qx2 tkhk#h tk#hkh tkhch tkhkh tcqhqv tcqhqx remarks 1. q00 refers to output from address a0+0. q01 refers to output from the next in ternal burst address following a0,i.e.,a0+1. 2. outputs are disabled (high impedance) 3.5 clocks a fter the last read (r# = low) is input in the sequences of [read]-[nop]-[nop], [read]- [write]-[nop] and [read ]-[nop]-[write]. 3. in this example, if address a2 = a1, data q 20 = d10, q21 = d11, q 22 = d12 and q23 = d13. write data is forwarded i mmediately as read results. < r > < r >
24 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 application example sram controller data in data out address r# w# bw# sram#1 cq/cq# sram#4 cq/cq# source clk/clk# return clk/clk# zq q cq# cq sram#4 d a r# w# bwx# c/c# k/k# r r v t v t r v t r v t r v t r v t r = 250 r = 250 zq q cq# cq sram#1 d a r# w# bwx# c/c# k/k# r = 50 v t = v ref . . . . . . remark ac specifications are defined at the condition of sram outputs, cq, cq# and q with termination.
25 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 jtag specification these products support a limited set of jtag functions as in ieee standard 1149.1. test access port (tap) pins pin name pin assignments description tck 2r test clock input. all input are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms 10r test mode select. this is the command input for the tap controller state machine. tdi 11r test data input. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction. tdo 1r test data output. this is the output si de of the serial registers placed between tdi and tdo. output changes in response to the falling edge of tck. remark the device does not have trst (tap reset). the test -logic reset state is entered while tms is held high for five rising edges of tck. the tap contro ller state is also reset on the sram power-up. jtag dc characteristics (v dd = 1.8 0.1 v, unless otherwise noted) parameter symbol conditions min. typ. max. unit jtag input leakage current i li 0 v v in v dd ?5.0 ? +5.0 a jtag i/o leakage current i lo 0 v v in v dd q, ?5.0 ? +5.0 a outputs disabled jtag input high voltage v ih 1.3 ? v dd +0.3 v jtag input low voltage v il ?0.3 ? +0.5 v jtag output high voltage v oh1 | i ohc | = 100 a 1.6 ? ? v v oh2 | i oht | = 2 ma 1.4 ? ? v jtag output low voltage v ol1 i olc = 100 a ? ? 0.2 v v ol2 i olt = 2 ma ? ? 0.4 v
26 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 jtag ac test conditions input waveform (rise / fall time 1 ns) 0.9 v 0.9 v test points 1.8 v 0 v output waveform 0.9 v 0.9 v test points output load figure 2. external load at test tdo z o = 50 v tt = 0.9 v 20 pf 50
27 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 jtag ac characteristics parameter symbol conditions min. typ. max. unit clock clock cycle time t thth 50 ? ? ns clock frequency f tf ? ? 20 mhz clock high time t thtl 20 ? ? ns clock low time t tlth 20 ? ? ns output time tck low to tdo unknown t tlox 0 ? ? ns tck low to tdo valid t tlov ? ? 10 ns setup time tms setup time t mvth 5 ? ? ns tdi valid to tck high t dvth 5 ? ? ns capture setup time t cs 5 ? ? ns hold time tms hold time t thmx 5 ? ? ns tck high to tdi invalid t thdx 5 ? ? ns capture hold time t ch 5 ? ? ns jtag timing diagram t thth t tlov t tlth t thtl t mvth t thdx t dvth t thmx tck tms tdi tdo t tlox < r >
28 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 scan register definition (1) register name description instruction register the instruction register holds the instru ctions that are executed by the tap controller when it is moved into the run-test/idle or the various data regi ster state. the register can be loaded when it is placed between the tdi and tdo pins. the instructi on register is automatically preloaded with the idcode instruction at power-up whenever the c ontroller is placed in test-logic-reset state. bypass register the bypass regi ster is a single bit register that can be pl aced between tdi and tdo. it allows serial test data to be passed through the rams tap to anot her device in the scan chai n with as little delay as possible. id register the id register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the register is then placed between the tdi and tdo pi ns when the controller is moved into shift-dr state. boundary register the boundary register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in captur e-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. several tap instructions can be used to activate the boundary register. the scan exit order tables describe which device bump connects to each boundary register location. the first column defines the bit?s posit ion in the boundary register. the second column is the name of the input or i/o at the bump and the third column is the bump number. scan register definition (2) register name bit size unit instruction register 3 bit bypass register 1 bit id register 32 bit boundary register 109 bit id register definition part number organization id [31:28] vendor revision no. id [ 27:12] part no. id [11:1] vendor id no. id [0] fix bit pd44325084 4m x 8 xxxx 0000 0000 0100 1101 00000010000 1 pd44325094 4m x 9 xxxx 0000 0000 0100 1110 00000010000 1 pd44325184 2m x 18 xxxx 0000 0000 0100 1111 00000010000 1 pd44325364 1m x 36 xxxx 0000 0000 0101 0000 00000010000 1
29 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 scan exit order bit signal name bump bit signal name bump bit signal name bump no. x8 x9 x18 x36 id no. x8 x9 x18 x36 id no. x8 x9 x18 x36 id 1 c# 6r 37 nc nc nc d15 10d 73 nc nc nc q28 2c 2 c 6p 38 nc nc nc q15 9e 74 q4 q5 q11 q20 3e 3 a 6n 39 nc nc q7 q7 10c 75 d4 d5 d11 d20 2d 4 a 7p 40 nc nc d7 d7 11d 76 nc nc nc d29 2e 5 a 7n 41 nc nc nc d16 9c 77 nc nc nc q29 1e 6 a 7r 42 nc nc nc q16 9d 78 nc nc q12 q21 2f 7 a 8r 43 q3 q4 q8 q8 11b 79 nc nc d12 d21 3f 8 a 8p 44 d3 d4 d8 d8 11c 80 nc nc nc d30 1g 9 a 9r 45 nc nc nc d17 9b 81 nc nc nc q30 1f 10 nc q0 q0 q0 11p 46 nc nc nc q17 10b 82 q5 q6 q13 q22 3g 11 nc d0 d0 d0 10p 47 cq 11a 83 d5 d6 d13 d22 2g 12 nc nc nc d9 10n 48 a a v ss v ss 10a 84 dll# 1h 13 nc nc nc q9 9p 49 a 9a 85 nc nc nc d31 1j 14 nc nc q1 q1 10m 50 a 8b 86 nc nc nc q31 2j 15 nc nc d1 d1 11n 51 a 7c 87 nc nc q14 q23 3k 16 nc nc nc d10 9m 52 nc 6c 88 nc nc d14 d23 3j 17 nc nc nc q10 9n 53 r# 8a 89 nc nc nc d32 2k 18 q0 q1 q2 q2 11l 54 nc nc nc bw1# 7a 90 nc nc nc q32 1k 19 d0 d1 d2 d2 11m 55 nw0# bw0# bw0# bw0# 7b 91 q6 q7 q15 q24 2l 20 nc nc nc d11 9l 56 k 6b 92 d6 d7 d15 d24 3l 21 nc nc nc q11 10l 57 k# 6a 93 nc nc nc d33 1m 22 nc nc q3 q3 11k 58 nc nc nc bw3# 5b 94 nc nc nc q33 1l 23 nc nc d3 d3 10k 59 nw1# nc bw1# bw2# 5a 95 nc nc q16 q25 3n 24 nc nc nc d12 9j 60 w# 4a 96 nc nc d16 d25 3m 25 nc nc nc q12 9k 61 a 5c 97 nc nc nc d34 1n 26 q1 q2 q4 q4 10j 62 a 4b 98 nc nc nc q34 2m 27 d1 d2 d4 d4 11j 63 a a a nc 3a 99 q7 q8 q17 q26 3p 28 zq 11h 64 v ss 2a 100 d7 d8 d17 d26 2n 29 nc nc nc d13 10g 65 cq# 1a 101 nc nc nc d35 2p 30 nc nc nc q13 9g 66 nc nc q9 q18 2b 102 nc nc nc q35 1p 31 nc nc q5 q5 11f 67 nc nc d9 d18 3b 103 a 3r 32 nc nc d5 d5 11g 68 nc nc nc d27 1c 104 a 4r 33 nc nc nc d14 9f 69 nc nc nc q27 1b 105 a 4p 34 nc nc nc q14 10f 70 nc nc q10 q19 3d 106 a 5p 35 q2 q3 q6 q6 11e 71 nc nc d10 d19 3c 107 a 5n 36 d2 d3 d6 d6 10e 72 nc nc nc d28 1d 108 a 5r 109 ? internal remark bump id 10a of bit no. 48 can also be us ed as nc if the product is x18 or x36. bump id 2a of bit no. 64 can also be used as nc. the register always indicates low, however.
30 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 jtag instructions instructions description extest the extest instruction allows circuitry external to the component package to be tested. boundary- scan register cells at output pins are used to apply te st vectors, while those at input pins capture test results. typically, the first test vector to be appli ed using the extest instruction will be shifted into the boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output drive is turned on and the prel oad data is driven onto the output pins. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register betw een the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. bypass when the bypass instruction is loaded in the inst ruction register, the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to fa cilitate testing of other devices in the scan path. sample / preload sample / preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instruction r egister, moving the tap controller into the capture- dr state loads the data in the rams input and q pi ns into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck ) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable input will not harm the device, repeatable results cannot be expected. ram input signals must be st abilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ri ng contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo pins. sample-z if the sample-z instruction is loaded in the inst ruction register, all ram q pins are forced to an inactive drive state (high impedance) and the bou ndary register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. jtag instruction coding ir2 ir1 ir0 instruction note 0 0 0 extest 0 0 1 idcode 0 1 0 sample-z 1 0 1 1 reserved 2 1 0 0 sample / preload 1 0 1 reserved 2 1 1 0 reserved 2 1 1 1 bypass notes 1. tristate all q pins and capture the pad values into a serial scan latch. 2. do not use this instruction code because t he vendor uses it to evaluate this product.
31 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 output pin states of cq, cq# and q instructions control-register status output pin status cq,cq# q extest 0 update high-z 1 update update idcode 0 sram sram 1 sram sram sample-z 0 high-z high-z 1 high-z high-z sample 0 sram sram 1 sram sram bypass 0 sram sram 1 sram sram remark the output pin statuses during eac h instruction vary according to the control-register st atus (value of boundary scan register, bit no. 109). there are three statuses: update : contents of the ?updat e register? are output to the output pin (qdr pad). sram : contents of the sram internal output ?sram output? are output to the output pin (qdr pad). high-z : the output pin (qdr pad) becomes high impedance by controlling of the ?high-z jtag ctrl?. the control-register status is set during update-dr at the extest or sample instruction. sram capture register boundary scan register update register qdr pad sram output driver high-z jtag ctrl high-z update sram output
32 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 boundary scan register status of output pins cq, cq# and q instructions sram status boundary scan register status note cq,cq# q extest read (low-z) pad pad nop (high-z) pad pad idcode read (low-z) ? ? no definition nop (high-z) ? ? sample-z read (low-z) pad pad nop (high-z) pad pad sample read (low-z) internal internal nop (high-z) internal pad bypass read (low-z) ? ? no definition nop (high-z) ? ? remark the boundary scan register stat uses during execution each instruction vary according to the instruction code and sram operation mode. there are two statuses: pad : contents of the output pi n (qdr pad) are captured in the ?capture register? in the boundary scan register. internal : contents of the sram internal output ?sram output? are captured in the ?capture register? in the boundary scan register. pad internal sram output driver update register qdr pad high-z jtag ctrl capture register sram output boundary scan register
33 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 tap controller state diagram test-logic-reset run-test / idle select-dr-scan capture-dr capture-ir shift-dr exit1-dr pause-dr exit2-dr update-dr update-ir exit2-ir pause-ir exit1-ir shift-ir select-ir-scan 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 0 0 10 10 11 1 0 1 1 0 1 0 11 disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude mid level inputs. tdi and tms may be left open but fix them to v dd via a resistor of about 1 k when the tap controller is not used. tdo should be left unconnected also when the tap controller is not used.
34 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 test logic operation (instruction scan) tck controller state tdi tms tdo test-logic-reset run-test/idle select-dr-scan select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir shift-ir exit1-ir update-ir run-test/idle idcode instruction register state new instruction output inactive
35 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 test logic (data scan) controller state tdi tms tdo run-test/idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr shift-dr exit1-dr update-dr test-logic-reset instruction instruction register state idcode run-test/idle select-dr-scan select-ir-scan output inactive tck
36 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 package drawing 165-pin plastic bga (13x15) item dimensions d e w e a a1 a2 13.00 0.10 15.00 0.10 0.15 0.40 0.05 1.00 1.40 0.11 1.00 0.50 0.05 (unit:mm) 0.08 0.10 0.20 1.50 0.50 p165f5-100-eq2 x y y1 zd ze b a 11 10 9 8 7 6 5 4 3 2 1 index mark ze zd b s wb e s wa d s y s a a2 a1 e y1 s s x ba b m ? rpnml k jhgfedcba
37 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 recommended soldering condition please consult with our sales offices for soldering conditions of these products. types of surface mount devices pd44325084f5-eq2 : 165-pin plastic bga (13 x 15) pd44325094f5-eq2 : 165-pin plastic bga (13 x 15) pd44325184f5-eq2 : 165-pin plastic bga (13 x 15) pd44325364f5-eq2 : 165-pin plastic bga (13 x 15) pd44325084f5-eq2-a : 165-pin plastic bga (13 x 15) pd44325094f5-eq2-a : 165-pin plastic bga (13 x 15) pd44325184f5-eq2-a : 165-pin plastic bga (13 x 15) pd44325364f5-eq2-a : 165-pin plastic bga (13 x 15)
38 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 4th edition/ throughout throughout addition ? -e40y, -e50y (industrial) mar. 2007 p.9 pp.7, 8 modification pin identification zq, dll#, nc text has been modified. p.18 p.17 modification recommended ac operating conditions note 1 has been modified. p.22 p.21 modification read and write cycle note 1 has been modified. addition note 4 has been added. p.23 p.22 addition read and write timing tcqhqx has been added. modification remark 2 has been modified. p.27 p.26 modification jtag ac characteristics jtag ac char acteristics has been modified.
39 data sheet m16784ej4v0ds pd44325084, 44325094, 44325184, 44325364 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
pd44325084, 44325094, 44325184, 44325364 qdr rams and quad data rate rams comprise a new seri es of products developed by cypress semiconductor, renesas, idt, nec electronics, and samsung. the information in this document is current as of march, 2007. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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