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? semiconductor components industries, llc, 2008 october, 2008 ? rev. 7 1 publication order number: ncv8518/d ncv8518 low dropout linear regulator with watchdog, wake up, reset , and enable the ncv8518 device is a precision micropower voltage regulator. it has a fixed output voltage of 5.0 v and regulates within 2%. it is suitable for use in all automotive environments and contains all the required functions to control a microprocessor. this device has low dropout voltage and low quiescent current. it includes a watchdog timer, adjustable reset, wake up and enable function. also encompassed in this device are safety features such as thermal shutdown and short circuit protection. it is capable of handling up to 45 v transients. features ? output voltage of 5.0 v ? 2% output voltage tolerance ? output current up to 250 ma ? micropower compatible control functions: ? enable ? watchdog ? reset ? wake up ? ncv prefix for automotive and other applications requiring site and change control ? low dropout voltage ? low quiescent current of 100 a ? protection features: ? thermal shutdown ? short circuit ? low sleep mode current less than 1.0 a ? aec qualified ? ppap capable ? these are pb ? free devices applications ? tire pressure monitor ? battery powered consumer electronics soic ? 16 lead wide body exposed pad case 751ag marking diagrams ncv8518 awlyywwg 1 16 1 16 http://onsemi.com 1 8 soic ? 8 exposed pad case 751ac a = assembly location wl = wafer lot yy, y = year ww = work week , or g = pb ? free package v8518 ayww 1 8 device package shipping ? ordering information NCV8518PDG soic ? 8* 98 units / rail soic ? 8* 2500 / tape & reel ncv8518pdr2g soic ? 16* 47 units / rail ncv8518pwr2g ncv8518pwg soic ? 16* 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. *these packages are inherently pb ? free.
ncv8518 http://onsemi.com 2 pin connections v in v out 18 wdi delay enable gnd reset wake up soic ? 8 ep v in v out 1 16 nc nc enable nc nc delay wdi nc nc gnd reset nc wake up nc soic ? 16 ep pin function description pin soic ? 8 ep soic ? 16 e pad symbol description 4 8 v out regulated output voltage. 5 9 v in input s upply voltage. 7 13 wdi cmos compatible watchdog input. the watchdog function monitors the falling edge of the incoming signal. 2 3 gnd ground connection. 6 11 enable enable control for the ic. positive logic. 8 15 reset cmos compatible output reset goes low whenever v out drops by more than 7.0% from nominal, or during the absence of a correct watchdog signal. 3 5 delay buffered reference voltage used to create timing current for reset and watchdog threshold frequency from r delay. ? 1, 2, 4, 6, 7, 10, 12, 14 nc no connection. 1 16 wake up continuously generated signal that interrupts the microprocessor from sleep mode. epad epad epad connect to ground potential or leave unconnected.
ncv8518 http://onsemi.com 3 v in reset v out wdi delay enable wake up enable reference vbg buffer iref + - timing circuit osch oscl watchdog + wakeup logic wakeup driver reset driver + - uvlo rail + - oscl fb osch tsd ilimit figure 1. block diagram
ncv8518 http://onsemi.com 4 maximum ratings rating symbol value unit input voltage v in , enable ? 0.3 to 45 v output voltage v out ? 0.3 to +7.0 v reset voltage v reset 0 v to v out v reset current (reset may be incidentally shorted either to v out or to gnd without damage) i reset internally limited ma esd susceptibility (human body model) ? 2.0 kv logic inputs/outputs (reset, wdi, wake up, delay) ? ? 0.3 to +7.0 v operating junction temperature t j ? 40 to150 c storage temperature range t s ? 55 to +150 c moisture sensitivity level soic ? 16 ep (case 751r) soic ? 8 ep (case 751ac) msl 1 3 lead temperature soldering: reflow leaded part 60 ? 150 sec above 183 c, 30 sec max at peak lead ? free part 60 ? 150 sec above 217 c, 40 sec max at peak ? ? 240 peak 265 peak c c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. thermal characteristics parameter board/mounting conditions typical value unit so ? 8 exposed pad package minimum ? pad board (note 1) 1 sq. inch spreader board (note 2) junction to case top ( ? jt, jt ) 19 8 c/w junction to pin1 ( ? jl1, jl1 ) 68 63 c/w junction to board ( ? jb, jb ) 3 9 10 c/w junction to ambient (r ja , ja ) 235 57 c/w so ? 16 exposed pad package minimum ? pad board (note 3) 1 sq. inch spreader board (note 2) junction to case top ( ? jt, jt ) 30 16 c/w junction to pin1 ( ? jl1, jl1 ) 70 65 c/w junction to board ( ? jb, jb ) (note 4) 15 17 c/w junction to ambient (r ja , ja ) 150 55 c/w specific notes on thermal characterization conditions: all boards are 0.062? thick fr4, 3? square, with varying amounts of copper heat spreader, in still air (free convection) condit ions. numerical values are derived from an axisymmetric finite ? element model where active die area, total die area, flag area, pad area, and board area are equated to the actual corresponding areas. 1. 1 oz copper, 6 x 9 mm, 0.062? thick fr ? 4. 2. 1 oz copper, 645 mm 2 (1in 2 ) spreader area (includes exposed pad). 3. 1 oz copper, 17.2 mm 2 spreader area (minimum exposed pad, not including traces which are assumed). 4. ?board? is defined as center of exposed pad soldered to board; this is the recommended number to be used for thermal calcula tions, as it best represents the primary heat flow path and is least sensitive to board and ambient properties.
ncv8518 http://onsemi.com 5 electrical characteristics ( ? 40 c t j 150 c; 6.0 v v in 28 v, 100 a i out 150 ma, c 2 = 1.0 f, r delay = 60 k; unless otherwise specified.) characteristic symbol min typ max unit output output voltage v out 4.9 ? 2% 5.00 5.10 +2% v dropout voltage (v in ? v out , i out = 150 ma) (note 5) v do ? 425 750 mv load regulation (v in = 13.5 v, 100 a i out 150 ma) reg load ? 5.0 30 mv line regulation (6.0 v v in 28 v, i out = 5.0 ma) reg line ? 5.0 20 mv current limit i lim 255 400 ? ma thermal shutdown (guaranteed by design) t jmax 150 180 210 c quiescent current (v in = 13.5 v, i out = 100 a, 150 ma, enable = 2.0 v) (enable = 0 v) i q ? ? 100 ? 150 1.0 a reset threshold voltage ? 4.50 4.65 4.75 v output low (r load = 10 k to v out , v out = 1.0 v) ? ? 0.2 0.4 v output high (r load = 10 k to gnd) ? v out ? 0.4 v out ? 0.2 ? v power on reset delay time (v in = 13.5 v, r delay = 60 k, i out = 5.0 ma) (v in = 13.5 v, r delay = 120 k, i out = 5.0 ma) v in = 13.5 v, r delay = 500 k, i out = 5.0 ma) t d 2.0 ? ? 3.0 6.0 25 4.0 ? ? ms watchdog input threshold wdi high 30 50 70 %v out hysteresis wdi hys 25 100 ? mv input current (wdi = 6.0 v) ? ? 0.1 2.0 a wake up wdi wake up rising edge to wdi falling edge delay ? 5.0 ? ? s enable (note 6) input threshold logic low logic high v th(en) ? 2.0 ? ? 0.8 ? v input current (enable = 2.0 v) ? ? 3.0 10 a 5. measured when the output voltage has dropped 2% from the nominal value. 6. if enable is connected to v in , a 20 k resistor must be placed in series.
ncv8518 http://onsemi.com 6 electrical characteristics (continued) ( ? 40 c t j 150 c; 6.0 v v in 28 v, 100 a i out 150 ma, c 2 = 1.0 f, r delay = 60 k; unless otherwise specified.) characteristic symbol min typ max unit wake up output (v in = 14 v, i out = 5.0 ma) wake up period (r delay = 60 k) (r delay = 120 k) (r delay = 500 k) ? 18 ? ? 25 50 208 32 ? ? ms wake up duty cycle nominal ? 45 50 55 % reset high to wake up rising delay time (r delay = 60 k) 50% reset rising edge to 50% wake up edge (r delay = 120 k) (r delay = 500 k) ? 9.0 ? ? 12.5 25 104 16 ? ? ms wake up response to watchdog input 50% wdi falling edge to 50% wake up falling edge ? ? 0.1 5.0 s wake up response to reset 50% reset falling edge to 50% wake up falling edge (v out = 5.0 v 4.5 v) ? ? 0.1 5.0 s output low (r load = 10 k) ? ? 0.2 0.4 v output high (r load = 10 k) ? v out ? 0.5 v out ? 0.25 ? v delay output voltage (r delay = 60 k, 120 k, 500 k) ? ? 0.48 ? v definition of terms dropout voltage: the input ? to ? output voltage dif ferential at which the circuit ceases to regulate against further reduction in input voltage. measured when the output voltage has dropped 100 mv from the nominal value obtained at 14 v input, dropout voltage is dependent upon load current and junction temperature. input voltage: the dc voltage applied to the input terminals with respect to ground. line regulation: the change in output voltage for a change in the input voltage. the measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. load regulation: the change in output voltage for a change in load current at constant chip temperature. quiescent current: the part of the positive input current that does not contribute to the positive load current. the regulator ground lead current with no load. current limit: peak current that can be delivered to the output.
ncv8518 http://onsemi.com 7 timing diagrams v in , enable reset wake up wdi v out por reset delay time reset high to wake up delay time wake up period por reset wake up wdi v in , enable reset threshold por v out decreasing power down wake up period figure 2. power up, sleep mode and normal operation v in , enable reset wake up wdi v out wake up duty cycle = 50% power up microprocessor sleep mode normal operation with varying watchdog signal reset high to wake up delay time por wake up duty cycle will be 50% when the wdi pulse occurs at the low state of the wake up signal. figure 3. error condition: watchdog remains low and a reset is issued v out min wdi falling edge delay after wake up rising edge wake up response to reset wake up response to wdi figure 4. power down, restart sequence, and wake up response to wdi
ncv8518 http://onsemi.com 8 typical performance characteristics ? 50 output voltage (v) 4.9 t j , temperature ( c) 5.0 5.1 0 50 100 150 figure 5. output voltage vs. temperature output voltage (v) 4.99 input voltage (v) 5.01 5.00 51015202530 figure 6. output voltage vs. input voltage ? 50 por delay (ms) 2.7 t j , temperature ( c) 3.0 3.1 3.2 3.3 2.9 2.8 0 50 100 150 figure 7. por delay vs. temperature, 60 k rdelay ? 50 por delay (ms) 5.6 t j , temperature ( c) 6.2 6.4 6.0 5.8 0 50 100 150 figure 8. por delay vs. temperature, 120 k rdelay figure 9. stability region of capacitive esr vs. output current 5 ma load 25 c 60 k rdelay figure 10. wakeup period vs. temperature 120 k rdelay 0 esr ( ) 0.1 output current (ma) 100 1000 10000 100 25 50 75 unstable region stable region, all cap values 0.1 f unstable 100 f 0.1 ? 10 f 1 10 ? 50 wakeup period (ms) 23 t j , temperature ( c) 25 26 27 24 0 50 100 150 60 k rdelay
ncv8518 http://onsemi.com 9 typical performance characteristics wakeup period (ms) rdelay (k ) por delay (ms) figure 11. wakeup period vs. rdelay figure 12. por delay vs. rdelay 0 output voltage (v) 0 input voltage (v) 123 4 0 v out transient (mv) 0 switching current (ma) 50 100 150 200 figure 13. output voltage vs. input voltage, 5 ma load figure 14. load transient response 6 1 2 3 4 5 6 250 10 20 30 40 50 60 100 f, 0.12 esr ? 40 c 0 dropout voltage (mv) 0 load current (ma) 50 100 150 0 quiescent current ( a) load current (ma) 50 figure 15. dropout voltage vs. output current figure 16. quiescent current vs. output current 100 200 300 400 700 125 c 25 c 150 96 98 102 ? 40 c 125 c 25 c 100 104 5 22 f, 0.20 esr 4.7 f, 0.32 esr 500 600 100 0 50 100 150 200 250 0 100 200 300 400 500 0 5 10 15 20 25 30 0 100 200 300 400 500 rdelay (k )
ncv8518 http://onsemi.com 10 operating description general the ncv8518 is a precision micropower voltage regulator featuring low quiescent current (100 a typical at 250 ma load) and low dropout voltage (450 mv typical at 150 ma). integrated microprocessor control functions include w atchdog, wakeup and reset . an enable input is provided for logic level control of the regulator state. the combination of low quiescent current and comprehensive microprocessor interface functions make the ncv8518 ideal for use in both battery operated and automotive applications. the ncv8518 is internally protected against short circuit and thermal runaway conditions. no external components are required to engage these protective mechanisms. the device continues to operate through 45 volt input transients, an important consideration in automotive environments. wakeup and watchdog to reduce battery drain, a microprocessor or microcontroller can transition to a low current consumption (?sleep?) mode when code execution is suspended or complete. the ncv8518 wakeup signal is generated and output periodically to interrupt sleep mode. the nominal wakeup output is a 5 volt square wave (generated from vout) with a duty cycle of 50%, at a frequency determined by external timing resistor r delay . in response to the rising edge of the wakeup signal, the microprocessor will subsequently output a watchdog pulse and check its inputs to decide if it should resume normal operation or remain in sleep mode. the ncv8518 responds to the falling edge of the watchdog signal, which it expects at least once during each wakeup period. when the correct watchdog signal is received, the wakeup output is forced low. other w atchdog pulses received within the same cycle are ignored. the watchdog circuitry continuously monitors the input watchdog signal (wdi) from the microprocessor. the absence of a falling edge on the watchdog input during one wakeup cycle will cause a reset pulse to be output at the end of the wakeup cycle (see figure 4). reset as output voltage falls, the reset output will maintain its current state down to v out = 1 v. a reset signal (active low) is asserted for any of four conditions: 1. during power up, reset is held low until the output voltage is in regulation. 2. during operation, if the output voltage falls below the reset threshold, reset switches low, and will remain low until both the output voltage has recovered and the reset delay timer cycle has completed following that recovery. 3. reset will switch low if the regulator does not receive a watchdog input signal within a wakeup period. 4. regardless of output voltage, reset will switch low if the regulator input voltage v in , falls below a level required to sustain the internal control circuits. the specific voltage is temperature dependent, and is approximately 4.75 v at 20 c. the wakeup output is pulled low during a reset regardless of the cause of the reset . after the reset returns high, the wakeup cycle begins again (see figure 4). the reset delay time, wakeup signal frequency and reset high to w akeup delay time are all set by one external resistor, rdelay, according to the following equations: wakeup period (seconds) = (4.17 10 ? 7 ) * r delay ( ) reset delay time (seconds) = (5.21 10 ? 8 ) * r delay ( ) reset high to wakeup delay time (seconds) = (2.08 10 ? 7 ) * r delay ( ) the voltage present at the delay pin is a buf fered bandgap voltage (~1.25 v) and can be used as a reference for an external tracking regulator. enable this is a standard ttl and cmos logic compatible input that can be used to turn the regulator on or off. logic high enables the regulator; logic low disables it (also called shutdown ). in the disabled/shutdown state, the pass transistor is off and total quiescent current is less than 1 a. c1* v out gnd v in wdi 1.0 f i/o reset reset 0.1 f c2 microprocessor delay r delay 120 k v bat *c1 required if regulator is located far from power supply filter. v dd enable figure 17. application circuit ncv8518 wake up i/o fault ok on off
ncv8518 http://onsemi.com 11 package dimensions soic ? 8 ep d suffix case 751ac ? 01 issue b ?? ?? h c 0.10 d e1 a d pin one 2 x 8 x seating plane exposed gauge plane 14 5 8 d c 0.10 a-b 2 x e b e c 0.10 2 x top view side view bottom view detail a end view section a ? a 8 x b a-b 0.25 d c c c 0.10 c 0.20 a a2 g f 1 4 58 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters (angles in degrees). 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the ?b? dimension at maximum material condition. 4. datums a and b to be determined at datum plane h. dim min max millimeters a 1.35 1.75 a1 0.00 0.10 a2 1.35 1.65 b 0.31 0.51 b1 0.28 0.48 c 0.17 0.25 c1 0.17 0.23 d 4.90 bsc e 6.00 bsc e 1.27 bsc l 0.40 1.27 l1 1.04 ref f 2.24 3.20 g 1.55 2.51 h 0.25 0.50 0 8 h aa detail a (b) b1 c c1 0.25 l (l1) pad e1 3.90 bsc a1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* location exposed pad 1.52 0.060 2.03 0.08 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 7.0 0.275 2.72 0.107
ncv8518 http://onsemi.com 12 package dimensions soic ? 16 lead wide body, exposed pad pdw suffix case 751ag ? 01 issue a g ? w ? ? u ? p m 0.25 (0.010) w ? t ? seating plane k d 16 pl c m 0.25 (0.010) t uw s s m f detail e detail e r x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable protrusion shall be 0.13 (0.005) total in excess of the d dimension at maximum material condition. 6. 751r-01 obsolete, new standard 751r-02. j m 14 pl pin 1 i.d. 8 1 16 9 top side 0.10 (0.004) t 16 exposed pad 18 back side l h dim a min max min max inches 10.15 10.45 0.400 0.411 millimeters b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc h 3.45 3.66 0.136 0.144 j 0.25 0.32 0.010 0.012 k 0.00 0.10 0.000 0.004 l 4.72 4.93 0.186 0.194 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 a b 9 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.350 0.175 0.050 0.376 0.188 0.200 0.074 dimensions: inches 0.024 0.150 exposed pad c l c l on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv8518/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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