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ds07-08201-1e fujitsu semiconductor data sheet family fr450 series vliw embedded microprocessor mb93461 description mb93461 realizes excellent performance in the fiel d by combining advanced general processing and media processing for digital av equipments such as television, ad vanced projector, ip tv phone, portable media player, etc. the processor core embedded in mb93461 can combine maximum two instructions out of integer operation instruction, media instruction, and branch instruction and can issue them in units of vliw (very long instruction word) instruction per cycle. moreover, peripheral resource modules including mmu (memory management unit) , sdram controller (sdramc) , interrupt controlle r (irc) , dma controller (dmac) , asynchronous transfer module (uart) , timer/counter, general-purpose input/ output (gpio) , video display controller (vdc) , video capture controller (vcc) , audio interface, serial interface (i 2 c*) , usb interface (full speed host/function) , memory stick interface, and sd-io interface are embedded in mb93461. * : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specific ation as defined by philips. packages 420-ball plastic bga 400-ball plastic pfbga (bga-420p-m25) (bga-400p-m04)
mb93461 2 features fr450 cpu core ? 2-way vliw processor core core frequency : 400 mhz/360 mhz mmu is embedded peak performance (core frequency : 400 mhz) 800 mips (integer operation performance) , 3200 mops + 400 mips (media operation performance, 4mac + integer) 64 32-bit registers (32gr + 32fr) cache instruction cache 32 kb (2way) , line size 32 byte data cache 32 kb (2way) , line size 32 byte non-blocking cache (data cache) 64-byte store buffer (data cache) sdram interface sdram compliant with pc133 standard can be conn ected, variable 32-bit/16-bit data bus and 4 cs local bus interface 32-bit address/32-bit, 16-bit, or 8-bit data directly connecting sram/rom, etc. is possible jtag boundary scan function compliant with ieee1149.1 is supported av peripheral resource video display controller (vdc) scan method : progressive/interlace horizontal resolution : 320 to 1920 pixels , vertical resolution : 240 to 1200 pixels osd display : max 1920x1200 pixels , 255/15 colors + transparent video capture controller ( vcc ) scan method : progressive/interlace horizontal resolution : 320 to 1920 pixels , vertical resolution : 240 to 1200 pixels reduce scaler audio output 3-line serial (spd-if, i 2 s, msb-justified) , pcm highway, and digital volume are supported audio input 3-line serial (i 2 s, msb-justified) and pcm highway are supported serial interface (i 2 c, 2 channels) standard transfer (100 kbps) and high- speed transfer (400 kbps) are supported usb interface usb 2.0 fs host/function ms1.4 interface sd-io interface av-dmac (8 channels) gpio (32-bit) (continued)
mb93461 3 (continued) general-purpose peripheral resource interrupt controller (irc) dmac (8 channels) uart (2 channels) timer (3 channels) gpio (22-bit) recommended operation condition and external shape power supply voltage and current externally 3.3 v 0.15 v, internally 1.4 v 0.07 v (at 400 mhz) , internally 1.3 v 0.065 v (at 360 mhz) operating temperature range from 0 c to + 70 c product lineup these specifications have indicate d four kinds of following products. 1) mb93461pb-ge1 2) MB93461-40PB-GE1 3) mb93461bgl-ge1 4) mb93461-40bgl-ge1 part number mb93461pb-ge1 mb93461-40p b-ge1 mb93461bgl-ge1 mb93461-40bgl-ge1 core frequency 360 mhz 400 mhz 360 mhz 400 mhz voltage external/ internal 3.3 v 0.15 v/ 1.3 v 0.065 v 3.3 v 0.15 v/ 1.4 v 0.07 v 3.3 v 0.15 v/ 1.3 v 0.065 v 3.3 v 0.15 v/ 1.4 v 0.07 v ta 0 c to + 70 c package (code) bga420 (bga-420p-m 25) pfbga400 (bga-400p-m04) thermal resistance rth (ja) 19 c/w (0 m/s) 42 c/w (0 m/s) remarks lead-free solder ball
mb93461 4 pin assignment 1. bga420 64 pins from k10 to u17 are for thermal. connect them to vss. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a b c d e f g h j k l m n p r t u v w y a a a b a c a d a e af 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 27 99 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 125 28 98 191 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 215 126 29 97 190 275 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 297 216 127 30 96 189 274 351 420 95 188 273 350 419 94 187 272 349 418 93 186 271 348 417 92 185 270 347 416 91 184 269 346 415 90 183 268 345 414 89 182 267 344 413 88 181 266 343 412 87 180 265 342 411 86 179 264 341 410 85 178 263 340 409 84 177 262 339 408 83 176 261 338 407 82 175 260 337 406 81 174 259 336 405 371 298 217 128 31 372 299 218 129 32 373 300 219 130 33 374 301 220 131 34 375 302 221 132 35 376 303 222 133 36 377 304 223 134 37 378 305 224 135 38 379 306 225 136 39 380 307 226 137 40 381 308 227 138 41 382 309 228 139 42 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss 383 310 229 140 43 384 311 230 141 44 385 312 231 142 45 386 313 232 143 46 80 173 258 335 404 403 402 401 400 399 398 397 396 395 394 393 392 391 390 389 388 387 314 233 144 47 79 172 257 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 234 145 48 78 171 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 146 49 77 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 50 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 91011121314151617181920212223242526 index (bga-420p-m25)
mb93461 5 (continued) pin no. position pin name pin no. position pin name pin no. position pin name 1 a1 n.c. 37 af12 vss 73 d26 n.c. 2 b1 n.c. 38 af13 da[0] 74 c26 n.c. 3 c1 n.c. 39 af14 da[1] 75 b26 n.c. 4 d1 n.c. 40 af15 da[4] 76 a26 n.c. 5 e1 hpwren 41 af16 da[9] 77 a25 n.c. 6 f1 vcg[0] 42 af17 dba[1] 78 a24 n.c. 7g1vcg[5]43af18ddqm[3]79a23n.c. 8 h1 vss 44 af19 ddq[17] 80 a22 a[23] 9 j1 vcr[1] 45 af20 ddq[22] 81 a21 a[26] 10 k1 vcr[6] 46 af21 ddq[25] 82 a20 vss 11 l1 vcb[1] 47 af22 ddq[30] 83 a19 bstreq# 12 m1 vcb[6] 48 af23 n.c. 84 a18 bstack# 13 n1 vdr[0] 49 af24 n.c. 85 a17 bs# 14 p1 vdr[1] 50 af25 n.c. 86 a16 cs#[1] 15 r1 vdr[6] 51 af26 n.c. 87 a15 cs#[6] 16 t1 vdg[1] 52 ae26 n.c. 88 a14 pp[00] 17 u1 vdg[6] 53 ad26 n.c. 89 a13 pp[01] 18 v1 vdb[1] 54 ac26 n.c. 90 a12 pp[04] 19 w1 vdb[6] 55 ab26 trst# 91 a11 pp[09] 20 y1 enable 56 aa26 vss 92 a10 pp[12] 21 aa1 vde 57 y26 prst# 93 a9 pp[17] 22 ab1 vss 58 w26 cmode[3] 94 a8 pp[13] 23 ac1 n.c. 59 v26 vdd 95 a7 sdcmd 24 ad1 n.c. 60 u26 d[2] 96 a6 vss 25 ae1 n.c. 61 t26 d[7] 97 a5 vdd 26 af1 n.c. 62 r26 d[10] 98 a4 n.c. 27 af2 n.c. 63 p26 d[15] 99 a3 n.c. 28 af3 n.c. 64 n26 d[16] 100 a2 n.c. 29 af4 n.c. 65 m26 d[19] 101 b2 n.c. 30 af5 vdd 66 l26 d[24] 102 c2 n.c. 31 af6 ddq[2] 67 k26 d[27] 103 d2 n.c. 32 af7 ddq[7] 68 j26 be[0] 104 e2 vdd 33 af8 ddq[9] 69 h26 bclko 105 f2 vdd 34 af9 ddq[14] 70 g26 a[5] 106 g2 vcg[4] 35 af10 dcas# 71 f26 a[8] 107 h2 vcvsync 36 af11 dcs#[2] 72 e26 a[13] 108 j2 vcr[0]
mb93461 6 (continued) pin no. position pin name pin no. position pin name pin no. position pin name 109 k2 vcr[5] 143 ae21 ddq[26] 177 b18 a[31] 110 l2 vcb[0] 144 ae22 ddq[31] 178 b17 we# 111 m2 vcb[5] 145 ae23 test- mode 179 b16 cs#[0] 112 n2 vcb[7] 146 ae24 n.c. 180 b15 cs#[5] 113 p2 vdr[2] 147 ae25 n.c. 181 b14 cpuhold 114 r2 vdr[7] 148 ad25 n.c. 182 b13 pp[02] 115 t2 vdg[2] 149 ac25 n.c. 183 b12 pp[05] 116 u2 vdg[7] 150 ab25 tms 184 b11 pp[10] 117 v2 vdb[2] 151 aa25 ed 185 b10 pp[15] 118 w2 vdb[7] 152 y25 vde 186 b9 pp[20] 119 y2 topfield 153 w25 cmode[2] 187 b8 pp[16] 120 aa2 disable 154 v25 clkin 188 b7 sddat[0] 121 ab2 vde 155 u25 d[1] 189 b6 sdcki 122 ac2 n.c. 156 t25 d[6] 190 b5 uscki 123 ad2 n.c. 157 r25 d[9] 191 b4 udm 124 ae2 n.c. 158 p25 d[14] 192 b3 n.c. 125 ae3 n.c. 159 n25 d[17] 193 c3 n.c. 126 ae4 sda[1] 160 m25 d[20] 194 d3 vde 127 ae5 vss 161 l25 d[25] 195 e3 vss 128 ae6 ddq[1] 162 k25 d[28] 196 f3 vde 129 ae7 ddq[6] 163 j25 be[1] 197 g3 vcg[3] 130 ae8 ddq[8] 164 h25 be[3] 198 h3 vchsync 131 ae9 ddq[13] 165 g25 a[6] 199 j3 vdd 132 ae10 dwe# 166 f25 a[9] 200 k3 vcr[4] 133 ae11 dcs#[1] 167 e25 a[14] 201 l3 vcr[7] 134 ae12 dclkfb 168 d25 a[16] 202 m3 vcb[4] 135 ae13 dras# 169 c25 n.c. 203 n3 vss 136 ae14 da[2] 170 b25 n.c. 204 p3 vdr[3] 137 ae15 da[5] 171 b24 n.c. 205 r3 vdg[0] 138 ae16 da[10] 172 b23 n.c. 206 t3 vdg[3] 139 ae17 da[11] 173 b22 a[22] 207 u3 vdb[0] 140 ae18 ddq[16] 174 b21 a[25] 208 v3 vdb[3] 141 ae19 ddq[18] 175 b20 a[30] 209 w3 vdclk- out 142 ae20 ddq[23] 176 b19 ibw 210 y3 vdd
mb93461 7 (continued) pin no. position pin name pin no. position pin name pin no. position pin name 211 aa3 fscki 246 n24 d[18] 281 h4 vcg[7] 212 ab3 lrcki 247 m24 d[21] 282 j4 vde 213 ac3 sdo 248 l24 d[26] 283 k4 vcr[3] 214 ad3 n.c. 249 k24 d[29] 284 l4 vde 215 ad4 sda[0] 250 j24 be[2] 285 m4 vcb[3] 216 ad5 scl[1] 251 h24 a[2] 286 n4 vde 217 ad6 ddq[0] 252 g24 a[7] 287 p4 vdr[4] 218 ad7 ddq[5] 253 f24 a[10] 288 r4 vss 219 ad8 vdd 254 e24 a[15] 289 t4 vdg[4] 220 ad9 ddq[12] 255 d24 a[17] 290 u4 vss 221 ad10 ddq[15] 256 c24 n.c. 291 v4 vdb[4] 222 ad11 dcs#[0] 257 c23 a[19] 292 w4 vdhsync 223 ad12 vss 258 c22 a[21] 293 y4 vss 224 ad13 dcs#[3] 259 c21 a[24] 294 aa4 sdi 225 ad14 da[3] 260 c20 a[29] 295 ab4 bcko 226 ad15 da[6] 261 c19 breq# 296 ac4 vde 227 ad16 dba[0] 262 c18 vde 297 ac5 scl[0] 228 ad17 da[12] 263 c17 rd# 298 ac6 vde 229 ad18 vss 264 c16 bgnt# 299 ac7 ddq[4] 230 ad19 ddq[19] 265 c15 cs#[4] 300 ac8 vde 231 ad20 ddq[24] 266 c14 cs#[7] 301 ac9 ddq[11] 232 ad21 ddq[27] 267 c13 pp[03] 302 ac10 vde 233 ad22 vss 268 c12 pp[06] 303 ac11 ddqm[1] 234 ad23 tdc 269 c11 pp[11] 304 ac12 dclk 235 ad24 n.c. 270 c10 pp[18] 305 ac13 vss 236 ac24 tdo 271 c9 pp[21] 306 ac14 vss 237 ab24 tdi 272 c8 sdclk 307 ac15 da[7] 238 aa24 erst# 273 c7 sddat[1] 308 ac16 vss 239 y24 ram- boot# 274 c6 vde 309 ac17 dcke 240 w24 cmode[1] 275 c5 vdd 310 ac18 vde 241 v24 vss 276 c4 udp 311 ac19 ddq[20] 242 u24 d[0] 277 d4 vde 312 ac20 vss 243 t24 d[5] 278 e4 udm1 313 ac21 ddq[28] 244 r24 d[8] 279 f4 vss 314 ac22 vde 245 p24 d[13] 280 g4 vcg[2] 315 ac23 mtest- mode
mb93461 8 (continued) pin no. position pin name pin no. position pin name pin no. position pin name 316 ab23 tck 349 d8 sdwp 382 ab17 ddqm[2] 317 aa23 hrst# 350 d7 sddat[2] 383 ab18 vdd 318 y23 vss 351 d6 sdcd 384 ab19 ddq[21] 319 w23 cmode[0] 352 d5 vss 385 ab20 vde 320 v23 vss 353 e5 udp1 386 ab21 ddq[29] 321 u23 rstout# 354 f5 hovr- cur# 387 ab22 vdd 322 t23 d[4] 355 g5 vcg[1] 388 aa22 ecv 323 r23 vde 356 h5 vcg[6] 389 y22 eclk 324 p23 d[12] 357 j5 vcd- clkin 390 w22 vdd 325 n23 vss 358 k5 vcr[2] 391* v22 vdd 326 m23 d[22] 359 l5 vss 392 u22 vde 327 l23 vss 360 m5 vcb[2] 393 t22 d[3] 328 k23 d[30] 361 n5 vss 394 r22 vss 329 j23 vss 362 p5 vdr[5] 395 p22 d[11] 330 h23 a[3] 363 r5 vde 396 n22 vde 331 g23 vss 364 t5 vdg[5] 397 m22 d[23] 332 f23 a[11] 365 u5 vde 398 l22 vde 333 e23 vss 366 v5 vdb[5] 399 k22 d[31] 334 d23 a[18] 367 w5 vdvsync 400 j22 vde 335 d22 a[20] 368 y5 vdp- clkin 401 h22 a[4] 336 d21 vde 369 aa5 bcki 402 g22 vde 337 d20 a[28] 370 ab5 lrcko 403 f22 a[12] 338 d19 err# 371 ab6 vss 404 e22 vdd 339 d18 vdd 372 ab7 ddq[3] 405 e21 vss 340 d17 rdy# 373 ab8 vss 406 e20 a[27] 341 d16 vde 374 ab9 ddq[10] 407 e19 vdd 342 d15 cs#[3] 375 ab10 vss 408 e18 vss 343 d14 vde 376 ab11 ddqm[0] 409 e17 dir 344 d13 vss 377 ab12 vdd 410 e16 vss 345 d12 pp[07] 378* ab13 vdd 411 e15 cs#[2] 346 d11 vss 379 ab14 vde 412 e14 vss 347 d10 pp[19] 380 ab15 da[8] 413 e13 vde 348 d9 vss 381 ab16 vde 414 e12 pp[08]
mb93461 9 (continued) * : pin no. 378 and 391 are the anal og power supply pins of pll. pin no. position pin name 415 e11 vde 416 e10 pp[14] 417 e9 vdd 418 e8 msdirp 419 e7 sddat[3] 420 e6 sdmsse- lect
mb93461 10 2. pfbga400 81 pins from l11 to w19 are for thermal. connect them to vss. index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 30 111 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 140 31 110 215 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 242 141 32 109 214 311 400 108 213 310 399 107 212 309 398 106 211 308 397 105 210 307 396 104 209 306 395 103 208 305 394 102 207 304 393 101 206 303 392 100 205 302 391 99 204 301 390 98 203 300 389 97 202 299 388 96 201 298 397 95 200 297 386 94 199 296 385 93 198 295 384 92 197 294 383 91 196 293 382 90 195 292 381 89 194 291 380 336 243 142 33 337 244 143 34 338 245 144 35 339 246 145 36 340 247 146 37 341 248 147 38 342 249 148 39 343 250 149 40 344 251 150 41 345 252 151 42 346 253 152 43 347 254 153 44 348 255 154 45 349 256 155 46 350 257 156 47 351 258 157 48 352 259 158 49 353 260 159 50 354 261 160 51 355 262 161 52 356 263 162 53 88 193 290 379 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 363 362 361 360 359 358 357 264 163 54 87 192 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 164 55 86 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 56 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 1 2 3 4 5 6 7 8 910111213141514171819 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss 20 21 22 23 24 25 26 27 28 29 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj (bga-400p-m04) (top view)
mb93461 11 (continued) pin no. position pin name pin no. position pin name pin no. position pin name 1 a1 n.c. 35 aj7 vde 69 u29 d[12] 2 b1 n.c. 36 aj8 ddq[10] 70 t29 d[16] 3 c1 udp1 37 aj9 ddq[14] 71 r29 vde 4 d1 hpwren 38 aj10 dwe# 72 p29 d[22] 5 e1 vdd 39 aj11 dcs#[0] 73 n29 d[26] 6 f1 vcg[3] 40 aj12 dclk 74 m29 d[28] 7 g1 vcg[7] 41* aj13 vdd 75 l29 be[0] 8h1 vcd- clkin 42 aj14 da[0] 76 k29 vde 9 j1 vcr[1] 43 aj15 vss 77 j29 a[3] 10 k1 vcr[5] 44 aj16 da[6] 78 h29 a[7] 11 l1 vcr[7] 45 aj17 da[10] 79 g29 a[9] 12 m1 vcb[3] 46 aj18 dba[1] 80 f29 a[13] 13 n1 vss 47 aj19 ddqm[2] 81 e29 vdd 14 p1 vdr[0] 48 aj20 vde 82 d29 a[18] 15 r1 vdr[4] 49 aj21 ddq[19] 83 c29 n.c. 16 t1 vdg[0] 50 aj22 ddq[23] 84 b29 n.c. 17 u1 vdg[2] 51 aj23 ddq[25] 85 a29 n.c. 18 v1 vdg[6] 52 aj24 ddq[29] 86 a28 n.c. 19 w1 vde 53 aj25 vde 87 a27 a[20] 20 y1 vdb[4] 54 aj26 tdc 88 a26 vss 21 aa1 vdclk- out 55 aj27 n.c. 89 a25 a[26] 22 ab1 topfield 56 aj28 n.c. 90 a24 a[30] 23 ac1 vde 57 aj29 n.c. 91 a23 breq# 24 ad1 bcki 58 ah29 n.c. 92 a22 vdd 25 ae1 bcko 59 ag29 tck 93 a21 dir 26 af1 n.c. 60 af29 ecv 94 a20 bs# 27 ag1 n.c. 61 ae29 vss 95 a19 cs#[0] 28 ah1 n.c. 62 ad29 vde 96 a18 cs#[4] 29 aj1 n.c. 63 ac29 cmode[1] 97 a17 vde 30 aj2 n.c. 64 ab29 vss 98 a16 pp[01] 31 aj3 sda[1] 65 aa29 vde 99 a15 vde 32 aj4 vdd 66 y29 d[2] 100 a14 pp[07] 33 aj5 ddq[1] 67 w29 d[6] 101 a13 pp[11] 34 aj6 ddq[5] 68 v29 d[8] 102 a12 pp[15]
mb93461 12 (continued) pin no. position pin name pin no. position pin name pin no. position pin name 103 a11 pp[17] 136 ae2 lrcki 169 ad28 ram- boot# 104 a10 vdd 137 af2 sdo 170 ac28 cmode[0] 105 a9 sdwp 138 ag2 n.c. 171 ab28* vdd 106 a8 sddat[1] 139 ah2 n.c. 172 aa28 vdd 107 a7 sdcki 140 ah3 sda[0] 173 y28 d[1] 108 a6 vdd 141 ah4 vss 174 w28 d[5] 109 a5 udm 142 ah5 ddq[0] 175 v28 vde 110 a4 n.c. 143 ah6 ddq[4] 176 u28 d[11] 111 a3 n.c. 144 ah7 vss 177 t28 d[15] 112 a2 n.c. 145 ah8 ddq[9] 178 r28 vss 113 b2 n.c. 146 ah9 ddq[13] 179 p28 d[21] 114 c2 vde 147 ah10 ddq[15] 180 n28 d[25] 115 d2 vdd 148 ah11 ddqm[1] 181 m28 d[27] 116 e2 vde 149 ah12 vdd 182 l28 d[31] 117 f2 vcg[2] 150 ah13 vss 183 k28 vss 118 g2 vcg[6] 151 ah14 dras# 184 j28 a[2] 119 h2 vss 152 ah15 da[3] 185 h28 a[6] 120 j2 vcr[0] 153 ah16 da[5] 186 g28 a[8] 121 k2 vcr[4] 154 ah17 da[9] 187 f28 a[12] 122 l2 vde 155 ah18 vde 188 e28 vss 123 m2 vcb[2] 156 ah19 dcke 189 d28 a[17] 124 n2 vcb[6] 157 ah20 vss 190 c28 n.c. 125 p2 vcb[7] 158 ah21 ddq[18] 191 b28 n.c. 126 r2 vdr[3] 159 ah22 ddq[22] 192 b27 a[19] 127 t2 vdr[7] 160 ah23 vde 193 b26 a[23] 128 u2 vdg[1] 161 ah24 ddq[28] 194 b25 a[25] 129 v2 vdg[5] 162 ah25 vss 195 b24 a[29] 130 w2 vss 163 ah26 test- mode 196 b23 err# 131 y2 vdb[3] 164 ah27 n.c. 197 b22 vss 132 aa2 vdb[7] 165 ah28 n.c. 198 b21 bstack# 133 ab2 enable 166 ag28 tdo 199 b20 we# 134 ac2 vdp- clkin 167 af28 trst# 200 b19 bgnt# 135 ad2 sdi 168 ae28 ed 201 b18 cs#[3]
mb93461 13 (continued) pin no. position pin name pin no. position pin name pin no. position pin name 202 b17 vss 236 ab3 vdvsync 270 ab27 cmode[3] 203 b16 pp[00] 237 ac3 vss 271 aa27 clkin 204 b15 vss 238 ad3 fscki 272 y27 d[0] 205 b14 pp[06] 239 ae3 vde 273 w27 d[4] 206 b13 pp[10] 240 af3 lrcko 274 v27 vss 207 b12 pp[12] 241 ag3 vde 275 u27 d[10] 208 b11 pp[14] 242 ag4 scl[1] 276 t27 d[14] 209 b10 vss 243 ag5 vde 277 r27 d[18] 210 b9 sdclk 244 ag6 ddq[3] 278 p27 d[20] 211 b8 sddat[0] 245 ag7 ddq[7] 279 n27 d[24] 212 b7 vss 246 ag8 ddq[8] 280 m27 vde 213 b6 sdmsse- lect 247 ag9 ddq[12] 281 l27 d[30] 214 b5 vss 248 ag10 vde 282 k27 be[2] 215 b4 vde 249 ag11 ddqm[0] 283 j27 be[3] 216 b3 n.c. 250 ag12 dcs#[2] 284 h27 a[5] 217 c3 n.c. 251 ag13 dclkfb 285 g27 vde 218 d3 vss 252 ag14 dcs#[3] 286 f27 a[11] 219 e3 vss 253 ag15 da[2] 287 e27 a[15] 220 f3 vcg[1] 254 ag16 da[4] 288 d27 a[16] 221 g3 vcg[5] 255 ag17 da[8] 289 c27 n.c. 222 h3 vcvsync 256 ag18 vss 290 c26 a[22] 223 j3 vdd 257 ag19 da[12] 291 c25 a[24] 224 k3 vcr[3] 258 ag20 ddq[16] 292 c24 a[28] 225 l3 vss 259 ag21 ddq[17] 293 c23 vdd 226 m3 vcb[1] 260 ag22 ddq[21] 294 c22 bstreq# 227 n3 vcb[5] 261 ag23 vss 295 c21 a[31] 228 p3 vss 262 ag24 ddq[27] 296 c20 rd# 229 r3 vdr[2] 263 ag25 ddq[31] 297 c19 vde 230 t3 vdr[6] 264 ag26 vdd 298 c18 cs#[2] 231 u3 vde 265 ag27 mtest- mode 299 c17 cs#[6] 232 v3 vdg[4] 266 af27 tms 300 c16 cpuhold 233 w3 vdb[0] 267 ae27 erst# 301 c15 pp[03] 234 y3 vdb[2] 268 ad27 vss 302 c14 pp[05] 235 aa3 vdb[6] 269 ac27 vdd 303 c13 pp[09]
mb93461 14 (continued) * : pin no. 41 and 171 are the anal og power supply pins of pll. pin no. position pin name pin no. position pin name pin no. position pin name 304 c12 vde 338 af7 ddq[6] 372 l26 d[29] 305 c11 pp[19] 339 af8 vdd 373 k26 be[1] 306 c10 pp[21] 340 af9 ddq[11] 374 j26 bclko 307 c9 pp[16] 341 af10 vss 375 h26 a[4] 308 c8 sdcmd 342 af11 dcas# 376 g26 vss 309 c7 sddat[3] 343 af12 dcs#[1] 377 f26 a[10] 310 c6 sdcd 344 af13 vss 378 e26 a[14] 311 c5 vdd 345 af14 vss 379 d26 a[21] 312 c4 udp 346 af15 da[1] 380 d25 vde 313 d4 udm1 347 af16 vde 381 d24 a[27] 314 e4 hovr- cur# 348 af17 da[7] 382 d23 vss 315 f4 vcg[0] 349 af18 dba[0] 383 d22 ibw 316 g4 vcg[4] 350 af19 da[11] 384 d21 vde 317 h4 vchsync 351 af20 ddqm[3] 385 d20 rdy# 318 j4 vde 352 af21 vdd 386 d19 vss 319 k4 vcr[2] 353 af22 ddq[20] 387 d18 cs#[1] 320 l4 vcr[6] 354 af23 ddq[24] 388 d17 cs#[5] 321 m4 vcb[0] 355 af24 ddq[26] 389 d16 cs#[7] 322 n4 vcb[4] 356 af25 ddq[30] 390 d15 pp[02] 323 p4 vde 357 af26 tdi 391 d14 pp[04] 324 r4 vdr[1] 358 ae26 hrst# 392 d13 pp[08] 325 t4 vdr[5] 359 ad26 eclk 393 d12 vss 326 u4 vss 360 ac26 prst# 394 d11 pp[18] 327 v4 vdg[3] 361 ab26 cmode[2] 395 d10 pp[20] 328 w4 vdg[7] 362 aa26 vss 396 d9 pp[13] 329 y4 vdb[1] 363 y26 rstout# 397 d8 msdirp 330 aa4 vdb[5] 364 w26 d[3] 398 d7 sddat[2] 331 ab4 vdhsync 365 v26 d[7] 399 d6 vde 332 ac4 vdd 366 u26 d[9] 400 d5 uscki 333 ad4 vdcdis- able 367 t26 d[13] 334 ae4 vss 368 r26 d[17] 335 af4 scl[0] 369 p26 d[19] 336 af5 vss 370 n26 d[23] 337 af6 ddq[2] 371 m26 vss
mb93461 15 pin description 1. format pin name : indicates name of external pin if several signals share the same pin, t he names are separated by a slash (/) . ?# ? in a signal line name indicates ?active low.? direction : indicates i/o of signal with reference to lsi chip input : indicates pin for input signal to lsi chip output : indicates pin for output signal from lsi chip input/output : indicates pin for bidirectional signal type : indicates pin input/output circuit type each symbol has the following meaning : note : explains outline of function and relationship with other pins. bs : indicates whether the targ et of boundary-scan or not. pin no. pin name direction type bs description symbol description sd solid drive type of output pin. normal output. the pin never becomes high impedance. ts tri - state type of output or input/output pin. the pin may become high impedance. pu pull - up type of input pin or input/output pin. a pu ll-up resistor is built into the circuit. pd pull - down type of input pin or input/output pin. a pu ll-down resistor is built into the circuit. od open-drain type of output pin. the pi n may become high impedance.
mb93461 16 2. local bus interface (continued) pin no. pin name direction type bs description bga pfbga 261 91 breq# input ? yes bus request this signal inputs a bus release request from the bus master device. 264 200 bgnt# output sd yes bus grant this signal indicates that the local bus is released. 177 175 260 337 406 81 174 259 80 173 258 335 257 334 255 168 254 167 72 403 332 253 166 71 252 165 70 401 330 251 295 90 195 292 381 89 194 291 193 290 379 87 192 82 189 288 287 378 80 187 286 377 79 186 78 185 284 375 77 184 a[31] a[30] a[29] a[28] a[27] a[26] a[25] a[24] a[23] a[22] a[21] a[20] a[19] a[18] a[17] a[16] a[15] a[14] a[13] a[12] a[11] a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] input/ output ts yes address a word address is output. when the local bus is released, this pin becomes input.
mb93461 17 (continued) pin no. pin name direction type bs description bga pfbga 399 328 249 162 67 248 161 66 397 326 247 160 65 246 159 64 63 158 245 324 395 62 157 244 61 156 243 322 393 60 155 242 182 281 372 74 181 73 180 279 370 72 179 278 369 277 368 70 177 276 367 69 176 275 366 68 365 67 174 273 364 66 173 272 d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] input/ output ts yes data this is the data bus; d[31] is msb. when connecting a 16-bit slave device to this signal, connect it to d[31 : 16] (higher) . when connecting a 8-bit slave device to this signal, connect it to d[31 : 24] (higher) . if all of the cs# that allowed to assert are con- figured to 8-bit or 16-bit (by lcr0-7.bw) , d[15 : 00] are not driven.
mb93461 18 (continued) pin no. pin name direction type bs description bga pfbga 68 163 250 164 75 373 282 283 be[0]/be#[0] be[1]/be#[1] be[2]/be#[2] be[3]/be#[3] input/ output ts yes byte enable this specifies byte lanes for data transfer. the correspondence betw een this signal and the data bus when accessing the 32-bit slave device is shown below (the cs area can be set only to the big endian (lcrx.le = 0) .) : be[0] d [31 : 24] be[1] d [23 : 16] be[2] d [15 : 08] be[3] d [07 : 00] be[0 : 1] is used to access a 16-bit slave de- vice; the correspondence between this signal and the data bus is shown below : 1) the cs area set to big endian (lcrx.le = 0) be[0] d [31 : 24] (higher byte) be[1] d [23 : 16] (lower byte) 2) the cs area set to little endian (lcrx.le = 1) be[0] d [23 : 16] (higher byte) be[1] d [31 : 24] (lower byte) be[2] is used to access halfword address. be[2] a[1] be[0] is used to access a 8-bit slave device; the correspondence be tween this signal and the data bus is shown below : be[0] d [31 : 24] be[2 : 3] is used to access byte address. be[2] a[1] be[3] a[0] these pins become input when the bus is re- leased. to access this lsi as the slave de- vice when this bus is released, it must be treated as a 32-bit slave device. be[0] must be pulled- down/pulled-up accord- ing to be/#be polarity (when rstout# is asserted, the value of be[0] is reflected in lgcr.bed) . 85 94 bs# input/ output ts yes bus cycle start this is asserted for only 1 clkin cycle at the beginning of a bus cycle to indicate the start of the bus cycle. this pin is input when the bus is released. 263 296 rd# output ts yes read this pin is asserted during the second or later clkin cycles of read local bus cycles. this pin becomes high impedance when the local bus is released.
mb93461 19 (continued) pin no. pin name direction type bs description bga pfbga 178 199 we# output ts yes write enable this pin is asserted duri ng a write cycles. it can be used as a strobe pulse for write data. this pin becomes high impedance when the bus is released. 409 93 dir input/ output ts yes direction indicates transfer direction of d[31 : 00] pins l : input (read) , h : output (write) this pin becomes input when the bus is re- leased. this lsi determines whether the lo- cal bus cycles that performed by external devices are reads or writes, based on the dir signal. this pin becomes ?l? when bus is idle. 340 385 rdy# input/ output ts yes ready this pin is in the input state while the bus is not released; the bus cycle completion no- tice is ?input? from the slave device to this pin. this pin becomes output while this lsi is op- erating as the slave bus when the bus re- leased; it notifies the bus master device of the bus cycle completion. when rstout# is asserted, the value of rdy# is reflected in lcr0.rc. 338 196 err# input ? yes error this is sampled at the end of the bus cycle; the error notice is input from the slave de- vice to this pin. this pin is ignored when the bus is released. 342 411 86 179 201 298 387 95 cs#[3] cs#[2] cs#[1] cs#[0] output sd yes chip select this signal selects slave device under con- trol of mb93461. the corresponding address is determined from the settings of the programmable ad- dress decoder built into mb93461. connect the boot rom to the cs#[0] pin. 266 87 180 265 389 299 388 96 cs#[7]/irq#[7] cs#[6]/irq#[6] cs#[5]/irq#[5] cs#[4]/irq#[4] input/ output ts/ pu yes chip select / interrupt request 7 - 4 this signal is used as chip select or interrupt request. chip select selects slave device under control of this lsi. this signal works as irq#[7 : 4] after power-on reset and need to set lgcr.cse to use as cs#. when use as cs#, the corresponding ad- dress is determined from the setting of the programmable address decoder built into this lsi.
mb93461 20 (continued) pin no. pin name direction type bs description bga pfbga 176 383 ibw input ? yes initial bus width this pin is used to specify the data bus width of the boot rom to be connected to the cs#[0] pin. the data bus width specified for this signal can be changed later via software. 16 bits : input low level 32 bits : input high level 83 294 bstreq# input/ output ts yes burst request this pin is used to request burst transfer. 84 198 bstack# input/ output ts yes burst acknowledge this pin is used to enable burst transfer. 69 374 bclko output sd yes bus clock out this clock is supplied to the device connected with the local bus. output stops during power-on reset.
mb93461 21 3. sdram interface (continued) pin no. pin name direction type bs description bga pfbga 224 36 133 222 252 250 343 39 dcs#[3] dcs#[2] dcs#[1] dcs#[0] output sd yes chip select this signal is output based on the setting of the programmable address decoder incorporated in this lsi. dcs#[2] and dcs#[3] are only used for con- necting the 168-pin registered dimm. 42 227 46 349 dba[1] dba[0] output sd yes bank address the bank address is output. 228 139 138 41 380 307 226 137 40 225 136 39 38 257 350 45 154 255 348 44 153 254 152 253 346 42 da[12] da[11] da[10] da[9] da[8] da[7] da[6] da[5] da[4] da[3] da[2] da[1] da[0] output sd yes multiplexed address the address multiplexed for sdram is output. 135 151 dras# output sd yes row address strobe row address strobe signal to sdram. 35 342 dcas# output sd yes column address strobe column address strobe signal to sdram. 132 38 dwe# output sd yes write enable write enable signal to sdram. 309 156 dcke output sd yes clock enable clock enable signal to sdram. 376 303 382 43 249 148 47 351 ddqm[0] ddqm[1] ddqm[2] ddqm[3] output sd yes data mask these pins (signal) ar e combined with other signals to specify the byte lane to be written. at read, all the bits are driven low. the correspondence between this signal and the data bus when connecting 32-bit sdram is shown below : ddqm[0] ddq[31 : 24] ddqm[1] ddq[23 : 16] ddqm[2] ddq[15 : 08] ddqm[3] ddq[07 : 00] the correspondence between this signal and the data bus when connecting 16-bit sdram is shown below : ddqm[0] ddq[31 : 24] ddqm[1] ddq[23 : 16]
mb93461 22 (continued) pin no. pin name direction type bs description bga pfbga 144 47 386 313 232 143 46 231 142 45 384 311 230 141 44 140 221 34 131 220 301 374 33 130 32 129 218 299 372 31 128 217 263 356 52 161 262 355 51 354 50 159 260 353 49 158 259 258 147 37 146 247 340 36 145 246 245 338 34 143 244 337 33 142 ddq[31] ddq[30] ddq[29] ddq[28] ddq[27] ddq[26] ddq[25] ddq[24] ddq[23] ddq[22] ddq[21] ddq[20] ddq[19] ddq[18] ddq[17] ddq[16] ddq[15] ddq[14] ddq[13] ddq[12] ddq[11] ddq[10] ddq[9] ddq[8] ddq[7] ddq[6] ddq[5] ddq[4] ddq[3] ddq[2] ddq[1] ddq[0] input/ output ts yes data this signal is connected to the sdram data bus; ddq[31] is msb. when connecting 16-bit sdram, connect it to ddq[31 : 16] when the bus width is set to 16 bits by dcfg.bw, ddq[15 : 00] is fixed to the high-im- pedance state. 304 40 dclk output sd yes sdram clock this is the output of the clock signal supplied to sdram. the output is halted while the pll is halted. the output is also halted during a power-on re- set. 134 251 dclkfb input ? yes feedback for sdram clock to adjust the dclk phas e, feedback input to the pll built into this lsi chip.
mb93461 23 4. general-purpose peripheral resource (continued) pin no. pin name direction type bs description bga pfbga 88 89 182 267 203 98 390 301 irq#[0]/pp[00] irq#[1]/pp[01] irq#[2]/pp[02] irq#[3]/pp[03] input/ output ts yes interrupt request 0 to 3 / gpio 0 to 3 these pins are used as the interrupt input and as a general-purpose i/o port (gpio) . 90 391 tout[0]/ gate[0]/pp[04] input/ output ts yes timer ch 0 output / timer ch 0 gate / gpio 4 this pin is used as the timer ch 0 pin and as a general-purpose i/o port (gpio) . 183 302 tout[1]/ gate[1]/pp[05] input/ output ts yes timer ch 1 output / timer ch 1 gate / gpio 5 this pin is used as the timer ch 1 pin and as a general-purpose i/o port (gpio) . 268 205 rxd[0]/pp[06] input/ output ts yes uart ch 0 receive data / gpio 6 this pin is used as the uart ch 0 receive data and as a general-purpose i/o port (gpio) . 345 100 txd[0]/pp[07] input/ output ts yes uart ch 0 transmit data / gpio 7 this pin is used as the uart ch 0 transmit data and as a general-purpose i/o port (gpio) . 414 392 cts#[0]/pp[08] input/ output ts yes uart ch 0 clear to send signal / gpio 8 this pin is used as the uart ch 0 cts sig- nal and as a general-purpose i/o port (gpio) . 91 303 rts#[0]/pp[09] input/ output ts yes uart ch 0 request to send signal / gpio 9 this pin is used as the uart ch 0 rts sig- nal and as a general-purpose i/o port (gpio) . 184 206 rxd[1]/pp[10] input/ output ts yes uart ch 1 receive data / gpio 10 this pin is used as the uart ch 1 receive data and as a general-purpose i/o port (gpio) . 269 101 txd[1]/pp[11] input/ output ts yes uart ch 1 transmit data / gpio 11 this pin is used as the uart ch 1 transmit data and as a general-purpose i/o port (gpio) . 92 207 dreq#[0]/pp[12] input/ output ts yes dmac ch 0 transfer request / gpio 12 this pin is used as the uart ch 0 transfer request and as a general-purpose i/o port (gpio) . 94 396 dack#[0]/pp[13] input/ output ts yes dmac ch 0 acknowledge / gpio 13 this pin is used as th e dmac ch 0 transfer acknowledge signal and as a general-pur- pose i/o port (gpio) .
mb93461 24 (continued) pin no. pin name direction type bs description bga pfbga 416 208 done#[0]/ dreq#[4]/pp[14] input/ output ts yes dmac ch 0 transfer done / dmac ch4 transfer request / gpio 14 this pin is used as the dmac ch 0 transfer end signal, as the dmac ch 4 transfer re- quest, and as a general-purpose i/o port (gpio) . 185 102 dreq#[1]/pp[15] input/ output ts yes dmac ch 1 transfer request / gpio 15 this pin is used as the dmac ch 1 transfer request and as a general-purpose i/o port (gpio) . 187 307 dack#[1]/pp[16] input/ output ts yes dmac ch 1 acknowledge / gpio 16 this pin is used as the dmac ch 1 transfer acknowledge signal and as a general-pur- pose i/o port (gpio) . 93 103 done#[1]/ dreq#[5]/ pp[17] input/ output ts yes dmac ch 1 transfer done / dmac ch 5 transfer request / gpio 17 this pin is used as the dmac ch 1 transfer end signal, as the dmac ch 5 transfer re- quest, and as a general-purpose i/o port (gpio) . 270 394 dreq#[2]/pp[18] input/ output ts yes dmac ch 2 transfer request / gpio 18 this pin is used as the dmac ch 2 transfer request and as a general-purpose i/o port (gpio) . 347 305 dreq#[3]/pp[19] input/ output ts yes dmac ch 3 transfer request / gpio 19 this pin is used as the dmac ch 3 transfer request and as a general-purpose i/o port (gpio) . 186 395 dack#[2]/ dreq#[6]/ pp[20] input/ output ts yes dmac ch 2 transfer acknowledge / dmac ch 6 transfer request / gpio 20 this pin is used as the dmac ch 2 transfer acknowledge signal, as the dmac ch 6 transfer request, and as a general-purpose i/o port (gpio) . 271 306 dack#[3]/ dreq#[7]/ pp[21] input/ output ts yes dmac ch 3 transfer acknowledge / dmac ch 7 transfer request / gpio 21 this pin is used as the dmac ch 3 transfer acknowledge signal, as the dmac ch 7 transfer request, and as a general-purpose i/o port (gpio) .
mb93461 25 5. ice interface pin no. pin name direction type bs description bga pfbga 238 267 erst# input pd yes esb reset for the printed circuit board using the ice, connect the connector in tended for the ice to this pin; for the printed circuit board not using the ice, open this pin. 317 358 hrst# input ? yes hard reset this is the reset input dedicated to the ice. this pin function is equivalent to reset by the debugger hardware rese t command. reset by this pin will not reset debug related set- tings, so this pin can be used for debugging the reset sequence, etc. when using this pin, connect the reset switch signal to this pin; when not using this pin, fix it to the high level. 388 60 ecv input pu yes esb command valid command valid signal for ice interface. for the printed circuit board using the ice, connect the connector in tended for the ice to this pin; for the printed circuit board not using the ice, open this pin. 151 168 ed input/ output ts/ pd yes esb data data i/o signal for ice interface. for the printed circuit board using the ice, connect the connector in tended for the ice to this pin; for the printed circuit board not using the ice, open this pin. 389 359 eclk output ts yes esb clock clock signal (output) for ice interface. for the printed circuit board using the ice, connect the connector in tended for the ice to this pin; for the printed circuit board not using the ice, open this pin.
mb93461 26 6. reset-related pin 7. cpu status pin no. pin name direction type bs description bga pfbga 57 360 prst# input ? yes power - on reset this is the level trigger initialization signal. apply the l level to this pin for 16 clkin clock cycles or more. this pin is used to cause a power-on reset; it initializes all registers and sequencers except cache and gr/fr. 321 363 rstout# output sd yes reset output this signal is asserted during a power-on re- set. the power-on reset operation is prolonged in the lsi until the oscillation stabilization wait time for the internal pll has elapsed. conse- quently, use this signal to detect that the pow- er-on reset operation has been completed in the lsi. when hrst# is asserted with the ice used, this signal (rstout#) is asserted as in the power-on reset. 239 169 ramboot# input ? yes ram boot a software reset can be caused by applying a low level to this pin. when this signal and the prst# pin are as- serted simultaneously, the power-on reset op- eration is preferred. at a power-on reset, the level input to this pin is reflected in the sa bit of the register hsr0, and then the reset vector address is deter- mined as shown below based on the sa bit. low level : 0x00000000 high level : 0xff000000 pin no. pin name direction type bs description bga pfbga 181 300 cpuhold output sd yes cpu hold signal indicating that cpu stops in hold state.
mb93461 27 8. clock 9. pin related to jtag 10. test pin no. pin name direction type bs description bga pfbga 154 271 clkin input ? yes clock input external clock are input to this pin. 58 153 240 319 270 361 63 170 cmode[3] cmode[2] cmode[1] cmode[0] input ? yes clock mode determines operating frequency of each sec- tion in lsi. pin no. pin name direction type bs description bga pfbga 237 357 tdi input pu no test data input this is the test data input pin. this signal is sampled on the rising edge of tck. 236 166 tdo output ts no test data output this is the test data output pin. this drives active when the atp controller is the shift-ir or shift-dr state. this signal changes on the falling edge of tck. 150 266 tms input pu no test mode select this is the test mode select pin. this signal is sampled on the rising edge of tck. 316 59 tck input pu no test clock this is the test clock pin. 55 167 trst# input pu no test reset this is the tap cont roller asynchronous re- set. this pin initializes the tap controller. when not using the jtag function on the printed circuit board, input the same signal as prst# to this pin. pin no. pin name direction type bs description bga pfbga 145 163 testmode input ? yes test mode input fix it at low level on the printed circuit board. 234 54 tdc input ? no test input fix it at low level on the printed circuit board. 315 265 mtestmode input ? yes ultest mode input fix it at low level on the printed circuit board.
mb93461 28 11. vdc pin (continued) pin no. pin name direction type bs description bga pfbga 114 15 362 287 204 113 14 13 127 230 325 15 126 229 324 14 vdr[7]/vdcr[7]/avpp[23] vdr[6]/vdcr[6]/avpp[22] vdr[5]/vdcr[5]/avpp[21] vdr[4]/vdcr[4]/avpp[20] vdr[3]/vdcr[3]/avpp[19] vdr[2]/vdcr[2]/avpp[18] vdr[1]/vdcr[1]/avpp[17] vdr[0]/vdcr[0]/avpp[16] input/ output ts yes r component output / cr compo- nent output / gpio these pins are display video data output pins. in the rgb mode, the red component is output. in the 24-bit yc mode, cr component is output. these pins are shared by gpio unit and set as gpio input setting after reset. 116 17 364 289 206 115 16 205 328 18 129 232 327 17 128 16 vdg[7]/vdy[7]/vdx[7] vdg[6]/vdy[6]/vdx[6] vdg[5]/vdy[5]/vdx[5] vdg[4]/vdy[4]/vdx[4] vdg[3]/vdy[3]/vdx[3] vdg[2]/vdy[2]/vdx[2] vdg[1]/vdy[1]/vdx[1] vdg[0]/vdy[0]/vdx[0] output ts yes g component output / y compo- nent output / yc multiplexed output these pins are display video data output pins. in the rgb mode, the green component is output. also, in the 16-bit or 24-bit yc mode, the y component is output. when 8-bit yc mode is selected, multi- plexed pixel data is output. 118 19 366 291 208 117 18 207 132 235 330 20 131 234 329 233 vdb[7]/vdcx[7]/vdcb[7]/ avpp[39] vdb[6]/vdcx[6]/vdcb[6]/ avpp[38] vdb[5]/vdcx[5]/vdcb[5]/ avpp[37] vdb[4]/vdcx[4]/vdcb[4]/ avpp[36] vdb[3]/vdcx[3]/vdcb[3]/ avpp[35] vdb[2]/vdcx[2]/vdcb[2]/ avpp[34] vdb[1]/vdcx[1]/vdcb[1]/ avpp[33] vdb[0]/vdcx[0]/vdcb[0]/ avpp[32] input/ output ts yes b component output / c compo- nent output / cb component output / gpio these pins are display video data output pins. in the rgb mode, the blue component is output. in the 16-bit yc mode, the cb compo- nent and the c r component are time-shared and output. more- over, in the 24-bit yc mode, cb component is output. these pins are shared by gpio unit and set as gpio input setting after reset. 292 331 vdhsync/vdhsync# output ts yes horizontal synchronous signal output this pin is for display synchronous signal output. its polarity is pro- grammable. 367 236 vdvsync/vdvsync# output ts yes vertical synchronous signal out- put this pin is for display synchronous signal output. its polarity is pro- grammable.
mb93461 29 (continued) pin no. pin name direction type bs description bga pfbga 368 134 vdpclkin input ? yes vertical pixel clock input this pin inputs a basic clock to generate display pixel clock out- put. 209 21 vdclkout output ts yes display pixel clock output pixel data is output in synchroni- zation with this signal. 20 133 enable/enable# output ts yes pixel output enable this signal shows that effective pixel data is output . its polarity is programmable. 119 22 topfield/topfield# output ts yes top field this pin shows that the top field is displayed. its polarity is program- mable. 120 333 disable input ? yes video output disable when this signal is asserted, vdr[7 : 0]/vdcr[7 : 0], vdg[7 : 0]/vdy[7 : 0], vdb[7 : 0]/vdcx[7 : 0]/vdcb[7 : 0], vdhsync, vd- vsync, and vdclkout go in to the high-impedance state. howev- er, ordinary operation continues inside.
mb93461 30 12. vcc pin pin no. pin name direction type bs description bga pfbga 201 10 109 200 283 358 9 108 11 320 10 121 224 319 9 120 vcr[7]/vccr[7]/avpp[15] vcr[6]/vccr[6]/avpp[14] vcr[5]/vccr[5]/avpp[13] vcr[4]/vccr[4]/avpp[12] vcr[3]/vccr[3]/avpp[11] vcr[2]/vccr[2]/avpp[10] vcr[1]/vccr[1]/avpp[9] vcr[0]/vccr[0]/avpp[8] input/ output ts yes r component input / cr component input / gpio these pins are capture video data input pins. in the rgb mode, the red component is input. in the 24- bit yc mode, cr component is in- put. these pins are shared by gpio unit and set as gpio input setting after reset. 281 356 7 106 197 280 355 6 7 118 221 316 6 117 220 315 vcg[7]/vcy[7]/vcx[7] vcg[6]/vcy[6]/vcx[6] vcg[5]/vcy[5]/vcx[5] vcg[4]/vcy[4]/vcx[4] vcg[3]/vcy[3]/vcx[3] vcg[2]/vcy[2]/vcx[2] vcg[1]/vcy[1]/vcx[1] vcg[0]/vcy[0]/vcx[0] input ? yes g component input / y component input / yc multiplexed input these pins are capture video data input pins. in the rgb mode, the green component is input. also, in the 24-bit yc mode, the y compo- nent is input. when 8-bit yc mode is selected, multiplexed pixel data is output. 112 12 111 202 285 360 11 110 125 124 227 322 12 123 226 321 vcb[7]/vccx[7]/vccb[7]/ avpp[31] vcb[6]/vccx[6]/vccb[6]/ avpp[30] vcb[5]/vccx[5]/vccb[5]/ avpp[29] vcb[4]/vccx[4]/vccb[4]/ avpp[28] vcb[3]/vccx[3]/vccb[3]/ avpp[27] vcb[2]/vccx[2]/vccb[2]/ avpp[26] vcb[1]/vccx[1]/vccb[1]/ avpp[25] vcb[0]/vccx[0]/vccb[0]/ avpp[24] input/ output ts yes b component input / c component input / cb component input / gpio these pins are capture video data input pins. in the rgb mode, the blue component is input. also, in the 16-bit yc mode, cb compo- nent and cr component are time- shared and input. moreover, in the 24-bit yc mode, cb component is input. these pins are shared by gpio unit and set as gpio input setting after reset. 198 317 vchsync/vchsync# input ? yes horizontal synchronous signal in- put this pin is a capture synchronous signal input pin. its polarity is pro- grammable. 107 222 vcvsync/vcvsync# input ? yes vertical synchronous signal input this pin is a capture synchronous signal input pin. its polarity is pro- grammable. 357 8 vcdclkin input ? yes capture pixel clock input this pin is a sampling clock for capture. the edge to use is pro- grammable.
mb93461 31 13. audio pin pin no. pin name direction type bs description bga pfbga 213 137 sdo/dx output ts yes audio data output audio serial data is output. 370 240 lrcko/fs0 output sd yes lr clock output / ch0 synchronous signal lr clock is output when it is i 2 s and msb-jus- tified output. moreover, if it is output that sup- ports pcm highway, ch0 synchronous signal fs0 is output. 295 25 bcko/mclk output sd yes bit clock output this pin is for bit clock output for audio input/ output. input/output that supports pcm high- way always operates in the master mode, therefore, mclk output by mb93461 is used for input as well. 294 135 sdi/dr input ? yes audio data input this pin is for audio serial data input. 212 136 lrcki/fs1 input/ output ts yes lr clock input / ch1 synchronous signal out- put in the case of i 2 s and msb-justified input, it becomes lr clock input. moreover, in the case of input/output that supports pcm high- way, ch1 synchronous si gnal fs1 is output. 369 24 bcki input ? yes bit clock input this pin is for the input of bit clock used for i 2 s and msb-justified audio input. 211 238 fscki input ? yes basic clock input for audio output this pin is for the input of basic clocks (256f s / 384f s /512f s /756f s ) to generate bit clock of msb-justified or i 2 s audio output, lr clock and mclk, fs0 and fs1 at supporting pcm highway.
mb93461 32 14. usb/usb-host 15. i 2 c pin pin no. pin name direction type bs description bga pfbga 276 312 udp input/ output ts no usb d + signal this pin is for differential signal ( + ) of usb function. 191 109 udm input/ output ts no usb d ? signal this pin is for differential signal ( ? ) of usb function. 190 400 uscki input ? yes usb clock input this pin inputs 48 mhz clock that is required by usb interface. 353 3 udp1 input/ output ts no usb d + signal this pin is for differential signal ( + ) of usb host. 278 313 udm1 input/ output ts no usb d - signal this pin is for differential signal ( ? ) of usb host. 354 314 hovrcur# input ? yes usb over current detection this signal is asserted when over current oc- curs in the down stream. it is read to the over current indicator of hcrhstatus. over-cur- rent mode is set by no over current protec- tion of hcrh descriptor a and over currentprotection mode. in the individual over-current mode, it is read into port over current indicator of hcrh port status. this pin must be pulled up on the printed circuit board if not used. 5 4 hpwren output sd yes usb port power enable global power to the usb port is controlled by this signal. when no power switching is set, this signal is always active. pin no. pin name direction type bs description bga pfbga 216 297 242 335 scl[1] scl[0] input/out- put od no i 2 c clock these pins are used for a clock signal of the i 2 c bus. scl[0] corresponds to i 2 c ch 0; scl[1] corresponds to i 2 c ch 1. 126 215 31 140 sda[1] sda[0] input/out- put od no i 2 c data these pins are used for data signals for the i 2 c bus. sda[0] corresponds to i 2 c ch 0; sda[1] corresponds to i 2 c ch 1.
mb93461 33 16. sd/ms pin note : customers are advised to consult with our sales representatives, if you use sd or ms. pin no. pin name direction type bs description bga pfbga 189 107 sdcki/ mscki input ? yes clock input for the sd / memory stick if both of sd and ms are not used, set this pin to the ?h? level on the printed cir- cuit board. 349 105 sdwp/ msdirs input/ output ? yes data direction output of sddat[0] / ms- dio[0] if both of sd and ms are not used, set this pin to the ?h? level on the printed cir- cuit board. 418 397 msdirp input/ output ? yes data direction output of sddat[3 : 1] / msdio[3 : 1] if both of sd and ms are not used, set this pin open on the printed circuit board. 351 310 sdcd/mscd input ? yes sd / memory stick insertion / extraction detection signal if both of sd and ms are not used, set this pin to the ?h? level on the printed cir- cuit board. 95 308 sdcmd/msbs input/ output sd yes sd command i / o / memory stick bus state signal if both of sd and ms are not used, set this pin to the ?h? level on the printed cir- cuit board. 272 210 sdclk/msclk output sd yes transfer clock output for sd / memory stick if both of sd and ms are not used, set this pin open on the printed circuit board. 188 211 sddat[0]/msdio[0] input/ output ts yes data signal for sd / memory stick ( at seri- al ) if both of sd and ms are not used, set this pin to the ?h? level on the printed cir- cuit board. 419 350 273 309 398 106 sddat[3]/msdio[3] sddat[2]/msdio[2] sddat[1]/msdio[1] input/ output ts yes data signal for sd / memory stick ( at par- allel ) if both of sd and ms are not used, set this pin to the ?h? level on the printed cir- cuit board. 420 213 sdmsselect input ? yes sd / memory stick selection signal input if both of sd and ms are not used, set this pin to the ?h? level on the printed cir- cuit board.
mb93461 34 pin state h : indicates high level l : indicates low level hiz : indicates high-impedance state x : indicates either high level or low level a : indicates output of clock note : initial value : indicates pin state immediately afte r power-on reset. the meaning of each symbol is given below : (continued) pin name initial state core sleep mode bus sleep mode pll operation mode pll stop mode breq# ??? ? ? bgnt# h operation h h h a[31 : 2] hiz operation x x x d[31 : 0] hiz operation hiz hiz hiz be[0 : 3]/be#[0 : 3] hiz operation x x x bs# , rd# , we# hiz operation h h h dir hiz operation x x x rdy# hiz operation hiz hiz hiz err# ??? ? ? cs#[3 : 0] h operation h h h cs#[7 : 4]/irq#[7 : 4] hiz operation h or hiz h or hiz h or hiz ibw ??? ? ? bstreq# hiz operation h h h bstack# hiz operation hiz hiz hiz bclko l operation operation l l dcs#[3 : 0] h operation l l l dba[1 : 0] l operation x x x da[12 : 0] x operation x x x dras# , dcas# h operation l l l dwe# h operation h h h dcke h operation l l l ddqm[0 : 3] h operation h h h ddq[31 : 0] hiz operation hiz hiz hiz dclk l operation operation operation l dclkfb ??? ? ? irq#[3 : 0]/pp[03 : 00] hiz operation operation x or hiz x or hiz tout[0]/gate[0]/pp[04] hiz operation operation x or hiz x or hiz tout[1]/gate[1]/pp[05] hiz operation operation x or hiz x or hiz
mb93461 35 (continued) pin name initial state core sleep mode bus sleep mode pll operation mode pll stop mode rxd[0]/pp[06] hiz operation operation x or hiz x or hiz txd[0]/pp[07] hiz operation operation x or hiz x or hiz cts#[0]/pp[08] hiz operation operation x or hiz x or hiz rts#[0]/pp[09] hiz operation operation x or hiz x or hiz rxd[1]/pp[10] hiz operation operation x or hiz x or hiz txd[1]/pp[11] hiz operation operation x or hiz x or hiz dreq#[0]/pp[12] hiz operation x or hiz x or hiz x or hiz dack#[0]/pp[13] hiz operation x or hiz x or hiz x or hiz done#[0]/dreq#[4]/pp[14] hiz operation x or hiz x or hiz x or hiz dreq#[1]/pp[15] hiz operation x or hiz x or hiz x or hiz dack#[1]/pp[16] hiz operation x or hiz x or hiz x or hiz done#[1]/dreq#[5]/pp[17] hiz operation x or hiz x or hiz x or hiz dreq#[2]/pp[18] hiz operation x or hiz x or hiz x or hiz dreq#[3]/pp[19] hiz operation x or hiz x or hiz x or hiz dack#[2]/dreq#[6]/pp[20] hiz operation x or hiz x or hiz x or hiz dack#[3]/dreq#[7]/pp[21] hiz operation x or hiz x or hiz x or hiz erst# , hrst# ??? ? ? ecv ??? ? ? ed hiz hiz hiz hiz hiz eclk l l l l l prst# ??? ? ? rstout# l operation operation operation operation ramboot# ??? ? ? cpuhold lxxxx clkin ??? ? ? cmode[3 : 0] ??? ? ? tdi ??? ? ? tdo hiz hiz hiz hiz hiz tms , tck , trst# ??? ? ? testmode , tdc , mtestmode ??? ? ? vdr[7 : 0]/vdcr[7 : 0] /avpp[23 : 16] ? operation x or hiz x or hiz x or hiz vdg[7 : 0]/vdy[7 : 0]/vdx[7 : 0] ? operation x x x
mb93461 36 (continued) pin name initial state core sleep mode bus sleep mode pll operation mode pll stop mode vdb[7 : 0]/vdcx[7 : 0]/ vdcb[7 : 0]/avpp[39 : 32] ? operation x or hiz x or hiz x or hiz vdhsync/vdhsync# ? operation x x x vdvsync/vdvsync# ? operation x x x vdpclkin ??? ? ? vdclkout ? operation operation operation operation enable/enable# ? operation x x x topfield/topfield# ? operation x x x disable ??? ? ? vcr[7 : 0]/vccr[7 : 0]/ avpp[15 : 8] ? operation x or hiz x or hiz x or hiz vcg[7 : 0]/vcy[7 : 0]/vcx[7 : 0] ??? ? ? vcb[7 : 0]/vccx[7 : 0]/ vccb[7 : 0]/avpp[31 : 24] ? operation x or hiz x or hiz x or hiz vchsync/vchsync# ??? ? ? vcvsync/vcvsync# ??? ? ? vcdclkin ??? ? ? sdo/dx ? operation x x x lrcko/fs0 ? operation operation operation operation bcko/mclk ? operation operation operation operation sdi/dr ??? ? ? lrcki/fs1 ? operation x or hiz x or hiz x or hiz bcki ??? ? ? fscki ??? ? ? udp ? operation hiz hiz hiz udm ? operation hiz hiz hiz uscki ??? ? ? udp1 ? operation hiz hiz hiz udm1 ? operation hiz hiz hiz hovrcur# ??? ? ? hpwren ? operation x x x scl[1 : 0] ? hiz hiz hiz hiz sda[1 : 0] ? hiz hiz hiz hiz sdcki/mscki ??? ? ? sdwp/msdirs ? operation x or hiz x or hiz x or hiz msdirp ? operation x x x
mb93461 37 (continued) pin name initial state core sleep mode bus sleep mode pll operation mode pll stop mode sdcd/mscd ??? ? ? sdcmd/msbs ? operation x or hiz x or hiz x or hiz sdclk/msclk ? operation operation operation operation sddat[0]/msdio[0] ? operation x or hiz x or hiz x or hiz sddat[3 : 1]/msdio[3 : 1] ? operation x or hiz x or hiz x or hiz sdmsselect ??? ? ?
mb93461 38 handling devices ? preventing latch-up cmos ic chips may suffer latch- up under the following conditions : ? a voltage higher than v de or lower than v ss is applied to an input or output pin. ? a voltage higher than the rated volt age is applied between vde pin and vss pin. latch-up may increase the power supply current dr astically, causing thermal damage to the device. for the same reason, care must also be take n in not allowing the analog power-supply voltage (v dd ) to exceed the digital power-supply voltage. ? handling unused pins leaving unused input pins open may result in misbehav ior or latch-up and possible permanent damage of the device. therefore they must be pulled up or pulled down through resistors. in this case those resistors should be more than 2 k ? . unused bi-directional pins should be set to the output st ate and can be left open, or the input state with the above described connection. when not using usb/usb-host pin, fix both udp1 and udm1 to the opposite level for each other. ? power supply pins in products with multiple vde, vdd, or vss pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. however you must connect the pins to an external power and a ground line to lower the electro- magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, a nd to conform to the total current rating. make sure to connect vde, vdd, and vss pi ns via the lowest impedance to power lines. it is recommended to provide a bypass capacitor of around 0.1 f between vde, vdd, and vss pins near the device. ? pull-up/down resistors the mb93461 does not support internal pull-up/down resi stors (except pu/pd pin type) . use external compo- nents where needed. ? n.c. pin the n.c. (internally connected) pin must be opened for use.
mb93461 39 block diagram sdr- sdram 32-bit 32-bit local bus low bandwidth peripheral bus timer local bus interface uart irc gpio fr450 core (cpu, cache) bus bridge dmac dsu external memory controller fr450 soc platform video capture cntl i 2 c 2 gpio bus bridge video display cntl audio output (i 2 s) audio input (i 2 s) ms 1.4/ sd-io usb 2.0 host (fs) dmac usb 2.0 function (fs) fr-v digital - av peripherals cache-unit bus interface 32 64 64 64 64 fr450 core block diagram i-cache 32 kb 2-way 1rw d-cache 32 kb 2-way 1rw mmu gr 32w 32b 5r/3w fr 32w 32b 5r/3w integer-unit instruction fetch media-unit bypass bypass iimm pipeline control static branch prediction media 0 slot media 1 slot integer 0 slot integer 1 slot high bandwidth system interconnect high bandwidth system interconnect
mb93461 40 electrical characteristics 1. absolute maximum ratings note : v ss = 0 v warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit min max power supply voltage (external) v de v ss ? 0.5 v ss + 4.0 v power supply voltage (internal) v dd v ss ? 0.5 v ss + 1.8 v input voltage v i v ss ? 0.5 v de + 0.5 ( 4.0) v storage temperature t stg ? 55 + 125 c
mb93461 41 2. recommended operating conditions [v ss = 0 v] usb [v ss = 0 v] *1 : if usb function is used , it is nec essary to attach ?rpu? outside to d + or d ? . *2 : if usb host is used , it is neces sary to attach ?rpd? outside to d + and d ? . notes : board wiring for connecting the power supply and ground (gnd) , use multiple vdd and vss pins. the system board based on the mb93461 must be a multi-layer board containing power supply (v dd ) and gnd (v ss ) layers for stable power supply. insert sufficient decoupling capacitors (condensers) near the mb93461. changes to the output levels of many of the output pins on the mb93461 (i n particular, those with large load capacitance) may cause variation in power supply. for those systems which run at a high frequency, lo w-inductance capacitors and mutual wiring are recom- mended. inductance can be lowered by shortening the distance between the processor and decoupling ca- pacitor. warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit min typ max power supply voltage (external) v de 360 mhz 3.15 3.3 3.45 v 400 mhz 3.15 3.3 3.45 v power supply voltage (internal) v ddi 360 mhz 1.235 1.3 1.365 v 400 mhz 1.33 1.4 1.47 v ?l? level input voltage v il ? 0.3 ? 0.8 v ?h? level input voltage v ih 2.0 ? v de + 0.3 v operating temperature t a 02570 c parameter symbol value unit min typ max ?h? level input voltage v ihu 2.0 ?? v ?l? level input voltage v ilu ?? 0.8 v differential input sensitivity v diu 0.2 ?? v differential common mode range v cmu 0.8 ? 2.5 v ?h? level output voltage v ohu 2.8 ? 3.45 v ?l? level output voltage v olu 0.0 ? 0.3 v output signal crossover voltage v crsu 1.3 ? 2.0 v bus pull-up/down resistor on upstream port rpu *1 1.425 ? 1.575 k ? rpd *2 14.25 ? 15.75 k ? termination voltage on upstream port pull-up v term 3.15 ? 3.45 v
mb93461 42 3. dc characteristics [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] parameter symbol condition value unit min typ max ?l? level input voltage v il ? 0 ? 0.8 v ?h? level input voltage v ih ? 2.0 ? v de v ?l? level output voltage v ol i ol = 100 a0 ? 0.2 v ?h? level output voltage v oh i oh = ? 100 av de ? 0.2 ? v de v input leakage current i li v in = 0 or v de ? 5 ? 5 a tri-state output leakage current i lz v out = 0 or v de ? 5 ? 5 a power supply current (v de ) i de 360 mhz cmode = 0x3, clkin = 60 mhz, (dhrystone2.1 + dma transfer) no load 04080ma 400 mhz cmode = 0x3, clkin = 66mhz, (dhrystone2.1 + dma transfer) no load 04488ma power supply current (v dd ) i dd 360 mhz cmode = 0x3, clkin = 60 mhz, (dhrystone2.1 + dma transfer) ? 196 420 ma 400 mhz cmode = 0x3, clkin = 66 mhz, (dhrystone2.1 + dma transfer) ? 245 520 ma at sleep power supply current i coresleep 360 mhz core sleep mode, clkin = 60 mhz ? 70 ? ma 400 mhz core sleep mode, clkin = 66 mhz ? 87 ? ma i bussleep 360 mhz bus sleep mode, clkin = 60 mhz ? 32.4 ? ma 400 mhz bus sleep mode, clkin = 66 mhz ? 40.6 ? ma i pllon 360 mhz pll on mode, clkin = 60 mhz ? 18.2 ? ma 400 mhz pll on mode, clkin = 66 mhz ? 22.4 ? ma i plloff pll stop mode, clkin = 0 mhz ? 5 ? ma capacity of pins c pin v de = v i = 0, f = 1 mhz ?? 16 pf
mb93461 43 usb [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] i 2 c [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] parameter symbol conditions value unit min typ max ?l? level output voltage v ol i ol = 20 ma 0 ? 0.4 v ?h? level output voltage v oh i oh = ? 20 ma v de ? 0.5 ? v de v ?l? level output current i ol v ol = 0.4 v 20 ?? ma ?h? level output current i oh v oh = v de ? 0.4 v ? 20 ?? ma output short-circuit current i os ??? 300 ma parameter symbol conditions value unit min typ max ?l? level input voltage v il ?? 0.5 ? 0.3 v de v ?h? level input voltage v ih ? 0.7 v de ? v de v ?l? level output voltage 1 v ol1 i ol = 3 ma 0 ? 0.4 v schmitt trigger hysteresis v hys ? 0.05 v de ?? v data line leakage i i ?? 10 ? 10 a
mb93461 44 4. ac characteristics (1) local bus interface [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] * : refer to ?5. clock setting? for details. (continued) item parameter reference signal 360 mhz 400 mhz unit min max min max clkin input clkin period (t clkin ) ? 15* 27* 15* 23.5* ns clkin high time ? 6.0 ? 6.0 ? ns clkin low time ? 6.0 ? 6.0 ? ns clkin rise time ?? 1.0 ? 1.0 ns clkin fall time ?? 1.0 ? 1.0 ns local-bus i/f output bgnt# output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns a [31 : 2] output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns output hold time clkin rise 1.5 ? 1.5 ? ns d [31 : 0] output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns output hold time clkin rise 1.5 ? 1.5 ? ns be/be# [0 : 3] output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns output hold time clkin rise 1.5 ? 1.5 ? ns bs# output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns output hold time clkin rise 1.5 ? 1.5 ? ns rd# output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns we# output valid delay time clkin fall 1.0 7.0 1.0 7.0 ns dir output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns output hold time clkin rise 1.5 ? 1.5 ? ns rdy# output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns output hold time clkin rise 1.5 ? 1.5 ? ns cs# [3 : 0] output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns cs# [7 : 4]/ irq# [7 : 4] output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns output hold time clkin rise 1.5 ? 1.5 ? ns bstreq# output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns output hold time clkin rise 1.5 ? 1.5 ? ns bstack# output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns output hold time clkin rise 1.5 ? 1.5 ? ns
mb93461 45 (continued) [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] notes : ? each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, the input level is 0.4 v to 2.4 v, and the input rise time and fall time are 1.5 ns or less. the external output load capacitance is 30 pf. ? maximum frequency of clkin varies depending on the sett ing of cmode [0] to [3] pins. please refer to ? 5. clock setting.? item parameter reference signal 360mhz 400mhz unit min max min max local-bus i/f input breq# input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns a [31 : 2] input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns d [31 : 0] input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns be/be# [0 : 3] input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns bs# input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dir input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns rdy# input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns err# input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns cs# [7 : 4]/ irq# [7 : 4] input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns ibw input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns bstreq# input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns bstack# input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns
mb93461 46 c lkin i nput pin o utput pin i nput-and-output pin w e# setup hold hold hold valid valid
mb93461 47 (2) sdram interface [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] * : this value is decided by cmode. notes : ? each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, the input level is 0.4 v to 2.4 v, and the input ri se time and fall time are 1.5 ns or less unless otherwise noted. the external output load capacitance is 30 pf unless otherwise noted. ? the frequency of the input to dclkfb and the output from dclk is decided by the input frequency to clkin, and setup of a cmode [3 : 0] pins . refer to ?5. clock setting? for details. item parameter reference signal 360 mhz 400 mhz unit min max min max dclkfb input dclkfb period (t dclkfb ) ? 7.5* 20* 7.5* 17.5* ns dclkfb high time ? 2.5 ? 2.5 ? ns dclkfb low time ? 2.5 ? 2.5 ? ns dclkfb rise time ?? 1.0 ? 1.0 ns dclkfb fall time ?? 1.0 ? 1.0 ns sdram i/f output dcs# [3 : 0] output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns dba [1 : 0] output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns da [12 : 0] output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns dras# output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns dcas# output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns dwe# output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns dcke output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns ddqm [0 : 3] output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns ddq [31 : 0] output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns output hold time dclkfb rise 1.0 ? 1.0 ? ns sdram i/f input ddq [31 : 0] input setup time dclkfb rise 1.0 ? 1.0 ? ns input hold time dclkfb rise 1.0 ? 1.0 ? ns d clkfb o utput pin i nput-and- o utput pin setup hold hold valid
mb93461 48 ? this lsi outputs dclk which is supplied to sdram as a clock. pll is built into this lsi. adjust the phase of dclk so that the clk pin of sdram and the internal phase in this lsi may be nearly equal. therefore, when connecting, adjust the delay time of the feedba ck path from dclk to dclkfb, so that the phase of the clock input to dclkfb which is the feedback signal to pll and the phase of the clock (wave shape on the reception edge of dclk) input to clk of sdram may be nearly equal.
mb93461 49 (3) general-purpose peripheral resource [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] (continued) item parameter reference signal 360 mhz 400 mhz unit min max min max resources output irq# [3 : 0]/ pp [03 : 00] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns tout[0]/ gate[0]/ pp[04] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns tout[1]/ gate[1]/ pp[05] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns rxd[0]/ pp[06] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns txd[0]/pp[07] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns cts# [0]/ pp[08] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns rst# [0]/ pp[09] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns rxd[1]/ pp[10] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns txd[1]/pp[11] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns dreq# [0]/ pp[12] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns dack# [0]/ pp[13] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns done# [0]/ dreq# [4]/ pp[14] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns dreq# [1]/ pp[15] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns dack# [1]/ pp[16] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns done# [1]/ dreq# [5]/ pp[17] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns
mb93461 50 [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] (continued) item parameter reference signal 360 mhz 400 mhz unit min max min max resources output dreq#[2]/ pp[18] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns dreq#[3]/ pp[19] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns dack#[2]/ dreq#[6]/ pp[20] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns dack#[3]/ dreq#[7]/ pp[21] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns resources input irq#[3 : 0]/ pp [03 : 00] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns tout[0]/ gate[0]/ pp[04] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns tout[1]/ gate[1]/ pp[05] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns rxd[0]/ pp[06] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns txd[0]/pp[07] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns cts#[0]/ pp[08] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns rst#[0]/ pp[09] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns rxd[1]/ pp[10] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns txd[1]/pp[11] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dreq#[0]/ pp[12] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dack#[0]/ pp[13] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns
mb93461 51 (continued) [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] note : each parameter is valid within the specified r anges of temperature and supp ly voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, the input level is 0.4 v to 2.4 v, and the i nput rise time and fall time are 1.5 ns or less. the external output load capacit ance is 30 pf unless otherwise noted. item parameter reference signal 360 mhz 400 mhz unit min max min max resources input done#[0]/ dreq#[4]/ pp[14] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dreq#[1]/ pp[15] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dack#[1]/ pp[16] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns done#[1]/ dreq#[5]/ pp[17] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dreq#[2]/ pp[18] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dreq#[3]/ pp[19] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dack#[2]/ dreq#[6]/ pp[20] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dack#[3]/ dreq#[7]/ pp[21] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns c lkin i nput pin o utput pin i nput-and- o utput pin setup hold hold valid
mb93461 52 (4) ice interface [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] * : unit of t clkin is clkin period. please refer to ?4. (1) local bus interface?. note : each parameter is valid within the specified r anges of temperature and supp ly voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, and the input level is 0.4 v to 2.4 v. the input ri se time and fall time are 1.5 ns or less. the external output load capacitance is 30 pf unless otherwise noted. item parameter reference signal 360 mhz 400 mhz unit min max min max eclk output eclk output period ? 30 ? 30 ? ns eclk output high time ? 13.0 ? 13.0 ? ns eclk output low time ? 13.0 ? 13.0 ? ns eclk output rise time ?? 2.0 ? 2.0 ns eclk output fall time ?? 2.0 ? 2.0 ns ice output ed output valid delay time eclk rise ? 8.0 ? 8.0 ns output hold time eclk rise 0.0 ? 0.0 ? ns ice input erst# input setup time eclk rise 5.0 ? 5.0 ? ns input hold time eclk rise 0.0 ? 0.0 ? ns hrst# low pulse width ? 16 ? 16 ? t clkin * ecv input setup time eclk rise 5.0 ? 5.0 ? ns input hold time eclk rise 0.0 ? 0.0 ? ns ed input setup time eclk rise 5.0 ? 5.0 ? ns input hold time eclk rise 0.0 ? 0.0 ? ns e clk i nput pin i nput-and -output pin setup hold hold valid
mb93461 53 (5) reset-related pin [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] * : unit of t clkin is clkin period. please refer to ?4. (1) local bus interface?. (6) cpu status [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] (7) clock [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] (8) test [360 mhz : v de = 3.3 v 0.15, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] item parameter reference signal 360 mhz 400 mhz unit min max min max reset output rstout# output valid delay time clkin rise 0 8.0 0 8.0 ns reset input prst# low pulse width ? 16 ? 16 ? t clkin * boot input ramboot# low pulse width ? 16 ? 16 ? t clkin * item parameter reference signal 360 mhz 400 mhz unit min max min max cpu output cpuhold output valid delay time clkin rise 0 8.0 0 8.0 ns item parameter reference signal 360 mhz 400 mhz unit min max min max clock mode input cmode[3 : 0] input setup time ? must be fixed to ?h? or ?l? ? input hold time ? must be fixed to ?h? or ?l? ? item parameter reference signal 360 mhz 400 mhz unit min max min max test mode input testmode input setup time ? must be fixed to ?l? ? input hold time ? must be fixed to ?l? ? tdc input setup time ? must be fixed to ?l? ? input hold time ? must be fixed to ?l? ? mtestmode input setup time ? must be fixed to ?l? ? input hold time ? must be fixed to ?l? ?
mb93461 54 (9) video display controller (vdc) [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] * : the falling edge of vdclkout is synchronous with respect to the rising edge of vdpclkin. note : each parameter is valid within the specified ranges of temperature and supply voltage unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, and the input level is 0.4 v to 2.4 v. the external output load capacitance is 15 pf. item parameter reference signal 360 mhz/400 mhz unit min max vdc clock input vdpclkin period ? 12.5 125 ns vdpclkin high time ? 4 ? ns vdpclkin low time ? 4 ? ns vdc i/f output vdr [7 : 0]/vdcr [7 : 0] output valid delay time vdclkout fall ? 23ns output hold time vdclkout fall ? 2 ? ns vdg [7 : 0]/vdy [7 : 0]/ vdx[7 : 0] output valid delay time vdclkout fall ? 23ns vdb [7 : 0]/vdcx[7 : 0]/ vdcb [7 : 0] output valid delay time vdclkout fall ? 23ns output hold time vdclkout fall ? 2 ? ns vdhsync/ vdhsync# output valid delay time vdclkout fall ? 23ns vdvsync/ vdvsync# output valid delay time vdclkout fall ? 23ns enable/enable# output valid delay time vdclkout fall ? 23ns topfield/ topfield# output valid delay time vdclkout fall ? 23ns vdclkout* output valid delay time vdpclkin rise 7 11 ns vdc i/f input disable input setup time vdpclkin rise 2.5 ? ns input hold time vdpclkin rise 1.5 ? ns
mb93461 55 (10) video capture controller (vcc) [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] *: the reference signak of vcc interface is decided by the setting pf register in the vcc unit. rcc.es = 0 : falling edge of vcdclkin rcc.es = 1 : rising edge of vcdclkin please refer to mb9 3461 lsi specification. note : each parameter is valid within the specified r anges of temperature and supp ly voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, and the input level is 1.0 v to 2.0 v. the external output load capacitance is 30 pf. item parameter reference signal 360 mhz/400 mhz unit min max vcc clock input vcdclkin period ? 12.5 125 ns vcdclkin high time ? 4 ? ns vcdclkin low time ? 4 ? ns vcc i/f input vcr [7 : 0]/vccr [7 : 0] input setup time vcdclkin edge* 2.5 ? ns input hold time vcdclkin edge* 1.5 ? ns vcg[7 : 0]/vcy[7 : 0]/ vcx[7 : 0] input setup time vcdclkin edge* 2.5 ? ns input hold time vcdclkin edge* 1.5 ? ns vcb[7 : 0]/vccx[7 : 0]/ vccb[7 : 0] input setup time vcdclkin edge* 2.5 ? ns input hold time vcdclkin edge* 1.5 ? ns vchsync/ vchsync# input setup time vcdclkin edge* 2.5 ? ns input hold time vcdclkin edge* 1.5 ? ns vcvsync/ vcvsync# input setup time vcdclkin edge* 2.5 ? ns input hold time vcdclkin edge* 1.5 ? ns
mb93461 56 (11) audio [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] * : lrcko and sdo signals are generated with respect to the falling edge of bcko (duty 50 % ) . note : each parameter is valid within the specified r anges of temperature and supp ly voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, and the input level is 0.4 v to 2.4 v. the external output load capacitance is 30 pf. item parameter reference signal 360 mhz/400 mhz unit min max audio clock input fscki period ? 25 ? ns fscki high time ? 10.5 ? ns fscki low time ? 10.5 ? ns bcki period ? 100 ? ns bcki high time ? 42 ? ns bcki low time ? 42 ? ns audio i/f output sdo* output valid delay time fscki rise 3 11 ns lrcko* output valid delay time fscki rise 3 11 ns bcko* output valid delay time fscki rise 3 11 ns lrcki output valid delay time fscki rise 3 11 ns audio i/f input sdi input setup time bcki rise 15 ? ns input hold time bcki rise 15 ? ns lrcki input setup time bcki rise 15 ? ns input hold time bcki rise 15 ? ns
mb93461 57 (12) usb interface [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] notes : ? frequency of uscki is set to 48 mhz in order to ca rry out operation based on the standard of usb 2.0 fs. furthermore, it is necessary to put in a clock with a frequency accuracy of 2500 ppm. ? in order to fulfill the standard of us b 2.0 fs, it is necessary to add 25 ? to 30 ? in-series resistance outside. item parameter reference signal 360 mhz/400 mhz unit min max usb clock input uscki period ? 20 ? ns uscki high time ? 8 ? ns uscki low time ? 8 ? ns usb driver d + /d ? rise time t fr ? 420ns d + /d ? fall time t ff ? 420ns differential rise and fall time matching ? 90 111.11 % driver output resistance ? 28 44 ? 90% d - t fr d + 10% 90% 10% t ff
mb93461 58 (13) i 2 c [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] * : 20 + 0.1 c (c = capacitance of one bus line in pf) notes : ? each parameter is valid within t he specified ranges of temperature and supply voltages unless otherwise noted. ? each voltage value is based on the gnd (v ss = 0.0 v) level. the timing m easurement reference point is 1.5 v, the input level is 0.4 v to 2.4 v, and the input rise time and fall time are 1.5 ns or less. ? the external output load capacitance is 30 pf. (14) gpio [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] notes : ? avpp[39 : 8] is an asynchronous pin. ? each parameter is valid within the specified range s of temperature and supply voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, and the input level is 0.4 v to 2.4 v. the external output load capacitance is 30 pf. (15) memory stick interface note : customers are advised to consult with our sales representatives , if you use ms. (16) sd-io interface note : customers are advised to consult with our sales representatives , if you use sd. item parameter reference signal 360 mhz/400 mhz unit min max i 2 c i/f output scl[1 : 0] output fall time ? 23* 250 ns output rise time ? 23* 300 ns sda[1 : 0] output fall time ? 23* 250 ns output rise time ? 23* 300 ns item parameter reference signal 360 mhz/400 mhz unit min max gpio i/f output avpp[39 : 8] output valid delay time ??? ns output hold time ??? ns gpio i/f input avpp[39 : 8] input setup time ??? ns input hold time ??? ns
mb93461 59 (17) power sequence [360 mhz : v de = 3.3 v 0.15 v, v dd = 1.3 v 0.065 v, v ss = 0 v, ta = 0 c to + 70 c] [400 mhz : v de = 3.3 v 0.15 v, v dd = 1.4 v 0.07 v, v ss = 0 v, ta = 0 c to + 70 c] note : power-off sequence is not defined. item parameter reference signal 360 mhz/400 mhz unit min max power-on vde rise time t re ?? 30 ms vdd rise time t rd ?? 15 ms delay time from v de rise to v dd rise t dred ?? 100 100 ms power-on sequence v de -min v dd -min v de v dd t re t rd t dred
mb93461 60 5. clock setting in this lsi, the clock signal inputted into clkin is multiplied by internal pl l, and it has distributed to each part in lsi. the multiplication rate for each clock is decided using th e cmode [3 : 0] pins. depending on this setup, the maximum frequency of clkin may be restricted. the maximum frequency that can be inputted into clkin and the frequency of each par t of lsi are shown below. (continued) cmode [0] to [3] ratio clkin freq. internal operating clock of this lsi clkin input 360 mhz or 400 mhz period (t clkin ) [ns] freq. [mhz] 3210 external bus sdram core bus core dsu min max min max 0000 ratio 1 1 1 1 1 0.5 360 mhz 15.0 18.0 55.6 66.7 400 mhz 15.0 15.5 64.5 66.7 0001 ratio 1 1 1 1 3 0.25 360 mhz 15.0 20.0 50.0 66.7 400 mhz 15.0 17.5 57.1 66.7 0010 ratio 1 1 1 2 6 0.5 360 mhz 16.7 20.0 50.0 60.0 400 mhz 15.0 17.5 57.1 66.7 0011 ratio 1 1 2 2 6 0.5 360 mhz 16.7 20.0 50.0 60.0 400 mhz 15.0 17.5 57.1 66.7 0100 ratio 1 1 1 2 2 0.16 360 mhz 15.0 18.0 55.6 66.7 400 mhz 15.0 15.5 64.5 66.7 0101 reserved 0110 reserved 0111 reserved 1000 ratio 1 1 1 1 2 0.16 360 mhz 15.0 18.0 55.6 66.7 400 mhz 15.0 15.5 64.5 66.7
mb93461 61 (continued) notes : ? ? ? indicates the frequency ratio for the external input clock. ? by default, the operating frequency of the resource bus clock is the same as that of the external bus. ? when clkc.p0 is set to ?1?, the operating frequency of th e resource bus clock is half that of the external bus. however, the frequency of the resource bus clock is fixed to 1/2 operating frequency of the external bus when cmode = f regardless of the setting of clkc.p0. ? as the setting of cmode = 5, 6, 7, a, b, d that is the hatc hed part in the table is not confirmed for operation guarantee, do not set them. cmode [0] to [3] ratio clkin freq. internal operating clock of this lsi clkin input 360 mhz or 400 mhz period (t clkin ) [ns] freq. [mhz] 3210 external bus sdram core bus core dsu min max min max 1001 ratio 1 1 2 2 4 0.33 360 mhz 15.0 18.0 55.6 66.7 400 mhz 15.0 15.5 64.5 66.7 1010 reserved 1011 reserved 1100 ratio 1 1 1 2 4 0.33 360 mhz 15.0 18.0 55.6 66.7 400 mhz 15.0 15.5 64.5 66.7 1101 reserved 1110 ratio 1 1 3 3 9 0.75 360 mhz 25.0 27.0 37.0 40.0 400 mhz 22.5 23.5 42.6 44.4 1111 ratio 1 1 1.5 1.5 4.5 0.375 360 mhz 15.0 20.0 50.0 66.7 400 mhz 15.0 17.5 57.1 66.7
mb93461 62 connection with memory 1. connection with rom or sram an example of connection between this proc essor and rom or sram, etc. is shown below. example : four srams (each of ?256 k 8 bits?) are connected to the 32-bit bus (the polarity of be/be# is positive logic) . sram (1) a [17:0] i/o [7:0] oe# cs1# cs2 sram (2) a [17:0] i/o [7:0] oe# cs1# cs2 sram (3) a [17:0] i/o [7:0] oe# we# cs1# cs2 sram (4) a [17:0] i/o [7:0] oe# we# cs1# cs2 mb93461 a [19:2] cs# [n] dir we# be [0]/be# [0] be [1]/be# [1] be [2]/be# [2] be [3]/be# [3] d [31:24] d [23:16] d [15:8] d [7:0] rdy# we# we#
mb93461 63 2. connection with sdram sdram can be connected directly to dcs# [0] or dcs# [1]. an example in which two sdrams (each of ?1 m 4 banks 16 bits?) are connected to the 32-bit bus is shown below. note : this lsi outputs dclk which is s upplied to sdram as a clock. pll is bu ilt into this lsi. adjust the phase of dclk so that the clk pin of sd ram and the internal phase in this lsi may be nearly equal. therefore, when connecting, adjust the delay time of the feedback path from dclk to dclkfb , so that the phase of the clock input to dclkfb which is the feedback si gnal to pll and the phase of the clock (wave shape on the reception edge of dclk) input to clk of sdram may be nearly equal. mb93461 dba [1:0] dcas# dcs# [0] dras# dwe# da [11:0] ddq [31:16] sdram (1) ba [1:0] a [11:0] cs# ras# cas# we# dqm u , l dq [15:0] cke clk ddqm [0:1] dcke dclk dclkfb sdram (2) ba [1:0] a [11:0] cs# ras# cas# we# dqm u , l dq [15:0] cke clk ddq [15:0] ddqm [2:3]
mb93461 64 example : connecting registered-dimm to dcs#[3 : 2] dcs#[2] and dcs#[3] are only used for connecting the 1 68-pin registered dimm. connect the 168-pin registered dimm as follows. the dimm must be ?registered?. in the registered dimm, it is assumed that the module connected to dcs#[2] or dcs#[3] is used after dc s#, dba, da, dras#, dcas#, dwe#, ddqm, and dcke are latched once at the rising of dclk signal. when using dcs#[2] or dc s#[3], the bus width must be set to the 32-bit mode. mb93461 dba [1:0] dcas# dcs# [2] dras# dwe# da [12:0] ddq [31:16] 168-pin registered-dimm ba [1:0] a [12:0] s0# ras# cas# we# cke clk ddqm [0:1] dcke dclk dclkfb dcs# [3] ddqm [2:3] ddq [15:0] s2# dqmb [4:5] dqmb [6:7] dqmb [0:1] dqmb [2:3] dq [47:32] dq [63:48] dq [15:0] dq [31:16]
mb93461 65 connection with peripheral device 1. connection with mb93441 (pci bridge chip) an example of connection between this proc essor and peripheral device is shown below. clock gen. mb93461 mb93441 clkin breq# bgnt# d[31:00] a[27:2] be[0:3] dir clkin breq# bgnt# d[31:00] a[27:2] be[0:3] dir bs# rdy# dreq# csc# csr# irq# bstreq# bstack# prst# bw16 reset gen. bstreq# bstack# prst# bs# rdy# dreq#[n] (n : 0 to 7) cs#[n] (n : arbitrary except 0) irq[n]/pp[n] (n : 0 to 3) correspondence is arbitrary. correspondence is arbitrary. correspondence is arbitrary.
mb93461 66 2. connection with mb93443 (ide/pc-card host controller) an example of connection between this proc essor and peripheral device is shown below. clock gen. mb93461 mb93443 clkin d[31:00] a[15:2] be[0:3] dir clkin d[31:00] a[15:2] be[0:3] dir bs# rdy# dreq# csc# csr# irq# bstreq# bstack# prst# bw16 reset gen. bstreq# bstack# prst# bs# rdy# dreq#[n] (n : 0 to 7) cs#[n] (n : arbitrary except 0) irq[n]/pp[n] (n : 0 to 3) correspondence is arbitrary. correspondence is arbitrary. correspondence is arbitrary.
mb93461 67 package dimensions 420-ball plastic bga (bga-420p-m25) 400-ball plastic pfbga (bga-400p-m04) c 2005 fujitsu limited bga420025sc-1-2 27.00 0.20(1.063 .008) 27.00 0.20 (1.063 .008) c 0.35(.014) c 0.15(.006) c seating plane b a 25.00(.984)bsc 0.50(.020) bsc (.046 .002) 1.17 0.05 (.020 .004) 0.50 0.10 (.022 .002) 0.56 0.06 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 af ae ad ac ab aa ywvutrpnmlkjhgfedcba 3-r0.5 (3-r.020) 2.23 0.21 (.088 .008) c 0.25(.010) +0.70 ? 0.05 +.028 ? .002 .945 24.00 24.00 .945 ? .002 +.028 ? 0.05 +0.70 1 pin index 4x10.00 (4x.394) ? 0.63 0.15(.025 .006) m 0.30(.012) 0.10(.004) m c c a b 25.00(.984) bsc bsc 0.50(.020) bsc 1.00(.039) 4-c2.0 (4-c.079 ) dimensions in mm (inches). note: the values in parent heses are reference values . c 2004 fujitsu limited b400004s-c-1-1 15.00 0.10(.591 .004) 14.00(.551) ref 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag 28 29 aj ah (stand off) (.010 .004) 0.25 0.10 (seated height) 1.15 0.20 (.045 .008) 0.20(.008) b s (index area) 0.20(.008) a s (.591 .004) 15.00 0.10 s 0.15(.006) s typ 0.50(.020) a (481- ? .012 .004) 481- ? 0.30 0.10 m s ab ? 0.05(.002) index b 14.00(.551)ref 0.50(.020) typ dimensions in mm (inches). note: the values in parent heses are reference values .
mb93461 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0504 ? 2005 fujitsu limited printed in japan

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