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april 2000 advance information copyright ?2000 alliance semiconductor. all rights reserved. ? as7c3256pfd16a as7c3256pfd18a did 11-20027-a. 6/8/00 alliance semiconductor 1 3.3v 256k 16/18 pipeline burst s ynchronous sram cd features ? organization: 262,144 words 16 or 18 bits ? fast clock speeds to 166 mhz in lvttl/lvcmos ? fast clock to data access: 3.5/3.8/4/5 ns ?fast oe access time: 3.5/3.5/3.8/5.0 ns ? fully synchronous register-to-register operation ? flow-through mode ? double-cycle deselect - single-cycle deselect also available (as7c3256pfs16a/ as7c3256pfs18a) ? pentium? compatible architecture and timing ? synchronous and asynchronous output enable control ? economical 100-pin tqfp package ? byte write enables ? clock enable for operation hold ? multiple chip enables for easy expansion ? 3.3v core power supply ? 2.5v or 3.3v i/o operation with separate v ddq ? automatic power down: 30 mw typical standby power ? ntd? pipeline architecture available (as7c3256ntd16a/as7c3256ntd18a) logic block diagram q0 q1 256k32/36 memory array burst logic clk clr ce address dq ce clk dqd clk dq byte write registers register dqc clk dq byte write registers dqb clk dq byte write registers dqa clk dq byte write registers enable clk dq register enable clk dq delay register ce output registers input registers power down data [35:0] 36/32 4 36/32 36/32 18 16 18 18 gwe bwe bw d adv adsc adsp clk ce0 ce1 ce2 bw c bw b bw a oe a[17:0] zz lbo oe le ft clk clk [31:0] pin arrangement lbo a a a a a1 a0 nc nc v ss v dd nc nc a a a a a a 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a ce0 ce1 nc nc bwb bwa ce2 v dd v ss clk gwe bwe oe adsc adsp adv a a a nc nc nc v ddq v ssq nc nc dqb dqb v ssq v ddq dqb dqb ft v dd nc v ss dqb dqb v ccq v ssq dqb dqb dqpb/nc nc v ssq v ddq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a nc nc v ddq v ssq nc dqpa/nc dqa dqa v ssq v ddq dqa dqa v ss zz dqa dqa v ddq v ssq dqa dqa nc nc v ssq v ddq nc nc nc nc v dd tqfp 1420mm note: pins 24, 74 are nc for 16. selection guide ntd? is a trademark of alliance semiconductor corporation pentium? is a registered trademark of intel corporation. as7c3256pfd16- 3.5 as7c3256pfd16- 3.8 as7c3256pfd16- 4 as7c3256pfd16- 5units minimum cycle time 6 6.7 7.5 10 ns maximum pipelined clock frequency 166.7 150 133.3 100 mhz maximum pipelined clock access time 3.5 3.8 4 5 ns maximum operating current 450 400 350 300 ma maximum standby current 60 60 60 60 ma maximum cmos standby current (dc) 5 5 5 5 ma
as7c3256pfd16a as7c3256pfd18a ? advance information 2 alliance semiconductor did 11-20027-a. 6/8/00 functional description the as7c3256pfd16a and as7c3256pfd18a are high performance cmos 4 mbit synchronous static random access memory (sram) devices organized as 262,144 words 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology. timing for this device is compatible with existing pentium synchronous cache specifications. this architecture is suited for as ic, dsp (tms320c6x), and powerpc-based systems in computing, datacomm, instrumentation, and telecommunications systems. fast cycle times of 6/6.7/7.5/10 ns with clock access times (t cd ) of 3.5/3.5/3.8/5.0 ns enable 167, 150, 133 and 100 mhz bus frequencies. three chip enable inputs permit easy memory expansion. burst operation is initiated in one of two ways: the contro l ler address strobe ( adsc ), or the processor address strobe ( adsp ). the burst advance pin ( adv ) allows subsequent internally generated burst addresses. read cycles are initiated with adsp (regardless of we and adsc ) using the new external address clocked into the on-chip address register when adsp is sampled low, the chip enables are sampled active, and the output buffer is enabled with oe . in a read operation the data accessed by the current address, registered in the address registers by the positive edge of clk, are carried to the data-out registers and driven on the output pins on the next positive edge of clk. adv is ignored on the clock edge that samples adsp asserted, but is sampled on all subsequent clock edges. address is incremented internally for the next access of the burst when we is sampled high, adv is sampled low, and both address strobes are high. burst operation is selectable with the mode input. with mode unconnected or driven high, burst operat ions use a pentium count sequence. with mode driven low the device uses a linear count sequence, suitable for powerpc and many other applications. write cycles are performed by disabling the output buffers with oe and asserting a write command. a global write enable gwe writes all 32 bits regardless of the state of individual bw[a:d] inputs. alternately, when gwe is high, one or more bytes may be written by asserting bwe and the appropriate individual byte bw signal(s). bwn is ignored on the clock edge that samples adsp low, but is sampled on all subsequent clock edges. output buffers are disabled when bwn is sampled low (regardless of oe ). data is clocked into the data input register when bwn is sampled low. address is incremented internally to the next burst of address if bwn and adv are sampled low. read or write cycles may also be initiated with adsc instead of adsp . the differences between cycles initiated with adsc and adsp follow. ? adsp must be sampled high when adsc is sampled low to initiate a cycle with adsc . ? we signals are sampled on the clock edge that samples adsc low (and adsp high). ? master chip select ce0 blocks adsp , but not adsc . the as7c3256k16pd and as7c3256k18pd operate from a 3.3v supply. i/os use a separate power supply that can operate at 2.5v or 3. 3v. these devices are available in a 100-pin 1420 mm tqfp packaging. capacitance 1 write enable truth table (per byte) key: x = dont care, l = low, h = high parameter symbol signals test conditions max unit input capacitance c in address and control pins v in = 0v 4 pf i/o capacitance c i/o i/o pins v in = v out = 0v 5 pf gwe bwe bwn function l x x write all bytes h l l write byte(s)n hhxread hl hread
? as7c3256pfd16a as7c3256pfd18a advance information did 11-20027-a. 6/8/00 alliance semiconductor 3 signal descriptions absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat i on is not implied. exposure to absolute maximum rating conditions may affect reliability. signal i/o properties description clk i clock clock. all inputs except oe are synchronous to this clock. a0Ca17 i sync address. sampled when all chip enables are active and adsc or adsp are asserted. dq[a,b,c,d] i/o sync data. driven as output when the chip is enabled and oe is active. ce0 isync master chip enable. sampled on clock edges when adsp or adsc is active. when ce0 is inactive, adsp is blocked. refer to the synchronous truth table for more information. ce1, ce2 isync synchronous chip enables. active high and active low, respectively. sampled on clock edges when adsc is active or when ce1 and adsp are active. adsp i sync address strobe (processor). asserted low to load a new address or to enter standby mode. adsc i sync address strobe (controller). asserted low to load a new address or to enter standby mode. adv i sync burst advance. asserted low to continue burst read/write. gwe isync global write enable. asserted low to write all 36 bits. when high, bwe and bw[a:b] control write enable. bwe i sync byte write enable. asserted low with gwe = high to enable effect of bw[a:b] inputs. bw[a:b] isync write enables. used to control write of individual bytes when gwe = high and bwe = low. if any of bw[a:b] is active with gwe = high and bwe = low the cycle is a write cycle. if all bw[a:b] are inactive, the cycle is a read cycle. oe iasync asynchronous output enable. i/o pins are driven when oe is active and the chip is synchronously enabled. lbo i static default = high count mode. when driven high, count sequence follows intel xor convention. when driven low, count sequence follows linear convention. this signal is internally pulled high. ft i static default = high flow-through mode.when low, enables single register flow-through mode. connect to v dd if unused or for pipelined operation. this signal is internally pulled high zz i async sleep. places device in low power mode; data is retained. connect to gnd if unused. parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq C0.5 +4.6 v input voltage relative to gnd (input pins) v in C0.5 v dd + 0.5 v input voltage relative to gnd (i/o pins) v in C0.5 v ddq + 0.5 v power dissipation p d C1.4w dc output current i out C50ma storage temperature (plastic) t stg C65 +150 o c temperature under bias t bias C65 +150 o c
as7c3256pfd16a as7c3256pfd18a ? advance information 4 alliance semiconductor did 11-20027-a. 6/8/00 synchronous truth table key: x = dont care, l = low, h = high. ? see write enable truth table for more information. ce0 ce1 ce2 adsp adsc adv write n ? oe address accessed clk operation dq h x x x l x x x na l to h deselect hi-z l l x l x x x x na l to h deselect hi-z l l x h l x x x na l to h deselect hi-z l x h l x x x x na l to h deselect hi-z l x h h l x x x na l to h deselect hi-z lhllxxf lexternal l to hbegin readhi-z l h l l x x f h external l to h begin read hi-z lhlhlxf lexternal l to hbegin readhi-z lhlhlxf hexternal l to hbegin readhi-z xxxhhl f l next l to hcont. readdq x x x h h l f h next l to h cont. read hi-z x x x hhhf l current l to hsuspend readdq x x x hhhf hcurrent l to hsuspend readhi-z hxxxhl f l next l to hcont. readdq h x x x h l f h next l to h cont. read hi-z h x x x h h f l current l to h suspend read dq h x x x h h f h current l to h suspend read hi-z l h l h l x t x external l to h begin write hi-z x x x h h l t x next l to h cont. write hi-z h x x x h l t x next l to h cont. write hi-z x x x hhht hcurrent l to hsuspend writehi-z h x x x h h t h current l to h suspend write hi-z
? as7c3256pfd16a as7c3256pfd18a advance information did 11-20027-a. 6/8/00 alliance semiconductor 5 recommended operating conditions tqfp thermal resistance *this parameter is sampled. bga thermal resistance *this parameter is sampled. parameter symbol min nominal max unit supply voltage v dd 3.135 3.3 3.465 v gnd 0.0 0.0 0.0 3.3v i/o supply voltage v ddq 3.135 3.3 3.465 v gnd q 0.0 0.0 0.0 2.5v i/o supply voltage v ddq 2.35 2.5 2.65 v gnd q 0.0 0.0 0.0 input voltages ? address and control pins v ih 2.0 C v dd + 0.3 v v il C0.5 * * v il min = -2.0v for pulse width less than 0.2 t rc . ? input voltage ranges apply to 3.3v i/o operation. for 2.5v i/o operation, contact factory for input specifications. C0.8 i/o pins v ih 2.0 C v ddq + 0.3 v v il -0.5 * C0.8 ambient operating temperature t a 0C70c description conditions symbol typical units thermal resistance (junction to ambient)* test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 1-layer q ja 40 c/w 4-layer q ja 22 c/w thermal resistance (junction to top of case)* q jc 8c/w description conditions symbol typical units junction to ambient (airflow of 1m/s)* test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 1-layer q ja 40 c/w 4-layer q ja 25 c/w junction to top of case* q jc 9c/w junction to bottom of bumps* q jb 17 c/w
as7c3256pfd16a as7c3256pfd18a ? advance information 6 alliance semiconductor did 11-20027-a. 6/8/00 dc electrical characteristics dc electrical characteristics for 2.5v i/o operation parameter symbol test conditions -166 -150 -133 -100 unit min max min max min max min max input leakage current | i li | v dd = max, v in = gnd to v dd C2C2C2C2a output leakage current | i lo | oe 3 v ih, v dd = max, v out = gnd to v dd C2C2C2C2a operating power supply current i cc ce = v il , ce = v ih , ce = v il , f = f max, i out = 0 ma C 450 C 400 C 350 C 300 ma standby power supply current i sb deselected, f = f max C90C80C70C60 ma i sb1 deselected, f = 0 , all v in 0.2v or 3 v dd - 0.2v C5C5C5C5 output voltage v ol i ol = 8 ma, v ddq = 3.465v C0.4C0.4C0.4C0.4 v v oh i oh = C4 ma, v ddq = 3.135v 2.4 C 2.4 C 2.4 C 2.4 C parameter symbol test conditions -166 -150 -133 -100 unit min max min max min max min max output leakage current | i lo | oe 3 v ih, v dd = max, v out = gnd to v dd -11-11-11-11a output voltage v ol i ol = 2 ma, v ddq = 2.65v C 0.7 C 0.7 C 0.7 C 0.7 v v oh i oh = C2 ma, v ddq = 2.35v 1.7 C 1.7 C 1.7 C 1.7 C
? as7c3256pfd16a as7c3256pfd18a advance information did 11-20027-a. 6/8/00 alliance semiconductor 7 timing characteristics over operating range see notes on page 11. key to switching waveforms parameter symbol -3.5 -3.8 -4 -5 unit notes min max min max min max min max clock frequency f max -166-150-133-100mhz1 cycle time (pipelined mode) t cyc 6 - 6.6 - 7.5 - 10 - ns cycle time (flow-through mode) t cycf 10-10-12-15- ns clock access time (pipelined mode) t cd -3.5-3.8-4.0-5.0ns clock access time (flow-through mode) t cdf -8-8-9-12ns output enable low to data valid t oe -3.5-3.5-3.8-5.0ns clock high to output low z t lzc 0-0-0-0-ns8 data output invalid from clock high t oh 1.5 - 1.5 - 1.5 - 1.5 - ns 8 output enable low to output low z t lzoe 0-0-0-0-ns8 output enable high to output high z t hzoe -3.0-3.0-3.8-5.0ns8 clock high to output high z t hzc -3.0-3.3-3.3-4.5ns8 clock high to output high z t hzcn -1.5-1.5- 2 -2.5ns1,9 clock high pulse width t ch 2.0 - 2.0 - 2.0 - 2.5 - ns clock low pulse width t cl 2.0 - 2.0 - 2.0 - 2.5 - ns address and control setup to clock high t as 1.5 - 1.5 - 1.5 - 1.5 - ns data setup to clock high t ds 1.5 - 1.5 - 1.5 - 1.5 - ns write setup to clock high t ws 1.5 - 1.5 - 1.5 - 1.5 - ns chip select setup to clock high t css 1.5 - 1.5 - 1.5 - 1.5 - ns address hold from clock high t ah 0.5 - 0.5 - 0.5 - 0.5 - ns data hold from clock high t dh 0.5 - 0.5 - 0.5 - 0.5 - ns write hold from clock high t wh 0.5 - 0.5 - 0.5 - 0.5 - ns chip select hold from clock high t csh 0.5 - 0.5 - 0.5 - 0.5 - ns output rise time (0 pf load) t r 1.5 - 1.5 - 1.5 - 1.5 - v/ns 1 output fall time (0 pf load) t f 1.5 - 1.5 - 1.5 - 1.5 - v/ns 1 undefined/dont care falling input rising input
as7c3256pfd16a as7c3256pfd18a ? advance information 8 alliance semiconductor did 11-20027-a. 6/8/00 timing waveform of read cycle note: ? = xor when mode = high/no connect; ? = add when mode = low. we [0:3] is dont care. t cyc t ch t cl t as t ah t as t ah t ws t as t oh clk adsp adsc address gwe , bwe ce0 , ce2 adv oe d out t css t csh t hzc t lzoe t cd t lzc t oe t wh t ah t hzoe t as t ah load new address adv inserts wait states q(a2 ? 10) q(a2 ? 11) q(a3) q(a2) q(a2 ? 01) q(a3 ? 01) q(a3 ? 10) q(a3 ? 11) q(a1) a2 a1 a3 ce1 (pipelined mode) d out q(a2 ? 10) q(a2 ? 11) q(a3) q(a2 ? 01) q(a3 ? 01) q(a3 ? 10) q(a3 ? 11) q(a1) (flow-through mode) t hzc t cdf t oe t lzoe
? as7c3256pfd16a as7c3256pfd18a advance information did 11-20027-a. 6/8/00 alliance semiconductor 9 timing waveform of write cycle note: ? = xor when mode = high/no connect; ? = add when mode = low. t cyc t cl t as t ah t as t ah t as t ah t ws t wh t css t as t ds t dh clk adsp adsc address bwe , ce0 , ce2 adv oe data in t csh t ah d(a2 ? 01) d(a2 ? 10) d(a3) d(a2) d(a2 ? 01) d(a3 ? 01) d(a3 ? 10) d(a1) d(a2 ? 11) adv suspends burst adsc loads new address a1 a2 a3 t ch ce1 bwa,b
as7c3256pfd16a as7c3256pfd18a ? advance information 10 alliance semiconductor did 11-20027-a. 6/8/00 timing waveform of read/write cycle note: ? = xor when mode = high/no connect; ? = add when mode = low. t ch t cyc t cl t as t ah t as t ah t ws t wh t advs t as t ah t oh clk adsp address gwe ce0 , ce2 adv oe d in d out t lzc t advh t lzoe t oe t cd q(a1) q(a3 ? 01) d(a2) q(a3) q(a3 ? 10) q(a3 ? 11) a1 a2 a3 ce1 t hzoe (pipeline mode) d out q(a1) q(a3 ? 01) q(a3 ? 10) (flow-through mode) t cdf q(a3 ? 11)
did 11-20027-a. copyright ?2000 alliance semiconductor corporation (alliance)'s three-point logo, our name, and intelliwatt? ar e trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this web site and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this web site. alliance does not assume any responsibilit y or liability arising out of the application or use of any product described herein, and disclaims any express or implied warrantie s related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as expressly agreed to in alliance's terms and conditions of sale (available from alliance). all sales of alliance products are made exclusi vely according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license und er any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third pa rties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction o r fail- ure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assume s all risk of such use and agrees to indemnify alliance against all claim s arising from such use. ? as7c3256pfd16a as7c3256pfd18a advance information did 11-20027-a. 6/8/00 alliance semiconductor 11 notes ac test conditions as7c3256pfd18a and as7c3256pfd16a ordering information as7c3256pfd18a and as7c3256pfd16a part numbering system package width 166 mhz 150 mhz 133 mhz 100 mhz tqfp 16 as7c3256pfd16a-3.5tqc as7c3256pfd16a-3.8tqc as7c3256pfd16a-4tqc as7c3256pfd16a-5tqc tqfp 18 as7c3256pfd18a-3.5tqc as7c3256pfd18a-3.8tqc AS7C3256PFD18A-4TQC as7c3256pfd18a-5tqc as7c 3 256k p d 16, 18 Cxx xx c sram prefix operating voltage part number timing ntd=ntd? timing p=pbsram d = double- cycle deselect organization access time (ns) package: tq = tqfp commercial temperature, 0c to 70 c 1 this parameter is guaranteed but not tested. 2 for test conditions, see ac test conditions , figures a, b, c. 3 this parameter is sampled and not 100% tested. 4 this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk. all other synchronous inputs must meet the setup and hold times with sta ble logic levels for all rising edges of clk when chip is enabled. 5 typical values measured at 3.3v, 25c and 10 ns cycle time. 6i cc given with no output loading. i cc increases with faster cycle times and greater output loading. 7 transitions are measured 500 mv from steady state voltage. output loading specified with c l = 5 pf as in figure c. 8t hzoe is less than t lzoe ; and t hzc is less than t lzc at any given temperature and voltage. 9t hzcn is ano load parameter to indicate exactly when sram outputs have stopped driving. 351 w 5 pf* 317 w d out gnd +3.3v figure c: output load(b) *including scope and jig capacitance z 0 =50 w d out 50 w v l =1.5v figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +3.0v ? output load: see figure b, except for t lzc , t lzoe , t hzoe , t hzc see figure c. ? input pulse level: gnd to 3v. see figure a. ? input rise and fall time (measured at 0.3v and 2.7v): 2 ns. see figure a. ? input and output timing reference levels: 1.5v.

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