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1 m e m o r y all data sheets are subject to change without notice (619) 503-3300- fax: (619) 503-3301 - www.maxwell.com 1 megabit (128k x 8-bit) cmos sram 33c108 ?2002 maxwell technologies all rights reserved. 06.14.02 rev 2 f eatures : ?r ad -p ak ? technology radiation-hardened against natural space radiation 128k x 8 bit organization total dose hardness: - > 100 krad (si) - dependent upon space mission excellent single event effects: - sel th : no lu > 68 mev/mg/cm 2 - seu th : < 3 mev/mg/cm 2 package: - 32-pin r ad -p ak ? flat pack fast access time: - 20, 25 and 30 ns maximum times available single 5v + 10% power supply fully static operation - no clock or refresh required three state outputs ttl compatible inputs and outputs low power: - standby: 60ma (ttl) and 10ma (cmos) - operation: 180ma (20ns), 170ma (25ns) and 160ma (30ns) d escription : maxwell technologies? 33c108 high-density 1 megabit sram microcircuit features a greater than 100 krad (si) total dose tolerance. using maxwell?s radiation-hardened r ad -p ak ? packaging technology, the 33c108 realizes a higher density, higher performance, and lower power consumption. its fully static design eliminates the need for external clocks, while the cmos circuitry reduces power consumption and provides higher reliability. the 33c108 is equipped with eight common input/output lines, chip select and output enable, allowing for greater system flexibility and eliminating bus contention. the 33c108 features the same advanced 128k x 8 sram, high- speed, and low-power demand as the commercial counter- part. maxwell technologies' patented r ad -p ak packaging technol- ogy incorporates radiation shielding in the microcircuit pack- age. it eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. in a geo orbit, r ad -p ak provides greater than 100 krad (si) radiation dose tolerance. this product is available with screening up to class s. functional block diagram
m e m o r y 2 06.14.02 rev 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 1 megabit (128k x 8-bit) cmos sram 33c108 t able 1. p inout d escription p in s ymbol d escription 12-5, 27, 26, 23, 25, 4, 28, 3, 31, 2 a0-a16 address inputs 29 we write enable 22 cs chip select 24 oe output enable 13-15, 17-21 i/o 1-i/o 7 data inputs/outputs 32 v cc power (+5.0v) 16 v ss ground 1, 30 nc no connection
m e m o r y 3 06.14.02 rev 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 1 megabit (128k x 8-bit) cmos sram 33c108 t able 2. 33c108 a bsolute m aximum r atings p arameter s ymbol m in m ax u niys voltage on any pin relative to v ss v in , v out -0.5 v cc +0.5v v voltage on v cc supply relative to v ss v cc -0.5 7.0 v power dissipation p d -- 1.0 w storage temperature t s -65 +150 c operating temperature t a -55 +125 c thermal impedance tjc -- 6.04 c/w t able 3. 33c108 r ecommended o perating c onditions p arameter s ymbol m in m ax u nits supply voltage v cc 4.5 5.5 v ground v ss 00v input high voltage 1 1. v ih (min) = +2.0v ac (pulse width < 10 ns) for i < 20 ma. v ih 2.2 v cc + 0.5 v input low voltage 2 2. v il (min) = -2.0v ac (pulse width < 10 ns) for i < 20 ma. v il -0.5 0.8 v t able 4. 33c108 dc e lectrical c haracteristics (v cc = 4.5 to 5.5v; v ss = 0 v; t a = -55 to +125c, unless otherwise specified) p arameter s ubgroups s ymbol m in m ax u nits input leakage current v in = v ss to v cc 1, 2, 3 i li -2 2 a output leakage current cs = v ih , v out = v ss to v cc 1, 2, 3 i lo -2 2 a output low voltage, i ol = 8 ma 1, 2, 3 v ol -- 0.4 v output high voltage, i oh = -4 ma 1, 2, 3 v oh 2.4 -- v average operating current min cycle, 100% duty cs =v il , i out = 0ma v in = v ih or v il -20 -25 -30 1, 2, 3 i cc -- -- -- 180 170 160 ma standby power supply current cs = v ih , cycle time > 25ns 1, 2, 3 isb -- 60 ma cmos standby current cs > v cc - 0.2v, f = 0 mhz, v in > v cc - 0.2v orv in < 0.2v 1, 2, 3 i sb1 10
m e m o r y 4 06.14.02 rev 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 1 megabit (128k x 8-bit) cmos sram 33c108 input capacitance v in = 0v 1 1, 2, 3 c in -- 7 pf output capacitance vi/o = 0v 1 1, 2, 3 c out -- 8 pf 1. guaranteed by design. t able 4. 33c108 dc e lectrical c haracteristics (v cc = 4.5 to 5.5v; v ss = 0 v; t a = -55 to +125c, unless otherwise specified) p arameter s ubgroups s ymbol m in m ax u nits
m e m o r y 5 06.14.02 rev 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 1 megabit (128k x 8-bit) cmos sram 33c108 t able 5. 33c108 f unctional d escription cs we oe m ode i/o p in s upply c urrent h x x not select high-z isb, isb1 l h h output disable high-z i cc l h l read d out i cc llxwrited in i cc t able 6. 33c108 ac e lectrical c haracteristics for r ead c ycle (v cc = 4.5 to 5.5v; v ss = 0 v; t a = -55 to +125c, unless otherwise specified) p arameter s ubgroups s ymbol m in t yp m ax u nits read cycle time -20 -25 -30 9, 10, 11 t rc 20 25 30 -- -- -- -- -- -- ns address access time -20 -25 -30 9, 10, 11 t aa -- -- -- -- -- -- 20 25 30 ns chip select access time -20 -25 -30 9, 10, 11 t co -- -- -- -- -- -- 20 25 30 ns output enable to output valid -20 -25 -30 9, 10, 11 t oe -- -- -- -- -- -- 10 12 14 ns chip select to output in low-z 1 -20 -25 -30 9, 10, 11 t lz -- -- -- 3 3 3 -- -- -- ns output enable to output in low-z 1 -20 -25 -30 9, 10, 11 t olz -- -- -- 0 0 0 -- -- -- ns chip deselect to output in high-z 1 -20 -25 -30 9, 10, 11 t hz -- -- -- 5 6 8 -- -- -- ns output disable to output in high-z 1 -20 -25 -30 9, 10, 11 t ohz -- -- -- 5 6 8 -- -- -- ns
m e m o r y 6 06.14.02 rev 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 1 megabit (128k x 8-bit) cmos sram 33c108 output hold from address change -20 -25 -30 9, 10, 11 t oh -- -- -- 3 5 6 -- -- -- ns chip select to power up time 1 -20 -25 -30 9, 10, 11 t pu 0 0 0 0 0 0 -- -- -- ns chip select to power down time 1 -20 -25 -30 9, 10, 11 t pd -- -- -- 10 15 20 -- -- -- ns 1. guaranteed by design. t able 7. 33c108 ac e lectrical c haracteristics for w rite c ycle (v cc = 4.5 to 5.5v; v ss = 0 v; t a = -55 to +125c, unless otherwise specified) p arameter s ubgroups s ymbol m in t yp m ax u nits write cycle time -20 -25 -30 9, 10, 11 t wc 20 25 30 -- -- -- ns chip select to end of write -20 -25 -30 9, 10, 11 t cw 14 15 17 -- -- -- ns address setup time -20 -25 -30 9, 10, 11 t as 0 0 0 -- -- -- ns address valid to end of write -20 -25 -30 9, 10, 11 t aw 14 15 17 -- -- -- ns write pulse width(oe high) -20 -25 -30 9, 10, 11 t wp 14 15 17 -- -- -- ns write pulse width(oe low) -20 -25 -30 9, 10, 11 t wp1 -- -- -- 20 25 30 -- -- -- ns t able 6. 33c108 ac e lectrical c haracteristics for r ead c ycle (v cc = 4.5 to 5.5v; v ss = 0 v; t a = -55 to +125c, unless otherwise specified) p arameter s ubgroups s ymbol m in t yp m ax u nits
m e m o r y 7 06.14.02 rev 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 1 megabit (128k x 8-bit) cmos sram 33c108 f igure 1. t iming w aveform of r ead c ycle (1) write recovery time -20 -25 -30 9, 10, 11 t wr 0 0 0 -- -- -- ns write to output in high-z 1 -20 -25 -30 9, 10, 11 t whz -- -- -- 5 5 6 -- -- -- ns data to write time overlap -20 -25 -30 9, 10, 11 t dw 9 10 11 -- -- -- ns end write to output low-z 1 -20 -25 -30 9, 10, 11 t ow -- -- -- 6 7 8 -- -- -- ns data hold from write time -20 -25 -30 9, 10, 11 t dh 0 0 0 -- -- -- ns 1. guaranteed by design. t able 7. 33c108 ac e lectrical c haracteristics for w rite c ycle (v cc = 4.5 to 5.5v; v ss = 0 v; t a = -55 to +125c, unless otherwise specified) p arameter s ubgroups s ymbol m in t yp m ax u nits
m e m o r y 8 06.14.02 rev 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 1 megabit (128k x 8-bit) cmos sram 33c108 f igure 2. t iming w aveform of r ead c ycle (2) read cycle notes: 1 .we is high for read cycle. 2 . all read cycle timing is referenced form the last valid address to the first transition address. 3 .t hz and t ohz are defined as the time at which the outputs achiev e the open circuit condition and are not referenced to v oh or v ol levels. 4 . at any given temperature and voltage condition, t hz(max) is less than t lz(min) both for a given device and from device to device. 5 . transition is measured + 200mv from steady state voltage wi th load(b). this parameter is sampled and not 100% tested. 6 . device is continuously selected with cs = v il. 7 . address valid prior to coincident with cs transition low. 8 . for common i/o applications, minimization or elimination of bus contention conditi on is necessary during read and write cycle. f igure 3. t iming w aveform of w rite c ycle (1)
m e m o r y 9 06.14.02 rev 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 1 megabit (128k x 8-bit) cmos sram 33c108 f igure 4. t iming w aveform of w rite c ycle (2)
m e m o r y 10 06.14.02 rev 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 1 megabit (128k x 8-bit) cmos sram 33c108 f igure 5. t iming w aveform of w rite c ycle (3) w rite c ycle n ote : 1 . all write cycle timing is referenced from the last valid address to the first transition address. 2 . a write occurs during the overlap of a low cs and a low we . a write begins at the latest transition among cs going low and we going low: a write ends at the earliest transition among cs going high and we going high. t wp is measured from begin- ning of write to the end of write. 3 .t cw is measured from the later of cs going low to end of write. 4 .t as is measured from the address valid to the beginning of write. 5 .t wr is measured form the end of write to the address change. twr applied in case a write ends as cs , or wr going high. 6 . if oe , cs and we are in the read mode during this period, the i/o pi ns are in the output low-z state. inputs of opposite phase of the output must not be appl ied because bus contention can occur. 7 . for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8 .ic cs goes low simultaneously with we going low or after we going low, the outputs remain high impedance state. 9 .d out is the read data of the new address. 10 . when cs is low: i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied.
m e m o r y 11 06.14.02 rev 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 1 megabit (128k x 8-bit) cmos sram 33c108 f igure 6. sram h eavy i on c ross s ection f igure 7. sram p roton seu c ross s ection s tatic
m e m o r y 12 06.14.02 rev 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 1 megabit (128k x 8-bit) cmos sram 33c108 f32-06 note: all dimensions in inches 32 p in r ad -p ak ? f lat p ackage s ymbol d imension m in n om m ax a 0.120 0.135 0.155 b 0.013 0.015 0.020 c 0.008 0.010 0.012 d -- 0.930 0.940 e 0.635 0.645 0.655 e1 -- -- 0.690 e2 0.550 0.565 -- e3 0.030 0.040 -- e 0.050 bsc l 0.390 0.400 0.410 q 0.026 0.098 -- s1 0.005 0.082 -- n32
m e m o r y 13 06.14.02 rev 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 1 megabit (128k x 8-bit) cmos sram 33c108 important notice: these data sheets are created using the chip manufacturer?s published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the use of this information. maxwell technologies? products are not authorized for use as critical components in life support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.

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